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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
1125 | serge | 33 | #include |
34 | #include |
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1123 | serge | 35 | #include |
1321 | serge | 36 | #include |
1125 | serge | 37 | #include |
1179 | serge | 38 | #include |
1125 | serge | 39 | #include |
1179 | serge | 40 | #include "radeon_fixed.h" |
1117 | serge | 41 | |
1179 | serge | 42 | struct radeon_device; |
43 | |||
1117 | serge | 44 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
45 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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46 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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47 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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48 | |||
49 | enum radeon_rmx_type { |
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50 | RMX_OFF, |
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51 | RMX_FULL, |
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52 | RMX_CENTER, |
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53 | RMX_ASPECT |
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54 | }; |
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55 | |||
56 | enum radeon_tv_std { |
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57 | TV_STD_NTSC, |
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58 | TV_STD_PAL, |
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59 | TV_STD_PAL_M, |
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60 | TV_STD_PAL_60, |
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61 | TV_STD_NTSC_J, |
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62 | TV_STD_SCART_PAL, |
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63 | TV_STD_SECAM, |
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64 | TV_STD_PAL_CN, |
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1404 | serge | 65 | TV_STD_PAL_N, |
1117 | serge | 66 | }; |
67 | |||
1321 | serge | 68 | /* radeon gpio-based i2c |
69 | * 1. "mask" reg and bits |
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70 | * grabs the gpio pins for software use |
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71 | * 0=not held 1=held |
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72 | * 2. "a" reg and bits |
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73 | * output pin value |
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74 | * 0=low 1=high |
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75 | * 3. "en" reg and bits |
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76 | * sets the pin direction |
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77 | * 0=input 1=output |
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78 | * 4. "y" reg and bits |
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79 | * input pin value |
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80 | * 0=low 1=high |
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81 | */ |
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1117 | serge | 82 | struct radeon_i2c_bus_rec { |
83 | bool valid; |
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1321 | serge | 84 | /* id used by atom */ |
85 | uint8_t i2c_id; |
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86 | /* can be used with hw i2c engine */ |
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87 | bool hw_capable; |
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88 | /* uses multi-media i2c engine */ |
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89 | bool mm_i2c; |
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90 | /* regs and bits */ |
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1117 | serge | 91 | uint32_t mask_clk_reg; |
92 | uint32_t mask_data_reg; |
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93 | uint32_t a_clk_reg; |
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94 | uint32_t a_data_reg; |
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1321 | serge | 95 | uint32_t en_clk_reg; |
96 | uint32_t en_data_reg; |
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97 | uint32_t y_clk_reg; |
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98 | uint32_t y_data_reg; |
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1117 | serge | 99 | uint32_t mask_clk_mask; |
100 | uint32_t mask_data_mask; |
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101 | uint32_t a_clk_mask; |
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102 | uint32_t a_data_mask; |
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1321 | serge | 103 | uint32_t en_clk_mask; |
104 | uint32_t en_data_mask; |
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105 | uint32_t y_clk_mask; |
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106 | uint32_t y_data_mask; |
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1117 | serge | 107 | }; |
108 | |||
109 | struct radeon_tmds_pll { |
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110 | uint32_t freq; |
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111 | uint32_t value; |
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112 | }; |
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113 | |||
114 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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115 | |||
116 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
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117 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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118 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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119 | #define RADEON_PLL_LEGACY (1 << 3) |
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120 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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121 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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122 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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123 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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124 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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125 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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126 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 127 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1404 | serge | 128 | #define RADEON_PLL_USE_POST_DIV (1 << 12) |
1117 | serge | 129 | |
130 | struct radeon_pll { |
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1404 | serge | 131 | /* reference frequency */ |
132 | uint32_t reference_freq; |
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133 | |||
134 | /* fixed dividers */ |
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135 | uint32_t reference_div; |
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136 | uint32_t post_div; |
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137 | |||
138 | /* pll in/out limits */ |
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1117 | serge | 139 | uint32_t pll_in_min; |
140 | uint32_t pll_in_max; |
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141 | uint32_t pll_out_min; |
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142 | uint32_t pll_out_max; |
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1404 | serge | 143 | uint32_t best_vco; |
1117 | serge | 144 | |
1404 | serge | 145 | /* divider limits */ |
1117 | serge | 146 | uint32_t min_ref_div; |
147 | uint32_t max_ref_div; |
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148 | uint32_t min_post_div; |
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149 | uint32_t max_post_div; |
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150 | uint32_t min_feedback_div; |
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151 | uint32_t max_feedback_div; |
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152 | uint32_t min_frac_feedback_div; |
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153 | uint32_t max_frac_feedback_div; |
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1404 | serge | 154 | |
155 | /* flags for the current clock */ |
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156 | uint32_t flags; |
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157 | |||
158 | /* pll id */ |
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159 | uint32_t id; |
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1117 | serge | 160 | }; |
161 | |||
162 | struct radeon_i2c_chan { |
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1321 | serge | 163 | struct i2c_adapter adapter; |
1117 | serge | 164 | struct drm_device *dev; |
1321 | serge | 165 | union { |
166 | struct i2c_algo_dp_aux_data dp; |
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167 | struct i2c_algo_bit_data bit; |
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168 | } algo; |
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1117 | serge | 169 | struct radeon_i2c_bus_rec rec; |
170 | }; |
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171 | |||
172 | /* mostly for macs, but really any system without connector tables */ |
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173 | enum radeon_connector_table { |
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174 | CT_NONE, |
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175 | CT_GENERIC, |
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176 | CT_IBOOK, |
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177 | CT_POWERBOOK_EXTERNAL, |
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178 | CT_POWERBOOK_INTERNAL, |
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179 | CT_POWERBOOK_VGA, |
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180 | CT_MINI_EXTERNAL, |
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181 | CT_MINI_INTERNAL, |
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182 | CT_IMAC_G5_ISIGHT, |
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183 | CT_EMAC, |
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184 | }; |
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185 | |||
1321 | serge | 186 | enum radeon_dvo_chip { |
187 | DVO_SIL164, |
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188 | DVO_SIL1178, |
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189 | }; |
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190 | |||
1117 | serge | 191 | struct radeon_mode_info { |
192 | struct atom_context *atom_context; |
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1268 | serge | 193 | struct card_info *atom_card_info; |
1117 | serge | 194 | enum radeon_connector_table connector_table; |
195 | bool mode_config_initialized; |
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1179 | serge | 196 | struct radeon_crtc *crtcs[2]; |
197 | /* DVI-I properties */ |
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198 | struct drm_property *coherent_mode_property; |
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199 | /* DAC enable load detect */ |
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200 | struct drm_property *load_detect_property; |
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201 | /* TV standard load detect */ |
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202 | struct drm_property *tv_std_property; |
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203 | /* legacy TMDS PLL detect */ |
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204 | struct drm_property *tmds_pll_property; |
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205 | |||
1117 | serge | 206 | }; |
207 | |||
1179 | serge | 208 | #define MAX_H_CODE_TIMING_LEN 32 |
209 | #define MAX_V_CODE_TIMING_LEN 32 |
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210 | |||
211 | /* need to store these as reading |
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212 | back code tables is excessive */ |
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213 | struct radeon_tv_regs { |
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214 | uint32_t tv_uv_adr; |
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215 | uint32_t timing_cntl; |
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216 | uint32_t hrestart; |
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217 | uint32_t vrestart; |
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218 | uint32_t frestart; |
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219 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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220 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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221 | }; |
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222 | |||
1117 | serge | 223 | struct radeon_crtc { |
1123 | serge | 224 | struct drm_crtc base; |
1117 | serge | 225 | int crtc_id; |
1179 | serge | 226 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 227 | bool enabled; |
228 | bool can_tile; |
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229 | uint32_t crtc_offset; |
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1321 | serge | 230 | struct drm_gem_object *cursor_bo; |
1117 | serge | 231 | uint64_t cursor_addr; |
232 | int cursor_width; |
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233 | int cursor_height; |
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1179 | serge | 234 | uint32_t legacy_display_base_addr; |
235 | uint32_t legacy_cursor_offset; |
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236 | enum radeon_rmx_type rmx_type; |
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237 | fixed20_12 vsc; |
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238 | fixed20_12 hsc; |
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1268 | serge | 239 | struct drm_display_mode native_mode; |
1117 | serge | 240 | }; |
241 | |||
242 | struct radeon_encoder_primary_dac { |
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243 | /* legacy primary dac */ |
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244 | uint32_t ps2_pdac_adj; |
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245 | }; |
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246 | |||
247 | struct radeon_encoder_lvds { |
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248 | /* legacy lvds */ |
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249 | uint16_t panel_vcc_delay; |
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250 | uint8_t panel_pwr_delay; |
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251 | uint8_t panel_digon_delay; |
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252 | uint8_t panel_blon_delay; |
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253 | uint16_t panel_ref_divider; |
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254 | uint8_t panel_post_divider; |
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255 | uint16_t panel_fb_divider; |
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256 | bool use_bios_dividers; |
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257 | uint32_t lvds_gen_cntl; |
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258 | /* panel mode */ |
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1268 | serge | 259 | struct drm_display_mode native_mode; |
1117 | serge | 260 | }; |
261 | |||
262 | struct radeon_encoder_tv_dac { |
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263 | /* legacy tv dac */ |
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264 | uint32_t ps2_tvdac_adj; |
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265 | uint32_t ntsc_tvdac_adj; |
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266 | uint32_t pal_tvdac_adj; |
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267 | |||
1179 | serge | 268 | int h_pos; |
269 | int v_pos; |
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270 | int h_size; |
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271 | int supported_tv_stds; |
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272 | bool tv_on; |
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1117 | serge | 273 | enum radeon_tv_std tv_std; |
1179 | serge | 274 | struct radeon_tv_regs tv; |
1117 | serge | 275 | }; |
276 | |||
277 | struct radeon_encoder_int_tmds { |
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278 | /* legacy int tmds */ |
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279 | struct radeon_tmds_pll tmds_pll[4]; |
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280 | }; |
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281 | |||
1321 | serge | 282 | struct radeon_encoder_ext_tmds { |
283 | /* tmds over dvo */ |
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284 | struct radeon_i2c_chan *i2c_bus; |
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285 | uint8_t slave_addr; |
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286 | enum radeon_dvo_chip dvo_chip; |
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287 | }; |
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288 | |||
1268 | serge | 289 | /* spread spectrum */ |
290 | struct radeon_atom_ss { |
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291 | uint16_t percentage; |
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292 | uint8_t type; |
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293 | uint8_t step; |
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294 | uint8_t delay; |
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295 | uint8_t range; |
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296 | uint8_t refdiv; |
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297 | }; |
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298 | |||
1117 | serge | 299 | struct radeon_encoder_atom_dig { |
300 | /* atom dig */ |
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301 | bool coherent_mode; |
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1404 | serge | 302 | int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */ |
1117 | serge | 303 | /* atom lvds */ |
304 | uint32_t lvds_misc; |
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305 | uint16_t panel_pwr_delay; |
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1268 | serge | 306 | struct radeon_atom_ss *ss; |
1117 | serge | 307 | /* panel mode */ |
1268 | serge | 308 | struct drm_display_mode native_mode; |
1117 | serge | 309 | }; |
310 | |||
1179 | serge | 311 | struct radeon_encoder_atom_dac { |
312 | enum radeon_tv_std tv_std; |
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313 | }; |
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314 | |||
1117 | serge | 315 | struct radeon_encoder { |
316 | struct drm_encoder base; |
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317 | uint32_t encoder_id; |
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318 | uint32_t devices; |
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1179 | serge | 319 | uint32_t active_device; |
1117 | serge | 320 | uint32_t flags; |
321 | uint32_t pixel_clock; |
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322 | enum radeon_rmx_type rmx_type; |
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1268 | serge | 323 | struct drm_display_mode native_mode; |
1117 | serge | 324 | void *enc_priv; |
1404 | serge | 325 | int hdmi_offset; |
326 | int hdmi_audio_workaround; |
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327 | int hdmi_buffer_status; |
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1117 | serge | 328 | }; |
329 | |||
330 | struct radeon_connector_atom_dig { |
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331 | uint32_t igp_lane_info; |
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332 | bool linkb; |
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1321 | serge | 333 | /* displayport */ |
334 | struct radeon_i2c_chan *dp_i2c_bus; |
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335 | u8 dpcd[8]; |
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336 | u8 dp_sink_type; |
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337 | int dp_clock; |
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338 | int dp_lane_count; |
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1117 | serge | 339 | }; |
340 | |||
1321 | serge | 341 | struct radeon_gpio_rec { |
342 | bool valid; |
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343 | u8 id; |
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344 | u32 reg; |
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345 | u32 mask; |
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346 | }; |
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347 | |||
348 | enum radeon_hpd_id { |
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349 | RADEON_HPD_NONE = 0, |
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350 | RADEON_HPD_1, |
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351 | RADEON_HPD_2, |
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352 | RADEON_HPD_3, |
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353 | RADEON_HPD_4, |
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354 | RADEON_HPD_5, |
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355 | RADEON_HPD_6, |
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356 | }; |
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357 | |||
358 | struct radeon_hpd { |
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359 | enum radeon_hpd_id hpd; |
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360 | u8 plugged_state; |
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361 | struct radeon_gpio_rec gpio; |
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362 | }; |
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363 | |||
1117 | serge | 364 | struct radeon_connector { |
365 | struct drm_connector base; |
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366 | uint32_t connector_id; |
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367 | uint32_t devices; |
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368 | struct radeon_i2c_chan *ddc_bus; |
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1268 | serge | 369 | /* some systems have a an hdmi and vga port with a shared ddc line */ |
370 | bool shared_ddc; |
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1179 | serge | 371 | bool use_digital; |
372 | /* we need to mind the EDID between detect |
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373 | and get modes due to analog/digital/tvencoder */ |
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374 | struct edid *edid; |
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1117 | serge | 375 | void *con_priv; |
1179 | serge | 376 | bool dac_load_detect; |
1268 | serge | 377 | uint16_t connector_object_id; |
1321 | serge | 378 | struct radeon_hpd hpd; |
1117 | serge | 379 | }; |
380 | |||
381 | struct radeon_framebuffer { |
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1123 | serge | 382 | struct drm_framebuffer base; |
383 | struct drm_gem_object *obj; |
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1117 | serge | 384 | }; |
385 | |||
1404 | serge | 386 | extern enum radeon_tv_std |
387 | radeon_combios_get_tv_info(struct radeon_device *rdev); |
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388 | extern enum radeon_tv_std |
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389 | radeon_atombios_get_tv_info(struct radeon_device *rdev); |
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390 | |||
1321 | serge | 391 | extern void radeon_connector_hotplug(struct drm_connector *connector); |
392 | extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); |
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393 | extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector, |
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394 | struct drm_display_mode *mode); |
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395 | extern void radeon_dp_set_link_config(struct drm_connector *connector, |
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396 | struct drm_display_mode *mode); |
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397 | extern void dp_link_train(struct drm_encoder *encoder, |
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398 | struct drm_connector *connector); |
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399 | extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); |
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400 | extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); |
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401 | extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, |
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402 | int action, uint8_t lane_num, |
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403 | uint8_t lane_set); |
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404 | extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
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405 | uint8_t write_byte, uint8_t *read_byte); |
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406 | |||
407 | extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, |
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408 | struct radeon_i2c_bus_rec *rec, |
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409 | const char *name); |
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1117 | serge | 410 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
411 | struct radeon_i2c_bus_rec *rec, |
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412 | const char *name); |
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413 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
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1321 | serge | 414 | extern void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, |
415 | u8 slave_addr, |
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416 | u8 addr, |
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417 | u8 *val); |
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418 | extern void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c, |
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419 | u8 slave_addr, |
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420 | u8 addr, |
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421 | u8 val); |
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1117 | serge | 422 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
423 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
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424 | |||
1123 | serge | 425 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
1117 | serge | 426 | |
427 | extern void radeon_compute_pll(struct radeon_pll *pll, |
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428 | uint64_t freq, |
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429 | uint32_t *dot_clock_p, |
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430 | uint32_t *fb_div_p, |
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431 | uint32_t *frac_fb_div_p, |
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432 | uint32_t *ref_div_p, |
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1404 | serge | 433 | uint32_t *post_div_p); |
1117 | serge | 434 | |
1321 | serge | 435 | extern void radeon_compute_pll_avivo(struct radeon_pll *pll, |
436 | uint64_t freq, |
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437 | uint32_t *dot_clock_p, |
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438 | uint32_t *fb_div_p, |
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439 | uint32_t *frac_fb_div_p, |
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440 | uint32_t *ref_div_p, |
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1404 | serge | 441 | uint32_t *post_div_p); |
1321 | serge | 442 | |
443 | extern void radeon_setup_encoder_clones(struct drm_device *dev); |
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444 | |||
1117 | serge | 445 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
446 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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447 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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448 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
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449 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
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450 | extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); |
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1321 | serge | 451 | extern void atombios_digital_setup(struct drm_encoder *encoder, int action); |
1117 | serge | 452 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
1179 | serge | 453 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
1117 | serge | 454 | |
455 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
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456 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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457 | struct drm_framebuffer *old_fb); |
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458 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
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459 | struct drm_display_mode *mode, |
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460 | struct drm_display_mode *adjusted_mode, |
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461 | int x, int y, |
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462 | struct drm_framebuffer *old_fb); |
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463 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
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464 | |||
465 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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466 | struct drm_framebuffer *old_fb); |
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467 | |||
468 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
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469 | struct drm_file *file_priv, |
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470 | uint32_t handle, |
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471 | uint32_t width, |
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472 | uint32_t height); |
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473 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
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474 | int x, int y); |
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475 | |||
476 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
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477 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
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478 | extern struct radeon_encoder_atom_dig * |
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479 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
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1321 | serge | 480 | extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
1179 | serge | 481 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 482 | extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1179 | serge | 483 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 484 | extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1179 | serge | 485 | struct radeon_encoder_int_tmds *tmds); |
1321 | serge | 486 | extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
487 | struct radeon_encoder_ext_tmds *tmds); |
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488 | extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
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489 | struct radeon_encoder_ext_tmds *tmds); |
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1117 | serge | 490 | extern struct radeon_encoder_primary_dac * |
491 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
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492 | extern struct radeon_encoder_tv_dac * |
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493 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
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494 | extern struct radeon_encoder_lvds * |
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495 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
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496 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
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497 | extern struct radeon_encoder_tv_dac * |
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498 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
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499 | extern struct radeon_encoder_primary_dac * |
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500 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
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1321 | serge | 501 | extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); |
502 | extern void radeon_external_tmds_setup(struct drm_encoder *encoder); |
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1117 | serge | 503 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
504 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
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505 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
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506 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
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1179 | serge | 507 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
508 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
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1117 | serge | 509 | extern void |
510 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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511 | extern void |
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512 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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513 | extern void |
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514 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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515 | extern void |
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516 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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517 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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518 | u16 blue, int regno); |
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1221 | serge | 519 | extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
520 | u16 *blue, int regno); |
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1117 | serge | 521 | struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
522 | struct drm_mode_fb_cmd *mode_cmd, |
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523 | struct drm_gem_object *obj); |
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524 | |||
525 | int radeonfb_probe(struct drm_device *dev); |
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526 | |||
527 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
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528 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
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529 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
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530 | void radeon_atombios_init_crtc(struct drm_device *dev, |
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531 | struct radeon_crtc *radeon_crtc); |
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532 | void radeon_legacy_init_crtc(struct drm_device *dev, |
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533 | struct radeon_crtc *radeon_crtc); |
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1321 | serge | 534 | extern void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state); |
1117 | serge | 535 | |
536 | void radeon_get_clock_info(struct drm_device *dev); |
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537 | |||
538 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
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539 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
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540 | |||
541 | void radeon_enc_destroy(struct drm_encoder *encoder); |
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542 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
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543 | void radeon_combios_asic_init(struct drm_device *dev); |
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544 | extern int radeon_static_clocks_init(struct drm_device *dev); |
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1179 | serge | 545 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
546 | struct drm_display_mode *mode, |
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547 | struct drm_display_mode *adjusted_mode); |
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548 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
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1123 | serge | 549 | |
1179 | serge | 550 | /* legacy tv */ |
551 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
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552 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
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553 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
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554 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
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555 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
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556 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
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557 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
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558 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
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559 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
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560 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
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561 | struct drm_display_mode *mode, |
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562 | struct drm_display_mode *adjusted_mode); |
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1117 | serge | 563 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><> |