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1117 | serge | 1 | /* |
2 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
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3 | * VA Linux Systems Inc., Fremont, California. |
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4 | * Copyright 2008 Red Hat Inc. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Original Authors: |
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25 | * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
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26 | * |
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27 | * Kernel port Author: Dave Airlie |
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28 | */ |
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29 | |||
30 | #ifndef RADEON_MODE_H |
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31 | #define RADEON_MODE_H |
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32 | |||
1125 | serge | 33 | #include |
34 | #include |
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1123 | serge | 35 | #include |
1125 | serge | 36 | #include |
1179 | serge | 37 | #include |
1125 | serge | 38 | #include |
1179 | serge | 39 | #include "radeon_fixed.h" |
1117 | serge | 40 | |
1179 | serge | 41 | struct radeon_device; |
42 | |||
1117 | serge | 43 | #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
44 | #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
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45 | #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
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46 | #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
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47 | |||
48 | enum radeon_connector_type { |
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49 | CONNECTOR_NONE, |
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50 | CONNECTOR_VGA, |
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51 | CONNECTOR_DVI_I, |
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52 | CONNECTOR_DVI_D, |
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53 | CONNECTOR_DVI_A, |
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54 | CONNECTOR_STV, |
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55 | CONNECTOR_CTV, |
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56 | CONNECTOR_LVDS, |
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57 | CONNECTOR_DIGITAL, |
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58 | CONNECTOR_SCART, |
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59 | CONNECTOR_HDMI_TYPE_A, |
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60 | CONNECTOR_HDMI_TYPE_B, |
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61 | CONNECTOR_0XC, |
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62 | CONNECTOR_0XD, |
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63 | CONNECTOR_DIN, |
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64 | CONNECTOR_DISPLAY_PORT, |
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65 | CONNECTOR_UNSUPPORTED |
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66 | }; |
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67 | |||
68 | enum radeon_dvi_type { |
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69 | DVI_AUTO, |
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70 | DVI_DIGITAL, |
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71 | DVI_ANALOG |
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72 | }; |
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73 | |||
74 | enum radeon_rmx_type { |
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75 | RMX_OFF, |
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76 | RMX_FULL, |
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77 | RMX_CENTER, |
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78 | RMX_ASPECT |
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79 | }; |
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80 | |||
81 | enum radeon_tv_std { |
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82 | TV_STD_NTSC, |
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83 | TV_STD_PAL, |
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84 | TV_STD_PAL_M, |
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85 | TV_STD_PAL_60, |
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86 | TV_STD_NTSC_J, |
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87 | TV_STD_SCART_PAL, |
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88 | TV_STD_SECAM, |
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89 | TV_STD_PAL_CN, |
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90 | }; |
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91 | |||
92 | struct radeon_i2c_bus_rec { |
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93 | bool valid; |
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94 | uint32_t mask_clk_reg; |
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95 | uint32_t mask_data_reg; |
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96 | uint32_t a_clk_reg; |
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97 | uint32_t a_data_reg; |
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98 | uint32_t put_clk_reg; |
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99 | uint32_t put_data_reg; |
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100 | uint32_t get_clk_reg; |
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101 | uint32_t get_data_reg; |
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102 | uint32_t mask_clk_mask; |
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103 | uint32_t mask_data_mask; |
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104 | uint32_t put_clk_mask; |
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105 | uint32_t put_data_mask; |
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106 | uint32_t get_clk_mask; |
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107 | uint32_t get_data_mask; |
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108 | uint32_t a_clk_mask; |
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109 | uint32_t a_data_mask; |
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110 | }; |
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111 | |||
112 | struct radeon_tmds_pll { |
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113 | uint32_t freq; |
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114 | uint32_t value; |
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115 | }; |
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116 | |||
117 | #define RADEON_MAX_BIOS_CONNECTOR 16 |
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118 | |||
119 | #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
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120 | #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
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121 | #define RADEON_PLL_USE_REF_DIV (1 << 2) |
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122 | #define RADEON_PLL_LEGACY (1 << 3) |
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123 | #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
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124 | #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
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125 | #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
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126 | #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
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127 | #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
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128 | #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
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129 | #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
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1179 | serge | 130 | #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) |
1117 | serge | 131 | |
132 | struct radeon_pll { |
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133 | uint16_t reference_freq; |
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134 | uint16_t reference_div; |
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135 | uint32_t pll_in_min; |
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136 | uint32_t pll_in_max; |
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137 | uint32_t pll_out_min; |
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138 | uint32_t pll_out_max; |
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139 | uint16_t xclk; |
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140 | |||
141 | uint32_t min_ref_div; |
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142 | uint32_t max_ref_div; |
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143 | uint32_t min_post_div; |
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144 | uint32_t max_post_div; |
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145 | uint32_t min_feedback_div; |
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146 | uint32_t max_feedback_div; |
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147 | uint32_t min_frac_feedback_div; |
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148 | uint32_t max_frac_feedback_div; |
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149 | uint32_t best_vco; |
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150 | }; |
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151 | |||
152 | struct radeon_i2c_chan { |
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153 | struct drm_device *dev; |
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1123 | serge | 154 | struct i2c_adapter adapter; |
155 | struct i2c_algo_bit_data algo; |
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1117 | serge | 156 | struct radeon_i2c_bus_rec rec; |
157 | }; |
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158 | |||
159 | /* mostly for macs, but really any system without connector tables */ |
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160 | enum radeon_connector_table { |
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161 | CT_NONE, |
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162 | CT_GENERIC, |
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163 | CT_IBOOK, |
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164 | CT_POWERBOOK_EXTERNAL, |
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165 | CT_POWERBOOK_INTERNAL, |
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166 | CT_POWERBOOK_VGA, |
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167 | CT_MINI_EXTERNAL, |
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168 | CT_MINI_INTERNAL, |
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169 | CT_IMAC_G5_ISIGHT, |
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170 | CT_EMAC, |
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171 | }; |
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172 | |||
173 | struct radeon_mode_info { |
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174 | struct atom_context *atom_context; |
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175 | enum radeon_connector_table connector_table; |
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176 | bool mode_config_initialized; |
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1179 | serge | 177 | struct radeon_crtc *crtcs[2]; |
178 | /* DVI-I properties */ |
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179 | struct drm_property *coherent_mode_property; |
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180 | /* DAC enable load detect */ |
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181 | struct drm_property *load_detect_property; |
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182 | /* TV standard load detect */ |
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183 | struct drm_property *tv_std_property; |
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184 | /* legacy TMDS PLL detect */ |
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185 | struct drm_property *tmds_pll_property; |
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186 | |||
1117 | serge | 187 | }; |
188 | |||
1179 | serge | 189 | struct radeon_native_mode { |
190 | /* preferred mode */ |
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191 | uint32_t panel_xres, panel_yres; |
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192 | uint32_t hoverplus, hsync_width; |
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193 | uint32_t hblank; |
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194 | uint32_t voverplus, vsync_width; |
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195 | uint32_t vblank; |
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196 | uint32_t dotclock; |
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197 | uint32_t flags; |
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198 | }; |
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199 | |||
200 | #define MAX_H_CODE_TIMING_LEN 32 |
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201 | #define MAX_V_CODE_TIMING_LEN 32 |
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202 | |||
203 | /* need to store these as reading |
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204 | back code tables is excessive */ |
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205 | struct radeon_tv_regs { |
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206 | uint32_t tv_uv_adr; |
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207 | uint32_t timing_cntl; |
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208 | uint32_t hrestart; |
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209 | uint32_t vrestart; |
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210 | uint32_t frestart; |
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211 | uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; |
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212 | uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; |
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213 | }; |
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214 | |||
1117 | serge | 215 | struct radeon_crtc { |
1123 | serge | 216 | struct drm_crtc base; |
1117 | serge | 217 | int crtc_id; |
1179 | serge | 218 | u16 lut_r[256], lut_g[256], lut_b[256]; |
1117 | serge | 219 | bool enabled; |
220 | bool can_tile; |
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221 | uint32_t crtc_offset; |
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222 | // struct drm_gem_object *cursor_bo; |
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223 | uint64_t cursor_addr; |
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224 | int cursor_width; |
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225 | int cursor_height; |
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1179 | serge | 226 | uint32_t legacy_display_base_addr; |
227 | uint32_t legacy_cursor_offset; |
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228 | enum radeon_rmx_type rmx_type; |
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229 | fixed20_12 vsc; |
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230 | fixed20_12 hsc; |
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231 | struct radeon_native_mode native_mode; |
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1117 | serge | 232 | }; |
233 | |||
234 | struct radeon_encoder_primary_dac { |
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235 | /* legacy primary dac */ |
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236 | uint32_t ps2_pdac_adj; |
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237 | }; |
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238 | |||
239 | struct radeon_encoder_lvds { |
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240 | /* legacy lvds */ |
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241 | uint16_t panel_vcc_delay; |
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242 | uint8_t panel_pwr_delay; |
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243 | uint8_t panel_digon_delay; |
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244 | uint8_t panel_blon_delay; |
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245 | uint16_t panel_ref_divider; |
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246 | uint8_t panel_post_divider; |
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247 | uint16_t panel_fb_divider; |
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248 | bool use_bios_dividers; |
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249 | uint32_t lvds_gen_cntl; |
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250 | /* panel mode */ |
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251 | struct radeon_native_mode native_mode; |
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252 | }; |
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253 | |||
254 | struct radeon_encoder_tv_dac { |
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255 | /* legacy tv dac */ |
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256 | uint32_t ps2_tvdac_adj; |
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257 | uint32_t ntsc_tvdac_adj; |
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258 | uint32_t pal_tvdac_adj; |
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259 | |||
1179 | serge | 260 | int h_pos; |
261 | int v_pos; |
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262 | int h_size; |
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263 | int supported_tv_stds; |
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264 | bool tv_on; |
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1117 | serge | 265 | enum radeon_tv_std tv_std; |
1179 | serge | 266 | struct radeon_tv_regs tv; |
1117 | serge | 267 | }; |
268 | |||
269 | struct radeon_encoder_int_tmds { |
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270 | /* legacy int tmds */ |
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271 | struct radeon_tmds_pll tmds_pll[4]; |
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272 | }; |
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273 | |||
274 | struct radeon_encoder_atom_dig { |
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275 | /* atom dig */ |
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276 | bool coherent_mode; |
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277 | int dig_block; |
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278 | /* atom lvds */ |
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279 | uint32_t lvds_misc; |
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280 | uint16_t panel_pwr_delay; |
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281 | /* panel mode */ |
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282 | struct radeon_native_mode native_mode; |
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283 | }; |
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284 | |||
1179 | serge | 285 | struct radeon_encoder_atom_dac { |
286 | enum radeon_tv_std tv_std; |
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287 | }; |
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288 | |||
1117 | serge | 289 | struct radeon_encoder { |
290 | struct drm_encoder base; |
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291 | uint32_t encoder_id; |
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292 | uint32_t devices; |
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1179 | serge | 293 | uint32_t active_device; |
1117 | serge | 294 | uint32_t flags; |
295 | uint32_t pixel_clock; |
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296 | enum radeon_rmx_type rmx_type; |
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297 | struct radeon_native_mode native_mode; |
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298 | void *enc_priv; |
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299 | }; |
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300 | |||
301 | struct radeon_connector_atom_dig { |
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302 | uint32_t igp_lane_info; |
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303 | bool linkb; |
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304 | }; |
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305 | |||
306 | struct radeon_connector { |
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307 | struct drm_connector base; |
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308 | uint32_t connector_id; |
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309 | uint32_t devices; |
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310 | struct radeon_i2c_chan *ddc_bus; |
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1179 | serge | 311 | bool use_digital; |
312 | /* we need to mind the EDID between detect |
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313 | and get modes due to analog/digital/tvencoder */ |
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314 | struct edid *edid; |
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1117 | serge | 315 | void *con_priv; |
1179 | serge | 316 | bool dac_load_detect; |
1117 | serge | 317 | }; |
318 | |||
319 | struct radeon_framebuffer { |
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1123 | serge | 320 | struct drm_framebuffer base; |
321 | struct drm_gem_object *obj; |
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1117 | serge | 322 | }; |
323 | |||
324 | extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
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325 | struct radeon_i2c_bus_rec *rec, |
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326 | const char *name); |
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327 | extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
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328 | extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
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329 | extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
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330 | |||
1123 | serge | 331 | extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
1117 | serge | 332 | |
333 | extern void radeon_compute_pll(struct radeon_pll *pll, |
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334 | uint64_t freq, |
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335 | uint32_t *dot_clock_p, |
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336 | uint32_t *fb_div_p, |
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337 | uint32_t *frac_fb_div_p, |
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338 | uint32_t *ref_div_p, |
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339 | uint32_t *post_div_p, |
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340 | int flags); |
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341 | |||
342 | struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
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343 | struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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344 | struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
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345 | struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
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346 | struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
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347 | extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); |
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348 | extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
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1179 | serge | 349 | extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); |
1117 | serge | 350 | |
351 | extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
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352 | extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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353 | struct drm_framebuffer *old_fb); |
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354 | extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
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355 | struct drm_display_mode *mode, |
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356 | struct drm_display_mode *adjusted_mode, |
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357 | int x, int y, |
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358 | struct drm_framebuffer *old_fb); |
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359 | extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
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360 | |||
361 | extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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362 | struct drm_framebuffer *old_fb); |
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363 | extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); |
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364 | |||
365 | extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
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366 | struct drm_file *file_priv, |
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367 | uint32_t handle, |
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368 | uint32_t width, |
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369 | uint32_t height); |
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370 | extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
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371 | int x, int y); |
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372 | |||
373 | extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
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374 | extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
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375 | extern struct radeon_encoder_atom_dig * |
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376 | radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
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1179 | serge | 377 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
378 | struct radeon_encoder_int_tmds *tmds); |
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379 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
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380 | struct radeon_encoder_int_tmds *tmds); |
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381 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
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382 | struct radeon_encoder_int_tmds *tmds); |
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1117 | serge | 383 | extern struct radeon_encoder_primary_dac * |
384 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
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385 | extern struct radeon_encoder_tv_dac * |
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386 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
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387 | extern struct radeon_encoder_lvds * |
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388 | radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
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389 | extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
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390 | extern struct radeon_encoder_tv_dac * |
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391 | radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
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392 | extern struct radeon_encoder_primary_dac * |
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393 | radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
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394 | extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
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395 | extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
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396 | extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
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397 | extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
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1179 | serge | 398 | extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); |
399 | extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); |
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1117 | serge | 400 | extern void |
401 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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402 | extern void |
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403 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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404 | extern void |
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405 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
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406 | extern void |
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407 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
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408 | extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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409 | u16 blue, int regno); |
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410 | struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
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411 | struct drm_mode_fb_cmd *mode_cmd, |
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412 | struct drm_gem_object *obj); |
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413 | |||
414 | int radeonfb_probe(struct drm_device *dev); |
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415 | |||
416 | int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
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417 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
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418 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
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419 | void radeon_atombios_init_crtc(struct drm_device *dev, |
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420 | struct radeon_crtc *radeon_crtc); |
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421 | void radeon_legacy_init_crtc(struct drm_device *dev, |
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422 | struct radeon_crtc *radeon_crtc); |
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423 | void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state); |
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424 | |||
425 | void radeon_get_clock_info(struct drm_device *dev); |
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426 | |||
427 | extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
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428 | extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
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429 | |||
430 | void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
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431 | struct drm_display_mode *mode, |
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432 | struct drm_display_mode *adjusted_mode); |
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433 | void radeon_enc_destroy(struct drm_encoder *encoder); |
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434 | void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
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435 | void radeon_combios_asic_init(struct drm_device *dev); |
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436 | extern int radeon_static_clocks_init(struct drm_device *dev); |
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1179 | serge | 437 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
438 | struct drm_display_mode *mode, |
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439 | struct drm_display_mode *adjusted_mode); |
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440 | void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); |
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1123 | serge | 441 | |
1179 | serge | 442 | /* legacy tv */ |
443 | void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, |
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444 | uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, |
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445 | uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); |
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446 | void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, |
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447 | uint32_t *htotal_cntl, uint32_t *ppll_ref_div, |
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448 | uint32_t *ppll_div_3, uint32_t *pixclks_cntl); |
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449 | void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, |
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450 | uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, |
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451 | uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); |
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452 | void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, |
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453 | struct drm_display_mode *mode, |
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454 | struct drm_display_mode *adjusted_mode); |
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1117 | serge | 455 | #endif><>><>><>><>><>><>><>><>><>><>><>><> |