WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_legacy_encoders.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
		28	#include
1123	serge	29	#include "radeon.h"
		30	#include "atom.h"
2997	Serge	31	#include
		32	#ifdef CONFIG_PMAC_BACKLIGHT
		33	#include
		34	#endif
1123	serge	35
1179	serge	36	static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
1123	serge	37	{
		38	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	39	struct drm_encoder_helper_funcs *encoder_funcs;
1123	serge	40
1179	serge	41	encoder_funcs = encoder->helper_private;
		42	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
		43	radeon_encoder->active_device = 0;
1123	serge	44	}
		45
1963	serge	46	static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
1123	serge	47	{
		48	struct drm_device *dev = encoder->dev;
		49	struct radeon_device *rdev = dev->dev_private;
		50	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		51	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
		52	int panel_pwr_delay = 2000;
1403	serge	53	bool is_mac = false;
1963	serge	54	uint8_t backlight_level;
		55	DRM_DEBUG_KMS("\n");
1123	serge	56
1963	serge	57	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		58	backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		59
1123	serge	60	if (radeon_encoder->enc_priv) {
		61	if (rdev->is_atom_bios) {
		62	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		63	panel_pwr_delay = lvds->panel_pwr_delay;
1963	serge	64	if (lvds->bl_dev)
		65	backlight_level = lvds->backlight_level;
1123	serge	66	} else {
		67	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		68	panel_pwr_delay = lvds->panel_pwr_delay;
1963	serge	69	if (lvds->bl_dev)
		70	backlight_level = lvds->backlight_level;
1123	serge	71	}
		72	}
		73
1403	serge	74	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
		75	* Taken from radeonfb.
		76	*/
		77	if ((rdev->mode_info.connector_table == CT_IBOOK) \|\|
		78	(rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) \|\|
		79	(rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) \|\|
		80	(rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
		81	is_mac = true;
		82
1123	serge	83	switch (mode) {
		84	case DRM_MODE_DPMS_ON:
		85	disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
		86	disp_pwr_man \|= RADEON_AUTO_PWRUP_EN;
		87	WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
		88	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		89	lvds_pll_cntl \|= RADEON_LVDS_PLL_EN;
		90	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
2997	Serge	91	mdelay(1);
1123	serge	92
		93	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		94	lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
		95	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		96
1963	serge	97	lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS \|
		98	RADEON_LVDS_BL_MOD_LEVEL_MASK);
		99	lvds_gen_cntl \|= (RADEON_LVDS_ON \| RADEON_LVDS_EN \|
		100	RADEON_LVDS_DIGON \| RADEON_LVDS_BLON \|
		101	(backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
1403	serge	102	if (is_mac)
		103	lvds_gen_cntl \|= RADEON_LVDS_BL_MOD_EN;
2997	Serge	104	mdelay(panel_pwr_delay);
1123	serge	105	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		106	break;
		107	case DRM_MODE_DPMS_STANDBY:
		108	case DRM_MODE_DPMS_SUSPEND:
		109	case DRM_MODE_DPMS_OFF:
		110	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
		111	WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
		112	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
1403	serge	113	if (is_mac) {
		114	lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
		115	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		116	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_EN);
		117	} else {
		118	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
1123	serge	119	lvds_gen_cntl &= ~(RADEON_LVDS_ON \| RADEON_LVDS_BLON \| RADEON_LVDS_EN \| RADEON_LVDS_DIGON);
1403	serge	120	}
2997	Serge	121	mdelay(panel_pwr_delay);
1123	serge	122	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		123	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
2997	Serge	124	mdelay(panel_pwr_delay);
1123	serge	125	break;
		126	}
		127
		128	if (rdev->is_atom_bios)
		129	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		130	else
		131	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	132
1123	serge	133	}
		134
1963	serge	135	static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
		136	{
		137	struct radeon_device *rdev = encoder->dev->dev_private;
		138	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		139	DRM_DEBUG("\n");
		140
		141	if (radeon_encoder->enc_priv) {
		142	if (rdev->is_atom_bios) {
		143	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		144	lvds->dpms_mode = mode;
		145	} else {
		146	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		147	lvds->dpms_mode = mode;
		148	}
		149	}
		150
		151	radeon_legacy_lvds_update(encoder, mode);
		152	}
		153
1123	serge	154	static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
		155	{
		156	struct radeon_device *rdev = encoder->dev->dev_private;
		157
		158	if (rdev->is_atom_bios)
		159	radeon_atom_output_lock(encoder, true);
		160	else
		161	radeon_combios_output_lock(encoder, true);
		162	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
		163	}
		164
		165	static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
		166	{
		167	struct radeon_device *rdev = encoder->dev->dev_private;
		168
		169	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
		170	if (rdev->is_atom_bios)
		171	radeon_atom_output_lock(encoder, false);
		172	else
		173	radeon_combios_output_lock(encoder, false);
		174	}
		175
		176	static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
		177	struct drm_display_mode *mode,
		178	struct drm_display_mode *adjusted_mode)
		179	{
		180	struct drm_device *dev = encoder->dev;
		181	struct radeon_device *rdev = dev->dev_private;
		182	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		183	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		184	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
		185
1963	serge	186	DRM_DEBUG_KMS("\n");
1123	serge	187
		188	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
		189	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
		190
		191	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1321	serge	192	if (rdev->is_atom_bios) {
		193	/* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
		194	* need to call that on resume to set up the reg properly.
		195	*/
		196	radeon_encoder->pixel_clock = adjusted_mode->clock;
		197	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		198	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		199	} else {
1123	serge	200	struct radeon_encoder_lvds lvds = (struct radeon_encoder_lvds )radeon_encoder->enc_priv;
		201	if (lvds) {
1963	serge	202	DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
1123	serge	203	lvds_gen_cntl = lvds->lvds_gen_cntl;
		204	lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		205	(0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		206	lvds_ss_gen_cntl \|= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) \|
		207	(lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
		208	} else
		209	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1321	serge	210	}
1123	serge	211	lvds_gen_cntl \|= RADEON_LVDS_DISPLAY_DIS;
		212	lvds_gen_cntl &= ~(RADEON_LVDS_ON \|
		213	RADEON_LVDS_BLON \|
		214	RADEON_LVDS_EN \|
		215	RADEON_LVDS_RST_FM);
		216
		217	if (ASIC_IS_R300(rdev))
		218	lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
		219
		220	if (radeon_crtc->crtc_id == 0) {
		221	if (ASIC_IS_R300(rdev)) {
1179	serge	222	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	223	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_RMX;
		224	} else
		225	lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
		226	} else {
		227	if (ASIC_IS_R300(rdev))
		228	lvds_pll_cntl \|= R300_LVDS_SRC_SEL_CRTC2;
		229	else
		230	lvds_gen_cntl \|= RADEON_LVDS_SEL_CRTC2;
		231	}
		232
		233	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
		234	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
		235	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
		236
		237	if (rdev->family == CHIP_RV410)
		238	WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
		239
		240	if (rdev->is_atom_bios)
		241	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		242	else
		243	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		244	}
		245
1321	serge	246	static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
2997	Serge	247	const struct drm_display_mode *mode,
1123	serge	248	struct drm_display_mode *adjusted_mode)
		249	{
		250	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		251
1268	serge	252	/* set the active encoder to connector routing */
		253	radeon_encoder_set_active_device(encoder);
1123	serge	254	drm_mode_set_crtcinfo(adjusted_mode, 0);
		255
1321	serge	256	/* get the native mode for LVDS */
1963	serge	257	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
		258	radeon_panel_mode_fixup(encoder, adjusted_mode);
1123	serge	259
		260	return true;
		261	}
		262
		263	static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
		264	.dpms = radeon_legacy_lvds_dpms,
1321	serge	265	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	266	.prepare = radeon_legacy_lvds_prepare,
		267	.mode_set = radeon_legacy_lvds_mode_set,
		268	.commit = radeon_legacy_lvds_commit,
1179	serge	269	.disable = radeon_legacy_encoder_disable,
1123	serge	270	};
		271
2997	Serge	272	u8
		273	radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
		274	{
		275	struct drm_device *dev = radeon_encoder->base.dev;
		276	struct radeon_device *rdev = dev->dev_private;
		277	u8 backlight_level;
1123	serge	278
2997	Serge	279	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		280	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
1963	serge	281
2997	Serge	282	return backlight_level;
		283	}
1963	serge	284
2997	Serge	285	void
		286	radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
		287	{
		288	struct drm_device *dev = radeon_encoder->base.dev;
		289	struct radeon_device *rdev = dev->dev_private;
		290	int dpms_mode = DRM_MODE_DPMS_ON;
		291
		292	if (radeon_encoder->enc_priv) {
		293	if (rdev->is_atom_bios) {
		294	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		295	if (lvds->backlight_level > 0)
		296	dpms_mode = lvds->dpms_mode;
		297	else
		298	dpms_mode = DRM_MODE_DPMS_OFF;
		299	lvds->backlight_level = level;
		300	} else {
		301	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		302	if (lvds->backlight_level > 0)
		303	dpms_mode = lvds->dpms_mode;
		304	else
		305	dpms_mode = DRM_MODE_DPMS_OFF;
		306	lvds->backlight_level = level;
		307	}
		308	}
		309
		310	radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
		311	}
		312
		313	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
		314
1963	serge	315	static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
		316	{
		317	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		318	uint8_t level;
		319
		320	/* Convert brightness to hardware level */
		321	if (bd->props.brightness < 0)
		322	level = 0;
2997	Serge	323	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
		324	level = RADEON_MAX_BL_LEVEL;
1963	serge	325	else
		326	level = bd->props.brightness;
		327
		328	if (pdata->negative)
2997	Serge	329	level = RADEON_MAX_BL_LEVEL - level;
1963	serge	330
		331	return level;
		332	}
		333
		334	static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
		335	{
		336	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		337	struct radeon_encoder *radeon_encoder = pdata->encoder;
		338
2997	Serge	339	radeon_legacy_set_backlight_level(radeon_encoder,
		340	radeon_legacy_lvds_level(bd));
1963	serge	341
		342	return 0;
		343	}
		344
		345	static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
		346	{
		347	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
		348	struct radeon_encoder *radeon_encoder = pdata->encoder;
		349	struct drm_device *dev = radeon_encoder->base.dev;
		350	struct radeon_device *rdev = dev->dev_private;
		351	uint8_t backlight_level;
		352
		353	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		354	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		355
2997	Serge	356	return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
1963	serge	357	}
		358
		359	static const struct backlight_ops radeon_backlight_ops = {
		360	.get_brightness = radeon_legacy_backlight_get_brightness,
		361	.update_status = radeon_legacy_backlight_update_status,
		362	};
		363
		364	void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
		365	struct drm_connector *drm_connector)
		366	{
		367	struct drm_device *dev = radeon_encoder->base.dev;
		368	struct radeon_device *rdev = dev->dev_private;
		369	struct backlight_device *bd;
		370	struct backlight_properties props;
		371	struct radeon_backlight_privdata *pdata;
		372	uint8_t backlight_level;
2997	Serge	373	char bl_name[16];
1963	serge	374
		375	if (!radeon_encoder->enc_priv)
		376	return;
		377
		378	#ifdef CONFIG_PMAC_BACKLIGHT
		379	if (!pmac_has_backlight_type("ati") &&
		380	!pmac_has_backlight_type("mnca"))
		381	return;
		382	#endif
		383
		384	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
		385	if (!pdata) {
		386	DRM_ERROR("Memory allocation failed\n");
		387	goto error;
		388	}
		389
2997	Serge	390	memset(&props, 0, sizeof(props));
		391	props.max_brightness = RADEON_MAX_BL_LEVEL;
1963	serge	392	props.type = BACKLIGHT_RAW;
2997	Serge	393	snprintf(bl_name, sizeof(bl_name),
		394	"radeon_bl%d", dev->primary->index);
		395	bd = backlight_device_register(bl_name, &drm_connector->kdev,
1963	serge	396	pdata, &radeon_backlight_ops, &props);
		397	if (IS_ERR(bd)) {
		398	DRM_ERROR("Backlight registration failed\n");
		399	goto error;
		400	}
		401
		402	pdata->encoder = radeon_encoder;
		403
		404	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
		405	RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
		406
		407	/* First, try to detect backlight level sense based on the assumption
		408	* that firmware set it up at full brightness
		409	*/
		410	if (backlight_level == 0)
		411	pdata->negative = true;
		412	else if (backlight_level == 0xff)
		413	pdata->negative = false;
		414	else {
		415	/* XXX hack... maybe some day we can figure out in what direction
		416	* backlight should work on a given panel?
		417	*/
		418	pdata->negative = (rdev->family != CHIP_RV200 &&
		419	rdev->family != CHIP_RV250 &&
		420	rdev->family != CHIP_RV280 &&
		421	rdev->family != CHIP_RV350);
		422
		423	#ifdef CONFIG_PMAC_BACKLIGHT
		424	pdata->negative = (pdata->negative \|\|
		425	of_machine_is_compatible("PowerBook4,3") \|\|
		426	of_machine_is_compatible("PowerBook6,3") \|\|
		427	of_machine_is_compatible("PowerBook6,5"));
		428	#endif
		429	}
		430
		431	if (rdev->is_atom_bios) {
		432	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		433	lvds->bl_dev = bd;
		434	} else {
		435	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		436	lvds->bl_dev = bd;
		437	}
		438
		439	bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
		440	bd->props.power = FB_BLANK_UNBLANK;
		441	backlight_update_status(bd);
		442
		443	DRM_INFO("radeon legacy LVDS backlight initialized\n");
		444
		445	return;
		446
		447	error:
		448	kfree(pdata);
		449	return;
		450	}
		451
		452	static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
		453	{
		454	struct drm_device *dev = radeon_encoder->base.dev;
		455	struct radeon_device *rdev = dev->dev_private;
		456	struct backlight_device *bd = NULL;
		457
		458	if (!radeon_encoder->enc_priv)
		459	return;
		460
		461	if (rdev->is_atom_bios) {
		462	struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
		463	bd = lvds->bl_dev;
		464	lvds->bl_dev = NULL;
		465	} else {
		466	struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
		467	bd = lvds->bl_dev;
		468	lvds->bl_dev = NULL;
		469	}
		470
		471	if (bd) {
2997	Serge	472	struct radeon_backlight_privdata *pdata;
1963	serge	473
		474	pdata = bl_get_data(bd);
		475	backlight_device_unregister(bd);
		476	kfree(pdata);
		477
		478	DRM_INFO("radeon legacy LVDS backlight unloaded\n");
		479	}
		480	}
		481
		482	#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
		483
		484	void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
		485	{
		486	}
		487
		488	static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
		489	{
		490	}
		491
		492	#endif
		493
		494
		495	static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
		496	{
		497	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		498
		499	if (radeon_encoder->enc_priv) {
		500	radeon_legacy_backlight_exit(radeon_encoder);
		501	kfree(radeon_encoder->enc_priv);
		502	}
		503	drm_encoder_cleanup(encoder);
		504	kfree(radeon_encoder);
		505	}
		506
1123	serge	507	static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
1963	serge	508	.destroy = radeon_lvds_enc_destroy,
1123	serge	509	};
		510
		511	static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
		512	{
		513	struct drm_device *dev = encoder->dev;
		514	struct radeon_device *rdev = dev->dev_private;
		515	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		516	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
		517	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		518
1963	serge	519	DRM_DEBUG_KMS("\n");
1123	serge	520
		521	switch (mode) {
		522	case DRM_MODE_DPMS_ON:
		523	crtc_ext_cntl \|= RADEON_CRTC_CRT_ON;
		524	dac_cntl &= ~RADEON_DAC_PDWN;
		525	dac_macro_cntl &= ~(RADEON_DAC_PDWN_R \|
		526	RADEON_DAC_PDWN_G \|
		527	RADEON_DAC_PDWN_B);
		528	break;
		529	case DRM_MODE_DPMS_STANDBY:
		530	case DRM_MODE_DPMS_SUSPEND:
		531	case DRM_MODE_DPMS_OFF:
		532	crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
		533	dac_cntl \|= RADEON_DAC_PDWN;
		534	dac_macro_cntl \|= (RADEON_DAC_PDWN_R \|
		535	RADEON_DAC_PDWN_G \|
		536	RADEON_DAC_PDWN_B);
		537	break;
		538	}
		539
3120	serge	540	/* handled in radeon_crtc_dpms() */
		541	if (!(rdev->flags & RADEON_SINGLE_CRTC))
1123	serge	542	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		543	WREG32(RADEON_DAC_CNTL, dac_cntl);
		544	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		545
		546	if (rdev->is_atom_bios)
		547	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		548	else
		549	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	550
1123	serge	551	}
		552
		553	static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
		554	{
		555	struct radeon_device *rdev = encoder->dev->dev_private;
		556
		557	if (rdev->is_atom_bios)
		558	radeon_atom_output_lock(encoder, true);
		559	else
		560	radeon_combios_output_lock(encoder, true);
		561	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		562	}
		563
		564	static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
		565	{
		566	struct radeon_device *rdev = encoder->dev->dev_private;
		567
		568	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		569
		570	if (rdev->is_atom_bios)
		571	radeon_atom_output_lock(encoder, false);
		572	else
		573	radeon_combios_output_lock(encoder, false);
		574	}
		575
		576	static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
		577	struct drm_display_mode *mode,
		578	struct drm_display_mode *adjusted_mode)
		579	{
		580	struct drm_device *dev = encoder->dev;
		581	struct radeon_device *rdev = dev->dev_private;
		582	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		583	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		584	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
		585
1963	serge	586	DRM_DEBUG_KMS("\n");
1123	serge	587
		588	if (radeon_crtc->crtc_id == 0) {
		589	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		590	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		591	~(RADEON_DISP_DAC_SOURCE_MASK);
		592	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		593	} else {
		594	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
		595	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		596	}
		597	} else {
		598	if (rdev->family == CHIP_R200 \|\| ASIC_IS_R300(rdev)) {
		599	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
		600	~(RADEON_DISP_DAC_SOURCE_MASK);
		601	disp_output_cntl \|= RADEON_DISP_DAC_SOURCE_CRTC2;
		602	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		603	} else {
		604	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC_CLK_SEL;
		605	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		606	}
		607	}
		608
		609	dac_cntl = (RADEON_DAC_MASK_ALL \|
		610	RADEON_DAC_VGA_ADR_EN \|
		611	/* TODO 6-bits */
		612	RADEON_DAC_8BIT_EN);
		613
		614	WREG32_P(RADEON_DAC_CNTL,
		615	dac_cntl,
		616	RADEON_DAC_RANGE_CNTL \|
		617	RADEON_DAC_BLANKING);
		618
		619	if (radeon_encoder->enc_priv) {
		620	struct radeon_encoder_primary_dac p_dac = (struct radeon_encoder_primary_dac )radeon_encoder->enc_priv;
		621	dac_macro_cntl = p_dac->ps2_pdac_adj;
		622	} else
		623	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		624	dac_macro_cntl \|= RADEON_DAC_PDWN_R \| RADEON_DAC_PDWN_G \| RADEON_DAC_PDWN_B;
		625	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		626
		627	if (rdev->is_atom_bios)
		628	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		629	else
		630	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		631	}
		632
		633	static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
		634	struct drm_connector *connector)
		635	{
		636	struct drm_device *dev = encoder->dev;
		637	struct radeon_device *rdev = dev->dev_private;
		638	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
		639	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
		640	enum drm_connector_status found = connector_status_disconnected;
		641	bool color = true;
		642
3764	Serge	643	/* just don't bother on RN50 those chip are often connected to remoting
		644	* console hw and often we get failure to load detect those. So to make
		645	* everyone happy report the encoder as always connected.
		646	*/
		647	if (ASIC_IS_RN50(rdev)) {
		648	return connector_status_connected;
		649	}
		650
1123	serge	651	/* save the regs we need */
		652	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
		653	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		654	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		655	dac_cntl = RREG32(RADEON_DAC_CNTL);
		656	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
		657
		658	tmp = vclk_ecp_cntl &
		659	~(RADEON_PIXCLK_ALWAYS_ONb \| RADEON_PIXCLK_DAC_ALWAYS_ONb);
		660	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
		661
		662	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		663	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		664
		665	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN \|
		666	RADEON_DAC_FORCE_DATA_EN;
		667
		668	if (color)
		669	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		670	else
		671	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		672
		673	if (ASIC_IS_R300(rdev))
		674	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
3120	serge	675	else if (ASIC_IS_RV100(rdev))
		676	tmp \|= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
1123	serge	677	else
		678	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		679
		680	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		681
		682	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK \| RADEON_DAC_PDWN);
		683	tmp \|= RADEON_DAC_RANGE_CNTL_PS2 \| RADEON_DAC_CMP_EN;
		684	WREG32(RADEON_DAC_CNTL, tmp);
		685
3120	serge	686	tmp = dac_macro_cntl;
1123	serge	687	tmp &= ~(RADEON_DAC_PDWN_R \|
		688	RADEON_DAC_PDWN_G \|
		689	RADEON_DAC_PDWN_B);
		690
		691	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
		692
2997	Serge	693	mdelay(2);
1123	serge	694
		695	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
		696	found = connector_status_connected;
		697
		698	/* restore the regs we used */
		699	WREG32(RADEON_DAC_CNTL, dac_cntl);
		700	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
		701	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		702	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		703	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
		704
		705	return found;
		706	}
		707
		708	static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
		709	.dpms = radeon_legacy_primary_dac_dpms,
1321	serge	710	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	711	.prepare = radeon_legacy_primary_dac_prepare,
		712	.mode_set = radeon_legacy_primary_dac_mode_set,
		713	.commit = radeon_legacy_primary_dac_commit,
		714	.detect = radeon_legacy_primary_dac_detect,
1179	serge	715	.disable = radeon_legacy_encoder_disable,
1123	serge	716	};
		717
		718
		719	static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
		720	.destroy = radeon_enc_destroy,
		721	};
		722
		723	static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
		724	{
		725	struct drm_device *dev = encoder->dev;
		726	struct radeon_device *rdev = dev->dev_private;
		727	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
1963	serge	728	DRM_DEBUG_KMS("\n");
1123	serge	729
		730	switch (mode) {
		731	case DRM_MODE_DPMS_ON:
		732	fp_gen_cntl \|= (RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		733	break;
		734	case DRM_MODE_DPMS_STANDBY:
		735	case DRM_MODE_DPMS_SUSPEND:
		736	case DRM_MODE_DPMS_OFF:
		737	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		738	break;
		739	}
		740
		741	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		742
		743	if (rdev->is_atom_bios)
		744	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		745	else
		746	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	747
1123	serge	748	}
		749
		750	static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
		751	{
		752	struct radeon_device *rdev = encoder->dev->dev_private;
		753
		754	if (rdev->is_atom_bios)
		755	radeon_atom_output_lock(encoder, true);
		756	else
		757	radeon_combios_output_lock(encoder, true);
		758	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
		759	}
		760
		761	static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
		762	{
		763	struct radeon_device *rdev = encoder->dev->dev_private;
		764
		765	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
		766
		767	if (rdev->is_atom_bios)
		768	radeon_atom_output_lock(encoder, true);
		769	else
		770	radeon_combios_output_lock(encoder, true);
		771	}
		772
		773	static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
		774	struct drm_display_mode *mode,
		775	struct drm_display_mode *adjusted_mode)
		776	{
		777	struct drm_device *dev = encoder->dev;
		778	struct radeon_device *rdev = dev->dev_private;
		779	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		780	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		781	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
		782	int i;
		783
1963	serge	784	DRM_DEBUG_KMS("\n");
1123	serge	785
		786	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
		787	tmp &= 0xfffff;
		788	if (rdev->family == CHIP_RV280) {
		789	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
		790	tmp ^= (1 << 22);
		791	tmds_pll_cntl ^= (1 << 22);
		792	}
		793
		794	if (radeon_encoder->enc_priv) {
		795	struct radeon_encoder_int_tmds tmds = (struct radeon_encoder_int_tmds )radeon_encoder->enc_priv;
		796
		797	for (i = 0; i < 4; i++) {
		798	if (tmds->tmds_pll[i].freq == 0)
		799	break;
		800	if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
		801	tmp = tmds->tmds_pll[i].value ;
		802	break;
		803	}
		804	}
		805	}
		806
		807	if (ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV280)) {
		808	if (tmp & 0xfff00000)
		809	tmds_pll_cntl = tmp;
		810	else {
		811	tmds_pll_cntl &= 0xfff00000;
		812	tmds_pll_cntl \|= tmp;
		813	}
		814	} else
		815	tmds_pll_cntl = tmp;
		816
		817	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
		818	~(RADEON_TMDS_TRANSMITTER_PLLRST);
		819
		820	if (rdev->family == CHIP_R200 \|\|
		821	rdev->family == CHIP_R100 \|\|
		822	ASIC_IS_R300(rdev))
		823	tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
		824	else /* RV chips got this bit reversed */
		825	tmds_transmitter_cntl \|= RADEON_TMDS_TRANSMITTER_PLLEN;
		826
		827	fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) \|
		828	(RADEON_FP_CRTC_DONT_SHADOW_VPAR \|
		829	RADEON_FP_CRTC_DONT_SHADOW_HEND));
		830
		831	fp_gen_cntl &= ~(RADEON_FP_FPON \| RADEON_FP_TMDS_EN);
		832
1268	serge	833	fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN \|
		834	RADEON_FP_DFP_SYNC_SEL \|
		835	RADEON_FP_CRT_SYNC_SEL \|
		836	RADEON_FP_CRTC_LOCK_8DOT \|
		837	RADEON_FP_USE_SHADOW_EN \|
		838	RADEON_FP_CRTC_USE_SHADOW_VEND \|
		839	RADEON_FP_CRT_SYNC_ALT);
		840
1123	serge	841	if (1) /* FIXME rgbBits == 8 */
		842	fp_gen_cntl \|= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
		843	else
		844	fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
		845
		846	if (radeon_crtc->crtc_id == 0) {
		847	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		848	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1179	serge	849	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	850	fp_gen_cntl \|= R200_FP_SOURCE_SEL_RMX;
		851	else
		852	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC1;
		853	} else
1268	serge	854	fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
1123	serge	855	} else {
		856	if (ASIC_IS_R300(rdev) \|\| rdev->family == CHIP_R200) {
		857	fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
		858	fp_gen_cntl \|= R200_FP_SOURCE_SEL_CRTC2;
		859	} else
		860	fp_gen_cntl \|= RADEON_FP_SEL_CRTC2;
		861	}
		862
		863	WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
		864	WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
		865	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
		866
		867	if (rdev->is_atom_bios)
		868	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		869	else
		870	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		871	}
		872
		873	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
		874	.dpms = radeon_legacy_tmds_int_dpms,
1321	serge	875	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	876	.prepare = radeon_legacy_tmds_int_prepare,
		877	.mode_set = radeon_legacy_tmds_int_mode_set,
		878	.commit = radeon_legacy_tmds_int_commit,
1179	serge	879	.disable = radeon_legacy_encoder_disable,
1123	serge	880	};
		881
		882
		883	static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
		884	.destroy = radeon_enc_destroy,
		885	};
		886
		887	static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
		888	{
		889	struct drm_device *dev = encoder->dev;
		890	struct radeon_device *rdev = dev->dev_private;
		891	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1963	serge	892	DRM_DEBUG_KMS("\n");
1123	serge	893
		894	switch (mode) {
		895	case DRM_MODE_DPMS_ON:
		896	fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
		897	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		898	break;
		899	case DRM_MODE_DPMS_STANDBY:
		900	case DRM_MODE_DPMS_SUSPEND:
		901	case DRM_MODE_DPMS_OFF:
		902	fp2_gen_cntl \|= RADEON_FP2_BLANK_EN;
		903	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		904	break;
		905	}
		906
		907	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		908
		909	if (rdev->is_atom_bios)
		910	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		911	else
		912	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	913
1123	serge	914	}
		915
		916	static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
		917	{
		918	struct radeon_device *rdev = encoder->dev->dev_private;
		919
		920	if (rdev->is_atom_bios)
		921	radeon_atom_output_lock(encoder, true);
		922	else
		923	radeon_combios_output_lock(encoder, true);
		924	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
		925	}
		926
		927	static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
		928	{
		929	struct radeon_device *rdev = encoder->dev->dev_private;
		930	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
		931
		932	if (rdev->is_atom_bios)
		933	radeon_atom_output_lock(encoder, false);
		934	else
		935	radeon_combios_output_lock(encoder, false);
		936	}
		937
		938	static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
		939	struct drm_display_mode *mode,
		940	struct drm_display_mode *adjusted_mode)
		941	{
		942	struct drm_device *dev = encoder->dev;
		943	struct radeon_device *rdev = dev->dev_private;
		944	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		945	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		946	uint32_t fp2_gen_cntl;
		947
1963	serge	948	DRM_DEBUG_KMS("\n");
1123	serge	949
		950	if (rdev->is_atom_bios) {
		951	radeon_encoder->pixel_clock = adjusted_mode->clock;
1963	serge	952	atombios_dvo_setup(encoder, ATOM_ENABLE);
1123	serge	953	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		954	} else {
		955	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		956
		957	if (1) /* FIXME rgbBits == 8 */
		958	fp2_gen_cntl \|= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
		959	else
		960	fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
		961
		962	fp2_gen_cntl &= ~(RADEON_FP2_ON \|
		963	RADEON_FP2_DVO_EN \|
		964	RADEON_FP2_DVO_RATE_SEL_SDR);
		965
		966	/* XXX: these are oem specific */
		967	if (ASIC_IS_R300(rdev)) {
		968	if ((dev->pdev->device == 0x4850) &&
		969	(dev->pdev->subsystem_vendor == 0x1028) &&
		970	(dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
		971	fp2_gen_cntl \|= R300_FP2_DVO_CLOCK_MODE_SINGLE;
		972	else
		973	fp2_gen_cntl \|= RADEON_FP2_PAD_FLOP_EN \| R300_FP2_DVO_CLOCK_MODE_SINGLE;
		974
		975	/*if (mode->clock > 165000)
		976	fp2_gen_cntl \|= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
		977	}
1321	serge	978	if (!radeon_combios_external_tmds_setup(encoder))
		979	radeon_external_tmds_setup(encoder);
1123	serge	980	}
		981
		982	if (radeon_crtc->crtc_id == 0) {
		983	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		984	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1179	serge	985	if (radeon_encoder->rmx_type != RMX_OFF)
1123	serge	986	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_RMX;
		987	else
		988	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC1;
		989	} else
		990	fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
		991	} else {
		992	if ((rdev->family == CHIP_R200) \|\| ASIC_IS_R300(rdev)) {
		993	fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
		994	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		995	} else
		996	fp2_gen_cntl \|= RADEON_FP2_SRC_SEL_CRTC2;
		997	}
		998
		999	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1000
		1001	if (rdev->is_atom_bios)
		1002	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1003	else
		1004	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1005	}
		1006
1321	serge	1007	static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
		1008	{
		1009	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2997	Serge	1010	/* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1321	serge	1011	kfree(radeon_encoder->enc_priv);
		1012	drm_encoder_cleanup(encoder);
		1013	kfree(radeon_encoder);
		1014	}
		1015
1123	serge	1016	static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
		1017	.dpms = radeon_legacy_tmds_ext_dpms,
1321	serge	1018	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	1019	.prepare = radeon_legacy_tmds_ext_prepare,
		1020	.mode_set = radeon_legacy_tmds_ext_mode_set,
		1021	.commit = radeon_legacy_tmds_ext_commit,
1179	serge	1022	.disable = radeon_legacy_encoder_disable,
1123	serge	1023	};
		1024
		1025
		1026	static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1321	serge	1027	.destroy = radeon_ext_tmds_enc_destroy,
1123	serge	1028	};
		1029
		1030	static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
		1031	{
		1032	struct drm_device *dev = encoder->dev;
		1033	struct radeon_device *rdev = dev->dev_private;
1179	serge	1034	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1123	serge	1035	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1179	serge	1036	uint32_t tv_master_cntl = 0;
		1037	bool is_tv;
1963	serge	1038	DRM_DEBUG_KMS("\n");
1123	serge	1039
1179	serge	1040	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
		1041
1123	serge	1042	if (rdev->family == CHIP_R200)
		1043	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		1044	else {
1179	serge	1045	if (is_tv)
		1046	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1047	else
1123	serge	1048	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1049	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1050	}
		1051
		1052	switch (mode) {
		1053	case DRM_MODE_DPMS_ON:
		1054	if (rdev->family == CHIP_R200) {
		1055	fp2_gen_cntl \|= (RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		1056	} else {
1179	serge	1057	if (is_tv)
		1058	tv_master_cntl \|= RADEON_TV_ON;
		1059	else
1123	serge	1060	crtc2_gen_cntl \|= RADEON_CRTC2_CRT2_ON;
1179	serge	1061
1123	serge	1062	if (rdev->family == CHIP_R420 \|\|
		1063	rdev->family == CHIP_R423 \|\|
		1064	rdev->family == CHIP_RV410)
		1065	tv_dac_cntl &= ~(R420_TV_DAC_RDACPD \|
		1066	R420_TV_DAC_GDACPD \|
		1067	R420_TV_DAC_BDACPD \|
		1068	RADEON_TV_DAC_BGSLEEP);
		1069	else
		1070	tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD \|
		1071	RADEON_TV_DAC_GDACPD \|
		1072	RADEON_TV_DAC_BDACPD \|
		1073	RADEON_TV_DAC_BGSLEEP);
		1074	}
		1075	break;
		1076	case DRM_MODE_DPMS_STANDBY:
		1077	case DRM_MODE_DPMS_SUSPEND:
		1078	case DRM_MODE_DPMS_OFF:
		1079	if (rdev->family == CHIP_R200)
		1080	fp2_gen_cntl &= ~(RADEON_FP2_ON \| RADEON_FP2_DVO_EN);
		1081	else {
1179	serge	1082	if (is_tv)
		1083	tv_master_cntl &= ~RADEON_TV_ON;
		1084	else
1123	serge	1085	crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1179	serge	1086
1123	serge	1087	if (rdev->family == CHIP_R420 \|\|
		1088	rdev->family == CHIP_R423 \|\|
		1089	rdev->family == CHIP_RV410)
		1090	tv_dac_cntl \|= (R420_TV_DAC_RDACPD \|
		1091	R420_TV_DAC_GDACPD \|
		1092	R420_TV_DAC_BDACPD \|
		1093	RADEON_TV_DAC_BGSLEEP);
		1094	else
		1095	tv_dac_cntl \|= (RADEON_TV_DAC_RDACPD \|
		1096	RADEON_TV_DAC_GDACPD \|
		1097	RADEON_TV_DAC_BDACPD \|
		1098	RADEON_TV_DAC_BGSLEEP);
		1099	}
		1100	break;
		1101	}
		1102
		1103	if (rdev->family == CHIP_R200) {
		1104	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1105	} else {
1179	serge	1106	if (is_tv)
		1107	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
3120	serge	1108	/* handled in radeon_crtc_dpms() */
		1109	else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1123	serge	1110	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1111	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1112	}
		1113
		1114	if (rdev->is_atom_bios)
		1115	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		1116	else
		1117	radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1430	serge	1118
1123	serge	1119	}
		1120
		1121	static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
		1122	{
		1123	struct radeon_device *rdev = encoder->dev->dev_private;
		1124
		1125	if (rdev->is_atom_bios)
		1126	radeon_atom_output_lock(encoder, true);
		1127	else
		1128	radeon_combios_output_lock(encoder, true);
		1129	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
		1130	}
		1131
		1132	static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
		1133	{
		1134	struct radeon_device *rdev = encoder->dev->dev_private;
		1135
		1136	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
		1137
		1138	if (rdev->is_atom_bios)
		1139	radeon_atom_output_lock(encoder, true);
		1140	else
		1141	radeon_combios_output_lock(encoder, true);
		1142	}
		1143
		1144	static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
		1145	struct drm_display_mode *mode,
		1146	struct drm_display_mode *adjusted_mode)
		1147	{
		1148	struct drm_device *dev = encoder->dev;
		1149	struct radeon_device *rdev = dev->dev_private;
		1150	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1151	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1152	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1153	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1179	serge	1154	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
		1155	bool is_tv = false;
1123	serge	1156
1963	serge	1157	DRM_DEBUG_KMS("\n");
1123	serge	1158
1179	serge	1159	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1123	serge	1160
		1161	if (rdev->family != CHIP_R200) {
		1162	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1163	if (rdev->family == CHIP_R420 \|\|
		1164	rdev->family == CHIP_R423 \|\|
		1165	rdev->family == CHIP_RV410) {
		1166	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1167	RADEON_TV_DAC_BGADJ_MASK \|
		1168	R420_TV_DAC_DACADJ_MASK \|
		1169	R420_TV_DAC_RDACPD \|
		1170	R420_TV_DAC_GDACPD \|
1221	serge	1171	R420_TV_DAC_BDACPD \|
1123	serge	1172	R420_TV_DAC_TVENABLE);
		1173	} else {
		1174	tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK \|
		1175	RADEON_TV_DAC_BGADJ_MASK \|
		1176	RADEON_TV_DAC_DACADJ_MASK \|
		1177	RADEON_TV_DAC_RDACPD \|
		1178	RADEON_TV_DAC_GDACPD \|
1221	serge	1179	RADEON_TV_DAC_BDACPD);
1123	serge	1180	}
		1181
1963	serge	1182	tv_dac_cntl \|= RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD;
		1183
		1184	if (is_tv) {
		1185	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		1186	tv_dac->tv_std == TV_STD_NTSC_J \|\|
		1187	tv_dac->tv_std == TV_STD_PAL_M \|\|
		1188	tv_dac->tv_std == TV_STD_PAL_60)
		1189	tv_dac_cntl \|= tv_dac->ntsc_tvdac_adj;
		1190	else
		1191	tv_dac_cntl \|= tv_dac->pal_tvdac_adj;
		1192
		1193	if (tv_dac->tv_std == TV_STD_NTSC \|\|
		1194	tv_dac->tv_std == TV_STD_NTSC_J)
		1195	tv_dac_cntl \|= RADEON_TV_DAC_STD_NTSC;
		1196	else
		1197	tv_dac_cntl \|= RADEON_TV_DAC_STD_PAL;
		1198	} else
		1199	tv_dac_cntl \|= (RADEON_TV_DAC_STD_PS2 \|
1123	serge	1200	tv_dac->ps2_tvdac_adj);
		1201
		1202	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1203	}
		1204
		1205	if (ASIC_IS_R300(rdev)) {
		1206	gpiopad_a = RREG32(RADEON_GPIOPAD_A) \| 1;
		1207	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1963	serge	1208	} else if (rdev->family != CHIP_R200)
		1209	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1210	else if (rdev->family == CHIP_R200)
		1211	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1179	serge	1212
1963	serge	1213	if (rdev->family >= CHIP_R200)
1179	serge	1214	disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1123	serge	1215
1179	serge	1216	if (is_tv) {
		1217	uint32_t dac_cntl;
		1218
		1219	dac_cntl = RREG32(RADEON_DAC_CNTL);
		1220	dac_cntl &= ~RADEON_DAC_TVO_EN;
		1221	WREG32(RADEON_DAC_CNTL, dac_cntl);
		1222
		1223	if (ASIC_IS_R300(rdev))
		1224	gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
		1225
		1226	dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
		1227	if (radeon_crtc->crtc_id == 0) {
		1228	if (ASIC_IS_R300(rdev)) {
		1229	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1230	disp_output_cntl \|= (RADEON_DISP_TVDAC_SOURCE_CRTC \|
		1231	RADEON_DISP_TV_SOURCE_CRTC);
		1232	}
		1233	if (rdev->family >= CHIP_R200) {
		1234	disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
		1235	} else {
		1236	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1237	}
		1238	} else {
		1239	if (ASIC_IS_R300(rdev)) {
		1240	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1241	disp_output_cntl \|= RADEON_DISP_TV_SOURCE_CRTC;
		1242	}
		1243	if (rdev->family >= CHIP_R200) {
		1244	disp_tv_out_cntl \|= RADEON_DISP_TV_PATH_SRC_CRTC2;
		1245	} else {
		1246	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		1247	}
		1248	}
		1249	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		1250	} else {
		1251
1123	serge	1252	dac2_cntl = RREG32(RADEON_DAC_CNTL2) \| RADEON_DAC2_DAC2_CLK_SEL;
		1253
		1254	if (radeon_crtc->crtc_id == 0) {
		1255	if (ASIC_IS_R300(rdev)) {
		1256	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1257	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC;
		1258	} else if (rdev->family == CHIP_R200) {
		1259	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1260	RADEON_FP2_DVO_RATE_SEL_SDR);
		1261	} else
		1262	disp_hw_debug \|= RADEON_CRT2_DISP1_SEL;
		1263	} else {
		1264	if (ASIC_IS_R300(rdev)) {
		1265	disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1266	disp_output_cntl \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1267	} else if (rdev->family == CHIP_R200) {
		1268	fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK \|
		1269	RADEON_FP2_DVO_RATE_SEL_SDR);
		1270	fp2_gen_cntl \|= R200_FP2_SOURCE_SEL_CRTC2;
		1271	} else
		1272	disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
		1273	}
		1274	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1179	serge	1275	}
1123	serge	1276
		1277	if (ASIC_IS_R300(rdev)) {
		1278	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1179	serge	1279	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1963	serge	1280	} else if (rdev->family != CHIP_R200)
		1281	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1282	else if (rdev->family == CHIP_R200)
		1283	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1179	serge	1284
		1285	if (rdev->family >= CHIP_R200)
		1286	WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1123	serge	1287
1179	serge	1288	if (is_tv)
		1289	radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
		1290
1123	serge	1291	if (rdev->is_atom_bios)
		1292	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1293	else
		1294	radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1295
		1296	}
		1297
1179	serge	1298	static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
		1299	struct drm_connector *connector)
		1300	{
		1301	struct drm_device *dev = encoder->dev;
		1302	struct radeon_device *rdev = dev->dev_private;
		1303	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1304	uint32_t disp_output_cntl, gpiopad_a, tmp;
		1305	bool found = false;
		1306
		1307	/* save regs needed */
		1308	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
		1309	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1310	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1311	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1312	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1313	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1314
		1315	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
		1316
		1317	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
		1318
		1319	WREG32(RADEON_CRTC2_GEN_CNTL,
		1320	RADEON_CRTC2_CRT2_ON \| RADEON_CRTC2_VSYNC_TRISTAT);
		1321
		1322	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1323	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1324	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1325
		1326	WREG32(RADEON_DAC_EXT_CNTL,
		1327	RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1328	RADEON_DAC2_FORCE_DATA_EN \|
		1329	RADEON_DAC_FORCE_DATA_SEL_RGB \|
		1330	(0xec << RADEON_DAC_FORCE_DATA_SHIFT));
		1331
		1332	WREG32(RADEON_TV_DAC_CNTL,
		1333	RADEON_TV_DAC_STD_NTSC \|
		1334	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1335	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1336
		1337	RREG32(RADEON_TV_DAC_CNTL);
		1338	mdelay(4);
		1339
		1340	WREG32(RADEON_TV_DAC_CNTL,
		1341	RADEON_TV_DAC_NBLANK \|
		1342	RADEON_TV_DAC_NHOLD \|
		1343	RADEON_TV_MONITOR_DETECT_EN \|
		1344	RADEON_TV_DAC_STD_NTSC \|
		1345	(8 << RADEON_TV_DAC_BGADJ_SHIFT) \|
		1346	(6 << RADEON_TV_DAC_DACADJ_SHIFT));
		1347
		1348	RREG32(RADEON_TV_DAC_CNTL);
		1349	mdelay(6);
		1350
		1351	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1352	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
		1353	found = true;
1963	serge	1354	DRM_DEBUG_KMS("S-video TV connection detected\n");
1179	serge	1355	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1356	found = true;
1963	serge	1357	DRM_DEBUG_KMS("Composite TV connection detected\n");
1179	serge	1358	}
		1359
		1360	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1361	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1362	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1363	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1364	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1365	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1366	return found;
		1367	}
		1368
		1369	static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
		1370	struct drm_connector *connector)
		1371	{
		1372	struct drm_device *dev = encoder->dev;
		1373	struct radeon_device *rdev = dev->dev_private;
		1374	uint32_t tv_dac_cntl, dac_cntl2;
		1375	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
		1376	bool found = false;
		1377
		1378	if (ASIC_IS_R300(rdev))
		1379	return r300_legacy_tv_detect(encoder, connector);
		1380
		1381	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1382	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
		1383	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1384	config_cntl = RREG32(RADEON_CONFIG_CNTL);
		1385	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
		1386
		1387	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
		1388	WREG32(RADEON_DAC_CNTL2, tmp);
		1389
		1390	tmp = tv_master_cntl \| RADEON_TV_ON;
		1391	tmp &= ~(RADEON_TV_ASYNC_RST \|
		1392	RADEON_RESTART_PHASE_FIX \|
		1393	RADEON_CRT_FIFO_CE_EN \|
		1394	RADEON_TV_FIFO_CE_EN \|
		1395	RADEON_RE_SYNC_NOW_SEL_MASK);
		1396	tmp \|= RADEON_TV_FIFO_ASYNC_RST \| RADEON_CRT_ASYNC_RST;
		1397	WREG32(RADEON_TV_MASTER_CNTL, tmp);
		1398
		1399	tmp = RADEON_TV_DAC_NBLANK \| RADEON_TV_DAC_NHOLD \|
		1400	RADEON_TV_MONITOR_DETECT_EN \| RADEON_TV_DAC_STD_NTSC \|
		1401	(8 << RADEON_TV_DAC_BGADJ_SHIFT);
		1402
		1403	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
		1404	tmp \|= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
		1405	else
		1406	tmp \|= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
		1407	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1408
		1409	tmp = RADEON_C_GRN_EN \| RADEON_CMP_BLU_EN \|
		1410	RADEON_RED_MX_FORCE_DAC_DATA \|
		1411	RADEON_GRN_MX_FORCE_DAC_DATA \|
		1412	RADEON_BLU_MX_FORCE_DAC_DATA \|
		1413	(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
		1414	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
		1415
		1416	mdelay(3);
		1417	tmp = RREG32(RADEON_TV_DAC_CNTL);
		1418	if (tmp & RADEON_TV_DAC_GDACDET) {
		1419	found = true;
1963	serge	1420	DRM_DEBUG_KMS("S-video TV connection detected\n");
1179	serge	1421	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
		1422	found = true;
1963	serge	1423	DRM_DEBUG_KMS("Composite TV connection detected\n");
1179	serge	1424	}
		1425
		1426	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
		1427	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
		1428	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
		1429	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1430	return found;
		1431	}
		1432
3120	serge	1433	static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
		1434	struct drm_connector *connector)
		1435	{
		1436	struct drm_device *dev = encoder->dev;
		1437	struct radeon_device *rdev = dev->dev_private;
		1438	uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
		1439	uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
		1440	uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
		1441	uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
		1442	uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
		1443	bool found = false;
		1444	int i;
		1445
		1446	/* save the regs we need */
		1447	gpio_monid = RREG32(RADEON_GPIO_MONID);
		1448	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
		1449	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1450	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
		1451	disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
		1452	disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
		1453	disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
		1454	disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
		1455	disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
		1456	disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
		1457	crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
		1458	crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
		1459	crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
		1460	crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
		1461
		1462	tmp = RREG32(RADEON_GPIO_MONID);
		1463	tmp &= ~RADEON_GPIO_A_0;
		1464	WREG32(RADEON_GPIO_MONID, tmp);
		1465
		1466	WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON \|
		1467	RADEON_FP2_PANEL_FORMAT \|
		1468	R200_FP2_SOURCE_SEL_TRANS_UNIT \|
		1469	RADEON_FP2_DVO_EN \|
		1470	R200_FP2_DVO_RATE_SEL_SDR));
		1471
		1472	WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX \|
		1473	RADEON_DISP_TRANS_MATRIX_GRAPHICS));
		1474
		1475	WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN \|
		1476	RADEON_CRTC2_DISP_REQ_EN_B));
		1477
		1478	WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
		1479	WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
		1480	WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
		1481	WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
		1482	WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
		1483	WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
		1484
		1485	WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
		1486	WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
		1487	WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
		1488	WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
		1489
		1490	for (i = 0; i < 200; i++) {
		1491	tmp = RREG32(RADEON_GPIO_MONID);
		1492	if (tmp & RADEON_GPIO_Y_0)
		1493	found = true;
		1494
		1495	if (found)
		1496	break;
		1497
		1498	msleep(1);
		1499	}
		1500
		1501	/* restore the regs we used */
		1502	WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
		1503	WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
		1504	WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
		1505	WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
		1506	WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
		1507	WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
		1508	WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
		1509	WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
		1510	WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
		1511	WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
		1512	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1513	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1514	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
		1515	WREG32(RADEON_GPIO_MONID, gpio_monid);
		1516
		1517	return found;
		1518	}
		1519
1123	serge	1520	static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
		1521	struct drm_connector *connector)
		1522	{
		1523	struct drm_device *dev = encoder->dev;
		1524	struct radeon_device *rdev = dev->dev_private;
3120	serge	1525	uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
		1526	uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
		1527	uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1123	serge	1528	enum drm_connector_status found = connector_status_disconnected;
1179	serge	1529	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1530	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1123	serge	1531	bool color = true;
1963	serge	1532	struct drm_crtc *crtc;
1123	serge	1533
1963	serge	1534	/* find out if crtc2 is in use or if this encoder is using it */
		1535	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		1536	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		1537	if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
		1538	if (encoder->crtc != crtc) {
		1539	return connector_status_disconnected;
		1540	}
		1541	}
		1542	}
		1543
1179	serge	1544	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO \|\|
		1545	connector->connector_type == DRM_MODE_CONNECTOR_Composite \|\|
		1546	connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
		1547	bool tv_detect;
1123	serge	1548
1179	serge	1549	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
		1550	return connector_status_disconnected;
		1551
		1552	tv_detect = radeon_legacy_tv_detect(encoder, connector);
		1553	if (tv_detect && tv_dac)
		1554	found = connector_status_connected;
		1555	return found;
		1556	}
		1557
		1558	/* don't probe if the encoder is being used for something else not CRT related */
		1559	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
		1560	DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
		1561	return connector_status_disconnected;
		1562	}
		1563
3120	serge	1564	/* R200 uses an external DAC for secondary DAC */
		1565	if (rdev->family == CHIP_R200) {
		1566	if (radeon_legacy_ext_dac_detect(encoder, connector))
		1567	found = connector_status_connected;
		1568	return found;
		1569	}
		1570
1123	serge	1571	/* save the regs we need */
		1572	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
3120	serge	1573
		1574	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1575	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
		1576	} else {
		1577	if (ASIC_IS_R300(rdev)) {
		1578	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
		1579	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
		1580	} else {
		1581	disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
		1582	}
1123	serge	1583	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
3120	serge	1584	}
1123	serge	1585	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
		1586	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
		1587	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
		1588
		1589	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
		1590	\| RADEON_PIX2CLK_DAC_ALWAYS_ONb);
		1591	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
		1592
3120	serge	1593	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1594	tmp = crtc_ext_cntl \| RADEON_CRTC_CRT_ON;
		1595	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
		1596	} else {
1123	serge	1597	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
		1598	tmp \|= RADEON_CRTC2_CRT2_ON \|
		1599	(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
		1600	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
		1601
		1602	if (ASIC_IS_R300(rdev)) {
3120	serge	1603	WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1123	serge	1604	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
		1605	tmp \|= RADEON_DISP_TVDAC_SOURCE_CRTC2;
		1606	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
		1607	} else {
		1608	tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
		1609	WREG32(RADEON_DISP_HW_DEBUG, tmp);
		1610	}
3120	serge	1611	}
1123	serge	1612
		1613	tmp = RADEON_TV_DAC_NBLANK \|
		1614	RADEON_TV_DAC_NHOLD \|
		1615	RADEON_TV_MONITOR_DETECT_EN \|
		1616	RADEON_TV_DAC_STD_PS2;
		1617
		1618	WREG32(RADEON_TV_DAC_CNTL, tmp);
		1619
		1620	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN \|
		1621	RADEON_DAC2_FORCE_DATA_EN;
		1622
		1623	if (color)
		1624	tmp \|= RADEON_DAC_FORCE_DATA_SEL_RGB;
		1625	else
		1626	tmp \|= RADEON_DAC_FORCE_DATA_SEL_G;
		1627
		1628	if (ASIC_IS_R300(rdev))
		1629	tmp \|= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
		1630	else
		1631	tmp \|= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
		1632
		1633	WREG32(RADEON_DAC_EXT_CNTL, tmp);
		1634
		1635	tmp = dac_cntl2 \| RADEON_DAC2_DAC2_CLK_SEL \| RADEON_DAC2_CMP_EN;
		1636	WREG32(RADEON_DAC_CNTL2, tmp);
		1637
2997	Serge	1638	mdelay(10);
1123	serge	1639
		1640	if (ASIC_IS_R300(rdev)) {
		1641	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
		1642	found = connector_status_connected;
		1643	} else {
		1644	if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
		1645	found = connector_status_connected;
		1646	}
		1647
		1648	/* restore regs we used */
		1649	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
		1650	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
		1651	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
3120	serge	1652
		1653	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1654	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
		1655	} else {
1123	serge	1656	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
		1657	if (ASIC_IS_R300(rdev)) {
		1658	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
		1659	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
		1660	} else {
		1661	WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
		1662	}
3120	serge	1663	}
		1664
1123	serge	1665	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
		1666
1179	serge	1667	return found;
1123	serge	1668
		1669	}
		1670
		1671	static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
		1672	.dpms = radeon_legacy_tv_dac_dpms,
1321	serge	1673	.mode_fixup = radeon_legacy_mode_fixup,
1123	serge	1674	.prepare = radeon_legacy_tv_dac_prepare,
		1675	.mode_set = radeon_legacy_tv_dac_mode_set,
		1676	.commit = radeon_legacy_tv_dac_commit,
		1677	.detect = radeon_legacy_tv_dac_detect,
1179	serge	1678	.disable = radeon_legacy_encoder_disable,
1123	serge	1679	};
		1680
		1681
		1682	static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
		1683	.destroy = radeon_enc_destroy,
		1684	};
		1685
1179	serge	1686
		1687	static struct radeon_encoder_int_tmds radeon_legacy_get_tmds_info(struct radeon_encoder encoder)
		1688	{
		1689	struct drm_device *dev = encoder->base.dev;
		1690	struct radeon_device *rdev = dev->dev_private;
		1691	struct radeon_encoder_int_tmds *tmds = NULL;
		1692	bool ret;
		1693
		1694	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
		1695
		1696	if (!tmds)
		1697	return NULL;
		1698
		1699	if (rdev->is_atom_bios)
		1700	ret = radeon_atombios_get_tmds_info(encoder, tmds);
		1701	else
		1702	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
		1703
		1704	if (ret == false)
		1705	radeon_legacy_get_tmds_info_from_table(encoder, tmds);
		1706
		1707	return tmds;
		1708	}
		1709
1321	serge	1710	static struct radeon_encoder_ext_tmds radeon_legacy_get_ext_tmds_info(struct radeon_encoder encoder)
		1711	{
		1712	struct drm_device *dev = encoder->base.dev;
		1713	struct radeon_device *rdev = dev->dev_private;
		1714	struct radeon_encoder_ext_tmds *tmds = NULL;
		1715	bool ret;
		1716
		1717	if (rdev->is_atom_bios)
		1718	return NULL;
		1719
		1720	tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
		1721
		1722	if (!tmds)
		1723	return NULL;
		1724
		1725	ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
		1726
		1727	if (ret == false)
		1728	radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
		1729
		1730	return tmds;
		1731	}
		1732
1123	serge	1733	void
1963	serge	1734	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1123	serge	1735	{
		1736	struct radeon_device *rdev = dev->dev_private;
		1737	struct drm_encoder *encoder;
		1738	struct radeon_encoder *radeon_encoder;
		1739
		1740	/* see if we already added it */
		1741	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1742	radeon_encoder = to_radeon_encoder(encoder);
1963	serge	1743	if (radeon_encoder->encoder_enum == encoder_enum) {
1123	serge	1744	radeon_encoder->devices \|= supported_device;
		1745	return;
		1746	}
		1747
		1748	}
		1749
		1750	/* add a new one */
		1751	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1752	if (!radeon_encoder)
		1753	return;
		1754
		1755	encoder = &radeon_encoder->base;
1221	serge	1756	if (rdev->flags & RADEON_SINGLE_CRTC)
		1757	encoder->possible_crtcs = 0x1;
		1758	else
1123	serge	1759	encoder->possible_crtcs = 0x3;
		1760
		1761	radeon_encoder->enc_priv = NULL;
		1762
1963	serge	1763	radeon_encoder->encoder_enum = encoder_enum;
		1764	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1123	serge	1765	radeon_encoder->devices = supported_device;
1179	serge	1766	radeon_encoder->rmx_type = RMX_OFF;
1123	serge	1767
		1768	switch (radeon_encoder->encoder_id) {
		1769	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1179	serge	1770	encoder->possible_crtcs = 0x1;
1123	serge	1771	drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1772	drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
		1773	if (rdev->is_atom_bios)
		1774	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1775	else
		1776	radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
		1777	radeon_encoder->rmx_type = RMX_FULL;
		1778	break;
		1779	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1780	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1781	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1179	serge	1782	radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1123	serge	1783	break;
		1784	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1785	drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
		1786	drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
		1787	if (rdev->is_atom_bios)
		1788	radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
		1789	else
		1790	radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
		1791	break;
		1792	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1793	drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1794	drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
		1795	if (rdev->is_atom_bios)
		1796	radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
		1797	else
		1798	radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
		1799	break;
		1800	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1801	drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1802	drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
		1803	if (!rdev->is_atom_bios)
1321	serge	1804	radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1123	serge	1805	break;
		1806	}
		1807	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_legacy_encoders.c @ 6104 – Rev 3764