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Rev | Author | Line No. | Line |
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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1179 | serge | 26 | #include |
27 | #include |
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28 | #include |
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1963 | serge | 29 | #include |
1123 | serge | 30 | #include "radeon.h" |
1179 | serge | 31 | #include "atom.h" |
1123 | serge | 32 | |
1321 | serge | 33 | static void radeon_overscan_setup(struct drm_crtc *crtc, |
34 | struct drm_display_mode *mode) |
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35 | { |
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36 | struct drm_device *dev = crtc->dev; |
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37 | struct radeon_device *rdev = dev->dev_private; |
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38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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39 | |||
40 | WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); |
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41 | WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); |
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42 | WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); |
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43 | } |
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44 | |||
1179 | serge | 45 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
1404 | serge | 46 | struct drm_display_mode *mode) |
1179 | serge | 47 | { |
48 | struct drm_device *dev = crtc->dev; |
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49 | struct radeon_device *rdev = dev->dev_private; |
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50 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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51 | int xres = mode->hdisplay; |
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52 | int yres = mode->vdisplay; |
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53 | bool hscale = true, vscale = true; |
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54 | int hsync_wid; |
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55 | int vsync_wid; |
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56 | int hsync_start; |
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57 | int blank_width; |
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58 | u32 scale, inc, crtc_more_cntl; |
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59 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
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60 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
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61 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
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1268 | serge | 62 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
1179 | serge | 63 | |
64 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
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65 | (RADEON_VERT_STRETCH_RESERVED | |
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66 | RADEON_VERT_AUTO_RATIO_INC); |
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67 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
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68 | (RADEON_HORZ_FP_LOOP_STRETCH | |
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69 | RADEON_HORZ_AUTO_RATIO_INC); |
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70 | |||
71 | crtc_more_cntl = 0; |
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72 | if ((rdev->family == CHIP_RS100) || |
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73 | (rdev->family == CHIP_RS200)) { |
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74 | /* This is to workaround the asic bug for RMX, some versions |
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75 | of BIOS dosen't have this register initialized correctly. */ |
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76 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
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77 | } |
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78 | |||
79 | |||
80 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
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81 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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82 | |||
83 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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84 | if (!hsync_wid) |
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85 | hsync_wid = 1; |
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86 | hsync_start = mode->crtc_hsync_start - 8; |
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87 | |||
88 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
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89 | | ((hsync_wid & 0x3f) << 16) |
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90 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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91 | ? RADEON_CRTC_H_SYNC_POL |
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92 | : 0)); |
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93 | |||
94 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
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95 | | ((mode->crtc_vdisplay - 1) << 16)); |
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96 | |||
97 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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98 | if (!vsync_wid) |
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99 | vsync_wid = 1; |
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100 | |||
101 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
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102 | | ((vsync_wid & 0x1f) << 16) |
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103 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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104 | ? RADEON_CRTC_V_SYNC_POL |
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105 | : 0)); |
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106 | |||
107 | fp_horz_vert_active = 0; |
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108 | |||
1268 | serge | 109 | if (native_mode->hdisplay == 0 || |
110 | native_mode->vdisplay == 0) { |
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1179 | serge | 111 | hscale = false; |
112 | vscale = false; |
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113 | } else { |
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1268 | serge | 114 | if (xres > native_mode->hdisplay) |
115 | xres = native_mode->hdisplay; |
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116 | if (yres > native_mode->vdisplay) |
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117 | yres = native_mode->vdisplay; |
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1179 | serge | 118 | |
1268 | serge | 119 | if (xres == native_mode->hdisplay) |
1179 | serge | 120 | hscale = false; |
1268 | serge | 121 | if (yres == native_mode->vdisplay) |
1179 | serge | 122 | vscale = false; |
123 | } |
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124 | |||
125 | switch (radeon_crtc->rmx_type) { |
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126 | case RMX_FULL: |
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127 | case RMX_ASPECT: |
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128 | if (!hscale) |
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129 | fp_horz_stretch |= ((xres/8-1) << 16); |
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130 | else { |
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131 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
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132 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
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1268 | serge | 133 | / native_mode->hdisplay + 1; |
1179 | serge | 134 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
135 | RADEON_HORZ_STRETCH_BLEND | |
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136 | RADEON_HORZ_STRETCH_ENABLE | |
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1268 | serge | 137 | ((native_mode->hdisplay/8-1) << 16)); |
1179 | serge | 138 | } |
139 | |||
140 | if (!vscale) |
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141 | fp_vert_stretch |= ((yres-1) << 12); |
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142 | else { |
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143 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
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144 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
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1268 | serge | 145 | / native_mode->vdisplay + 1; |
1179 | serge | 146 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
147 | RADEON_VERT_STRETCH_ENABLE | |
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148 | RADEON_VERT_STRETCH_BLEND | |
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1268 | serge | 149 | ((native_mode->vdisplay-1) << 12)); |
1179 | serge | 150 | } |
151 | break; |
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152 | case RMX_CENTER: |
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153 | fp_horz_stretch |= ((xres/8-1) << 16); |
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154 | fp_vert_stretch |= ((yres-1) << 12); |
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155 | |||
156 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
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157 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
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158 | |||
159 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
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160 | if (blank_width > 110) |
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161 | blank_width = 110; |
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162 | |||
163 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
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164 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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165 | |||
166 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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167 | if (!hsync_wid) |
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168 | hsync_wid = 1; |
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169 | |||
170 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
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171 | | ((hsync_wid & 0x3f) << 16) |
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172 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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173 | ? RADEON_CRTC_H_SYNC_POL |
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174 | : 0)); |
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175 | |||
176 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
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177 | | ((mode->crtc_vdisplay - 1) << 16)); |
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178 | |||
179 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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180 | if (!vsync_wid) |
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181 | vsync_wid = 1; |
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182 | |||
183 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
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184 | | ((vsync_wid & 0x1f) << 16) |
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185 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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186 | ? RADEON_CRTC_V_SYNC_POL |
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187 | : 0))); |
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188 | |||
1268 | serge | 189 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
190 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
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1179 | serge | 191 | break; |
192 | case RMX_OFF: |
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193 | default: |
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194 | fp_horz_stretch |= ((xres/8-1) << 16); |
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195 | fp_vert_stretch |= ((yres-1) << 12); |
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196 | break; |
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197 | } |
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198 | |||
199 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
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200 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
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201 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
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202 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
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203 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
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204 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
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205 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
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206 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
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207 | } |
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208 | |||
1123 | serge | 209 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
210 | { |
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211 | struct radeon_device *rdev = dev->dev_private; |
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212 | int i = 0; |
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213 | |||
214 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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215 | the cause yet, but this workaround will mask the problem for now. |
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216 | Other chips usually will pass at the very first test, so the |
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217 | workaround shouldn't have any effect on them. */ |
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218 | for (i = 0; |
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219 | (i < 10000 && |
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220 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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221 | i++); |
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222 | } |
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223 | |||
224 | static void radeon_pll_write_update(struct drm_device *dev) |
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225 | { |
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226 | struct radeon_device *rdev = dev->dev_private; |
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227 | |||
228 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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229 | |||
230 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
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231 | RADEON_PPLL_ATOMIC_UPDATE_W, |
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232 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
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233 | } |
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234 | |||
235 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
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236 | { |
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237 | struct radeon_device *rdev = dev->dev_private; |
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238 | int i = 0; |
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239 | |||
240 | |||
241 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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242 | the cause yet, but this workaround will mask the problem for now. |
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243 | Other chips usually will pass at the very first test, so the |
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244 | workaround shouldn't have any effect on them. */ |
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245 | for (i = 0; |
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246 | (i < 10000 && |
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247 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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248 | i++); |
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249 | } |
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250 | |||
251 | static void radeon_pll2_write_update(struct drm_device *dev) |
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252 | { |
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253 | struct radeon_device *rdev = dev->dev_private; |
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254 | |||
255 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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256 | |||
257 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
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258 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
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259 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
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260 | } |
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261 | |||
262 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
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263 | uint16_t fb_div) |
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264 | { |
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265 | unsigned int vcoFreq; |
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266 | |||
267 | if (!ref_div) |
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268 | return 1; |
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269 | |||
1963 | serge | 270 | vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; |
1123 | serge | 271 | |
272 | /* |
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273 | * This is horribly crude: the VCO frequency range is divided into |
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274 | * 3 parts, each part having a fixed PLL gain value. |
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275 | */ |
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276 | if (vcoFreq >= 30000) |
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277 | /* |
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278 | * [300..max] MHz : 7 |
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279 | */ |
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280 | return 7; |
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281 | else if (vcoFreq >= 18000) |
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282 | /* |
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283 | * [180..300) MHz : 4 |
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284 | */ |
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285 | return 4; |
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286 | else |
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287 | /* |
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288 | * [0..180) MHz : 1 |
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289 | */ |
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290 | return 1; |
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291 | } |
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292 | |||
2997 | Serge | 293 | static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
1123 | serge | 294 | { |
295 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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296 | struct drm_device *dev = crtc->dev; |
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297 | struct radeon_device *rdev = dev->dev_private; |
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298 | uint32_t mask; |
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299 | |||
300 | if (radeon_crtc->crtc_id) |
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1321 | serge | 301 | mask = (RADEON_CRTC2_DISP_DIS | |
1123 | serge | 302 | RADEON_CRTC2_VSYNC_DIS | |
303 | RADEON_CRTC2_HSYNC_DIS | |
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304 | RADEON_CRTC2_DISP_REQ_EN_B); |
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305 | else |
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306 | mask = (RADEON_CRTC_DISPLAY_DIS | |
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307 | RADEON_CRTC_VSYNC_DIS | |
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308 | RADEON_CRTC_HSYNC_DIS); |
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309 | |||
310 | switch (mode) { |
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311 | case DRM_MODE_DPMS_ON: |
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1963 | serge | 312 | radeon_crtc->enabled = true; |
313 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
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314 | radeon_pm_compute_clocks(rdev); |
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1123 | serge | 315 | if (radeon_crtc->crtc_id) |
1321 | serge | 316 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
1123 | serge | 317 | else { |
318 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
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319 | RADEON_CRTC_DISP_REQ_EN_B)); |
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320 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
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321 | } |
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1430 | serge | 322 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
1179 | serge | 323 | radeon_crtc_load_lut(crtc); |
1123 | serge | 324 | break; |
325 | case DRM_MODE_DPMS_STANDBY: |
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326 | case DRM_MODE_DPMS_SUSPEND: |
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327 | case DRM_MODE_DPMS_OFF: |
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1430 | serge | 328 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
1123 | serge | 329 | if (radeon_crtc->crtc_id) |
1321 | serge | 330 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
1123 | serge | 331 | else { |
332 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
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333 | RADEON_CRTC_DISP_REQ_EN_B)); |
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334 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
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335 | } |
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1963 | serge | 336 | radeon_crtc->enabled = false; |
337 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
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338 | radeon_pm_compute_clocks(rdev); |
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1123 | serge | 339 | break; |
340 | } |
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341 | } |
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342 | |||
343 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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344 | struct drm_framebuffer *old_fb) |
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345 | { |
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1963 | serge | 346 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
347 | } |
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348 | |||
349 | int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
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350 | struct drm_framebuffer *fb, |
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351 | int x, int y, enum mode_set_atomic state) |
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352 | { |
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353 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
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354 | } |
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355 | |||
356 | int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
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357 | struct drm_framebuffer *fb, |
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358 | int x, int y, int atomic) |
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359 | { |
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1123 | serge | 360 | struct drm_device *dev = crtc->dev; |
361 | struct radeon_device *rdev = dev->dev_private; |
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362 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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363 | struct radeon_framebuffer *radeon_fb; |
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1963 | serge | 364 | struct drm_framebuffer *target_fb; |
1123 | serge | 365 | struct drm_gem_object *obj; |
1321 | serge | 366 | struct radeon_bo *rbo; |
1123 | serge | 367 | uint64_t base; |
368 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
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369 | uint32_t crtc_pitch, pitch_pixels; |
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1179 | serge | 370 | uint32_t tiling_flags; |
371 | int format; |
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372 | uint32_t gen_cntl_reg, gen_cntl_val; |
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1321 | serge | 373 | int r; |
1123 | serge | 374 | |
1963 | serge | 375 | DRM_DEBUG_KMS("\n"); |
1321 | serge | 376 | /* no fb bound */ |
1963 | serge | 377 | if (!atomic && !crtc->fb) { |
378 | DRM_DEBUG_KMS("No FB bound\n"); |
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1321 | serge | 379 | return 0; |
380 | } |
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1123 | serge | 381 | |
1963 | serge | 382 | if (atomic) { |
383 | radeon_fb = to_radeon_framebuffer(fb); |
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384 | target_fb = fb; |
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385 | } |
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386 | else { |
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1123 | serge | 387 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1963 | serge | 388 | target_fb = crtc->fb; |
389 | } |
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1123 | serge | 390 | |
1963 | serge | 391 | switch (target_fb->bits_per_pixel) { |
1179 | serge | 392 | case 8: |
393 | format = 2; |
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394 | break; |
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395 | case 15: /* 555 */ |
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396 | format = 3; |
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397 | break; |
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398 | case 16: /* 565 */ |
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399 | format = 4; |
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400 | break; |
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401 | case 24: /* RGB */ |
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402 | format = 5; |
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403 | break; |
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404 | case 32: /* xRGB */ |
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405 | format = 6; |
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406 | break; |
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407 | default: |
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408 | return false; |
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409 | } |
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410 | |||
1321 | serge | 411 | /* Pin framebuffer & get tilling informations */ |
1123 | serge | 412 | obj = radeon_fb->obj; |
1963 | serge | 413 | rbo = gem_to_radeon_bo(obj); |
1321 | serge | 414 | r = radeon_bo_reserve(rbo, false); |
415 | if (unlikely(r != 0)) |
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416 | return r; |
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2997 | Serge | 417 | /* Only 27 bit offset for legacy CRTC */ |
1321 | serge | 418 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base); |
419 | if (unlikely(r != 0)) { |
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420 | radeon_bo_unreserve(rbo); |
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421 | return -EINVAL; |
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422 | } |
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423 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
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424 | radeon_bo_unreserve(rbo); |
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425 | if (tiling_flags & RADEON_TILING_MICRO) |
||
426 | DRM_ERROR("trying to scanout microtiled buffer\n"); |
||
1246 | serge | 427 | |
1179 | serge | 428 | /* if scanout was in GTT this really wouldn't work */ |
429 | /* crtc offset is from display base addr not FB location */ |
||
1430 | serge | 430 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; |
1179 | serge | 431 | |
432 | base -= radeon_crtc->legacy_display_base_addr; |
||
433 | |||
1123 | serge | 434 | crtc_offset_cntl = 0; |
435 | |||
2997 | Serge | 436 | pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
1963 | serge | 437 | crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + |
438 | ((target_fb->bits_per_pixel * 8) - 1)) / |
||
439 | (target_fb->bits_per_pixel * 8)); |
||
1123 | serge | 440 | crtc_pitch |= crtc_pitch << 16; |
441 | |||
1963 | serge | 442 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; |
1179 | serge | 443 | if (tiling_flags & RADEON_TILING_MACRO) { |
1123 | serge | 444 | if (ASIC_IS_R300(rdev)) |
445 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
||
446 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
447 | R300_CRTC_MACRO_TILE_EN); |
||
448 | else |
||
449 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
||
450 | } else { |
||
451 | if (ASIC_IS_R300(rdev)) |
||
452 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
||
453 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
454 | R300_CRTC_MACRO_TILE_EN); |
||
455 | else |
||
456 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
||
457 | } |
||
458 | |||
1179 | serge | 459 | if (tiling_flags & RADEON_TILING_MACRO) { |
1123 | serge | 460 | if (ASIC_IS_R300(rdev)) { |
461 | crtc_tile_x0_y0 = x | (y << 16); |
||
462 | base &= ~0x7ff; |
||
463 | } else { |
||
1963 | serge | 464 | int byteshift = target_fb->bits_per_pixel >> 4; |
1179 | serge | 465 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
1123 | serge | 466 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
467 | crtc_offset_cntl |= (y % 16); |
||
468 | } |
||
469 | } else { |
||
470 | int offset = y * pitch_pixels + x; |
||
1963 | serge | 471 | switch (target_fb->bits_per_pixel) { |
1179 | serge | 472 | case 8: |
473 | offset *= 1; |
||
474 | break; |
||
1123 | serge | 475 | case 15: |
476 | case 16: |
||
477 | offset *= 2; |
||
478 | break; |
||
479 | case 24: |
||
480 | offset *= 3; |
||
481 | break; |
||
482 | case 32: |
||
483 | offset *= 4; |
||
484 | break; |
||
485 | default: |
||
486 | return false; |
||
487 | } |
||
488 | base += offset; |
||
489 | } |
||
490 | |||
491 | base &= ~7; |
||
492 | |||
1179 | serge | 493 | if (radeon_crtc->crtc_id == 1) |
494 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
||
495 | else |
||
496 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
||
1123 | serge | 497 | |
1179 | serge | 498 | gen_cntl_val = RREG32(gen_cntl_reg); |
499 | gen_cntl_val &= ~(0xf << 8); |
||
500 | gen_cntl_val |= (format << 8); |
||
1963 | serge | 501 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; |
1179 | serge | 502 | WREG32(gen_cntl_reg, gen_cntl_val); |
503 | |||
1123 | serge | 504 | crtc_offset = (u32)base; |
505 | |||
1179 | serge | 506 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
1123 | serge | 507 | |
508 | if (ASIC_IS_R300(rdev)) { |
||
509 | if (radeon_crtc->crtc_id) |
||
510 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
||
511 | else |
||
512 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
||
513 | } |
||
514 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
||
515 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
||
516 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
||
517 | |||
1963 | serge | 518 | if (!atomic && fb && fb != crtc->fb) { |
519 | radeon_fb = to_radeon_framebuffer(fb); |
||
520 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
||
1321 | serge | 521 | r = radeon_bo_reserve(rbo, false); |
522 | if (unlikely(r != 0)) |
||
523 | return r; |
||
524 | radeon_bo_unpin(rbo); |
||
525 | radeon_bo_unreserve(rbo); |
||
526 | } |
||
1268 | serge | 527 | |
528 | /* Bytes per pixel may have changed */ |
||
529 | radeon_bandwidth_update(rdev); |
||
530 | |||
1123 | serge | 531 | return 0; |
532 | } |
||
533 | |||
534 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
535 | { |
||
536 | struct drm_device *dev = crtc->dev; |
||
537 | struct radeon_device *rdev = dev->dev_private; |
||
538 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1179 | serge | 539 | struct drm_encoder *encoder; |
1123 | serge | 540 | int format; |
541 | int hsync_start; |
||
542 | int hsync_wid; |
||
543 | int vsync_wid; |
||
544 | uint32_t crtc_h_total_disp; |
||
545 | uint32_t crtc_h_sync_strt_wid; |
||
546 | uint32_t crtc_v_total_disp; |
||
547 | uint32_t crtc_v_sync_strt_wid; |
||
1179 | serge | 548 | bool is_tv = false; |
1123 | serge | 549 | |
1963 | serge | 550 | DRM_DEBUG_KMS("\n"); |
1179 | serge | 551 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
552 | if (encoder->crtc == crtc) { |
||
553 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
554 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
555 | is_tv = true; |
||
556 | DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); |
||
557 | break; |
||
558 | } |
||
559 | } |
||
560 | } |
||
1123 | serge | 561 | |
562 | switch (crtc->fb->bits_per_pixel) { |
||
1179 | serge | 563 | case 8: |
564 | format = 2; |
||
565 | break; |
||
1123 | serge | 566 | case 15: /* 555 */ |
567 | format = 3; |
||
568 | break; |
||
569 | case 16: /* 565 */ |
||
570 | format = 4; |
||
571 | break; |
||
572 | case 24: /* RGB */ |
||
573 | format = 5; |
||
574 | break; |
||
575 | case 32: /* xRGB */ |
||
576 | format = 6; |
||
577 | break; |
||
578 | default: |
||
579 | return false; |
||
580 | } |
||
581 | |||
582 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
||
583 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
||
584 | |||
585 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
||
586 | if (!hsync_wid) |
||
587 | hsync_wid = 1; |
||
588 | hsync_start = mode->crtc_hsync_start - 8; |
||
589 | |||
590 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
||
591 | | ((hsync_wid & 0x3f) << 16) |
||
592 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
593 | ? RADEON_CRTC_H_SYNC_POL |
||
594 | : 0)); |
||
595 | |||
596 | /* This works for double scan mode. */ |
||
597 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
||
598 | | ((mode->crtc_vdisplay - 1) << 16)); |
||
599 | |||
600 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
||
601 | if (!vsync_wid) |
||
602 | vsync_wid = 1; |
||
603 | |||
604 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
||
605 | | ((vsync_wid & 0x1f) << 16) |
||
606 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
607 | ? RADEON_CRTC_V_SYNC_POL |
||
608 | : 0)); |
||
609 | |||
610 | if (radeon_crtc->crtc_id) { |
||
611 | uint32_t crtc2_gen_cntl; |
||
612 | uint32_t disp2_merge_cntl; |
||
613 | |||
1321 | serge | 614 | /* if TV DAC is enabled for another crtc and keep it enabled */ |
615 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; |
||
1123 | serge | 616 | crtc2_gen_cntl |= ((format << 8) |
617 | | RADEON_CRTC2_VSYNC_DIS |
||
618 | | RADEON_CRTC2_HSYNC_DIS |
||
619 | | RADEON_CRTC2_DISP_DIS |
||
620 | | RADEON_CRTC2_DISP_REQ_EN_B |
||
621 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
622 | ? RADEON_CRTC2_DBL_SCAN_EN |
||
623 | : 0) |
||
624 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
625 | ? RADEON_CRTC2_CSYNC_EN |
||
626 | : 0) |
||
627 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
628 | ? RADEON_CRTC2_INTERLACE_EN |
||
629 | : 0)); |
||
630 | |||
1963 | serge | 631 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
632 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
||
633 | crtc2_gen_cntl |= RADEON_CRTC2_EN; |
||
634 | |||
1123 | serge | 635 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
636 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
||
637 | |||
638 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
||
639 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1268 | serge | 640 | |
641 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
||
642 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
||
1123 | serge | 643 | } else { |
644 | uint32_t crtc_gen_cntl; |
||
645 | uint32_t crtc_ext_cntl; |
||
646 | uint32_t disp_merge_cntl; |
||
647 | |||
1321 | serge | 648 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; |
649 | crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN |
||
1123 | serge | 650 | | (format << 8) |
651 | | RADEON_CRTC_DISP_REQ_EN_B |
||
652 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
653 | ? RADEON_CRTC_DBL_SCAN_EN |
||
654 | : 0) |
||
655 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
656 | ? RADEON_CRTC_CSYNC_EN |
||
657 | : 0) |
||
658 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
659 | ? RADEON_CRTC_INTERLACE_EN |
||
660 | : 0)); |
||
661 | |||
1963 | serge | 662 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
663 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
||
664 | crtc_gen_cntl |= RADEON_CRTC_EN; |
||
665 | |||
1123 | serge | 666 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
667 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
||
668 | RADEON_CRTC_VSYNC_DIS | |
||
669 | RADEON_CRTC_HSYNC_DIS | |
||
670 | RADEON_CRTC_DISPLAY_DIS); |
||
671 | |||
672 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
||
673 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
||
674 | |||
675 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
||
676 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
||
677 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
678 | } |
||
679 | |||
1179 | serge | 680 | if (is_tv) |
681 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
||
682 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
||
683 | &crtc_v_sync_strt_wid); |
||
684 | |||
1123 | serge | 685 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
686 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
||
687 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
||
688 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
||
689 | |||
690 | return true; |
||
691 | } |
||
692 | |||
693 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
694 | { |
||
695 | struct drm_device *dev = crtc->dev; |
||
696 | struct radeon_device *rdev = dev->dev_private; |
||
697 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
698 | struct drm_encoder *encoder; |
||
699 | uint32_t feedback_div = 0; |
||
700 | uint32_t frac_fb_div = 0; |
||
701 | uint32_t reference_div = 0; |
||
702 | uint32_t post_divider = 0; |
||
703 | uint32_t freq = 0; |
||
704 | uint8_t pll_gain; |
||
705 | bool use_bios_divs = false; |
||
706 | /* PLL registers */ |
||
707 | uint32_t pll_ref_div = 0; |
||
708 | uint32_t pll_fb_post_div = 0; |
||
709 | uint32_t htotal_cntl = 0; |
||
1179 | serge | 710 | bool is_tv = false; |
1123 | serge | 711 | struct radeon_pll *pll; |
712 | |||
713 | struct { |
||
714 | int divider; |
||
715 | int bitvalue; |
||
716 | } *post_div, post_divs[] = { |
||
717 | /* From RAGE 128 VR/RAGE 128 GL Register |
||
718 | * Reference Manual (Technical Reference |
||
719 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
||
720 | * 3-17 (PLL_DIV_[3:0]). |
||
721 | */ |
||
722 | { 1, 0 }, /* VCLK_SRC */ |
||
723 | { 2, 1 }, /* VCLK_SRC/2 */ |
||
724 | { 4, 2 }, /* VCLK_SRC/4 */ |
||
725 | { 8, 3 }, /* VCLK_SRC/8 */ |
||
726 | { 3, 4 }, /* VCLK_SRC/3 */ |
||
727 | { 16, 5 }, /* VCLK_SRC/16 */ |
||
728 | { 6, 6 }, /* VCLK_SRC/6 */ |
||
729 | { 12, 7 }, /* VCLK_SRC/12 */ |
||
730 | { 0, 0 } |
||
731 | }; |
||
732 | |||
733 | if (radeon_crtc->crtc_id) |
||
734 | pll = &rdev->clock.p2pll; |
||
735 | else |
||
736 | pll = &rdev->clock.p1pll; |
||
737 | |||
1404 | serge | 738 | pll->flags = RADEON_PLL_LEGACY; |
739 | |||
1123 | serge | 740 | if (mode->clock > 200000) /* range limits??? */ |
1404 | serge | 741 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
1123 | serge | 742 | else |
1404 | serge | 743 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
1123 | serge | 744 | |
745 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
746 | if (encoder->crtc == crtc) { |
||
1179 | serge | 747 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
748 | |||
749 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
750 | is_tv = true; |
||
751 | break; |
||
752 | } |
||
753 | |||
1123 | serge | 754 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
1404 | serge | 755 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
1123 | serge | 756 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
1321 | serge | 757 | if (!rdev->is_atom_bios) { |
1123 | serge | 758 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
759 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
||
760 | if (lvds) { |
||
761 | if (lvds->use_bios_dividers) { |
||
762 | pll_ref_div = lvds->panel_ref_divider; |
||
763 | pll_fb_post_div = (lvds->panel_fb_divider | |
||
764 | (lvds->panel_post_divider << 16)); |
||
765 | htotal_cntl = 0; |
||
766 | use_bios_divs = true; |
||
767 | } |
||
768 | } |
||
1321 | serge | 769 | } |
1404 | serge | 770 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
1123 | serge | 771 | } |
772 | } |
||
773 | } |
||
774 | |||
1963 | serge | 775 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 776 | |
777 | if (!use_bios_divs) { |
||
1963 | serge | 778 | radeon_compute_pll_legacy(pll, mode->clock, |
1123 | serge | 779 | &freq, &feedback_div, &frac_fb_div, |
1404 | serge | 780 | &reference_div, &post_divider); |
1123 | serge | 781 | |
782 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
||
783 | if (post_div->divider == post_divider) |
||
784 | break; |
||
785 | } |
||
786 | |||
787 | if (!post_div->divider) |
||
788 | post_div = &post_divs[0]; |
||
789 | |||
1963 | serge | 790 | DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", |
1123 | serge | 791 | (unsigned)freq, |
792 | feedback_div, |
||
793 | reference_div, |
||
794 | post_divider); |
||
795 | |||
796 | pll_ref_div = reference_div; |
||
797 | #if defined(__powerpc__) && (0) /* TODO */ |
||
798 | /* apparently programming this otherwise causes a hang??? */ |
||
799 | if (info->MacModel == RADEON_MAC_IBOOK) |
||
800 | pll_fb_post_div = 0x000600ad; |
||
801 | else |
||
802 | #endif |
||
803 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
||
804 | |||
805 | htotal_cntl = mode->htotal & 0x7; |
||
806 | |||
807 | } |
||
808 | |||
809 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
||
810 | pll_ref_div & 0x3ff, |
||
811 | pll_fb_post_div & 0x7ff); |
||
812 | |||
813 | if (radeon_crtc->crtc_id) { |
||
814 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
||
815 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
||
816 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
||
817 | |||
1179 | serge | 818 | if (is_tv) { |
819 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
||
820 | &pll_ref_div, &pll_fb_post_div, |
||
821 | &pixclks_cntl); |
||
822 | } |
||
823 | |||
1123 | serge | 824 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
825 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
||
826 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
827 | |||
828 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
829 | RADEON_P2PLL_RESET |
||
830 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
831 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
||
832 | ~(RADEON_P2PLL_RESET |
||
833 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
834 | | RADEON_P2PLL_PVG_MASK)); |
||
835 | |||
836 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
||
837 | pll_ref_div, |
||
838 | ~RADEON_P2PLL_REF_DIV_MASK); |
||
839 | |||
840 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
841 | pll_fb_post_div, |
||
842 | ~RADEON_P2PLL_FB0_DIV_MASK); |
||
843 | |||
844 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
845 | pll_fb_post_div, |
||
846 | ~RADEON_P2PLL_POST0_DIV_MASK); |
||
847 | |||
848 | radeon_pll2_write_update(dev); |
||
849 | radeon_pll2_wait_for_read_update_complete(dev); |
||
850 | |||
851 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
||
852 | |||
853 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
854 | 0, |
||
855 | ~(RADEON_P2PLL_RESET |
||
856 | | RADEON_P2PLL_SLEEP |
||
857 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
||
858 | |||
1963 | serge | 859 | DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
1123 | serge | 860 | (unsigned)pll_ref_div, |
861 | (unsigned)pll_fb_post_div, |
||
862 | (unsigned)htotal_cntl, |
||
863 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
||
1963 | serge | 864 | DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", |
1123 | serge | 865 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
866 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
||
867 | (unsigned)((pll_fb_post_div & |
||
868 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
||
869 | |||
870 | mdelay(50); /* Let the clock to lock */ |
||
871 | |||
872 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
||
873 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
||
874 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
875 | |||
876 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
877 | } else { |
||
1179 | serge | 878 | uint32_t pixclks_cntl; |
879 | |||
880 | |||
881 | if (is_tv) { |
||
882 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
883 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
||
884 | &pll_fb_post_div, &pixclks_cntl); |
||
885 | } |
||
886 | |||
1123 | serge | 887 | if (rdev->flags & RADEON_IS_MOBILITY) { |
1963 | serge | 888 | /* A temporal workaround for the occasional blanking on certain laptop panels. |
1123 | serge | 889 | This appears to related to the PLL divider registers (fail to lock?). |
890 | It occurs even when all dividers are the same with their old settings. |
||
891 | In this case we really don't need to fiddle with PLL registers. |
||
892 | By doing this we can avoid the blanking problem with some panels. |
||
893 | */ |
||
894 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
||
895 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
||
896 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
||
897 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
898 | RADEON_PLL_DIV_SEL, |
||
899 | ~(RADEON_PLL_DIV_SEL)); |
||
900 | r100_pll_errata_after_index(rdev); |
||
901 | return; |
||
902 | } |
||
903 | } |
||
904 | |||
905 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
906 | RADEON_VCLK_SRC_SEL_CPUCLK, |
||
907 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
908 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
909 | RADEON_PPLL_RESET |
||
910 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
911 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
912 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
||
913 | ~(RADEON_PPLL_RESET |
||
914 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
915 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
916 | | RADEON_PPLL_PVG_MASK)); |
||
917 | |||
918 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
919 | RADEON_PLL_DIV_SEL, |
||
920 | ~(RADEON_PLL_DIV_SEL)); |
||
921 | r100_pll_errata_after_index(rdev); |
||
922 | |||
923 | if (ASIC_IS_R300(rdev) || |
||
924 | (rdev->family == CHIP_RS300) || |
||
925 | (rdev->family == CHIP_RS400) || |
||
926 | (rdev->family == CHIP_RS480)) { |
||
927 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
||
928 | /* When restoring console mode, use saved PPLL_REF_DIV |
||
929 | * setting. |
||
930 | */ |
||
931 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
932 | pll_ref_div, |
||
933 | 0); |
||
934 | } else { |
||
935 | /* R300 uses ref_div_acc field as real ref divider */ |
||
936 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
937 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
||
938 | ~R300_PPLL_REF_DIV_ACC_MASK); |
||
939 | } |
||
940 | } else |
||
941 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
942 | pll_ref_div, |
||
943 | ~RADEON_PPLL_REF_DIV_MASK); |
||
944 | |||
945 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
946 | pll_fb_post_div, |
||
947 | ~RADEON_PPLL_FB3_DIV_MASK); |
||
948 | |||
949 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
950 | pll_fb_post_div, |
||
951 | ~RADEON_PPLL_POST3_DIV_MASK); |
||
952 | |||
953 | radeon_pll_write_update(dev); |
||
954 | radeon_pll_wait_for_read_update_complete(dev); |
||
955 | |||
956 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
||
957 | |||
958 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
959 | 0, |
||
960 | ~(RADEON_PPLL_RESET |
||
961 | | RADEON_PPLL_SLEEP |
||
962 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
963 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
||
964 | |||
1963 | serge | 965 | DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
1123 | serge | 966 | pll_ref_div, |
967 | pll_fb_post_div, |
||
968 | (unsigned)htotal_cntl, |
||
969 | RREG32_PLL(RADEON_PPLL_CNTL)); |
||
1963 | serge | 970 | DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", |
1123 | serge | 971 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
972 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
||
973 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
||
974 | |||
975 | mdelay(50); /* Let the clock to lock */ |
||
976 | |||
977 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
978 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
||
979 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
980 | |||
1179 | serge | 981 | if (is_tv) |
982 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
1123 | serge | 983 | } |
984 | } |
||
985 | |||
986 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
||
2997 | Serge | 987 | const struct drm_display_mode *mode, |
1123 | serge | 988 | struct drm_display_mode *adjusted_mode) |
989 | { |
||
1179 | serge | 990 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
991 | return false; |
||
1123 | serge | 992 | return true; |
993 | } |
||
994 | |||
995 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
||
996 | struct drm_display_mode *mode, |
||
997 | struct drm_display_mode *adjusted_mode, |
||
998 | int x, int y, struct drm_framebuffer *old_fb) |
||
999 | { |
||
1179 | serge | 1000 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 1001 | |
1002 | /* TODO TV */ |
||
1003 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
1004 | radeon_set_crtc_timing(crtc, adjusted_mode); |
||
1005 | radeon_set_pll(crtc, adjusted_mode); |
||
1321 | serge | 1006 | radeon_overscan_setup(crtc, adjusted_mode); |
1179 | serge | 1007 | if (radeon_crtc->crtc_id == 0) { |
1404 | serge | 1008 | radeon_legacy_rmx_mode_set(crtc, adjusted_mode); |
1179 | serge | 1009 | } else { |
1010 | if (radeon_crtc->rmx_type != RMX_OFF) { |
||
1011 | /* FIXME: only first crtc has rmx what should we |
||
1012 | * do ? |
||
1013 | */ |
||
1014 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); |
||
1015 | } |
||
1016 | } |
||
1123 | serge | 1017 | return 0; |
1018 | } |
||
1019 | |||
1020 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
||
1021 | { |
||
2997 | Serge | 1022 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1321 | serge | 1023 | struct drm_device *dev = crtc->dev; |
1024 | struct drm_crtc *crtci; |
||
1025 | |||
2997 | Serge | 1026 | radeon_crtc->in_mode_set = true; |
1321 | serge | 1027 | /* |
1028 | * The hardware wedges sometimes if you reconfigure one CRTC |
||
1029 | * whilst another is running (see fdo bug #24611). |
||
1030 | */ |
||
1031 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) |
||
1032 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); |
||
1123 | serge | 1033 | } |
1034 | |||
1035 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
||
1036 | { |
||
2997 | Serge | 1037 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1321 | serge | 1038 | struct drm_device *dev = crtc->dev; |
1039 | struct drm_crtc *crtci; |
||
1040 | |||
1041 | /* |
||
1042 | * Reenable the CRTCs that should be running. |
||
1043 | */ |
||
1044 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { |
||
1045 | if (crtci->enabled) |
||
1046 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
||
1047 | } |
||
2997 | Serge | 1048 | radeon_crtc->in_mode_set = false; |
1123 | serge | 1049 | } |
1050 | |||
1051 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
||
1052 | .dpms = radeon_crtc_dpms, |
||
1053 | .mode_fixup = radeon_crtc_mode_fixup, |
||
1054 | .mode_set = radeon_crtc_mode_set, |
||
1055 | .mode_set_base = radeon_crtc_set_base, |
||
1963 | serge | 1056 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
1123 | serge | 1057 | .prepare = radeon_crtc_prepare, |
1058 | .commit = radeon_crtc_commit, |
||
1221 | serge | 1059 | .load_lut = radeon_crtc_load_lut, |
1123 | serge | 1060 | }; |
1061 | |||
1062 | |||
1063 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
1064 | struct radeon_crtc *radeon_crtc) |
||
1065 | { |
||
1066 | if (radeon_crtc->crtc_id == 1) |
||
1067 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
||
1068 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
||
1069 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |