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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1179 | serge | 26 | #include |
27 | #include |
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28 | #include |
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1963 | serge | 29 | #include |
1123 | serge | 30 | #include "radeon.h" |
1179 | serge | 31 | #include "atom.h" |
1123 | serge | 32 | |
1321 | serge | 33 | static void radeon_overscan_setup(struct drm_crtc *crtc, |
34 | struct drm_display_mode *mode) |
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35 | { |
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36 | struct drm_device *dev = crtc->dev; |
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37 | struct radeon_device *rdev = dev->dev_private; |
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38 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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39 | |||
40 | WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); |
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41 | WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); |
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42 | WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); |
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43 | } |
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44 | |||
1179 | serge | 45 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
1404 | serge | 46 | struct drm_display_mode *mode) |
1179 | serge | 47 | { |
48 | struct drm_device *dev = crtc->dev; |
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49 | struct radeon_device *rdev = dev->dev_private; |
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50 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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51 | int xres = mode->hdisplay; |
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52 | int yres = mode->vdisplay; |
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53 | bool hscale = true, vscale = true; |
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54 | int hsync_wid; |
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55 | int vsync_wid; |
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56 | int hsync_start; |
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57 | int blank_width; |
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58 | u32 scale, inc, crtc_more_cntl; |
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59 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
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60 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
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61 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
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1268 | serge | 62 | struct drm_display_mode *native_mode = &radeon_crtc->native_mode; |
1179 | serge | 63 | |
64 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
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65 | (RADEON_VERT_STRETCH_RESERVED | |
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66 | RADEON_VERT_AUTO_RATIO_INC); |
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67 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
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68 | (RADEON_HORZ_FP_LOOP_STRETCH | |
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69 | RADEON_HORZ_AUTO_RATIO_INC); |
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70 | |||
71 | crtc_more_cntl = 0; |
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72 | if ((rdev->family == CHIP_RS100) || |
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73 | (rdev->family == CHIP_RS200)) { |
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74 | /* This is to workaround the asic bug for RMX, some versions |
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75 | of BIOS dosen't have this register initialized correctly. */ |
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76 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
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77 | } |
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78 | |||
79 | |||
80 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
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81 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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82 | |||
83 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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84 | if (!hsync_wid) |
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85 | hsync_wid = 1; |
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86 | hsync_start = mode->crtc_hsync_start - 8; |
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87 | |||
88 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
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89 | | ((hsync_wid & 0x3f) << 16) |
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90 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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91 | ? RADEON_CRTC_H_SYNC_POL |
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92 | : 0)); |
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93 | |||
94 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
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95 | | ((mode->crtc_vdisplay - 1) << 16)); |
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96 | |||
97 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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98 | if (!vsync_wid) |
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99 | vsync_wid = 1; |
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100 | |||
101 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
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102 | | ((vsync_wid & 0x1f) << 16) |
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103 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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104 | ? RADEON_CRTC_V_SYNC_POL |
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105 | : 0)); |
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106 | |||
107 | fp_horz_vert_active = 0; |
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108 | |||
1268 | serge | 109 | if (native_mode->hdisplay == 0 || |
110 | native_mode->vdisplay == 0) { |
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1179 | serge | 111 | hscale = false; |
112 | vscale = false; |
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113 | } else { |
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1268 | serge | 114 | if (xres > native_mode->hdisplay) |
115 | xres = native_mode->hdisplay; |
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116 | if (yres > native_mode->vdisplay) |
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117 | yres = native_mode->vdisplay; |
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1179 | serge | 118 | |
1268 | serge | 119 | if (xres == native_mode->hdisplay) |
1179 | serge | 120 | hscale = false; |
1268 | serge | 121 | if (yres == native_mode->vdisplay) |
1179 | serge | 122 | vscale = false; |
123 | } |
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124 | |||
125 | switch (radeon_crtc->rmx_type) { |
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126 | case RMX_FULL: |
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127 | case RMX_ASPECT: |
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128 | if (!hscale) |
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129 | fp_horz_stretch |= ((xres/8-1) << 16); |
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130 | else { |
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131 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
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132 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
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1268 | serge | 133 | / native_mode->hdisplay + 1; |
1179 | serge | 134 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
135 | RADEON_HORZ_STRETCH_BLEND | |
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136 | RADEON_HORZ_STRETCH_ENABLE | |
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1268 | serge | 137 | ((native_mode->hdisplay/8-1) << 16)); |
1179 | serge | 138 | } |
139 | |||
140 | if (!vscale) |
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141 | fp_vert_stretch |= ((yres-1) << 12); |
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142 | else { |
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143 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
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144 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
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1268 | serge | 145 | / native_mode->vdisplay + 1; |
1179 | serge | 146 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
147 | RADEON_VERT_STRETCH_ENABLE | |
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148 | RADEON_VERT_STRETCH_BLEND | |
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1268 | serge | 149 | ((native_mode->vdisplay-1) << 12)); |
1179 | serge | 150 | } |
151 | break; |
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152 | case RMX_CENTER: |
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153 | fp_horz_stretch |= ((xres/8-1) << 16); |
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154 | fp_vert_stretch |= ((yres-1) << 12); |
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155 | |||
156 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
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157 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
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158 | |||
159 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
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160 | if (blank_width > 110) |
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161 | blank_width = 110; |
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162 | |||
163 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
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164 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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165 | |||
166 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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167 | if (!hsync_wid) |
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168 | hsync_wid = 1; |
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169 | |||
170 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
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171 | | ((hsync_wid & 0x3f) << 16) |
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172 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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173 | ? RADEON_CRTC_H_SYNC_POL |
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174 | : 0)); |
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175 | |||
176 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
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177 | | ((mode->crtc_vdisplay - 1) << 16)); |
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178 | |||
179 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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180 | if (!vsync_wid) |
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181 | vsync_wid = 1; |
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182 | |||
183 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
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184 | | ((vsync_wid & 0x1f) << 16) |
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185 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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186 | ? RADEON_CRTC_V_SYNC_POL |
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187 | : 0))); |
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188 | |||
1268 | serge | 189 | fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) | |
190 | (((native_mode->hdisplay / 8) & 0x1ff) << 16)); |
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1179 | serge | 191 | break; |
192 | case RMX_OFF: |
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193 | default: |
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194 | fp_horz_stretch |= ((xres/8-1) << 16); |
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195 | fp_vert_stretch |= ((yres-1) << 12); |
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196 | break; |
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197 | } |
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198 | |||
199 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
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200 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
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201 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
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202 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
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203 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
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204 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
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205 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
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206 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
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207 | } |
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208 | |||
1123 | serge | 209 | void radeon_restore_common_regs(struct drm_device *dev) |
210 | { |
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211 | /* don't need this yet */ |
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212 | } |
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213 | |||
214 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
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215 | { |
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216 | struct radeon_device *rdev = dev->dev_private; |
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217 | int i = 0; |
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218 | |||
219 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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220 | the cause yet, but this workaround will mask the problem for now. |
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221 | Other chips usually will pass at the very first test, so the |
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222 | workaround shouldn't have any effect on them. */ |
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223 | for (i = 0; |
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224 | (i < 10000 && |
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225 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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226 | i++); |
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227 | } |
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228 | |||
229 | static void radeon_pll_write_update(struct drm_device *dev) |
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230 | { |
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231 | struct radeon_device *rdev = dev->dev_private; |
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232 | |||
233 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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234 | |||
235 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
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236 | RADEON_PPLL_ATOMIC_UPDATE_W, |
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237 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
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238 | } |
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239 | |||
240 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
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241 | { |
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242 | struct radeon_device *rdev = dev->dev_private; |
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243 | int i = 0; |
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244 | |||
245 | |||
246 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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247 | the cause yet, but this workaround will mask the problem for now. |
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248 | Other chips usually will pass at the very first test, so the |
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249 | workaround shouldn't have any effect on them. */ |
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250 | for (i = 0; |
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251 | (i < 10000 && |
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252 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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253 | i++); |
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254 | } |
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255 | |||
256 | static void radeon_pll2_write_update(struct drm_device *dev) |
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257 | { |
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258 | struct radeon_device *rdev = dev->dev_private; |
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259 | |||
260 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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261 | |||
262 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
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263 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
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264 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
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265 | } |
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266 | |||
267 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
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268 | uint16_t fb_div) |
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269 | { |
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270 | unsigned int vcoFreq; |
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271 | |||
272 | if (!ref_div) |
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273 | return 1; |
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274 | |||
1963 | serge | 275 | vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; |
1123 | serge | 276 | |
277 | /* |
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278 | * This is horribly crude: the VCO frequency range is divided into |
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279 | * 3 parts, each part having a fixed PLL gain value. |
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280 | */ |
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281 | if (vcoFreq >= 30000) |
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282 | /* |
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283 | * [300..max] MHz : 7 |
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284 | */ |
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285 | return 7; |
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286 | else if (vcoFreq >= 18000) |
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287 | /* |
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288 | * [180..300) MHz : 4 |
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289 | */ |
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290 | return 4; |
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291 | else |
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292 | /* |
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293 | * [0..180) MHz : 1 |
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294 | */ |
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295 | return 1; |
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296 | } |
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297 | |||
298 | void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
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299 | { |
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300 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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301 | struct drm_device *dev = crtc->dev; |
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302 | struct radeon_device *rdev = dev->dev_private; |
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303 | uint32_t mask; |
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304 | |||
305 | if (radeon_crtc->crtc_id) |
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1321 | serge | 306 | mask = (RADEON_CRTC2_DISP_DIS | |
1123 | serge | 307 | RADEON_CRTC2_VSYNC_DIS | |
308 | RADEON_CRTC2_HSYNC_DIS | |
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309 | RADEON_CRTC2_DISP_REQ_EN_B); |
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310 | else |
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311 | mask = (RADEON_CRTC_DISPLAY_DIS | |
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312 | RADEON_CRTC_VSYNC_DIS | |
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313 | RADEON_CRTC_HSYNC_DIS); |
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314 | |||
315 | switch (mode) { |
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316 | case DRM_MODE_DPMS_ON: |
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1963 | serge | 317 | radeon_crtc->enabled = true; |
318 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
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319 | radeon_pm_compute_clocks(rdev); |
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1123 | serge | 320 | if (radeon_crtc->crtc_id) |
1321 | serge | 321 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); |
1123 | serge | 322 | else { |
323 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
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324 | RADEON_CRTC_DISP_REQ_EN_B)); |
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325 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
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326 | } |
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1430 | serge | 327 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
1179 | serge | 328 | radeon_crtc_load_lut(crtc); |
1123 | serge | 329 | break; |
330 | case DRM_MODE_DPMS_STANDBY: |
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331 | case DRM_MODE_DPMS_SUSPEND: |
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332 | case DRM_MODE_DPMS_OFF: |
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1430 | serge | 333 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
1123 | serge | 334 | if (radeon_crtc->crtc_id) |
1321 | serge | 335 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); |
1123 | serge | 336 | else { |
337 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
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338 | RADEON_CRTC_DISP_REQ_EN_B)); |
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339 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
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340 | } |
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1963 | serge | 341 | radeon_crtc->enabled = false; |
342 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
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343 | radeon_pm_compute_clocks(rdev); |
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1123 | serge | 344 | break; |
345 | } |
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346 | } |
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347 | |||
348 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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349 | struct drm_framebuffer *old_fb) |
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350 | { |
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1963 | serge | 351 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
352 | } |
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353 | |||
354 | int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, |
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355 | struct drm_framebuffer *fb, |
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356 | int x, int y, enum mode_set_atomic state) |
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357 | { |
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358 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
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359 | } |
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360 | |||
361 | int radeon_crtc_do_set_base(struct drm_crtc *crtc, |
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362 | struct drm_framebuffer *fb, |
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363 | int x, int y, int atomic) |
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364 | { |
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1123 | serge | 365 | struct drm_device *dev = crtc->dev; |
366 | struct radeon_device *rdev = dev->dev_private; |
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367 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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368 | struct radeon_framebuffer *radeon_fb; |
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1963 | serge | 369 | struct drm_framebuffer *target_fb; |
1123 | serge | 370 | struct drm_gem_object *obj; |
1321 | serge | 371 | struct radeon_bo *rbo; |
1123 | serge | 372 | uint64_t base; |
373 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
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374 | uint32_t crtc_pitch, pitch_pixels; |
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1179 | serge | 375 | uint32_t tiling_flags; |
376 | int format; |
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377 | uint32_t gen_cntl_reg, gen_cntl_val; |
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1321 | serge | 378 | int r; |
1123 | serge | 379 | |
1963 | serge | 380 | DRM_DEBUG_KMS("\n"); |
1321 | serge | 381 | /* no fb bound */ |
1963 | serge | 382 | if (!atomic && !crtc->fb) { |
383 | DRM_DEBUG_KMS("No FB bound\n"); |
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1321 | serge | 384 | return 0; |
385 | } |
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1123 | serge | 386 | |
1963 | serge | 387 | if (atomic) { |
388 | radeon_fb = to_radeon_framebuffer(fb); |
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389 | target_fb = fb; |
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390 | } |
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391 | else { |
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1123 | serge | 392 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
1963 | serge | 393 | target_fb = crtc->fb; |
394 | } |
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1123 | serge | 395 | |
1963 | serge | 396 | switch (target_fb->bits_per_pixel) { |
1179 | serge | 397 | case 8: |
398 | format = 2; |
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399 | break; |
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400 | case 15: /* 555 */ |
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401 | format = 3; |
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402 | break; |
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403 | case 16: /* 565 */ |
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404 | format = 4; |
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405 | break; |
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406 | case 24: /* RGB */ |
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407 | format = 5; |
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408 | break; |
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409 | case 32: /* xRGB */ |
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410 | format = 6; |
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411 | break; |
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412 | default: |
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413 | return false; |
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414 | } |
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415 | |||
1321 | serge | 416 | /* Pin framebuffer & get tilling informations */ |
1123 | serge | 417 | obj = radeon_fb->obj; |
1963 | serge | 418 | rbo = gem_to_radeon_bo(obj); |
1321 | serge | 419 | r = radeon_bo_reserve(rbo, false); |
420 | if (unlikely(r != 0)) |
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421 | return r; |
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422 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base); |
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423 | if (unlikely(r != 0)) { |
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424 | radeon_bo_unreserve(rbo); |
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425 | return -EINVAL; |
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426 | } |
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427 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
||
428 | radeon_bo_unreserve(rbo); |
||
429 | if (tiling_flags & RADEON_TILING_MICRO) |
||
430 | DRM_ERROR("trying to scanout microtiled buffer\n"); |
||
1246 | serge | 431 | |
1179 | serge | 432 | /* if scanout was in GTT this really wouldn't work */ |
433 | /* crtc offset is from display base addr not FB location */ |
||
1430 | serge | 434 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start; |
1179 | serge | 435 | |
436 | base -= radeon_crtc->legacy_display_base_addr; |
||
437 | |||
1123 | serge | 438 | crtc_offset_cntl = 0; |
439 | |||
1963 | serge | 440 | pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8); |
441 | crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + |
||
442 | ((target_fb->bits_per_pixel * 8) - 1)) / |
||
443 | (target_fb->bits_per_pixel * 8)); |
||
1123 | serge | 444 | crtc_pitch |= crtc_pitch << 16; |
445 | |||
1963 | serge | 446 | crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN; |
1179 | serge | 447 | if (tiling_flags & RADEON_TILING_MACRO) { |
1123 | serge | 448 | if (ASIC_IS_R300(rdev)) |
449 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
||
450 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
451 | R300_CRTC_MACRO_TILE_EN); |
||
452 | else |
||
453 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
||
454 | } else { |
||
455 | if (ASIC_IS_R300(rdev)) |
||
456 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
||
457 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
458 | R300_CRTC_MACRO_TILE_EN); |
||
459 | else |
||
460 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
||
461 | } |
||
462 | |||
1179 | serge | 463 | if (tiling_flags & RADEON_TILING_MACRO) { |
1123 | serge | 464 | if (ASIC_IS_R300(rdev)) { |
465 | crtc_tile_x0_y0 = x | (y << 16); |
||
466 | base &= ~0x7ff; |
||
467 | } else { |
||
1963 | serge | 468 | int byteshift = target_fb->bits_per_pixel >> 4; |
1179 | serge | 469 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
1123 | serge | 470 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
471 | crtc_offset_cntl |= (y % 16); |
||
472 | } |
||
473 | } else { |
||
474 | int offset = y * pitch_pixels + x; |
||
1963 | serge | 475 | switch (target_fb->bits_per_pixel) { |
1179 | serge | 476 | case 8: |
477 | offset *= 1; |
||
478 | break; |
||
1123 | serge | 479 | case 15: |
480 | case 16: |
||
481 | offset *= 2; |
||
482 | break; |
||
483 | case 24: |
||
484 | offset *= 3; |
||
485 | break; |
||
486 | case 32: |
||
487 | offset *= 4; |
||
488 | break; |
||
489 | default: |
||
490 | return false; |
||
491 | } |
||
492 | base += offset; |
||
493 | } |
||
494 | |||
495 | base &= ~7; |
||
496 | |||
1179 | serge | 497 | if (radeon_crtc->crtc_id == 1) |
498 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
||
499 | else |
||
500 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
||
1123 | serge | 501 | |
1179 | serge | 502 | gen_cntl_val = RREG32(gen_cntl_reg); |
503 | gen_cntl_val &= ~(0xf << 8); |
||
504 | gen_cntl_val |= (format << 8); |
||
1963 | serge | 505 | gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK; |
1179 | serge | 506 | WREG32(gen_cntl_reg, gen_cntl_val); |
507 | |||
1123 | serge | 508 | crtc_offset = (u32)base; |
509 | |||
1179 | serge | 510 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
1123 | serge | 511 | |
512 | if (ASIC_IS_R300(rdev)) { |
||
513 | if (radeon_crtc->crtc_id) |
||
514 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
||
515 | else |
||
516 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
||
517 | } |
||
518 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
||
519 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
||
520 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
||
521 | |||
1963 | serge | 522 | if (!atomic && fb && fb != crtc->fb) { |
523 | radeon_fb = to_radeon_framebuffer(fb); |
||
524 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
||
1321 | serge | 525 | r = radeon_bo_reserve(rbo, false); |
526 | if (unlikely(r != 0)) |
||
527 | return r; |
||
528 | radeon_bo_unpin(rbo); |
||
529 | radeon_bo_unreserve(rbo); |
||
530 | } |
||
1268 | serge | 531 | |
532 | /* Bytes per pixel may have changed */ |
||
533 | radeon_bandwidth_update(rdev); |
||
534 | |||
1123 | serge | 535 | return 0; |
536 | } |
||
537 | |||
538 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
539 | { |
||
540 | struct drm_device *dev = crtc->dev; |
||
541 | struct radeon_device *rdev = dev->dev_private; |
||
542 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1179 | serge | 543 | struct drm_encoder *encoder; |
1123 | serge | 544 | int format; |
545 | int hsync_start; |
||
546 | int hsync_wid; |
||
547 | int vsync_wid; |
||
548 | uint32_t crtc_h_total_disp; |
||
549 | uint32_t crtc_h_sync_strt_wid; |
||
550 | uint32_t crtc_v_total_disp; |
||
551 | uint32_t crtc_v_sync_strt_wid; |
||
1179 | serge | 552 | bool is_tv = false; |
1123 | serge | 553 | |
1963 | serge | 554 | DRM_DEBUG_KMS("\n"); |
1179 | serge | 555 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
556 | if (encoder->crtc == crtc) { |
||
557 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
558 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
559 | is_tv = true; |
||
560 | DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); |
||
561 | break; |
||
562 | } |
||
563 | } |
||
564 | } |
||
1123 | serge | 565 | |
566 | switch (crtc->fb->bits_per_pixel) { |
||
1179 | serge | 567 | case 8: |
568 | format = 2; |
||
569 | break; |
||
1123 | serge | 570 | case 15: /* 555 */ |
571 | format = 3; |
||
572 | break; |
||
573 | case 16: /* 565 */ |
||
574 | format = 4; |
||
575 | break; |
||
576 | case 24: /* RGB */ |
||
577 | format = 5; |
||
578 | break; |
||
579 | case 32: /* xRGB */ |
||
580 | format = 6; |
||
581 | break; |
||
582 | default: |
||
583 | return false; |
||
584 | } |
||
585 | |||
586 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
||
587 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
||
588 | |||
589 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
||
590 | if (!hsync_wid) |
||
591 | hsync_wid = 1; |
||
592 | hsync_start = mode->crtc_hsync_start - 8; |
||
593 | |||
594 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
||
595 | | ((hsync_wid & 0x3f) << 16) |
||
596 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
597 | ? RADEON_CRTC_H_SYNC_POL |
||
598 | : 0)); |
||
599 | |||
600 | /* This works for double scan mode. */ |
||
601 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
||
602 | | ((mode->crtc_vdisplay - 1) << 16)); |
||
603 | |||
604 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
||
605 | if (!vsync_wid) |
||
606 | vsync_wid = 1; |
||
607 | |||
608 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
||
609 | | ((vsync_wid & 0x1f) << 16) |
||
610 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
611 | ? RADEON_CRTC_V_SYNC_POL |
||
612 | : 0)); |
||
613 | |||
614 | if (radeon_crtc->crtc_id) { |
||
615 | uint32_t crtc2_gen_cntl; |
||
616 | uint32_t disp2_merge_cntl; |
||
617 | |||
1321 | serge | 618 | /* if TV DAC is enabled for another crtc and keep it enabled */ |
619 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080; |
||
1123 | serge | 620 | crtc2_gen_cntl |= ((format << 8) |
621 | | RADEON_CRTC2_VSYNC_DIS |
||
622 | | RADEON_CRTC2_HSYNC_DIS |
||
623 | | RADEON_CRTC2_DISP_DIS |
||
624 | | RADEON_CRTC2_DISP_REQ_EN_B |
||
625 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
626 | ? RADEON_CRTC2_DBL_SCAN_EN |
||
627 | : 0) |
||
628 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
629 | ? RADEON_CRTC2_CSYNC_EN |
||
630 | : 0) |
||
631 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
632 | ? RADEON_CRTC2_INTERLACE_EN |
||
633 | : 0)); |
||
634 | |||
1963 | serge | 635 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
636 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
||
637 | crtc2_gen_cntl |= RADEON_CRTC2_EN; |
||
638 | |||
1123 | serge | 639 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
640 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
||
641 | |||
642 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
||
643 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
1268 | serge | 644 | |
645 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid); |
||
646 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid); |
||
1123 | serge | 647 | } else { |
648 | uint32_t crtc_gen_cntl; |
||
649 | uint32_t crtc_ext_cntl; |
||
650 | uint32_t disp_merge_cntl; |
||
651 | |||
1321 | serge | 652 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000; |
653 | crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN |
||
1123 | serge | 654 | | (format << 8) |
655 | | RADEON_CRTC_DISP_REQ_EN_B |
||
656 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
657 | ? RADEON_CRTC_DBL_SCAN_EN |
||
658 | : 0) |
||
659 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
660 | ? RADEON_CRTC_CSYNC_EN |
||
661 | : 0) |
||
662 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
663 | ? RADEON_CRTC_INTERLACE_EN |
||
664 | : 0)); |
||
665 | |||
1963 | serge | 666 | /* rs4xx chips seem to like to have the crtc enabled when the timing is set */ |
667 | if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) |
||
668 | crtc_gen_cntl |= RADEON_CRTC_EN; |
||
669 | |||
1123 | serge | 670 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
671 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
||
672 | RADEON_CRTC_VSYNC_DIS | |
||
673 | RADEON_CRTC_HSYNC_DIS | |
||
674 | RADEON_CRTC_DISPLAY_DIS); |
||
675 | |||
676 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
||
677 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
||
678 | |||
679 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
||
680 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
||
681 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
682 | } |
||
683 | |||
1179 | serge | 684 | if (is_tv) |
685 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
||
686 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
||
687 | &crtc_v_sync_strt_wid); |
||
688 | |||
1123 | serge | 689 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
690 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
||
691 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
||
692 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
||
693 | |||
694 | return true; |
||
695 | } |
||
696 | |||
697 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
698 | { |
||
699 | struct drm_device *dev = crtc->dev; |
||
700 | struct radeon_device *rdev = dev->dev_private; |
||
701 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
702 | struct drm_encoder *encoder; |
||
703 | uint32_t feedback_div = 0; |
||
704 | uint32_t frac_fb_div = 0; |
||
705 | uint32_t reference_div = 0; |
||
706 | uint32_t post_divider = 0; |
||
707 | uint32_t freq = 0; |
||
708 | uint8_t pll_gain; |
||
709 | bool use_bios_divs = false; |
||
710 | /* PLL registers */ |
||
711 | uint32_t pll_ref_div = 0; |
||
712 | uint32_t pll_fb_post_div = 0; |
||
713 | uint32_t htotal_cntl = 0; |
||
1179 | serge | 714 | bool is_tv = false; |
1123 | serge | 715 | struct radeon_pll *pll; |
716 | |||
717 | struct { |
||
718 | int divider; |
||
719 | int bitvalue; |
||
720 | } *post_div, post_divs[] = { |
||
721 | /* From RAGE 128 VR/RAGE 128 GL Register |
||
722 | * Reference Manual (Technical Reference |
||
723 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
||
724 | * 3-17 (PLL_DIV_[3:0]). |
||
725 | */ |
||
726 | { 1, 0 }, /* VCLK_SRC */ |
||
727 | { 2, 1 }, /* VCLK_SRC/2 */ |
||
728 | { 4, 2 }, /* VCLK_SRC/4 */ |
||
729 | { 8, 3 }, /* VCLK_SRC/8 */ |
||
730 | { 3, 4 }, /* VCLK_SRC/3 */ |
||
731 | { 16, 5 }, /* VCLK_SRC/16 */ |
||
732 | { 6, 6 }, /* VCLK_SRC/6 */ |
||
733 | { 12, 7 }, /* VCLK_SRC/12 */ |
||
734 | { 0, 0 } |
||
735 | }; |
||
736 | |||
737 | if (radeon_crtc->crtc_id) |
||
738 | pll = &rdev->clock.p2pll; |
||
739 | else |
||
740 | pll = &rdev->clock.p1pll; |
||
741 | |||
1404 | serge | 742 | pll->flags = RADEON_PLL_LEGACY; |
743 | |||
1123 | serge | 744 | if (mode->clock > 200000) /* range limits??? */ |
1404 | serge | 745 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
1123 | serge | 746 | else |
1404 | serge | 747 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
1123 | serge | 748 | |
749 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
750 | if (encoder->crtc == crtc) { |
||
1179 | serge | 751 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
752 | |||
753 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
754 | is_tv = true; |
||
755 | break; |
||
756 | } |
||
757 | |||
1123 | serge | 758 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
1404 | serge | 759 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
1123 | serge | 760 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
1321 | serge | 761 | if (!rdev->is_atom_bios) { |
1123 | serge | 762 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
763 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
||
764 | if (lvds) { |
||
765 | if (lvds->use_bios_dividers) { |
||
766 | pll_ref_div = lvds->panel_ref_divider; |
||
767 | pll_fb_post_div = (lvds->panel_fb_divider | |
||
768 | (lvds->panel_post_divider << 16)); |
||
769 | htotal_cntl = 0; |
||
770 | use_bios_divs = true; |
||
771 | } |
||
772 | } |
||
1321 | serge | 773 | } |
1404 | serge | 774 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
1123 | serge | 775 | } |
776 | } |
||
777 | } |
||
778 | |||
1963 | serge | 779 | DRM_DEBUG_KMS("\n"); |
1123 | serge | 780 | |
781 | if (!use_bios_divs) { |
||
1963 | serge | 782 | radeon_compute_pll_legacy(pll, mode->clock, |
1123 | serge | 783 | &freq, &feedback_div, &frac_fb_div, |
1404 | serge | 784 | &reference_div, &post_divider); |
1123 | serge | 785 | |
786 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
||
787 | if (post_div->divider == post_divider) |
||
788 | break; |
||
789 | } |
||
790 | |||
791 | if (!post_div->divider) |
||
792 | post_div = &post_divs[0]; |
||
793 | |||
1963 | serge | 794 | DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n", |
1123 | serge | 795 | (unsigned)freq, |
796 | feedback_div, |
||
797 | reference_div, |
||
798 | post_divider); |
||
799 | |||
800 | pll_ref_div = reference_div; |
||
801 | #if defined(__powerpc__) && (0) /* TODO */ |
||
802 | /* apparently programming this otherwise causes a hang??? */ |
||
803 | if (info->MacModel == RADEON_MAC_IBOOK) |
||
804 | pll_fb_post_div = 0x000600ad; |
||
805 | else |
||
806 | #endif |
||
807 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
||
808 | |||
809 | htotal_cntl = mode->htotal & 0x7; |
||
810 | |||
811 | } |
||
812 | |||
813 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
||
814 | pll_ref_div & 0x3ff, |
||
815 | pll_fb_post_div & 0x7ff); |
||
816 | |||
817 | if (radeon_crtc->crtc_id) { |
||
818 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
||
819 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
||
820 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
||
821 | |||
1179 | serge | 822 | if (is_tv) { |
823 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
||
824 | &pll_ref_div, &pll_fb_post_div, |
||
825 | &pixclks_cntl); |
||
826 | } |
||
827 | |||
1123 | serge | 828 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
829 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
||
830 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
831 | |||
832 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
833 | RADEON_P2PLL_RESET |
||
834 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
835 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
||
836 | ~(RADEON_P2PLL_RESET |
||
837 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
838 | | RADEON_P2PLL_PVG_MASK)); |
||
839 | |||
840 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
||
841 | pll_ref_div, |
||
842 | ~RADEON_P2PLL_REF_DIV_MASK); |
||
843 | |||
844 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
845 | pll_fb_post_div, |
||
846 | ~RADEON_P2PLL_FB0_DIV_MASK); |
||
847 | |||
848 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
849 | pll_fb_post_div, |
||
850 | ~RADEON_P2PLL_POST0_DIV_MASK); |
||
851 | |||
852 | radeon_pll2_write_update(dev); |
||
853 | radeon_pll2_wait_for_read_update_complete(dev); |
||
854 | |||
855 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
||
856 | |||
857 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
858 | 0, |
||
859 | ~(RADEON_P2PLL_RESET |
||
860 | | RADEON_P2PLL_SLEEP |
||
861 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
||
862 | |||
1963 | serge | 863 | DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
1123 | serge | 864 | (unsigned)pll_ref_div, |
865 | (unsigned)pll_fb_post_div, |
||
866 | (unsigned)htotal_cntl, |
||
867 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
||
1963 | serge | 868 | DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n", |
1123 | serge | 869 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
870 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
||
871 | (unsigned)((pll_fb_post_div & |
||
872 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
||
873 | |||
874 | mdelay(50); /* Let the clock to lock */ |
||
875 | |||
876 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
||
877 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
||
878 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
879 | |||
880 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
881 | } else { |
||
1179 | serge | 882 | uint32_t pixclks_cntl; |
883 | |||
884 | |||
885 | if (is_tv) { |
||
886 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
887 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
||
888 | &pll_fb_post_div, &pixclks_cntl); |
||
889 | } |
||
890 | |||
1123 | serge | 891 | if (rdev->flags & RADEON_IS_MOBILITY) { |
1963 | serge | 892 | /* A temporal workaround for the occasional blanking on certain laptop panels. |
1123 | serge | 893 | This appears to related to the PLL divider registers (fail to lock?). |
894 | It occurs even when all dividers are the same with their old settings. |
||
895 | In this case we really don't need to fiddle with PLL registers. |
||
896 | By doing this we can avoid the blanking problem with some panels. |
||
897 | */ |
||
898 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
||
899 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
||
900 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
||
901 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
902 | RADEON_PLL_DIV_SEL, |
||
903 | ~(RADEON_PLL_DIV_SEL)); |
||
904 | r100_pll_errata_after_index(rdev); |
||
905 | return; |
||
906 | } |
||
907 | } |
||
908 | |||
909 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
910 | RADEON_VCLK_SRC_SEL_CPUCLK, |
||
911 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
912 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
913 | RADEON_PPLL_RESET |
||
914 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
915 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
916 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
||
917 | ~(RADEON_PPLL_RESET |
||
918 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
919 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
920 | | RADEON_PPLL_PVG_MASK)); |
||
921 | |||
922 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
923 | RADEON_PLL_DIV_SEL, |
||
924 | ~(RADEON_PLL_DIV_SEL)); |
||
925 | r100_pll_errata_after_index(rdev); |
||
926 | |||
927 | if (ASIC_IS_R300(rdev) || |
||
928 | (rdev->family == CHIP_RS300) || |
||
929 | (rdev->family == CHIP_RS400) || |
||
930 | (rdev->family == CHIP_RS480)) { |
||
931 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
||
932 | /* When restoring console mode, use saved PPLL_REF_DIV |
||
933 | * setting. |
||
934 | */ |
||
935 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
936 | pll_ref_div, |
||
937 | 0); |
||
938 | } else { |
||
939 | /* R300 uses ref_div_acc field as real ref divider */ |
||
940 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
941 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
||
942 | ~R300_PPLL_REF_DIV_ACC_MASK); |
||
943 | } |
||
944 | } else |
||
945 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
946 | pll_ref_div, |
||
947 | ~RADEON_PPLL_REF_DIV_MASK); |
||
948 | |||
949 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
950 | pll_fb_post_div, |
||
951 | ~RADEON_PPLL_FB3_DIV_MASK); |
||
952 | |||
953 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
954 | pll_fb_post_div, |
||
955 | ~RADEON_PPLL_POST3_DIV_MASK); |
||
956 | |||
957 | radeon_pll_write_update(dev); |
||
958 | radeon_pll_wait_for_read_update_complete(dev); |
||
959 | |||
960 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
||
961 | |||
962 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
963 | 0, |
||
964 | ~(RADEON_PPLL_RESET |
||
965 | | RADEON_PPLL_SLEEP |
||
966 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
967 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
||
968 | |||
1963 | serge | 969 | DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
1123 | serge | 970 | pll_ref_div, |
971 | pll_fb_post_div, |
||
972 | (unsigned)htotal_cntl, |
||
973 | RREG32_PLL(RADEON_PPLL_CNTL)); |
||
1963 | serge | 974 | DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n", |
1123 | serge | 975 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
976 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
||
977 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
||
978 | |||
979 | mdelay(50); /* Let the clock to lock */ |
||
980 | |||
981 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
982 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
||
983 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
984 | |||
1179 | serge | 985 | if (is_tv) |
986 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
1123 | serge | 987 | } |
988 | } |
||
989 | |||
990 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
||
991 | struct drm_display_mode *mode, |
||
992 | struct drm_display_mode *adjusted_mode) |
||
993 | { |
||
1963 | serge | 994 | struct drm_device *dev = crtc->dev; |
995 | struct radeon_device *rdev = dev->dev_private; |
||
996 | |||
997 | /* adjust pm to upcoming mode change */ |
||
998 | radeon_pm_compute_clocks(rdev); |
||
999 | |||
1179 | serge | 1000 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1001 | return false; |
||
1123 | serge | 1002 | return true; |
1003 | } |
||
1004 | |||
1005 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
||
1006 | struct drm_display_mode *mode, |
||
1007 | struct drm_display_mode *adjusted_mode, |
||
1008 | int x, int y, struct drm_framebuffer *old_fb) |
||
1009 | { |
||
1179 | serge | 1010 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1123 | serge | 1011 | |
1012 | /* TODO TV */ |
||
1013 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
1014 | radeon_set_crtc_timing(crtc, adjusted_mode); |
||
1015 | radeon_set_pll(crtc, adjusted_mode); |
||
1321 | serge | 1016 | radeon_overscan_setup(crtc, adjusted_mode); |
1179 | serge | 1017 | if (radeon_crtc->crtc_id == 0) { |
1404 | serge | 1018 | radeon_legacy_rmx_mode_set(crtc, adjusted_mode); |
1179 | serge | 1019 | } else { |
1020 | if (radeon_crtc->rmx_type != RMX_OFF) { |
||
1021 | /* FIXME: only first crtc has rmx what should we |
||
1022 | * do ? |
||
1023 | */ |
||
1024 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); |
||
1025 | } |
||
1026 | } |
||
1123 | serge | 1027 | return 0; |
1028 | } |
||
1029 | |||
1030 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
||
1031 | { |
||
1321 | serge | 1032 | struct drm_device *dev = crtc->dev; |
1033 | struct drm_crtc *crtci; |
||
1034 | |||
1035 | /* |
||
1036 | * The hardware wedges sometimes if you reconfigure one CRTC |
||
1037 | * whilst another is running (see fdo bug #24611). |
||
1038 | */ |
||
1039 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) |
||
1040 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF); |
||
1123 | serge | 1041 | } |
1042 | |||
1043 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
||
1044 | { |
||
1321 | serge | 1045 | struct drm_device *dev = crtc->dev; |
1046 | struct drm_crtc *crtci; |
||
1047 | |||
1048 | /* |
||
1049 | * Reenable the CRTCs that should be running. |
||
1050 | */ |
||
1051 | list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) { |
||
1052 | if (crtci->enabled) |
||
1053 | radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); |
||
1054 | } |
||
1123 | serge | 1055 | } |
1056 | |||
1057 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
||
1058 | .dpms = radeon_crtc_dpms, |
||
1059 | .mode_fixup = radeon_crtc_mode_fixup, |
||
1060 | .mode_set = radeon_crtc_mode_set, |
||
1061 | .mode_set_base = radeon_crtc_set_base, |
||
1963 | serge | 1062 | .mode_set_base_atomic = radeon_crtc_set_base_atomic, |
1123 | serge | 1063 | .prepare = radeon_crtc_prepare, |
1064 | .commit = radeon_crtc_commit, |
||
1221 | serge | 1065 | .load_lut = radeon_crtc_load_lut, |
1123 | serge | 1066 | }; |
1067 | |||
1068 | |||
1069 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
1070 | struct radeon_crtc *radeon_crtc) |
||
1071 | { |
||
1072 | if (radeon_crtc->crtc_id == 1) |
||
1073 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
||
1074 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
||
1075 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |