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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1179 | serge | 26 | #include |
27 | #include |
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28 | #include |
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1123 | serge | 29 | #include "radeon_fixed.h" |
30 | #include "radeon.h" |
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1179 | serge | 31 | #include "atom.h" |
1123 | serge | 32 | |
1179 | serge | 33 | static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc, |
34 | struct drm_display_mode *mode, |
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35 | struct drm_display_mode *adjusted_mode) |
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36 | { |
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37 | struct drm_device *dev = crtc->dev; |
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38 | struct radeon_device *rdev = dev->dev_private; |
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39 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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40 | int xres = mode->hdisplay; |
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41 | int yres = mode->vdisplay; |
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42 | bool hscale = true, vscale = true; |
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43 | int hsync_wid; |
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44 | int vsync_wid; |
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45 | int hsync_start; |
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46 | int blank_width; |
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47 | u32 scale, inc, crtc_more_cntl; |
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48 | u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; |
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49 | u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; |
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50 | u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; |
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51 | struct radeon_native_mode *native_mode = &radeon_crtc->native_mode; |
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52 | |||
53 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & |
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54 | (RADEON_VERT_STRETCH_RESERVED | |
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55 | RADEON_VERT_AUTO_RATIO_INC); |
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56 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) & |
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57 | (RADEON_HORZ_FP_LOOP_STRETCH | |
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58 | RADEON_HORZ_AUTO_RATIO_INC); |
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59 | |||
60 | crtc_more_cntl = 0; |
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61 | if ((rdev->family == CHIP_RS100) || |
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62 | (rdev->family == CHIP_RS200)) { |
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63 | /* This is to workaround the asic bug for RMX, some versions |
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64 | of BIOS dosen't have this register initialized correctly. */ |
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65 | crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN; |
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66 | } |
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67 | |||
68 | |||
69 | fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
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70 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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71 | |||
72 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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73 | if (!hsync_wid) |
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74 | hsync_wid = 1; |
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75 | hsync_start = mode->crtc_hsync_start - 8; |
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76 | |||
77 | fp_h_sync_strt_wid = ((hsync_start & 0x1fff) |
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78 | | ((hsync_wid & 0x3f) << 16) |
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79 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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80 | ? RADEON_CRTC_H_SYNC_POL |
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81 | : 0)); |
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82 | |||
83 | fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
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84 | | ((mode->crtc_vdisplay - 1) << 16)); |
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85 | |||
86 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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87 | if (!vsync_wid) |
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88 | vsync_wid = 1; |
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89 | |||
90 | fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
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91 | | ((vsync_wid & 0x1f) << 16) |
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92 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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93 | ? RADEON_CRTC_V_SYNC_POL |
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94 | : 0)); |
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95 | |||
96 | fp_horz_vert_active = 0; |
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97 | |||
98 | if (native_mode->panel_xres == 0 || |
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99 | native_mode->panel_yres == 0) { |
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100 | hscale = false; |
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101 | vscale = false; |
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102 | } else { |
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103 | if (xres > native_mode->panel_xres) |
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104 | xres = native_mode->panel_xres; |
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105 | if (yres > native_mode->panel_yres) |
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106 | yres = native_mode->panel_yres; |
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107 | |||
108 | if (xres == native_mode->panel_xres) |
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109 | hscale = false; |
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110 | if (yres == native_mode->panel_yres) |
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111 | vscale = false; |
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112 | } |
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113 | |||
114 | switch (radeon_crtc->rmx_type) { |
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115 | case RMX_FULL: |
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116 | case RMX_ASPECT: |
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117 | if (!hscale) |
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118 | fp_horz_stretch |= ((xres/8-1) << 16); |
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119 | else { |
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120 | inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; |
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121 | scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) |
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122 | / native_mode->panel_xres + 1; |
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123 | fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | |
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124 | RADEON_HORZ_STRETCH_BLEND | |
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125 | RADEON_HORZ_STRETCH_ENABLE | |
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126 | ((native_mode->panel_xres/8-1) << 16)); |
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127 | } |
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128 | |||
129 | if (!vscale) |
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130 | fp_vert_stretch |= ((yres-1) << 12); |
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131 | else { |
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132 | inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; |
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133 | scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) |
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134 | / native_mode->panel_yres + 1; |
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135 | fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | |
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136 | RADEON_VERT_STRETCH_ENABLE | |
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137 | RADEON_VERT_STRETCH_BLEND | |
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138 | ((native_mode->panel_yres-1) << 12)); |
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139 | } |
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140 | break; |
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141 | case RMX_CENTER: |
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142 | fp_horz_stretch |= ((xres/8-1) << 16); |
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143 | fp_vert_stretch |= ((yres-1) << 12); |
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144 | |||
145 | crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN | |
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146 | RADEON_CRTC_AUTO_VERT_CENTER_EN); |
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147 | |||
148 | blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8; |
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149 | if (blank_width > 110) |
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150 | blank_width = 110; |
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151 | |||
152 | fp_crtc_h_total_disp = (((blank_width) & 0x3ff) |
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153 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
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154 | |||
155 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
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156 | if (!hsync_wid) |
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157 | hsync_wid = 1; |
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158 | |||
159 | fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff) |
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160 | | ((hsync_wid & 0x3f) << 16) |
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161 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
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162 | ? RADEON_CRTC_H_SYNC_POL |
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163 | : 0)); |
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164 | |||
165 | fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff) |
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166 | | ((mode->crtc_vdisplay - 1) << 16)); |
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167 | |||
168 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
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169 | if (!vsync_wid) |
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170 | vsync_wid = 1; |
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171 | |||
172 | fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff) |
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173 | | ((vsync_wid & 0x1f) << 16) |
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174 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
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175 | ? RADEON_CRTC_V_SYNC_POL |
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176 | : 0))); |
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177 | |||
178 | fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) | |
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179 | (((native_mode->panel_xres / 8) & 0x1ff) << 16)); |
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180 | break; |
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181 | case RMX_OFF: |
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182 | default: |
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183 | fp_horz_stretch |= ((xres/8-1) << 16); |
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184 | fp_vert_stretch |= ((yres-1) << 12); |
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185 | break; |
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186 | } |
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187 | |||
188 | WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch); |
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189 | WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch); |
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190 | WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl); |
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191 | WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active); |
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192 | WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid); |
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193 | WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid); |
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194 | WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp); |
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195 | WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp); |
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196 | } |
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197 | |||
1123 | serge | 198 | void radeon_restore_common_regs(struct drm_device *dev) |
199 | { |
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200 | /* don't need this yet */ |
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201 | } |
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202 | |||
203 | static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev) |
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204 | { |
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205 | struct radeon_device *rdev = dev->dev_private; |
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206 | int i = 0; |
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207 | |||
208 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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209 | the cause yet, but this workaround will mask the problem for now. |
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210 | Other chips usually will pass at the very first test, so the |
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211 | workaround shouldn't have any effect on them. */ |
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212 | for (i = 0; |
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213 | (i < 10000 && |
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214 | RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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215 | i++); |
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216 | } |
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217 | |||
218 | static void radeon_pll_write_update(struct drm_device *dev) |
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219 | { |
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220 | struct radeon_device *rdev = dev->dev_private; |
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221 | |||
222 | while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); |
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223 | |||
224 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
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225 | RADEON_PPLL_ATOMIC_UPDATE_W, |
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226 | ~(RADEON_PPLL_ATOMIC_UPDATE_W)); |
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227 | } |
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228 | |||
229 | static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev) |
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230 | { |
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231 | struct radeon_device *rdev = dev->dev_private; |
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232 | int i = 0; |
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233 | |||
234 | |||
235 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of |
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236 | the cause yet, but this workaround will mask the problem for now. |
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237 | Other chips usually will pass at the very first test, so the |
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238 | workaround shouldn't have any effect on them. */ |
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239 | for (i = 0; |
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240 | (i < 10000 && |
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241 | RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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242 | i++); |
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243 | } |
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244 | |||
245 | static void radeon_pll2_write_update(struct drm_device *dev) |
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246 | { |
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247 | struct radeon_device *rdev = dev->dev_private; |
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248 | |||
249 | while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); |
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250 | |||
251 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
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252 | RADEON_P2PLL_ATOMIC_UPDATE_W, |
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253 | ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); |
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254 | } |
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255 | |||
256 | static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, |
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257 | uint16_t fb_div) |
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258 | { |
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259 | unsigned int vcoFreq; |
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260 | |||
261 | if (!ref_div) |
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262 | return 1; |
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263 | |||
264 | vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div; |
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265 | |||
266 | /* |
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267 | * This is horribly crude: the VCO frequency range is divided into |
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268 | * 3 parts, each part having a fixed PLL gain value. |
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269 | */ |
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270 | if (vcoFreq >= 30000) |
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271 | /* |
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272 | * [300..max] MHz : 7 |
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273 | */ |
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274 | return 7; |
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275 | else if (vcoFreq >= 18000) |
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276 | /* |
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277 | * [180..300) MHz : 4 |
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278 | */ |
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279 | return 4; |
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280 | else |
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281 | /* |
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282 | * [0..180) MHz : 1 |
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283 | */ |
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284 | return 1; |
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285 | } |
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286 | |||
287 | void radeon_crtc_dpms(struct drm_crtc *crtc, int mode) |
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288 | { |
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289 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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290 | struct drm_device *dev = crtc->dev; |
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291 | struct radeon_device *rdev = dev->dev_private; |
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292 | uint32_t mask; |
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293 | |||
294 | if (radeon_crtc->crtc_id) |
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295 | mask = (RADEON_CRTC2_EN | |
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296 | RADEON_CRTC2_DISP_DIS | |
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297 | RADEON_CRTC2_VSYNC_DIS | |
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298 | RADEON_CRTC2_HSYNC_DIS | |
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299 | RADEON_CRTC2_DISP_REQ_EN_B); |
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300 | else |
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301 | mask = (RADEON_CRTC_DISPLAY_DIS | |
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302 | RADEON_CRTC_VSYNC_DIS | |
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303 | RADEON_CRTC_HSYNC_DIS); |
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304 | |||
305 | switch (mode) { |
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306 | case DRM_MODE_DPMS_ON: |
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307 | if (radeon_crtc->crtc_id) |
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308 | WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); |
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309 | else { |
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310 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | |
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311 | RADEON_CRTC_DISP_REQ_EN_B)); |
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312 | WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); |
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313 | } |
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1179 | serge | 314 | // drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
315 | radeon_crtc_load_lut(crtc); |
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1123 | serge | 316 | break; |
317 | case DRM_MODE_DPMS_STANDBY: |
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318 | case DRM_MODE_DPMS_SUSPEND: |
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319 | case DRM_MODE_DPMS_OFF: |
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1179 | serge | 320 | // drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
1123 | serge | 321 | if (radeon_crtc->crtc_id) |
322 | WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); |
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323 | else { |
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324 | WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | |
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325 | RADEON_CRTC_DISP_REQ_EN_B)); |
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326 | WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask); |
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327 | } |
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328 | break; |
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329 | } |
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330 | } |
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331 | |||
332 | /* properly set crtc bpp when using atombios */ |
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333 | void radeon_legacy_atom_set_surface(struct drm_crtc *crtc) |
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334 | { |
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335 | struct drm_device *dev = crtc->dev; |
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336 | struct radeon_device *rdev = dev->dev_private; |
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337 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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338 | int format; |
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339 | uint32_t crtc_gen_cntl; |
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340 | uint32_t disp_merge_cntl; |
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341 | uint32_t crtc_pitch; |
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342 | |||
343 | switch (crtc->fb->bits_per_pixel) { |
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1179 | serge | 344 | case 8: |
345 | format = 2; |
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346 | break; |
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1123 | serge | 347 | case 15: /* 555 */ |
348 | format = 3; |
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349 | break; |
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350 | case 16: /* 565 */ |
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351 | format = 4; |
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352 | break; |
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353 | case 24: /* RGB */ |
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354 | format = 5; |
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355 | break; |
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356 | case 32: /* xRGB */ |
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357 | format = 6; |
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358 | break; |
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359 | default: |
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360 | return; |
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361 | } |
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362 | |||
363 | crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) + |
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364 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
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365 | (crtc->fb->bits_per_pixel * 8)); |
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366 | crtc_pitch |= crtc_pitch << 16; |
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367 | |||
368 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
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369 | |||
370 | switch (radeon_crtc->crtc_id) { |
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371 | case 0: |
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372 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
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373 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
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374 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
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375 | |||
376 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; |
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377 | crtc_gen_cntl |= (format << 8); |
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378 | crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN; |
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379 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
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380 | break; |
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381 | case 1: |
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382 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
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383 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
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384 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
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385 | |||
386 | crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; |
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387 | crtc_gen_cntl |= (format << 8); |
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388 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl); |
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389 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
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390 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
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391 | break; |
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392 | } |
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393 | } |
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394 | |||
395 | int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
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396 | struct drm_framebuffer *old_fb) |
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397 | { |
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398 | struct drm_device *dev = crtc->dev; |
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399 | struct radeon_device *rdev = dev->dev_private; |
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400 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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401 | struct radeon_framebuffer *radeon_fb; |
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402 | struct drm_gem_object *obj; |
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403 | uint64_t base; |
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404 | uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0; |
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405 | uint32_t crtc_pitch, pitch_pixels; |
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1179 | serge | 406 | uint32_t tiling_flags; |
407 | int format; |
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408 | uint32_t gen_cntl_reg, gen_cntl_val; |
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1123 | serge | 409 | |
410 | DRM_DEBUG("\n"); |
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411 | |||
412 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
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413 | |||
1179 | serge | 414 | switch (crtc->fb->bits_per_pixel) { |
415 | case 8: |
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416 | format = 2; |
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417 | break; |
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418 | case 15: /* 555 */ |
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419 | format = 3; |
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420 | break; |
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421 | case 16: /* 565 */ |
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422 | format = 4; |
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423 | break; |
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424 | case 24: /* RGB */ |
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425 | format = 5; |
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426 | break; |
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427 | case 32: /* xRGB */ |
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428 | format = 6; |
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429 | break; |
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430 | default: |
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431 | return false; |
||
432 | } |
||
433 | |||
1123 | serge | 434 | obj = radeon_fb->obj; |
435 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) { |
||
436 | // return -EINVAL; |
||
437 | // } |
||
1179 | serge | 438 | /* if scanout was in GTT this really wouldn't work */ |
439 | /* crtc offset is from display base addr not FB location */ |
||
440 | radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location; |
||
441 | |||
442 | base -= radeon_crtc->legacy_display_base_addr; |
||
443 | |||
1123 | serge | 444 | crtc_offset_cntl = 0; |
445 | |||
446 | pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
||
447 | crtc_pitch = (((pitch_pixels * crtc->fb->bits_per_pixel) + |
||
448 | ((crtc->fb->bits_per_pixel * 8) - 1)) / |
||
449 | (crtc->fb->bits_per_pixel * 8)); |
||
450 | crtc_pitch |= crtc_pitch << 16; |
||
451 | |||
1179 | serge | 452 | // radeon_object_get_tiling_flags(obj->driver_private, |
453 | // &tiling_flags, NULL); |
||
454 | if (tiling_flags & RADEON_TILING_MICRO) |
||
455 | DRM_ERROR("trying to scanout microtiled buffer\n"); |
||
456 | |||
457 | if (tiling_flags & RADEON_TILING_MACRO) { |
||
1123 | serge | 458 | if (ASIC_IS_R300(rdev)) |
459 | crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | |
||
460 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
461 | R300_CRTC_MACRO_TILE_EN); |
||
462 | else |
||
463 | crtc_offset_cntl |= RADEON_CRTC_TILE_EN; |
||
464 | } else { |
||
465 | if (ASIC_IS_R300(rdev)) |
||
466 | crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | |
||
467 | R300_CRTC_MICRO_TILE_BUFFER_DIS | |
||
468 | R300_CRTC_MACRO_TILE_EN); |
||
469 | else |
||
470 | crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; |
||
471 | } |
||
472 | |||
1179 | serge | 473 | if (tiling_flags & RADEON_TILING_MACRO) { |
1123 | serge | 474 | if (ASIC_IS_R300(rdev)) { |
475 | crtc_tile_x0_y0 = x | (y << 16); |
||
476 | base &= ~0x7ff; |
||
477 | } else { |
||
478 | int byteshift = crtc->fb->bits_per_pixel >> 4; |
||
1179 | serge | 479 | int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11; |
1123 | serge | 480 | base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); |
481 | crtc_offset_cntl |= (y % 16); |
||
482 | } |
||
483 | } else { |
||
484 | int offset = y * pitch_pixels + x; |
||
485 | switch (crtc->fb->bits_per_pixel) { |
||
1179 | serge | 486 | case 8: |
487 | offset *= 1; |
||
488 | break; |
||
1123 | serge | 489 | case 15: |
490 | case 16: |
||
491 | offset *= 2; |
||
492 | break; |
||
493 | case 24: |
||
494 | offset *= 3; |
||
495 | break; |
||
496 | case 32: |
||
497 | offset *= 4; |
||
498 | break; |
||
499 | default: |
||
500 | return false; |
||
501 | } |
||
502 | base += offset; |
||
503 | } |
||
504 | |||
505 | base &= ~7; |
||
506 | |||
1179 | serge | 507 | if (radeon_crtc->crtc_id == 1) |
508 | gen_cntl_reg = RADEON_CRTC2_GEN_CNTL; |
||
509 | else |
||
510 | gen_cntl_reg = RADEON_CRTC_GEN_CNTL; |
||
1123 | serge | 511 | |
1179 | serge | 512 | gen_cntl_val = RREG32(gen_cntl_reg); |
513 | gen_cntl_val &= ~(0xf << 8); |
||
514 | gen_cntl_val |= (format << 8); |
||
515 | WREG32(gen_cntl_reg, gen_cntl_val); |
||
516 | |||
1123 | serge | 517 | crtc_offset = (u32)base; |
518 | |||
1179 | serge | 519 | WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr); |
1123 | serge | 520 | |
521 | if (ASIC_IS_R300(rdev)) { |
||
522 | if (radeon_crtc->crtc_id) |
||
523 | WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0); |
||
524 | else |
||
525 | WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0); |
||
526 | } |
||
527 | WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl); |
||
528 | WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset); |
||
529 | WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); |
||
530 | |||
531 | if (old_fb && old_fb != crtc->fb) { |
||
532 | radeon_fb = to_radeon_framebuffer(old_fb); |
||
533 | // radeon_gem_object_unpin(radeon_fb->obj); |
||
534 | } |
||
535 | return 0; |
||
536 | } |
||
537 | |||
538 | static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
539 | { |
||
540 | struct drm_device *dev = crtc->dev; |
||
541 | struct radeon_device *rdev = dev->dev_private; |
||
542 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1179 | serge | 543 | struct drm_encoder *encoder; |
1123 | serge | 544 | int format; |
545 | int hsync_start; |
||
546 | int hsync_wid; |
||
547 | int vsync_wid; |
||
548 | uint32_t crtc_h_total_disp; |
||
549 | uint32_t crtc_h_sync_strt_wid; |
||
550 | uint32_t crtc_v_total_disp; |
||
551 | uint32_t crtc_v_sync_strt_wid; |
||
1179 | serge | 552 | bool is_tv = false; |
1123 | serge | 553 | |
554 | DRM_DEBUG("\n"); |
||
1179 | serge | 555 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
556 | if (encoder->crtc == crtc) { |
||
557 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
558 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
559 | is_tv = true; |
||
560 | DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id); |
||
561 | break; |
||
562 | } |
||
563 | } |
||
564 | } |
||
1123 | serge | 565 | |
566 | switch (crtc->fb->bits_per_pixel) { |
||
1179 | serge | 567 | case 8: |
568 | format = 2; |
||
569 | break; |
||
1123 | serge | 570 | case 15: /* 555 */ |
571 | format = 3; |
||
572 | break; |
||
573 | case 16: /* 565 */ |
||
574 | format = 4; |
||
575 | break; |
||
576 | case 24: /* RGB */ |
||
577 | format = 5; |
||
578 | break; |
||
579 | case 32: /* xRGB */ |
||
580 | format = 6; |
||
581 | break; |
||
582 | default: |
||
583 | return false; |
||
584 | } |
||
585 | |||
586 | crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff) |
||
587 | | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16)); |
||
588 | |||
589 | hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8; |
||
590 | if (!hsync_wid) |
||
591 | hsync_wid = 1; |
||
592 | hsync_start = mode->crtc_hsync_start - 8; |
||
593 | |||
594 | crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
||
595 | | ((hsync_wid & 0x3f) << 16) |
||
596 | | ((mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
597 | ? RADEON_CRTC_H_SYNC_POL |
||
598 | : 0)); |
||
599 | |||
600 | /* This works for double scan mode. */ |
||
601 | crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff) |
||
602 | | ((mode->crtc_vdisplay - 1) << 16)); |
||
603 | |||
604 | vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start; |
||
605 | if (!vsync_wid) |
||
606 | vsync_wid = 1; |
||
607 | |||
608 | crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff) |
||
609 | | ((vsync_wid & 0x1f) << 16) |
||
610 | | ((mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
611 | ? RADEON_CRTC_V_SYNC_POL |
||
612 | : 0)); |
||
613 | |||
614 | /* TODO -> Dell Server */ |
||
615 | if (0) { |
||
616 | uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
||
617 | uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
||
618 | uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
||
619 | uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
||
620 | |||
621 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
||
622 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
||
623 | |||
624 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
||
625 | enable it, even it's detected. |
||
626 | */ |
||
627 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
||
628 | tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); |
||
629 | tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); |
||
630 | |||
631 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
||
632 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
||
633 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
634 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
635 | } |
||
636 | |||
637 | if (radeon_crtc->crtc_id) { |
||
638 | uint32_t crtc2_gen_cntl; |
||
639 | uint32_t disp2_merge_cntl; |
||
640 | |||
641 | /* check to see if TV DAC is enabled for another crtc and keep it enabled */ |
||
642 | if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON) |
||
643 | crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; |
||
644 | else |
||
645 | crtc2_gen_cntl = 0; |
||
646 | |||
647 | crtc2_gen_cntl |= ((format << 8) |
||
648 | | RADEON_CRTC2_VSYNC_DIS |
||
649 | | RADEON_CRTC2_HSYNC_DIS |
||
650 | | RADEON_CRTC2_DISP_DIS |
||
651 | | RADEON_CRTC2_DISP_REQ_EN_B |
||
652 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
653 | ? RADEON_CRTC2_DBL_SCAN_EN |
||
654 | : 0) |
||
655 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
656 | ? RADEON_CRTC2_CSYNC_EN |
||
657 | : 0) |
||
658 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
659 | ? RADEON_CRTC2_INTERLACE_EN |
||
660 | : 0)); |
||
661 | |||
662 | disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
||
663 | disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
||
664 | |||
665 | WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); |
||
666 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
||
667 | } else { |
||
668 | uint32_t crtc_gen_cntl; |
||
669 | uint32_t crtc_ext_cntl; |
||
670 | uint32_t disp_merge_cntl; |
||
671 | |||
672 | crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN |
||
673 | | (format << 8) |
||
674 | | RADEON_CRTC_DISP_REQ_EN_B |
||
675 | | ((mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
676 | ? RADEON_CRTC_DBL_SCAN_EN |
||
677 | : 0) |
||
678 | | ((mode->flags & DRM_MODE_FLAG_CSYNC) |
||
679 | ? RADEON_CRTC_CSYNC_EN |
||
680 | : 0) |
||
681 | | ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
682 | ? RADEON_CRTC_INTERLACE_EN |
||
683 | : 0)); |
||
684 | |||
685 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
||
686 | crtc_ext_cntl |= (RADEON_XCRT_CNT_EN | |
||
687 | RADEON_CRTC_VSYNC_DIS | |
||
688 | RADEON_CRTC_HSYNC_DIS | |
||
689 | RADEON_CRTC_DISPLAY_DIS); |
||
690 | |||
691 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
||
692 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
||
693 | |||
694 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
||
695 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
||
696 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
||
697 | } |
||
698 | |||
1179 | serge | 699 | if (is_tv) |
700 | radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp, |
||
701 | &crtc_h_sync_strt_wid, &crtc_v_total_disp, |
||
702 | &crtc_v_sync_strt_wid); |
||
703 | |||
1123 | serge | 704 | WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp); |
705 | WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid); |
||
706 | WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp); |
||
707 | WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid); |
||
708 | |||
709 | return true; |
||
710 | } |
||
711 | |||
712 | static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
||
713 | { |
||
714 | struct drm_device *dev = crtc->dev; |
||
715 | struct radeon_device *rdev = dev->dev_private; |
||
716 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
717 | struct drm_encoder *encoder; |
||
718 | uint32_t feedback_div = 0; |
||
719 | uint32_t frac_fb_div = 0; |
||
720 | uint32_t reference_div = 0; |
||
721 | uint32_t post_divider = 0; |
||
722 | uint32_t freq = 0; |
||
723 | uint8_t pll_gain; |
||
724 | int pll_flags = RADEON_PLL_LEGACY; |
||
725 | bool use_bios_divs = false; |
||
726 | /* PLL registers */ |
||
727 | uint32_t pll_ref_div = 0; |
||
728 | uint32_t pll_fb_post_div = 0; |
||
729 | uint32_t htotal_cntl = 0; |
||
1179 | serge | 730 | bool is_tv = false; |
1123 | serge | 731 | struct radeon_pll *pll; |
732 | |||
733 | struct { |
||
734 | int divider; |
||
735 | int bitvalue; |
||
736 | } *post_div, post_divs[] = { |
||
737 | /* From RAGE 128 VR/RAGE 128 GL Register |
||
738 | * Reference Manual (Technical Reference |
||
739 | * Manual P/N RRG-G04100-C Rev. 0.04), page |
||
740 | * 3-17 (PLL_DIV_[3:0]). |
||
741 | */ |
||
742 | { 1, 0 }, /* VCLK_SRC */ |
||
743 | { 2, 1 }, /* VCLK_SRC/2 */ |
||
744 | { 4, 2 }, /* VCLK_SRC/4 */ |
||
745 | { 8, 3 }, /* VCLK_SRC/8 */ |
||
746 | { 3, 4 }, /* VCLK_SRC/3 */ |
||
747 | { 16, 5 }, /* VCLK_SRC/16 */ |
||
748 | { 6, 6 }, /* VCLK_SRC/6 */ |
||
749 | { 12, 7 }, /* VCLK_SRC/12 */ |
||
750 | { 0, 0 } |
||
751 | }; |
||
752 | |||
753 | if (radeon_crtc->crtc_id) |
||
754 | pll = &rdev->clock.p2pll; |
||
755 | else |
||
756 | pll = &rdev->clock.p1pll; |
||
757 | |||
758 | if (mode->clock > 200000) /* range limits??? */ |
||
759 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
||
760 | else |
||
761 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
||
762 | |||
763 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
764 | if (encoder->crtc == crtc) { |
||
1179 | serge | 765 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
766 | |||
767 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
||
768 | is_tv = true; |
||
769 | break; |
||
770 | } |
||
771 | |||
1123 | serge | 772 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
773 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
||
774 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { |
||
775 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
776 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
||
777 | if (lvds) { |
||
778 | if (lvds->use_bios_dividers) { |
||
779 | pll_ref_div = lvds->panel_ref_divider; |
||
780 | pll_fb_post_div = (lvds->panel_fb_divider | |
||
781 | (lvds->panel_post_divider << 16)); |
||
782 | htotal_cntl = 0; |
||
783 | use_bios_divs = true; |
||
784 | } |
||
785 | } |
||
786 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
||
787 | } |
||
788 | } |
||
789 | } |
||
790 | |||
791 | DRM_DEBUG("\n"); |
||
792 | |||
793 | if (!use_bios_divs) { |
||
794 | radeon_compute_pll(pll, mode->clock, |
||
795 | &freq, &feedback_div, &frac_fb_div, |
||
796 | &reference_div, &post_divider, |
||
797 | pll_flags); |
||
798 | |||
799 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { |
||
800 | if (post_div->divider == post_divider) |
||
801 | break; |
||
802 | } |
||
803 | |||
804 | if (!post_div->divider) |
||
805 | post_div = &post_divs[0]; |
||
806 | |||
807 | DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n", |
||
808 | (unsigned)freq, |
||
809 | feedback_div, |
||
810 | reference_div, |
||
811 | post_divider); |
||
812 | |||
813 | pll_ref_div = reference_div; |
||
814 | #if defined(__powerpc__) && (0) /* TODO */ |
||
815 | /* apparently programming this otherwise causes a hang??? */ |
||
816 | if (info->MacModel == RADEON_MAC_IBOOK) |
||
817 | pll_fb_post_div = 0x000600ad; |
||
818 | else |
||
819 | #endif |
||
820 | pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); |
||
821 | |||
822 | htotal_cntl = mode->htotal & 0x7; |
||
823 | |||
824 | } |
||
825 | |||
826 | pll_gain = radeon_compute_pll_gain(pll->reference_freq, |
||
827 | pll_ref_div & 0x3ff, |
||
828 | pll_fb_post_div & 0x7ff); |
||
829 | |||
830 | if (radeon_crtc->crtc_id) { |
||
831 | uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & |
||
832 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | |
||
833 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); |
||
834 | |||
1179 | serge | 835 | if (is_tv) { |
836 | radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl, |
||
837 | &pll_ref_div, &pll_fb_post_div, |
||
838 | &pixclks_cntl); |
||
839 | } |
||
840 | |||
1123 | serge | 841 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
842 | RADEON_PIX2CLK_SRC_SEL_CPUCLK, |
||
843 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
844 | |||
845 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
846 | RADEON_P2PLL_RESET |
||
847 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
848 | | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT), |
||
849 | ~(RADEON_P2PLL_RESET |
||
850 | | RADEON_P2PLL_ATOMIC_UPDATE_EN |
||
851 | | RADEON_P2PLL_PVG_MASK)); |
||
852 | |||
853 | WREG32_PLL_P(RADEON_P2PLL_REF_DIV, |
||
854 | pll_ref_div, |
||
855 | ~RADEON_P2PLL_REF_DIV_MASK); |
||
856 | |||
857 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
858 | pll_fb_post_div, |
||
859 | ~RADEON_P2PLL_FB0_DIV_MASK); |
||
860 | |||
861 | WREG32_PLL_P(RADEON_P2PLL_DIV_0, |
||
862 | pll_fb_post_div, |
||
863 | ~RADEON_P2PLL_POST0_DIV_MASK); |
||
864 | |||
865 | radeon_pll2_write_update(dev); |
||
866 | radeon_pll2_wait_for_read_update_complete(dev); |
||
867 | |||
868 | WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); |
||
869 | |||
870 | WREG32_PLL_P(RADEON_P2PLL_CNTL, |
||
871 | 0, |
||
872 | ~(RADEON_P2PLL_RESET |
||
873 | | RADEON_P2PLL_SLEEP |
||
874 | | RADEON_P2PLL_ATOMIC_UPDATE_EN)); |
||
875 | |||
876 | DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
||
877 | (unsigned)pll_ref_div, |
||
878 | (unsigned)pll_fb_post_div, |
||
879 | (unsigned)htotal_cntl, |
||
880 | RREG32_PLL(RADEON_P2PLL_CNTL)); |
||
881 | DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n", |
||
882 | (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, |
||
883 | (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK, |
||
884 | (unsigned)((pll_fb_post_div & |
||
885 | RADEON_P2PLL_POST0_DIV_MASK) >> 16)); |
||
886 | |||
887 | mdelay(50); /* Let the clock to lock */ |
||
888 | |||
889 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, |
||
890 | RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, |
||
891 | ~(RADEON_PIX2CLK_SRC_SEL_MASK)); |
||
892 | |||
893 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
894 | } else { |
||
1179 | serge | 895 | uint32_t pixclks_cntl; |
896 | |||
897 | |||
898 | if (is_tv) { |
||
899 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
900 | radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, |
||
901 | &pll_fb_post_div, &pixclks_cntl); |
||
902 | } |
||
903 | |||
1123 | serge | 904 | if (rdev->flags & RADEON_IS_MOBILITY) { |
905 | /* A temporal workaround for the occational blanking on certain laptop panels. |
||
906 | This appears to related to the PLL divider registers (fail to lock?). |
||
907 | It occurs even when all dividers are the same with their old settings. |
||
908 | In this case we really don't need to fiddle with PLL registers. |
||
909 | By doing this we can avoid the blanking problem with some panels. |
||
910 | */ |
||
911 | if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && |
||
912 | (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & |
||
913 | (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { |
||
914 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
915 | RADEON_PLL_DIV_SEL, |
||
916 | ~(RADEON_PLL_DIV_SEL)); |
||
917 | r100_pll_errata_after_index(rdev); |
||
918 | return; |
||
919 | } |
||
920 | } |
||
921 | |||
922 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
923 | RADEON_VCLK_SRC_SEL_CPUCLK, |
||
924 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
925 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
926 | RADEON_PPLL_RESET |
||
927 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
928 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
929 | | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT), |
||
930 | ~(RADEON_PPLL_RESET |
||
931 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
932 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN |
||
933 | | RADEON_PPLL_PVG_MASK)); |
||
934 | |||
935 | WREG32_P(RADEON_CLOCK_CNTL_INDEX, |
||
936 | RADEON_PLL_DIV_SEL, |
||
937 | ~(RADEON_PLL_DIV_SEL)); |
||
938 | r100_pll_errata_after_index(rdev); |
||
939 | |||
940 | if (ASIC_IS_R300(rdev) || |
||
941 | (rdev->family == CHIP_RS300) || |
||
942 | (rdev->family == CHIP_RS400) || |
||
943 | (rdev->family == CHIP_RS480)) { |
||
944 | if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
||
945 | /* When restoring console mode, use saved PPLL_REF_DIV |
||
946 | * setting. |
||
947 | */ |
||
948 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
949 | pll_ref_div, |
||
950 | 0); |
||
951 | } else { |
||
952 | /* R300 uses ref_div_acc field as real ref divider */ |
||
953 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
954 | (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), |
||
955 | ~R300_PPLL_REF_DIV_ACC_MASK); |
||
956 | } |
||
957 | } else |
||
958 | WREG32_PLL_P(RADEON_PPLL_REF_DIV, |
||
959 | pll_ref_div, |
||
960 | ~RADEON_PPLL_REF_DIV_MASK); |
||
961 | |||
962 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
963 | pll_fb_post_div, |
||
964 | ~RADEON_PPLL_FB3_DIV_MASK); |
||
965 | |||
966 | WREG32_PLL_P(RADEON_PPLL_DIV_3, |
||
967 | pll_fb_post_div, |
||
968 | ~RADEON_PPLL_POST3_DIV_MASK); |
||
969 | |||
970 | radeon_pll_write_update(dev); |
||
971 | radeon_pll_wait_for_read_update_complete(dev); |
||
972 | |||
973 | WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); |
||
974 | |||
975 | WREG32_PLL_P(RADEON_PPLL_CNTL, |
||
976 | 0, |
||
977 | ~(RADEON_PPLL_RESET |
||
978 | | RADEON_PPLL_SLEEP |
||
979 | | RADEON_PPLL_ATOMIC_UPDATE_EN |
||
980 | | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); |
||
981 | |||
982 | DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", |
||
983 | pll_ref_div, |
||
984 | pll_fb_post_div, |
||
985 | (unsigned)htotal_cntl, |
||
986 | RREG32_PLL(RADEON_PPLL_CNTL)); |
||
987 | DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n", |
||
988 | pll_ref_div & RADEON_PPLL_REF_DIV_MASK, |
||
989 | pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK, |
||
990 | (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16); |
||
991 | |||
992 | mdelay(50); /* Let the clock to lock */ |
||
993 | |||
994 | WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, |
||
995 | RADEON_VCLK_SRC_SEL_PPLLCLK, |
||
996 | ~(RADEON_VCLK_SRC_SEL_MASK)); |
||
997 | |||
1179 | serge | 998 | if (is_tv) |
999 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
||
1123 | serge | 1000 | } |
1001 | } |
||
1002 | |||
1003 | static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc, |
||
1004 | struct drm_display_mode *mode, |
||
1005 | struct drm_display_mode *adjusted_mode) |
||
1006 | { |
||
1179 | serge | 1007 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1008 | return false; |
||
1123 | serge | 1009 | return true; |
1010 | } |
||
1011 | |||
1012 | static int radeon_crtc_mode_set(struct drm_crtc *crtc, |
||
1013 | struct drm_display_mode *mode, |
||
1014 | struct drm_display_mode *adjusted_mode, |
||
1015 | int x, int y, struct drm_framebuffer *old_fb) |
||
1016 | { |
||
1179 | serge | 1017 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1018 | struct drm_device *dev = crtc->dev; |
||
1019 | struct radeon_device *rdev = dev->dev_private; |
||
1123 | serge | 1020 | |
1021 | /* TODO TV */ |
||
1022 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
1023 | radeon_set_crtc_timing(crtc, adjusted_mode); |
||
1024 | radeon_set_pll(crtc, adjusted_mode); |
||
1179 | serge | 1025 | radeon_bandwidth_update(rdev); |
1026 | if (radeon_crtc->crtc_id == 0) { |
||
1027 | radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); |
||
1028 | } else { |
||
1029 | if (radeon_crtc->rmx_type != RMX_OFF) { |
||
1030 | /* FIXME: only first crtc has rmx what should we |
||
1031 | * do ? |
||
1032 | */ |
||
1033 | DRM_ERROR("Mode need scaling but only first crtc can do that.\n"); |
||
1034 | } |
||
1035 | } |
||
1123 | serge | 1036 | return 0; |
1037 | } |
||
1038 | |||
1039 | static void radeon_crtc_prepare(struct drm_crtc *crtc) |
||
1040 | { |
||
1041 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
||
1042 | } |
||
1043 | |||
1044 | static void radeon_crtc_commit(struct drm_crtc *crtc) |
||
1045 | { |
||
1046 | radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
||
1047 | } |
||
1048 | |||
1049 | static const struct drm_crtc_helper_funcs legacy_helper_funcs = { |
||
1050 | .dpms = radeon_crtc_dpms, |
||
1051 | .mode_fixup = radeon_crtc_mode_fixup, |
||
1052 | .mode_set = radeon_crtc_mode_set, |
||
1053 | .mode_set_base = radeon_crtc_set_base, |
||
1054 | .prepare = radeon_crtc_prepare, |
||
1055 | .commit = radeon_crtc_commit, |
||
1056 | }; |
||
1057 | |||
1058 | |||
1059 | void radeon_legacy_init_crtc(struct drm_device *dev, |
||
1060 | struct radeon_crtc *radeon_crtc) |
||
1061 | { |
||
1062 | if (radeon_crtc->crtc_id == 1) |
||
1063 | radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP; |
||
1064 | drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs); |
||
1065 | }><>><>><>><>><>><>><>16)); |