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1125 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Jerome Glisse |
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29 | * Dave Airlie |
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30 | */ |
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31 | #include |
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32 | #include |
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2004 | serge | 33 | //#include |
1125 | serge | 34 | #include |
35 | #include |
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1986 | serge | 36 | #include |
1125 | serge | 37 | #include "drmP.h" |
38 | #include "drm.h" |
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39 | #include "radeon_reg.h" |
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40 | #include "radeon.h" |
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41 | |||
2004 | serge | 42 | static void radeon_fence_write(struct radeon_device *rdev, u32 seq) |
43 | { |
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44 | if (rdev->wb.enabled) { |
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45 | u32 scratch_index; |
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46 | if (rdev->wb.use_event) |
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47 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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48 | else |
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49 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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50 | rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);; |
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51 | } else |
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52 | WREG32(rdev->fence_drv.scratch_reg, seq); |
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53 | } |
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54 | |||
55 | static u32 radeon_fence_read(struct radeon_device *rdev) |
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56 | { |
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57 | u32 seq; |
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58 | |||
59 | if (rdev->wb.enabled) { |
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60 | u32 scratch_index; |
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61 | if (rdev->wb.use_event) |
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62 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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63 | else |
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64 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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65 | seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]); |
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66 | } else |
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67 | seq = RREG32(rdev->fence_drv.scratch_reg); |
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68 | return seq; |
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69 | } |
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70 | |||
1125 | serge | 71 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) |
72 | { |
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73 | unsigned long irq_flags; |
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74 | |||
75 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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76 | if (fence->emited) { |
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77 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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78 | return 0; |
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79 | } |
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80 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); |
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2004 | serge | 81 | if (!rdev->cp.ready) |
1125 | serge | 82 | /* FIXME: cp is not running assume everythings is done right |
83 | * away |
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84 | */ |
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2004 | serge | 85 | radeon_fence_write(rdev, fence->seq); |
86 | else |
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1125 | serge | 87 | radeon_fence_ring_emit(rdev, fence); |
1179 | serge | 88 | |
2004 | serge | 89 | // trace_radeon_fence_emit(rdev->ddev, fence->seq); |
1125 | serge | 90 | fence->emited = true; |
1986 | serge | 91 | list_move_tail(&fence->list, &rdev->fence_drv.emited); |
1125 | serge | 92 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
93 | return 0; |
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94 | } |
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95 | |||
96 | static bool radeon_fence_poll_locked(struct radeon_device *rdev) |
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97 | { |
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98 | struct radeon_fence *fence; |
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99 | struct list_head *i, *n; |
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100 | uint32_t seq; |
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101 | bool wake = false; |
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1963 | serge | 102 | unsigned long cjiffies; |
1125 | serge | 103 | |
2004 | serge | 104 | seq = radeon_fence_read(rdev); |
1963 | serge | 105 | if (seq != rdev->fence_drv.last_seq) { |
106 | rdev->fence_drv.last_seq = seq; |
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2005 | serge | 107 | rdev->fence_drv.last_jiffies = GetTimerTicks(); |
108 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
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1963 | serge | 109 | } else { |
2005 | serge | 110 | cjiffies = GetTimerTicks(); |
1963 | serge | 111 | if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) { |
112 | cjiffies -= rdev->fence_drv.last_jiffies; |
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113 | if (time_after(rdev->fence_drv.last_timeout, cjiffies)) { |
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114 | /* update the timeout */ |
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115 | rdev->fence_drv.last_timeout -= cjiffies; |
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116 | } else { |
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117 | /* the 500ms timeout is elapsed we should test |
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118 | * for GPU lockup |
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119 | */ |
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120 | rdev->fence_drv.last_timeout = 1; |
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121 | } |
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122 | } else { |
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123 | /* wrap around update last jiffies, we will just wait |
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124 | * a little longer |
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125 | */ |
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126 | rdev->fence_drv.last_jiffies = cjiffies; |
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1125 | serge | 127 | } |
1963 | serge | 128 | return false; |
1125 | serge | 129 | } |
130 | n = NULL; |
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131 | list_for_each(i, &rdev->fence_drv.emited) { |
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132 | fence = list_entry(i, struct radeon_fence, list); |
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133 | if (fence->seq == seq) { |
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134 | n = i; |
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135 | break; |
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136 | } |
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137 | } |
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138 | /* all fence previous to this one are considered as signaled */ |
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139 | if (n) { |
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2005 | serge | 140 | kevent_t event; |
141 | event.code = -1; |
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1125 | serge | 142 | i = n; |
143 | do { |
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144 | n = i->prev; |
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1986 | serge | 145 | list_move_tail(i, &rdev->fence_drv.signaled); |
1125 | serge | 146 | fence = list_entry(i, struct radeon_fence, list); |
147 | fence->signaled = true; |
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2005 | serge | 148 | // dbgprintf("fence %x done\n", fence); |
149 | RaiseEvent(fence->evnt, 0, &event); |
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1125 | serge | 150 | i = n; |
151 | } while (i != &rdev->fence_drv.emited); |
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152 | wake = true; |
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153 | } |
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154 | return wake; |
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155 | } |
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156 | |||
157 | |||
158 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) |
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159 | { |
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160 | unsigned long irq_flags; |
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161 | |||
162 | *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL); |
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163 | if ((*fence) == NULL) { |
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164 | return -ENOMEM; |
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165 | } |
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2005 | serge | 166 | |
167 | (*fence)->evnt = CreateEvent(NULL, MANUAL_DESTROY); |
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2004 | serge | 168 | // kref_init(&((*fence)->kref)); |
1125 | serge | 169 | (*fence)->rdev = rdev; |
170 | (*fence)->emited = false; |
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171 | (*fence)->signaled = false; |
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172 | (*fence)->seq = 0; |
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173 | INIT_LIST_HEAD(&(*fence)->list); |
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174 | |||
175 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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176 | list_add_tail(&(*fence)->list, &rdev->fence_drv.created); |
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177 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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178 | return 0; |
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179 | } |
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180 | |||
181 | |||
182 | bool radeon_fence_signaled(struct radeon_fence *fence) |
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183 | { |
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184 | unsigned long irq_flags; |
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185 | bool signaled = false; |
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186 | |||
1404 | serge | 187 | if (!fence) |
1125 | serge | 188 | return true; |
1404 | serge | 189 | |
190 | if (fence->rdev->gpu_lockup) |
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1125 | serge | 191 | return true; |
1404 | serge | 192 | |
1125 | serge | 193 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
194 | signaled = fence->signaled; |
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195 | /* if we are shuting down report all fence as signaled */ |
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196 | if (fence->rdev->shutdown) { |
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197 | signaled = true; |
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198 | } |
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199 | if (!fence->emited) { |
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200 | WARN(1, "Querying an unemited fence : %p !\n", fence); |
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201 | signaled = true; |
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202 | } |
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203 | if (!signaled) { |
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204 | radeon_fence_poll_locked(fence->rdev); |
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205 | signaled = fence->signaled; |
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206 | } |
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207 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
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208 | return signaled; |
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209 | } |
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210 | |||
1179 | serge | 211 | int radeon_fence_wait(struct radeon_fence *fence, bool intr) |
212 | { |
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213 | struct radeon_device *rdev; |
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1963 | serge | 214 | unsigned long irq_flags, timeout; |
215 | u32 seq; |
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1125 | serge | 216 | int r; |
217 | |||
218 | if (fence == NULL) { |
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219 | WARN(1, "Querying an invalid fence : %p !\n", fence); |
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220 | return 0; |
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221 | } |
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222 | rdev = fence->rdev; |
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223 | if (radeon_fence_signaled(fence)) { |
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224 | return 0; |
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225 | } |
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1963 | serge | 226 | timeout = rdev->fence_drv.last_timeout; |
1125 | serge | 227 | retry: |
1963 | serge | 228 | /* save current sequence used to check for GPU lockup */ |
229 | seq = rdev->fence_drv.last_seq; |
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2004 | serge | 230 | // trace_radeon_fence_wait_begin(rdev->ddev, seq); |
1179 | serge | 231 | if (intr) { |
1321 | serge | 232 | radeon_irq_kms_sw_irq_get(rdev); |
2005 | serge | 233 | // r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
234 | // radeon_fence_signaled(fence), timeout); |
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235 | |||
236 | WaitEvent(fence->evnt); |
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237 | |||
1321 | serge | 238 | radeon_irq_kms_sw_irq_put(rdev); |
1963 | serge | 239 | if (unlikely(r < 0)) { |
1321 | serge | 240 | return r; |
1963 | serge | 241 | } |
1125 | serge | 242 | } else { |
1321 | serge | 243 | radeon_irq_kms_sw_irq_get(rdev); |
2005 | serge | 244 | // r = wait_event_timeout(rdev->fence_drv.queue, |
245 | // radeon_fence_signaled(fence), timeout); |
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246 | |||
247 | WaitEvent(fence->evnt); |
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248 | |||
1321 | serge | 249 | radeon_irq_kms_sw_irq_put(rdev); |
1125 | serge | 250 | } |
2004 | serge | 251 | // trace_radeon_fence_wait_end(rdev->ddev, seq); |
1125 | serge | 252 | if (unlikely(!radeon_fence_signaled(fence))) { |
1963 | serge | 253 | /* we were interrupted for some reason and fence isn't |
254 | * isn't signaled yet, resume wait |
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255 | */ |
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256 | if (r) { |
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257 | timeout = r; |
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258 | goto retry; |
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1125 | serge | 259 | } |
1963 | serge | 260 | /* don't protect read access to rdev->fence_drv.last_seq |
261 | * if we experiencing a lockup the value doesn't change |
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262 | */ |
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263 | if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) { |
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264 | /* good news we believe it's a lockup */ |
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265 | WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", |
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266 | fence->seq, seq); |
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267 | /* FIXME: what should we do ? marking everyone |
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268 | * as signaled for now |
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269 | */ |
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270 | rdev->gpu_lockup = true; |
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2005 | serge | 271 | // r = radeon_gpu_reset(rdev); |
272 | // if (r) |
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273 | // return r; |
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274 | return true; |
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275 | |||
276 | // radeon_fence_write(rdev, fence->seq); |
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277 | // rdev->gpu_lockup = false; |
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1125 | serge | 278 | } |
2005 | serge | 279 | timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
1963 | serge | 280 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
2005 | serge | 281 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
282 | rdev->fence_drv.last_jiffies = GetTimerTicks(); |
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1963 | serge | 283 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
1125 | serge | 284 | goto retry; |
285 | } |
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286 | return 0; |
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287 | } |
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288 | |||
2004 | serge | 289 | #if 0 |
1125 | serge | 290 | int radeon_fence_wait_next(struct radeon_device *rdev) |
291 | { |
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292 | unsigned long irq_flags; |
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293 | struct radeon_fence *fence; |
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294 | int r; |
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295 | |||
296 | if (rdev->gpu_lockup) { |
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297 | return 0; |
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298 | } |
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299 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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300 | if (list_empty(&rdev->fence_drv.emited)) { |
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301 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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302 | return 0; |
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303 | } |
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304 | fence = list_entry(rdev->fence_drv.emited.next, |
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305 | struct radeon_fence, list); |
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306 | radeon_fence_ref(fence); |
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307 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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308 | r = radeon_fence_wait(fence, false); |
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309 | radeon_fence_unref(&fence); |
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310 | return r; |
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311 | } |
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312 | |||
313 | int radeon_fence_wait_last(struct radeon_device *rdev) |
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314 | { |
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315 | unsigned long irq_flags; |
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316 | struct radeon_fence *fence; |
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317 | int r; |
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318 | |||
319 | if (rdev->gpu_lockup) { |
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320 | return 0; |
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321 | } |
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322 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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323 | if (list_empty(&rdev->fence_drv.emited)) { |
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324 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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325 | return 0; |
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326 | } |
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327 | fence = list_entry(rdev->fence_drv.emited.prev, |
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328 | struct radeon_fence, list); |
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329 | radeon_fence_ref(fence); |
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330 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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331 | r = radeon_fence_wait(fence, false); |
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332 | radeon_fence_unref(&fence); |
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333 | return r; |
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334 | } |
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335 | |||
336 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence) |
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337 | { |
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338 | kref_get(&fence->kref); |
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339 | return fence; |
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340 | } |
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341 | |||
2004 | serge | 342 | #endif |
343 | |||
1125 | serge | 344 | void radeon_fence_unref(struct radeon_fence **fence) |
345 | { |
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2005 | serge | 346 | unsigned long irq_flags; |
1125 | serge | 347 | struct radeon_fence *tmp = *fence; |
348 | |||
349 | *fence = NULL; |
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2005 | serge | 350 | |
351 | if(tmp) |
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352 | { |
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353 | write_lock_irqsave(&tmp->rdev->fence_drv.lock, irq_flags); |
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354 | list_del(&tmp->list); |
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355 | tmp->emited = false; |
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356 | write_unlock_irqrestore(&tmp->rdev->fence_drv.lock, irq_flags); |
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357 | }; |
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1125 | serge | 358 | } |
359 | |||
360 | void radeon_fence_process(struct radeon_device *rdev) |
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361 | { |
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362 | unsigned long irq_flags; |
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363 | bool wake; |
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364 | |||
365 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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366 | wake = radeon_fence_poll_locked(rdev); |
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367 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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368 | } |
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369 | |||
370 | int radeon_fence_driver_init(struct radeon_device *rdev) |
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371 | { |
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372 | unsigned long irq_flags; |
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373 | int r; |
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374 | |||
375 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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376 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
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377 | if (r) { |
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1404 | serge | 378 | dev_err(rdev->dev, "fence failed to get scratch register\n"); |
1125 | serge | 379 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
380 | return r; |
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381 | } |
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2004 | serge | 382 | radeon_fence_write(rdev, 0); |
1125 | serge | 383 | atomic_set(&rdev->fence_drv.seq, 0); |
384 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
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385 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
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386 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
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2004 | serge | 387 | // init_waitqueue_head(&rdev->fence_drv.queue); |
1404 | serge | 388 | rdev->fence_drv.initialized = true; |
1125 | serge | 389 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
2004 | serge | 390 | return 0; |
1125 | serge | 391 | } |
392 | |||
393 | |||
394 | /* |
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395 | * Fence debugfs |
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396 | */ |
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397 | #if defined(CONFIG_DEBUG_FS) |
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398 | static int radeon_debugfs_fence_info(struct seq_file *m, void *data) |
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399 | { |
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400 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
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401 | struct drm_device *dev = node->minor->dev; |
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402 | struct radeon_device *rdev = dev->dev_private; |
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403 | struct radeon_fence *fence; |
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404 | |||
405 | seq_printf(m, "Last signaled fence 0x%08X\n", |
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2004 | serge | 406 | radeon_fence_read(rdev)); |
1125 | serge | 407 | if (!list_empty(&rdev->fence_drv.emited)) { |
408 | fence = list_entry(rdev->fence_drv.emited.prev, |
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409 | struct radeon_fence, list); |
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410 | seq_printf(m, "Last emited fence %p with 0x%08X\n", |
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411 | fence, fence->seq); |
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412 | } |
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413 | return 0; |
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414 | } |
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415 | |||
416 | static struct drm_info_list radeon_debugfs_fence_list[] = { |
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417 | {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, |
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418 | }; |
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419 | #endif |
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420 | |||
421 | int radeon_debugfs_fence_init(struct radeon_device *rdev) |
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422 | { |
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423 | #if defined(CONFIG_DEBUG_FS) |
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424 | return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); |
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425 | #else |
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426 | return 0; |
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427 | #endif |
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428 | }> |