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1125 | serge | 1 | /* |
2 | * Copyright 2009 Jerome Glisse. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Jerome Glisse |
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29 | * Dave Airlie |
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30 | */ |
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31 | #include |
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32 | #include |
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33 | #include |
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34 | #include |
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35 | #include |
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36 | #include "drmP.h" |
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37 | #include "drm.h" |
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38 | #include "radeon_reg.h" |
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39 | #include "radeon.h" |
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40 | |||
41 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) |
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42 | { |
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43 | unsigned long irq_flags; |
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44 | |||
45 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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46 | if (fence->emited) { |
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47 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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48 | return 0; |
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49 | } |
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50 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); |
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51 | if (!rdev->cp.ready) { |
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52 | /* FIXME: cp is not running assume everythings is done right |
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53 | * away |
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54 | */ |
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55 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); |
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1179 | serge | 56 | } else |
1125 | serge | 57 | radeon_fence_ring_emit(rdev, fence); |
1179 | serge | 58 | |
1125 | serge | 59 | fence->emited = true; |
60 | list_del(&fence->list); |
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61 | list_add_tail(&fence->list, &rdev->fence_drv.emited); |
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62 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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63 | return 0; |
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64 | } |
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65 | |||
66 | static bool radeon_fence_poll_locked(struct radeon_device *rdev) |
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67 | { |
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68 | struct radeon_fence *fence; |
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69 | struct list_head *i, *n; |
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70 | uint32_t seq; |
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71 | bool wake = false; |
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1963 | serge | 72 | unsigned long cjiffies; |
1125 | serge | 73 | |
1963 | serge | 74 | if (rdev->wb.enabled) { |
75 | u32 scratch_index; |
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76 | if (rdev->wb.use_event) |
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77 | scratch_index = R600_WB_EVENT_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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78 | else |
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79 | scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base; |
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80 | seq = rdev->wb.wb[scratch_index/4]; |
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81 | } else |
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82 | seq = RREG32(rdev->fence_drv.scratch_reg); |
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83 | if (seq != rdev->fence_drv.last_seq) { |
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84 | rdev->fence_drv.last_seq = seq; |
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85 | rdev->fence_drv.last_jiffies = jiffies; |
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86 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
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87 | } else { |
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88 | cjiffies = jiffies; |
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89 | if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) { |
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90 | cjiffies -= rdev->fence_drv.last_jiffies; |
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91 | if (time_after(rdev->fence_drv.last_timeout, cjiffies)) { |
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92 | /* update the timeout */ |
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93 | rdev->fence_drv.last_timeout -= cjiffies; |
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94 | } else { |
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95 | /* the 500ms timeout is elapsed we should test |
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96 | * for GPU lockup |
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97 | */ |
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98 | rdev->fence_drv.last_timeout = 1; |
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99 | } |
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100 | } else { |
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101 | /* wrap around update last jiffies, we will just wait |
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102 | * a little longer |
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103 | */ |
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104 | rdev->fence_drv.last_jiffies = cjiffies; |
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1125 | serge | 105 | } |
1963 | serge | 106 | return false; |
1125 | serge | 107 | } |
108 | n = NULL; |
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109 | list_for_each(i, &rdev->fence_drv.emited) { |
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110 | fence = list_entry(i, struct radeon_fence, list); |
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111 | if (fence->seq == seq) { |
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112 | n = i; |
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113 | break; |
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114 | } |
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115 | } |
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116 | /* all fence previous to this one are considered as signaled */ |
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117 | if (n) { |
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118 | i = n; |
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119 | do { |
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120 | n = i->prev; |
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121 | list_del(i); |
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122 | list_add_tail(i, &rdev->fence_drv.signaled); |
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123 | fence = list_entry(i, struct radeon_fence, list); |
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124 | fence->signaled = true; |
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125 | i = n; |
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126 | } while (i != &rdev->fence_drv.emited); |
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127 | wake = true; |
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128 | } |
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129 | return wake; |
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130 | } |
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131 | |||
132 | static void radeon_fence_destroy(struct kref *kref) |
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133 | { |
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134 | unsigned long irq_flags; |
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135 | struct radeon_fence *fence; |
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136 | |||
137 | fence = container_of(kref, struct radeon_fence, kref); |
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138 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
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139 | list_del(&fence->list); |
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140 | fence->emited = false; |
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141 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
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142 | kfree(fence); |
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143 | } |
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144 | |||
145 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) |
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146 | { |
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147 | unsigned long irq_flags; |
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148 | |||
149 | *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL); |
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150 | if ((*fence) == NULL) { |
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151 | return -ENOMEM; |
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152 | } |
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153 | kref_init(&((*fence)->kref)); |
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154 | (*fence)->rdev = rdev; |
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155 | (*fence)->emited = false; |
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156 | (*fence)->signaled = false; |
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157 | (*fence)->seq = 0; |
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158 | INIT_LIST_HEAD(&(*fence)->list); |
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159 | |||
160 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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161 | list_add_tail(&(*fence)->list, &rdev->fence_drv.created); |
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162 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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163 | return 0; |
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164 | } |
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165 | |||
166 | |||
167 | bool radeon_fence_signaled(struct radeon_fence *fence) |
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168 | { |
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169 | unsigned long irq_flags; |
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170 | bool signaled = false; |
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171 | |||
1404 | serge | 172 | if (!fence) |
1125 | serge | 173 | return true; |
1404 | serge | 174 | |
175 | if (fence->rdev->gpu_lockup) |
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1125 | serge | 176 | return true; |
1404 | serge | 177 | |
1125 | serge | 178 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
179 | signaled = fence->signaled; |
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180 | /* if we are shuting down report all fence as signaled */ |
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181 | if (fence->rdev->shutdown) { |
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182 | signaled = true; |
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183 | } |
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184 | if (!fence->emited) { |
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185 | WARN(1, "Querying an unemited fence : %p !\n", fence); |
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186 | signaled = true; |
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187 | } |
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188 | if (!signaled) { |
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189 | radeon_fence_poll_locked(fence->rdev); |
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190 | signaled = fence->signaled; |
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191 | } |
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192 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
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193 | return signaled; |
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194 | } |
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195 | |||
1179 | serge | 196 | int radeon_fence_wait(struct radeon_fence *fence, bool intr) |
197 | { |
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198 | struct radeon_device *rdev; |
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1963 | serge | 199 | unsigned long irq_flags, timeout; |
200 | u32 seq; |
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1125 | serge | 201 | int r; |
202 | |||
203 | if (fence == NULL) { |
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204 | WARN(1, "Querying an invalid fence : %p !\n", fence); |
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205 | return 0; |
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206 | } |
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207 | rdev = fence->rdev; |
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208 | if (radeon_fence_signaled(fence)) { |
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209 | return 0; |
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210 | } |
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1963 | serge | 211 | timeout = rdev->fence_drv.last_timeout; |
1125 | serge | 212 | retry: |
1963 | serge | 213 | /* save current sequence used to check for GPU lockup */ |
214 | seq = rdev->fence_drv.last_seq; |
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1179 | serge | 215 | if (intr) { |
1321 | serge | 216 | radeon_irq_kms_sw_irq_get(rdev); |
1125 | serge | 217 | r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
218 | radeon_fence_signaled(fence), timeout); |
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1321 | serge | 219 | radeon_irq_kms_sw_irq_put(rdev); |
1963 | serge | 220 | if (unlikely(r < 0)) { |
1321 | serge | 221 | return r; |
1963 | serge | 222 | } |
1125 | serge | 223 | } else { |
1321 | serge | 224 | radeon_irq_kms_sw_irq_get(rdev); |
1125 | serge | 225 | r = wait_event_timeout(rdev->fence_drv.queue, |
226 | radeon_fence_signaled(fence), timeout); |
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1321 | serge | 227 | radeon_irq_kms_sw_irq_put(rdev); |
1125 | serge | 228 | } |
229 | if (unlikely(!radeon_fence_signaled(fence))) { |
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1963 | serge | 230 | /* we were interrupted for some reason and fence isn't |
231 | * isn't signaled yet, resume wait |
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232 | */ |
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233 | if (r) { |
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234 | timeout = r; |
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235 | goto retry; |
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1125 | serge | 236 | } |
1963 | serge | 237 | /* don't protect read access to rdev->fence_drv.last_seq |
238 | * if we experiencing a lockup the value doesn't change |
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239 | */ |
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240 | if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) { |
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241 | /* good news we believe it's a lockup */ |
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242 | WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", |
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243 | fence->seq, seq); |
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244 | /* FIXME: what should we do ? marking everyone |
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245 | * as signaled for now |
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246 | */ |
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247 | rdev->gpu_lockup = true; |
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248 | r = radeon_gpu_reset(rdev); |
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249 | if (r) |
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250 | return r; |
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1125 | serge | 251 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); |
1963 | serge | 252 | rdev->gpu_lockup = false; |
1125 | serge | 253 | } |
1963 | serge | 254 | timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
255 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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256 | rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
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257 | rdev->fence_drv.last_jiffies = jiffies; |
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258 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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1125 | serge | 259 | goto retry; |
260 | } |
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261 | return 0; |
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262 | } |
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263 | |||
264 | int radeon_fence_wait_next(struct radeon_device *rdev) |
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265 | { |
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266 | unsigned long irq_flags; |
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267 | struct radeon_fence *fence; |
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268 | int r; |
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269 | |||
270 | if (rdev->gpu_lockup) { |
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271 | return 0; |
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272 | } |
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273 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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274 | if (list_empty(&rdev->fence_drv.emited)) { |
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275 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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276 | return 0; |
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277 | } |
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278 | fence = list_entry(rdev->fence_drv.emited.next, |
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279 | struct radeon_fence, list); |
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280 | radeon_fence_ref(fence); |
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281 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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282 | r = radeon_fence_wait(fence, false); |
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283 | radeon_fence_unref(&fence); |
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284 | return r; |
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285 | } |
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286 | |||
287 | int radeon_fence_wait_last(struct radeon_device *rdev) |
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288 | { |
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289 | unsigned long irq_flags; |
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290 | struct radeon_fence *fence; |
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291 | int r; |
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292 | |||
293 | if (rdev->gpu_lockup) { |
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294 | return 0; |
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295 | } |
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296 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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297 | if (list_empty(&rdev->fence_drv.emited)) { |
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298 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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299 | return 0; |
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300 | } |
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301 | fence = list_entry(rdev->fence_drv.emited.prev, |
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302 | struct radeon_fence, list); |
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303 | radeon_fence_ref(fence); |
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304 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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305 | r = radeon_fence_wait(fence, false); |
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306 | radeon_fence_unref(&fence); |
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307 | return r; |
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308 | } |
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309 | |||
310 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence) |
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311 | { |
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312 | kref_get(&fence->kref); |
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313 | return fence; |
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314 | } |
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315 | |||
316 | void radeon_fence_unref(struct radeon_fence **fence) |
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317 | { |
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318 | struct radeon_fence *tmp = *fence; |
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319 | |||
320 | *fence = NULL; |
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321 | if (tmp) { |
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322 | kref_put(&tmp->kref, &radeon_fence_destroy); |
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323 | } |
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324 | } |
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325 | |||
326 | void radeon_fence_process(struct radeon_device *rdev) |
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327 | { |
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328 | unsigned long irq_flags; |
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329 | bool wake; |
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330 | |||
331 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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332 | wake = radeon_fence_poll_locked(rdev); |
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333 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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334 | if (wake) { |
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335 | wake_up_all(&rdev->fence_drv.queue); |
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336 | } |
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337 | } |
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338 | |||
339 | int radeon_fence_driver_init(struct radeon_device *rdev) |
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340 | { |
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341 | unsigned long irq_flags; |
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342 | int r; |
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343 | |||
344 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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345 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
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346 | if (r) { |
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1404 | serge | 347 | dev_err(rdev->dev, "fence failed to get scratch register\n"); |
1125 | serge | 348 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
349 | return r; |
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350 | } |
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351 | WREG32(rdev->fence_drv.scratch_reg, 0); |
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352 | atomic_set(&rdev->fence_drv.seq, 0); |
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353 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
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354 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
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355 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
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356 | init_waitqueue_head(&rdev->fence_drv.queue); |
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1404 | serge | 357 | rdev->fence_drv.initialized = true; |
1125 | serge | 358 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
359 | if (radeon_debugfs_fence_init(rdev)) { |
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1404 | serge | 360 | dev_err(rdev->dev, "fence debugfs file creation failed\n"); |
1125 | serge | 361 | } |
362 | return 0; |
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363 | } |
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364 | |||
365 | void radeon_fence_driver_fini(struct radeon_device *rdev) |
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366 | { |
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367 | unsigned long irq_flags; |
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368 | |||
1404 | serge | 369 | if (!rdev->fence_drv.initialized) |
370 | return; |
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1125 | serge | 371 | wake_up_all(&rdev->fence_drv.queue); |
372 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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373 | radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); |
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374 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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1404 | serge | 375 | rdev->fence_drv.initialized = false; |
1125 | serge | 376 | } |
377 | |||
378 | |||
379 | /* |
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380 | * Fence debugfs |
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381 | */ |
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382 | #if defined(CONFIG_DEBUG_FS) |
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383 | static int radeon_debugfs_fence_info(struct seq_file *m, void *data) |
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384 | { |
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385 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
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386 | struct drm_device *dev = node->minor->dev; |
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387 | struct radeon_device *rdev = dev->dev_private; |
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388 | struct radeon_fence *fence; |
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389 | |||
390 | seq_printf(m, "Last signaled fence 0x%08X\n", |
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391 | RREG32(rdev->fence_drv.scratch_reg)); |
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392 | if (!list_empty(&rdev->fence_drv.emited)) { |
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393 | fence = list_entry(rdev->fence_drv.emited.prev, |
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394 | struct radeon_fence, list); |
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395 | seq_printf(m, "Last emited fence %p with 0x%08X\n", |
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396 | fence, fence->seq); |
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397 | } |
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398 | return 0; |
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399 | } |
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400 | |||
401 | static struct drm_info_list radeon_debugfs_fence_list[] = { |
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402 | {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, |
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403 | }; |
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404 | #endif |
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405 | |||
406 | int radeon_debugfs_fence_init(struct radeon_device *rdev) |
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407 | { |
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408 | #if defined(CONFIG_DEBUG_FS) |
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409 | return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); |
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410 | #else |
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411 | return 0; |
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412 | #endif |
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413 | }> |