Rev 1179 | Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
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| 1125 | serge | 1 | /* |
| 2 | * Copyright 2009 Jerome Glisse. |
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| 3 | * All Rights Reserved. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the |
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| 7 | * "Software"), to deal in the Software without restriction, including |
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| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
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| 9 | * distribute, sub license, and/or sell copies of the Software, and to |
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| 10 | * permit persons to whom the Software is furnished to do so, subject to |
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| 11 | * the following conditions: |
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| 12 | * |
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| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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| 17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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| 18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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| 19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 20 | * |
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| 21 | * The above copyright notice and this permission notice (including the |
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| 22 | * next paragraph) shall be included in all copies or substantial portions |
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| 23 | * of the Software. |
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| 24 | * |
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| 25 | */ |
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| 26 | /* |
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| 27 | * Authors: |
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| 28 | * Jerome Glisse |
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| 29 | * Dave Airlie |
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| 30 | */ |
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| 31 | #include |
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| 32 | #include |
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| 33 | #include |
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| 34 | #include |
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| 35 | #include |
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| 36 | #include "drmP.h" |
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| 37 | #include "drm.h" |
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| 38 | #include "radeon_reg.h" |
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| 39 | #include "radeon.h" |
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| 40 | |||
| 41 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) |
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| 42 | { |
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| 43 | unsigned long irq_flags; |
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| 44 | |||
| 45 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 46 | if (fence->emited) { |
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| 47 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 48 | return 0; |
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| 49 | } |
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| 50 | fence->seq = atomic_add_return(1, &rdev->fence_drv.seq); |
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| 51 | if (!rdev->cp.ready) { |
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| 52 | /* FIXME: cp is not running assume everythings is done right |
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| 53 | * away |
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| 54 | */ |
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| 55 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); |
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| 56 | } else { |
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| 57 | radeon_fence_ring_emit(rdev, fence); |
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| 58 | } |
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| 59 | fence->emited = true; |
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| 60 | fence->timeout = jiffies + ((2000 * HZ) / 1000); |
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| 61 | list_del(&fence->list); |
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| 62 | list_add_tail(&fence->list, &rdev->fence_drv.emited); |
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| 63 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 64 | return 0; |
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| 65 | } |
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| 66 | |||
| 67 | static bool radeon_fence_poll_locked(struct radeon_device *rdev) |
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| 68 | { |
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| 69 | struct radeon_fence *fence; |
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| 70 | struct list_head *i, *n; |
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| 71 | uint32_t seq; |
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| 72 | bool wake = false; |
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| 73 | |||
| 74 | if (rdev == NULL) { |
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| 75 | return true; |
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| 76 | } |
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| 77 | if (rdev->shutdown) { |
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| 78 | return true; |
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| 79 | } |
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| 80 | seq = RREG32(rdev->fence_drv.scratch_reg); |
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| 81 | rdev->fence_drv.last_seq = seq; |
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| 82 | n = NULL; |
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| 83 | list_for_each(i, &rdev->fence_drv.emited) { |
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| 84 | fence = list_entry(i, struct radeon_fence, list); |
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| 85 | if (fence->seq == seq) { |
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| 86 | n = i; |
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| 87 | break; |
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| 88 | } |
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| 89 | } |
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| 90 | /* all fence previous to this one are considered as signaled */ |
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| 91 | if (n) { |
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| 92 | i = n; |
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| 93 | do { |
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| 94 | n = i->prev; |
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| 95 | list_del(i); |
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| 96 | list_add_tail(i, &rdev->fence_drv.signaled); |
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| 97 | fence = list_entry(i, struct radeon_fence, list); |
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| 98 | fence->signaled = true; |
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| 99 | i = n; |
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| 100 | } while (i != &rdev->fence_drv.emited); |
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| 101 | wake = true; |
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| 102 | } |
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| 103 | return wake; |
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| 104 | } |
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| 105 | |||
| 106 | static void radeon_fence_destroy(struct kref *kref) |
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| 107 | { |
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| 108 | unsigned long irq_flags; |
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| 109 | struct radeon_fence *fence; |
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| 110 | |||
| 111 | fence = container_of(kref, struct radeon_fence, kref); |
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| 112 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
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| 113 | list_del(&fence->list); |
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| 114 | fence->emited = false; |
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| 115 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
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| 116 | kfree(fence); |
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| 117 | } |
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| 118 | |||
| 119 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) |
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| 120 | { |
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| 121 | unsigned long irq_flags; |
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| 122 | |||
| 123 | *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL); |
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| 124 | if ((*fence) == NULL) { |
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| 125 | return -ENOMEM; |
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| 126 | } |
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| 127 | kref_init(&((*fence)->kref)); |
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| 128 | (*fence)->rdev = rdev; |
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| 129 | (*fence)->emited = false; |
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| 130 | (*fence)->signaled = false; |
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| 131 | (*fence)->seq = 0; |
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| 132 | INIT_LIST_HEAD(&(*fence)->list); |
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| 133 | |||
| 134 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 135 | list_add_tail(&(*fence)->list, &rdev->fence_drv.created); |
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| 136 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 137 | return 0; |
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| 138 | } |
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| 139 | |||
| 140 | |||
| 141 | bool radeon_fence_signaled(struct radeon_fence *fence) |
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| 142 | { |
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| 143 | struct radeon_device *rdev = fence->rdev; |
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| 144 | unsigned long irq_flags; |
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| 145 | bool signaled = false; |
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| 146 | |||
| 147 | if (rdev->gpu_lockup) { |
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| 148 | return true; |
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| 149 | } |
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| 150 | if (fence == NULL) { |
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| 151 | return true; |
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| 152 | } |
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| 153 | write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
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| 154 | signaled = fence->signaled; |
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| 155 | /* if we are shuting down report all fence as signaled */ |
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| 156 | if (fence->rdev->shutdown) { |
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| 157 | signaled = true; |
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| 158 | } |
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| 159 | if (!fence->emited) { |
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| 160 | WARN(1, "Querying an unemited fence : %p !\n", fence); |
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| 161 | signaled = true; |
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| 162 | } |
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| 163 | if (!signaled) { |
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| 164 | radeon_fence_poll_locked(fence->rdev); |
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| 165 | signaled = fence->signaled; |
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| 166 | } |
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| 167 | write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
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| 168 | return signaled; |
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| 169 | } |
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| 170 | |||
| 171 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible) |
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| 172 | { |
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| 173 | struct radeon_device *rdev; |
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| 174 | unsigned long cur_jiffies; |
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| 175 | unsigned long timeout; |
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| 176 | bool expired = false; |
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| 177 | int r; |
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| 178 | |||
| 179 | |||
| 180 | if (fence == NULL) { |
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| 181 | WARN(1, "Querying an invalid fence : %p !\n", fence); |
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| 182 | return 0; |
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| 183 | } |
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| 184 | rdev = fence->rdev; |
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| 185 | if (radeon_fence_signaled(fence)) { |
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| 186 | return 0; |
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| 187 | } |
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| 188 | retry: |
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| 189 | cur_jiffies = jiffies; |
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| 190 | timeout = HZ / 100; |
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| 191 | if (time_after(fence->timeout, cur_jiffies)) { |
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| 192 | timeout = fence->timeout - cur_jiffies; |
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| 193 | } |
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| 194 | if (interruptible) { |
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| 195 | r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
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| 196 | radeon_fence_signaled(fence), timeout); |
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| 197 | if (unlikely(r == -ERESTARTSYS)) { |
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| 198 | return -ERESTART; |
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| 199 | } |
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| 200 | } else { |
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| 201 | r = wait_event_timeout(rdev->fence_drv.queue, |
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| 202 | radeon_fence_signaled(fence), timeout); |
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| 203 | } |
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| 204 | if (unlikely(!radeon_fence_signaled(fence))) { |
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| 205 | if (unlikely(r == 0)) { |
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| 206 | expired = true; |
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| 207 | } |
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| 208 | if (unlikely(expired)) { |
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| 209 | timeout = 1; |
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| 210 | if (time_after(cur_jiffies, fence->timeout)) { |
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| 211 | timeout = cur_jiffies - fence->timeout; |
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| 212 | } |
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| 213 | timeout = jiffies_to_msecs(timeout); |
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| 214 | if (timeout > 500) { |
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| 215 | DRM_ERROR("fence(%p:0x%08X) %lums timeout " |
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| 216 | "going to reset GPU\n", |
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| 217 | fence, fence->seq, timeout); |
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| 218 | radeon_gpu_reset(rdev); |
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| 219 | WREG32(rdev->fence_drv.scratch_reg, fence->seq); |
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| 220 | } |
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| 221 | } |
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| 222 | goto retry; |
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| 223 | } |
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| 224 | if (unlikely(expired)) { |
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| 225 | rdev->fence_drv.count_timeout++; |
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| 226 | cur_jiffies = jiffies; |
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| 227 | timeout = 1; |
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| 228 | if (time_after(cur_jiffies, fence->timeout)) { |
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| 229 | timeout = cur_jiffies - fence->timeout; |
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| 230 | } |
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| 231 | timeout = jiffies_to_msecs(timeout); |
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| 232 | DRM_ERROR("fence(%p:0x%08X) %lums timeout\n", |
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| 233 | fence, fence->seq, timeout); |
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| 234 | DRM_ERROR("last signaled fence(0x%08X)\n", |
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| 235 | rdev->fence_drv.last_seq); |
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| 236 | } |
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| 237 | return 0; |
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| 238 | } |
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| 239 | |||
| 240 | int radeon_fence_wait_next(struct radeon_device *rdev) |
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| 241 | { |
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| 242 | unsigned long irq_flags; |
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| 243 | struct radeon_fence *fence; |
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| 244 | int r; |
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| 245 | |||
| 246 | if (rdev->gpu_lockup) { |
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| 247 | return 0; |
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| 248 | } |
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| 249 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 250 | if (list_empty(&rdev->fence_drv.emited)) { |
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| 251 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 252 | return 0; |
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| 253 | } |
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| 254 | fence = list_entry(rdev->fence_drv.emited.next, |
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| 255 | struct radeon_fence, list); |
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| 256 | radeon_fence_ref(fence); |
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| 257 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 258 | r = radeon_fence_wait(fence, false); |
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| 259 | radeon_fence_unref(&fence); |
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| 260 | return r; |
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| 261 | } |
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| 262 | |||
| 263 | int radeon_fence_wait_last(struct radeon_device *rdev) |
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| 264 | { |
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| 265 | unsigned long irq_flags; |
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| 266 | struct radeon_fence *fence; |
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| 267 | int r; |
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| 268 | |||
| 269 | if (rdev->gpu_lockup) { |
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| 270 | return 0; |
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| 271 | } |
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| 272 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 273 | if (list_empty(&rdev->fence_drv.emited)) { |
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| 274 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 275 | return 0; |
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| 276 | } |
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| 277 | fence = list_entry(rdev->fence_drv.emited.prev, |
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| 278 | struct radeon_fence, list); |
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| 279 | radeon_fence_ref(fence); |
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| 280 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 281 | r = radeon_fence_wait(fence, false); |
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| 282 | radeon_fence_unref(&fence); |
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| 283 | return r; |
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| 284 | } |
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| 285 | |||
| 286 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence) |
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| 287 | { |
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| 288 | kref_get(&fence->kref); |
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| 289 | return fence; |
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| 290 | } |
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| 291 | |||
| 292 | void radeon_fence_unref(struct radeon_fence **fence) |
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| 293 | { |
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| 294 | struct radeon_fence *tmp = *fence; |
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| 295 | |||
| 296 | *fence = NULL; |
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| 297 | if (tmp) { |
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| 298 | kref_put(&tmp->kref, &radeon_fence_destroy); |
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| 299 | } |
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| 300 | } |
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| 301 | |||
| 302 | void radeon_fence_process(struct radeon_device *rdev) |
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| 303 | { |
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| 304 | unsigned long irq_flags; |
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| 305 | bool wake; |
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| 306 | |||
| 307 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 308 | wake = radeon_fence_poll_locked(rdev); |
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| 309 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 310 | if (wake) { |
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| 311 | wake_up_all(&rdev->fence_drv.queue); |
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| 312 | } |
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| 313 | } |
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| 314 | |||
| 315 | int radeon_fence_driver_init(struct radeon_device *rdev) |
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| 316 | { |
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| 317 | unsigned long irq_flags; |
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| 318 | int r; |
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| 319 | |||
| 320 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 321 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
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| 322 | if (r) { |
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| 323 | DRM_ERROR("Fence failed to get a scratch register."); |
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| 324 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 325 | return r; |
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| 326 | } |
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| 327 | WREG32(rdev->fence_drv.scratch_reg, 0); |
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| 328 | atomic_set(&rdev->fence_drv.seq, 0); |
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| 329 | INIT_LIST_HEAD(&rdev->fence_drv.created); |
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| 330 | INIT_LIST_HEAD(&rdev->fence_drv.emited); |
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| 331 | INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
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| 332 | rdev->fence_drv.count_timeout = 0; |
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| 333 | init_waitqueue_head(&rdev->fence_drv.queue); |
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| 334 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 335 | if (radeon_debugfs_fence_init(rdev)) { |
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| 336 | DRM_ERROR("Failed to register debugfs file for fence !\n"); |
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| 337 | } |
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| 338 | return 0; |
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| 339 | } |
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| 340 | |||
| 341 | void radeon_fence_driver_fini(struct radeon_device *rdev) |
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| 342 | { |
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| 343 | unsigned long irq_flags; |
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| 344 | |||
| 345 | wake_up_all(&rdev->fence_drv.queue); |
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| 346 | write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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| 347 | radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); |
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| 348 | write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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| 349 | DRM_INFO("radeon: fence finalized\n"); |
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| 350 | } |
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| 351 | |||
| 352 | |||
| 353 | /* |
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| 354 | * Fence debugfs |
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| 355 | */ |
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| 356 | #if defined(CONFIG_DEBUG_FS) |
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| 357 | static int radeon_debugfs_fence_info(struct seq_file *m, void *data) |
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| 358 | { |
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| 359 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
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| 360 | struct drm_device *dev = node->minor->dev; |
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| 361 | struct radeon_device *rdev = dev->dev_private; |
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| 362 | struct radeon_fence *fence; |
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| 363 | |||
| 364 | seq_printf(m, "Last signaled fence 0x%08X\n", |
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| 365 | RREG32(rdev->fence_drv.scratch_reg)); |
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| 366 | if (!list_empty(&rdev->fence_drv.emited)) { |
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| 367 | fence = list_entry(rdev->fence_drv.emited.prev, |
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| 368 | struct radeon_fence, list); |
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| 369 | seq_printf(m, "Last emited fence %p with 0x%08X\n", |
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| 370 | fence, fence->seq); |
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| 371 | } |
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| 372 | return 0; |
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| 373 | } |
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| 374 | |||
| 375 | static struct drm_info_list radeon_debugfs_fence_list[] = { |
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| 376 | {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, |
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| 377 | }; |
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| 378 | #endif |
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| 379 | |||
| 380 | int radeon_debugfs_fence_init(struct radeon_device *rdev) |
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| 381 | { |
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| 382 | #if defined(CONFIG_DEBUG_FS) |
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| 383 | return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); |
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| 384 | #else |
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| 385 | return 0; |
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| 386 | #endif |
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| 387 | } |