WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_encoders.c

Rev	Author	Line No.	Line
1125	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "drm_crtc_helper.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	extern int atom_debug;
		33
		34	uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
		36	{
		37	struct radeon_device *rdev = dev->dev_private;
		38	uint32_t ret = 0;
		39
		40	switch (supported_device) {
		41	case ATOM_DEVICE_CRT1_SUPPORT:
		42	case ATOM_DEVICE_TV1_SUPPORT:
		43	case ATOM_DEVICE_TV2_SUPPORT:
		44	case ATOM_DEVICE_CRT2_SUPPORT:
		45	case ATOM_DEVICE_CV_SUPPORT:
		46	switch (dac) {
		47	case 1: /* dac a */
		48	if ((rdev->family == CHIP_RS300) \|\|
		49	(rdev->family == CHIP_RS400) \|\|
		50	(rdev->family == CHIP_RS480))
		51	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		52	else if (ASIC_IS_AVIVO(rdev))
		53	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
		54	else
		55	ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
		56	break;
		57	case 2: /* dac b */
		58	if (ASIC_IS_AVIVO(rdev))
		59	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
		60	else {
		61	/*if (rdev->family == CHIP_R200)
		62	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		63	else*/
		64	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		65	}
		66	break;
		67	case 3: /* external dac */
		68	if (ASIC_IS_AVIVO(rdev))
		69	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		70	else
		71	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		72	break;
		73	}
		74	break;
		75	case ATOM_DEVICE_LCD1_SUPPORT:
		76	if (ASIC_IS_AVIVO(rdev))
		77	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		78	else
		79	ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
		80	break;
		81	case ATOM_DEVICE_DFP1_SUPPORT:
		82	if ((rdev->family == CHIP_RS300) \|\|
		83	(rdev->family == CHIP_RS400) \|\|
		84	(rdev->family == CHIP_RS480))
		85	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		86	else if (ASIC_IS_AVIVO(rdev))
		87	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
		88	else
		89	ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
		90	break;
		91	case ATOM_DEVICE_LCD2_SUPPORT:
		92	case ATOM_DEVICE_DFP2_SUPPORT:
		93	if ((rdev->family == CHIP_RS600) \|\|
		94	(rdev->family == CHIP_RS690) \|\|
		95	(rdev->family == CHIP_RS740))
		96	ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
		97	else if (ASIC_IS_AVIVO(rdev))
		98	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		99	else
		100	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		101	break;
		102	case ATOM_DEVICE_DFP3_SUPPORT:
		103	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		104	break;
		105	}
		106
		107	return ret;
		108	}
		109
		110	void
		111	radeon_link_encoder_connector(struct drm_device *dev)
		112	{
		113	struct drm_connector *connector;
		114	struct radeon_connector *radeon_connector;
		115	struct drm_encoder *encoder;
		116	struct radeon_encoder *radeon_encoder;
		117
		118	/* walk the list and link encoders to connectors */
		119	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		120	radeon_connector = to_radeon_connector(connector);
		121	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		122	radeon_encoder = to_radeon_encoder(encoder);
		123	if (radeon_encoder->devices & radeon_connector->devices)
		124	drm_mode_connector_attach_encoder(connector, encoder);
		125	}
		126	}
		127	}
		128
1179	serge	129	void radeon_encoder_set_active_device(struct drm_encoder *encoder)
		130	{
		131	struct drm_device *dev = encoder->dev;
		132	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		133	struct drm_connector *connector;
		134
		135	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		136	if (connector->encoder == encoder) {
		137	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		138	radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
		139	DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
		140	radeon_encoder->active_device, radeon_encoder->devices,
		141	radeon_connector->devices, encoder->encoder_type);
		142	}
		143	}
		144	}
		145
1125	serge	146	static struct drm_connector *
		147	radeon_get_connector_for_encoder(struct drm_encoder *encoder)
		148	{
		149	struct drm_device *dev = encoder->dev;
		150	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		151	struct drm_connector *connector;
		152	struct radeon_connector *radeon_connector;
		153
		154	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		155	radeon_connector = to_radeon_connector(connector);
		156	if (radeon_encoder->devices & radeon_connector->devices)
		157	return connector;
		158	}
		159	return NULL;
		160	}
		161
		162	/* used for both atom and legacy */
		163	void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
		164	struct drm_display_mode *mode,
		165	struct drm_display_mode *adjusted_mode)
		166	{
		167	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		168	struct drm_device *dev = encoder->dev;
		169	struct radeon_device *rdev = dev->dev_private;
		170	struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
		171
		172	if (mode->hdisplay < native_mode->panel_xres \|\|
		173	mode->vdisplay < native_mode->panel_yres) {
		174	if (ASIC_IS_AVIVO(rdev)) {
		175	adjusted_mode->hdisplay = native_mode->panel_xres;
		176	adjusted_mode->vdisplay = native_mode->panel_yres;
		177	adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
		178	adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
		179	adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
		180	adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
		181	adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
		182	adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
		183	/* update crtc values */
		184	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
		185	/* adjust crtc values */
		186	adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
		187	adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
		188	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
		189	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
		190	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
		191	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
		192	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
		193	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
		194	} else {
		195	adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
		196	adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
		197	adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
		198	adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
		199	adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
		200	adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
		201	/* update crtc values */
		202	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
		203	/* adjust crtc values */
		204	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
		205	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
		206	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
		207	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
		208	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
		209	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
		210	}
		211	adjusted_mode->flags = native_mode->flags;
		212	adjusted_mode->clock = native_mode->dotclock;
		213	}
		214	}
		215
		216	static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
		217	struct drm_display_mode *mode,
		218	struct drm_display_mode *adjusted_mode)
		219	{
		220	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		221
		222	drm_mode_set_crtcinfo(adjusted_mode, 0);
		223
		224	if (radeon_encoder->rmx_type != RMX_OFF)
		225	radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
		226
		227	/* hw bug */
		228	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
		229	&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
		230	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
		231
		232	return true;
		233	}
		234
		235	static void
		236	atombios_dac_setup(struct drm_encoder *encoder, int action)
		237	{
		238	struct drm_device *dev = encoder->dev;
		239	struct radeon_device *rdev = dev->dev_private;
		240	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		241	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
		242	int index = 0, num = 0;
1179	serge	243	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
1125	serge	244	enum radeon_tv_std tv_std = TV_STD_NTSC;
		245
1179	serge	246	if (dac_info->tv_std)
		247	tv_std = dac_info->tv_std;
		248
1125	serge	249	memset(&args, 0, sizeof(args));
		250
		251	switch (radeon_encoder->encoder_id) {
		252	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		253	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		254	index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
		255	num = 1;
		256	break;
		257	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		258	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		259	index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
		260	num = 2;
		261	break;
		262	}
		263
		264	args.ucAction = action;
		265
1179	serge	266	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
1125	serge	267	args.ucDacStandard = ATOM_DAC1_PS2;
1179	serge	268	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	269	args.ucDacStandard = ATOM_DAC1_CV;
		270	else {
		271	switch (tv_std) {
		272	case TV_STD_PAL:
		273	case TV_STD_PAL_M:
		274	case TV_STD_SCART_PAL:
		275	case TV_STD_SECAM:
		276	case TV_STD_PAL_CN:
		277	args.ucDacStandard = ATOM_DAC1_PAL;
		278	break;
		279	case TV_STD_NTSC:
		280	case TV_STD_NTSC_J:
		281	case TV_STD_PAL_60:
		282	default:
		283	args.ucDacStandard = ATOM_DAC1_NTSC;
		284	break;
		285	}
		286	}
		287	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		288
		289	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		290
		291	}
		292
		293	static void
		294	atombios_tv_setup(struct drm_encoder *encoder, int action)
		295	{
		296	struct drm_device *dev = encoder->dev;
		297	struct radeon_device *rdev = dev->dev_private;
		298	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		299	TV_ENCODER_CONTROL_PS_ALLOCATION args;
		300	int index = 0;
1179	serge	301	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
1125	serge	302	enum radeon_tv_std tv_std = TV_STD_NTSC;
		303
1179	serge	304	if (dac_info->tv_std)
		305	tv_std = dac_info->tv_std;
		306
1125	serge	307	memset(&args, 0, sizeof(args));
		308
		309	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
		310
		311	args.sTVEncoder.ucAction = action;
		312
1179	serge	313	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	314	args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
		315	else {
		316	switch (tv_std) {
		317	case TV_STD_NTSC:
		318	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		319	break;
		320	case TV_STD_PAL:
		321	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
		322	break;
		323	case TV_STD_PAL_M:
		324	args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
		325	break;
		326	case TV_STD_PAL_60:
		327	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
		328	break;
		329	case TV_STD_NTSC_J:
		330	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
		331	break;
		332	case TV_STD_SCART_PAL:
		333	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
		334	break;
		335	case TV_STD_SECAM:
		336	args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
		337	break;
		338	case TV_STD_PAL_CN:
		339	args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
		340	break;
		341	default:
		342	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		343	break;
		344	}
		345	}
		346
		347	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		348
		349	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		350
		351	}
		352
		353	void
		354	atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
		355	{
		356	struct drm_device *dev = encoder->dev;
		357	struct radeon_device *rdev = dev->dev_private;
		358	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		359	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
		360	int index = 0;
		361
		362	memset(&args, 0, sizeof(args));
		363
		364	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		365
		366	args.sXTmdsEncoder.ucEnable = action;
		367
		368	if (radeon_encoder->pixel_clock > 165000)
		369	args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
		370
		371	/if (pScrn->rgbBits == 8)/
		372	args.sXTmdsEncoder.ucMisc \|= (1 << 1);
		373
		374	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		375
		376	}
		377
		378	static void
		379	atombios_ddia_setup(struct drm_encoder *encoder, int action)
		380	{
		381	struct drm_device *dev = encoder->dev;
		382	struct radeon_device *rdev = dev->dev_private;
		383	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		384	DVO_ENCODER_CONTROL_PS_ALLOCATION args;
		385	int index = 0;
		386
		387	memset(&args, 0, sizeof(args));
		388
		389	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		390
		391	args.sDVOEncoder.ucAction = action;
		392	args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		393
		394	if (radeon_encoder->pixel_clock > 165000)
		395	args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
		396
		397	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		398
		399	}
		400
		401	union lvds_encoder_control {
		402	LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
		403	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
		404	};
		405
		406	static void
		407	atombios_digital_setup(struct drm_encoder *encoder, int action)
		408	{
		409	struct drm_device *dev = encoder->dev;
		410	struct radeon_device *rdev = dev->dev_private;
		411	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		412	union lvds_encoder_control args;
		413	int index = 0;
		414	uint8_t frev, crev;
		415	struct radeon_encoder_atom_dig *dig;
		416	struct drm_connector *connector;
		417	struct radeon_connector *radeon_connector;
		418	struct radeon_connector_atom_dig *dig_connector;
		419
		420	connector = radeon_get_connector_for_encoder(encoder);
		421	if (!connector)
		422	return;
		423
		424	radeon_connector = to_radeon_connector(connector);
		425
		426	if (!radeon_encoder->enc_priv)
		427	return;
		428
		429	dig = radeon_encoder->enc_priv;
		430
		431	if (!radeon_connector->con_priv)
		432	return;
		433
		434	dig_connector = radeon_connector->con_priv;
		435
		436	memset(&args, 0, sizeof(args));
		437
		438	switch (radeon_encoder->encoder_id) {
		439	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		440	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		441	break;
		442	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		443	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		444	index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
		445	break;
		446	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		447	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		448	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		449	else
		450	index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
		451	break;
		452	}
		453
		454	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		455
		456	switch (frev) {
		457	case 1:
		458	case 2:
		459	switch (crev) {
		460	case 1:
		461	args.v1.ucMisc = 0;
		462	args.v1.ucAction = action;
		463	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		464	args.v1.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		465	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		466	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		467	if (dig->lvds_misc & (1 << 0))
		468	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		469	if (dig->lvds_misc & (1 << 1))
		470	args.v1.ucMisc \|= (1 << 1);
		471	} else {
		472	if (dig_connector->linkb)
		473	args.v1.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		474	if (radeon_encoder->pixel_clock > 165000)
		475	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		476	/if (pScrn->rgbBits == 8) /
		477	args.v1.ucMisc \|= (1 << 1);
		478	}
		479	break;
		480	case 2:
		481	case 3:
		482	args.v2.ucMisc = 0;
		483	args.v2.ucAction = action;
		484	if (crev == 3) {
		485	if (dig->coherent_mode)
		486	args.v2.ucMisc \|= PANEL_ENCODER_MISC_COHERENT;
		487	}
		488	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		489	args.v2.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		490	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		491	args.v2.ucTruncate = 0;
		492	args.v2.ucSpatial = 0;
		493	args.v2.ucTemporal = 0;
		494	args.v2.ucFRC = 0;
		495	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		496	if (dig->lvds_misc & (1 << 0))
		497	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		498	if (dig->lvds_misc & (1 << 5)) {
		499	args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
		500	if (dig->lvds_misc & (1 << 1))
		501	args.v2.ucSpatial \|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
		502	}
		503	if (dig->lvds_misc & (1 << 6)) {
		504	args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
		505	if (dig->lvds_misc & (1 << 1))
		506	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
		507	if (((dig->lvds_misc >> 2) & 0x3) == 2)
		508	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_LEVEL_4;
		509	}
		510	} else {
		511	if (dig_connector->linkb)
		512	args.v2.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		513	if (radeon_encoder->pixel_clock > 165000)
		514	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		515	}
		516	break;
		517	default:
		518	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		519	break;
		520	}
		521	break;
		522	default:
		523	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		524	break;
		525	}
		526
		527	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		528
		529	}
		530
		531	int
		532	atombios_get_encoder_mode(struct drm_encoder *encoder)
		533	{
		534	struct drm_connector *connector;
		535	struct radeon_connector *radeon_connector;
		536
		537	connector = radeon_get_connector_for_encoder(encoder);
		538	if (!connector)
		539	return 0;
		540
		541	radeon_connector = to_radeon_connector(connector);
		542
		543	switch (connector->connector_type) {
		544	case DRM_MODE_CONNECTOR_DVII:
1179	serge	545	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
1125	serge	546	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		547	return ATOM_ENCODER_MODE_HDMI;
		548	else if (radeon_connector->use_digital)
		549	return ATOM_ENCODER_MODE_DVI;
		550	else
		551	return ATOM_ENCODER_MODE_CRT;
		552	break;
		553	case DRM_MODE_CONNECTOR_DVID:
		554	case DRM_MODE_CONNECTOR_HDMIA:
		555	default:
		556	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		557	return ATOM_ENCODER_MODE_HDMI;
		558	else
		559	return ATOM_ENCODER_MODE_DVI;
		560	break;
		561	case DRM_MODE_CONNECTOR_LVDS:
		562	return ATOM_ENCODER_MODE_LVDS;
		563	break;
		564	case DRM_MODE_CONNECTOR_DisplayPort:
		565	/*if (radeon_output->MonType == MT_DP)
		566	return ATOM_ENCODER_MODE_DP;
		567	else*/
		568	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		569	return ATOM_ENCODER_MODE_HDMI;
		570	else
		571	return ATOM_ENCODER_MODE_DVI;
		572	break;
		573	case CONNECTOR_DVI_A:
		574	case CONNECTOR_VGA:
		575	return ATOM_ENCODER_MODE_CRT;
		576	break;
		577	case CONNECTOR_STV:
		578	case CONNECTOR_CTV:
		579	case CONNECTOR_DIN:
		580	/* fix me */
		581	return ATOM_ENCODER_MODE_TV;
		582	/return ATOM_ENCODER_MODE_CV;/
		583	break;
		584	}
		585	}
		586
		587	static void
		588	atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
		589	{
		590	struct drm_device *dev = encoder->dev;
		591	struct radeon_device *rdev = dev->dev_private;
		592	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		593	DIG_ENCODER_CONTROL_PS_ALLOCATION args;
		594	int index = 0, num = 0;
		595	uint8_t frev, crev;
		596	struct radeon_encoder_atom_dig *dig;
		597	struct drm_connector *connector;
		598	struct radeon_connector *radeon_connector;
		599	struct radeon_connector_atom_dig *dig_connector;
		600
		601	connector = radeon_get_connector_for_encoder(encoder);
		602	if (!connector)
		603	return;
		604
		605	radeon_connector = to_radeon_connector(connector);
		606
		607	if (!radeon_connector->con_priv)
		608	return;
		609
		610	dig_connector = radeon_connector->con_priv;
		611
		612	if (!radeon_encoder->enc_priv)
		613	return;
		614
		615	dig = radeon_encoder->enc_priv;
		616
		617	memset(&args, 0, sizeof(args));
		618
		619	if (ASIC_IS_DCE32(rdev)) {
		620	if (dig->dig_block)
		621	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		622	else
		623	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
		624	num = dig->dig_block + 1;
		625	} else {
		626	switch (radeon_encoder->encoder_id) {
		627	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		628	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
		629	num = 1;
		630	break;
		631	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		632	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		633	num = 2;
		634	break;
		635	}
		636	}
		637
		638	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		639
		640	args.ucAction = action;
		641	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		642
		643	if (ASIC_IS_DCE32(rdev)) {
		644	switch (radeon_encoder->encoder_id) {
		645	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		646	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
		647	break;
		648	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		649	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
		650	break;
		651	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		652	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
		653	break;
		654	}
		655	} else {
		656	switch (radeon_encoder->encoder_id) {
		657	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		658	args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
		659	break;
		660	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		661	args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
		662	break;
		663	}
		664	}
		665
		666	if (radeon_encoder->pixel_clock > 165000) {
		667	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA_B;
		668	args.ucLaneNum = 8;
		669	} else {
		670	if (dig_connector->linkb)
		671	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKB;
		672	else
		673	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA;
		674	args.ucLaneNum = 4;
		675	}
		676
		677	args.ucEncoderMode = atombios_get_encoder_mode(encoder);
		678
		679	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		680
		681	}
		682
		683	union dig_transmitter_control {
		684	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
		685	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
		686	};
		687
		688	static void
		689	atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
		690	{
		691	struct drm_device *dev = encoder->dev;
		692	struct radeon_device *rdev = dev->dev_private;
		693	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		694	union dig_transmitter_control args;
		695	int index = 0, num = 0;
		696	uint8_t frev, crev;
		697	struct radeon_encoder_atom_dig *dig;
		698	struct drm_connector *connector;
		699	struct radeon_connector *radeon_connector;
		700	struct radeon_connector_atom_dig *dig_connector;
		701
		702	connector = radeon_get_connector_for_encoder(encoder);
		703	if (!connector)
		704	return;
		705
		706	radeon_connector = to_radeon_connector(connector);
		707
		708	if (!radeon_encoder->enc_priv)
		709	return;
		710
		711	dig = radeon_encoder->enc_priv;
		712
		713	if (!radeon_connector->con_priv)
		714	return;
		715
		716	dig_connector = radeon_connector->con_priv;
		717
		718	memset(&args, 0, sizeof(args));
		719
		720	if (ASIC_IS_DCE32(rdev))
		721	index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
		722	else {
		723	switch (radeon_encoder->encoder_id) {
		724	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		725	index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
		726	break;
		727	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		728	index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
		729	break;
		730	}
		731	}
		732
		733	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		734
		735	args.v1.ucAction = action;
		736
		737	if (ASIC_IS_DCE32(rdev)) {
		738	if (radeon_encoder->pixel_clock > 165000) {
		739	args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
		740	args.v2.acConfig.fDualLinkConnector = 1;
		741	} else {
		742	args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
		743	}
		744	if (dig->dig_block)
		745	args.v2.acConfig.ucEncoderSel = 1;
		746
		747	switch (radeon_encoder->encoder_id) {
		748	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		749	args.v2.acConfig.ucTransmitterSel = 0;
		750	num = 0;
		751	break;
		752	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		753	args.v2.acConfig.ucTransmitterSel = 1;
		754	num = 1;
		755	break;
		756	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		757	args.v2.acConfig.ucTransmitterSel = 2;
		758	num = 2;
		759	break;
		760	}
		761
		762	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		763	if (dig->coherent_mode)
		764	args.v2.acConfig.fCoherentMode = 1;
		765	}
		766	} else {
		767	args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
		768	args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
		769
		770	switch (radeon_encoder->encoder_id) {
		771	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		772	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
		773	if (rdev->flags & RADEON_IS_IGP) {
		774	if (radeon_encoder->pixel_clock > 165000) {
		775	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		776	ATOM_TRANSMITTER_CONFIG_LINKA_B);
		777	if (dig_connector->igp_lane_info & 0x3)
		778	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
		779	else if (dig_connector->igp_lane_info & 0xc)
		780	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
		781	} else {
		782	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA;
		783	if (dig_connector->igp_lane_info & 0x1)
		784	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		785	else if (dig_connector->igp_lane_info & 0x2)
		786	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
		787	else if (dig_connector->igp_lane_info & 0x4)
		788	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
		789	else if (dig_connector->igp_lane_info & 0x8)
		790	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
		791	}
		792	} else {
		793	if (radeon_encoder->pixel_clock > 165000)
		794	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		795	ATOM_TRANSMITTER_CONFIG_LINKA_B \|
		796	ATOM_TRANSMITTER_CONFIG_LANE_0_7);
		797	else {
		798	if (dig_connector->linkb)
		799	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		800	else
		801	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		802	}
		803	}
		804	break;
		805	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		806	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
		807	if (radeon_encoder->pixel_clock > 165000)
		808	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		809	ATOM_TRANSMITTER_CONFIG_LINKA_B \|
		810	ATOM_TRANSMITTER_CONFIG_LANE_0_7);
		811	else {
		812	if (dig_connector->linkb)
		813	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		814	else
		815	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		816	}
		817	break;
		818	}
		819
		820	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		821	if (dig->coherent_mode)
		822	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		823	}
		824	}
		825
		826	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		827
		828	}
		829
		830	static void
		831	atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
		832	{
		833	struct drm_device *dev = encoder->dev;
		834	struct radeon_device *rdev = dev->dev_private;
		835	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		836	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		837	ENABLE_YUV_PS_ALLOCATION args;
		838	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
		839	uint32_t temp, reg;
		840
		841	memset(&args, 0, sizeof(args));
		842
		843	if (rdev->family >= CHIP_R600)
		844	reg = R600_BIOS_3_SCRATCH;
		845	else
		846	reg = RADEON_BIOS_3_SCRATCH;
		847
		848	/* XXX: fix up scratch reg handling */
		849	temp = RREG32(reg);
1179	serge	850	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	851	WREG32(reg, (ATOM_S3_TV1_ACTIVE \|
		852	(radeon_crtc->crtc_id << 18)));
1179	serge	853	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	854	WREG32(reg, (ATOM_S3_CV_ACTIVE \| (radeon_crtc->crtc_id << 24)));
		855	else
		856	WREG32(reg, 0);
		857
		858	if (enable)
		859	args.ucEnable = ATOM_ENABLE;
		860	args.ucCRTC = radeon_crtc->crtc_id;
		861
		862	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		863
		864	WREG32(reg, temp);
		865	}
		866
		867	static void
		868	radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
		869	{
		870	struct drm_device *dev = encoder->dev;
		871	struct radeon_device *rdev = dev->dev_private;
		872	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		873	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
		874	int index = 0;
		875	bool is_dig = false;
1179	serge	876	int devices;
1125	serge	877
		878	memset(&args, 0, sizeof(args));
		879
1179	serge	880	/* on DPMS off we have no idea if active device is meaningful */
		881	if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
		882	devices = radeon_encoder->devices;
		883	else
		884	devices = radeon_encoder->active_device;
		885
		886	DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
		887	radeon_encoder->encoder_id, mode, radeon_encoder->devices,
		888	radeon_encoder->active_device);
1125	serge	889	switch (radeon_encoder->encoder_id) {
		890	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		891	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		892	index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
		893	break;
		894	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		895	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		896	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		897	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		898	is_dig = true;
		899	break;
		900	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		901	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		902	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		903	index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
		904	break;
		905	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		906	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		907	break;
		908	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		909	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		910	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		911	else
		912	index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
		913	break;
		914	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		915	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1179	serge	916	if (devices & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	917	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1179	serge	918	else if (devices & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	919	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		920	else
		921	index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
		922	break;
		923	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		924	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1179	serge	925	if (devices & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	926	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1179	serge	927	else if (devices & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	928	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		929	else
		930	index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
		931	break;
		932	}
		933
		934	if (is_dig) {
		935	switch (mode) {
		936	case DRM_MODE_DPMS_ON:
		937	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
		938	break;
		939	case DRM_MODE_DPMS_STANDBY:
		940	case DRM_MODE_DPMS_SUSPEND:
		941	case DRM_MODE_DPMS_OFF:
		942	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
		943	break;
		944	}
		945	} else {
		946	switch (mode) {
		947	case DRM_MODE_DPMS_ON:
		948	args.ucAction = ATOM_ENABLE;
		949	break;
		950	case DRM_MODE_DPMS_STANDBY:
		951	case DRM_MODE_DPMS_SUSPEND:
		952	case DRM_MODE_DPMS_OFF:
		953	args.ucAction = ATOM_DISABLE;
		954	break;
		955	}
		956	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		957	}
		958	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		959	}
		960
		961	union crtc_sourc_param {
		962	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
		963	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
		964	};
		965
		966	static void
		967	atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
		968	{
		969	struct drm_device *dev = encoder->dev;
		970	struct radeon_device *rdev = dev->dev_private;
		971	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		972	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		973	union crtc_sourc_param args;
		974	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
		975	uint8_t frev, crev;
		976
		977	memset(&args, 0, sizeof(args));
		978
		979	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		980
		981	switch (frev) {
		982	case 1:
		983	switch (crev) {
		984	case 1:
		985	default:
		986	if (ASIC_IS_AVIVO(rdev))
		987	args.v1.ucCRTC = radeon_crtc->crtc_id;
		988	else {
		989	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
		990	args.v1.ucCRTC = radeon_crtc->crtc_id;
		991	} else {
		992	args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
		993	}
		994	}
		995	switch (radeon_encoder->encoder_id) {
		996	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		997	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		998	args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
		999	break;
		1000	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1001	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1002	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
		1003	args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
		1004	else
		1005	args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
		1006	break;
		1007	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1008	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1009	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1010	args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
		1011	break;
		1012	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1013	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1179	serge	1014	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1015	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1179	serge	1016	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1017	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1018	else
		1019	args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
		1020	break;
		1021	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1022	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1179	serge	1023	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1024	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1179	serge	1025	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1026	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1027	else
		1028	args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
		1029	break;
		1030	}
		1031	break;
		1032	case 2:
		1033	args.v2.ucCRTC = radeon_crtc->crtc_id;
		1034	args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
		1035	switch (radeon_encoder->encoder_id) {
		1036	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1037	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1038	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1039	if (ASIC_IS_DCE32(rdev)) {
		1040	if (radeon_crtc->crtc_id)
		1041	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
		1042	else
		1043	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1044	} else
		1045	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1046	break;
		1047	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1048	args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
		1049	break;
		1050	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1051	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
		1052	break;
		1053	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1179	serge	1054	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1055	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1179	serge	1056	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1057	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1058	else
		1059	args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
		1060	break;
		1061	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1179	serge	1062	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1125	serge	1063	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1179	serge	1064	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1125	serge	1065	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1066	else
		1067	args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
		1068	break;
		1069	}
		1070	break;
		1071	}
		1072	break;
		1073	default:
		1074	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1075	break;
		1076	}
		1077
		1078	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1079
		1080	}
		1081
		1082	static void
		1083	atombios_apply_encoder_quirks(struct drm_encoder *encoder,
		1084	struct drm_display_mode *mode)
		1085	{
		1086	struct drm_device *dev = encoder->dev;
		1087	struct radeon_device *rdev = dev->dev_private;
		1088	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1089	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1090
		1091	/* Funky macbooks */
		1092	if ((dev->pdev->device == 0x71C5) &&
		1093	(dev->pdev->subsystem_vendor == 0x106b) &&
		1094	(dev->pdev->subsystem_device == 0x0080)) {
		1095	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1096	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
		1097
		1098	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		1099	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		1100
		1101	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
		1102	}
		1103	}
		1104
		1105	/* set scaler clears this on some chips */
		1106	if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
		1107	WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
		1108	}
		1109
		1110	static void
		1111	radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
		1112	struct drm_display_mode *mode,
		1113	struct drm_display_mode *adjusted_mode)
		1114	{
		1115	struct drm_device *dev = encoder->dev;
		1116	struct radeon_device *rdev = dev->dev_private;
		1117	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1118	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1119
		1120	if (radeon_encoder->enc_priv) {
		1121	struct radeon_encoder_atom_dig *dig;
		1122
		1123	dig = radeon_encoder->enc_priv;
		1124	dig->dig_block = radeon_crtc->crtc_id;
		1125	}
		1126	radeon_encoder->pixel_clock = adjusted_mode->clock;
		1127
		1128	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1129	atombios_set_encoder_crtc_source(encoder);
		1130
		1131	if (ASIC_IS_AVIVO(rdev)) {
1179	serge	1132	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT \| ATOM_DEVICE_TV_SUPPORT))
1125	serge	1133	atombios_yuv_setup(encoder, true);
		1134	else
		1135	atombios_yuv_setup(encoder, false);
		1136	}
		1137
		1138	switch (radeon_encoder->encoder_id) {
		1139	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1140	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1141	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1142	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1143	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		1144	break;
		1145	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1146	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1147	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1148	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1149	/* disable the encoder and transmitter */
		1150	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
		1151	atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
		1152
		1153	/* setup and enable the encoder and transmitter */
		1154	atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
		1155	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
		1156	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
		1157	break;
		1158	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1159	atombios_ddia_setup(encoder, ATOM_ENABLE);
		1160	break;
		1161	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1162	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1163	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		1164	break;
		1165	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1166	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1167	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1168	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1169	atombios_dac_setup(encoder, ATOM_ENABLE);
1179	serge	1170	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
1125	serge	1171	atombios_tv_setup(encoder, ATOM_ENABLE);
		1172	break;
		1173	}
		1174	atombios_apply_encoder_quirks(encoder, adjusted_mode);
		1175	}
		1176
		1177	static bool
1179	serge	1178	atombios_dac_load_detect(struct drm_encoder encoder, struct drm_connector connector)
1125	serge	1179	{
		1180	struct drm_device *dev = encoder->dev;
		1181	struct radeon_device *rdev = dev->dev_private;
		1182	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1183	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1125	serge	1184
		1185	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \|
		1186	ATOM_DEVICE_CV_SUPPORT \|
		1187	ATOM_DEVICE_CRT_SUPPORT)) {
		1188	DAC_LOAD_DETECTION_PS_ALLOCATION args;
		1189	int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
		1190	uint8_t frev, crev;
		1191
		1192	memset(&args, 0, sizeof(args));
		1193
		1194	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		1195
		1196	args.sDacload.ucMisc = 0;
		1197
		1198	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) \|\|
		1199	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
		1200	args.sDacload.ucDacType = ATOM_DAC_A;
		1201	else
		1202	args.sDacload.ucDacType = ATOM_DAC_B;
		1203
1179	serge	1204	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1125	serge	1205	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1179	serge	1206	else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1125	serge	1207	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1179	serge	1208	else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1125	serge	1209	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
		1210	if (crev >= 3)
		1211	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1179	serge	1212	} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1125	serge	1213	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
		1214	if (crev >= 3)
		1215	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		1216	}
		1217
		1218	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1219
		1220	return true;
		1221	} else
		1222	return false;
		1223	}
		1224
		1225	static enum drm_connector_status
		1226	radeon_atom_dac_detect(struct drm_encoder encoder, struct drm_connector connector)
		1227	{
		1228	struct drm_device *dev = encoder->dev;
		1229	struct radeon_device *rdev = dev->dev_private;
		1230	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1179	serge	1231	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1125	serge	1232	uint32_t bios_0_scratch;
		1233
1179	serge	1234	if (!atombios_dac_load_detect(encoder, connector)) {
1125	serge	1235	DRM_DEBUG("detect returned false \n");
		1236	return connector_status_unknown;
		1237	}
		1238
		1239	if (rdev->family >= CHIP_R600)
		1240	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1241	else
		1242	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1243
1179	serge	1244	DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
		1245	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1125	serge	1246	if (bios_0_scratch & ATOM_S0_CRT1_MASK)
		1247	return connector_status_connected;
1179	serge	1248	}
		1249	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1125	serge	1250	if (bios_0_scratch & ATOM_S0_CRT2_MASK)
		1251	return connector_status_connected;
1179	serge	1252	}
		1253	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1125	serge	1254	if (bios_0_scratch & (ATOM_S0_CV_MASK\|ATOM_S0_CV_MASK_A))
		1255	return connector_status_connected;
1179	serge	1256	}
		1257	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1125	serge	1258	if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE \| ATOM_S0_TV1_COMPOSITE_A))
		1259	return connector_status_connected; /* CTV */
		1260	else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO \| ATOM_S0_TV1_SVIDEO_A))
		1261	return connector_status_connected; /* STV */
		1262	}
		1263	return connector_status_disconnected;
		1264	}
		1265
		1266	static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
		1267	{
		1268	radeon_atom_output_lock(encoder, true);
		1269	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1179	serge	1270
		1271	radeon_encoder_set_active_device(encoder);
1125	serge	1272	}
		1273
		1274	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
		1275	{
		1276	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
		1277	radeon_atom_output_lock(encoder, false);
		1278	}
		1279
1179	serge	1280	static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
		1281	{
		1282	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1283	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
		1284	radeon_encoder->active_device = 0;
		1285	}
		1286
1125	serge	1287	static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
		1288	.dpms = radeon_atom_encoder_dpms,
		1289	.mode_fixup = radeon_atom_mode_fixup,
		1290	.prepare = radeon_atom_encoder_prepare,
		1291	.mode_set = radeon_atom_encoder_mode_set,
		1292	.commit = radeon_atom_encoder_commit,
1179	serge	1293	.disable = radeon_atom_encoder_disable,
1125	serge	1294	/* no detect for TMDS/LVDS yet */
		1295	};
		1296
		1297	static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
		1298	.dpms = radeon_atom_encoder_dpms,
		1299	.mode_fixup = radeon_atom_mode_fixup,
		1300	.prepare = radeon_atom_encoder_prepare,
		1301	.mode_set = radeon_atom_encoder_mode_set,
		1302	.commit = radeon_atom_encoder_commit,
		1303	.detect = radeon_atom_dac_detect,
		1304	};
		1305
		1306	void radeon_enc_destroy(struct drm_encoder *encoder)
		1307	{
		1308	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1309	kfree(radeon_encoder->enc_priv);
		1310	drm_encoder_cleanup(encoder);
		1311	kfree(radeon_encoder);
		1312	}
		1313
		1314	static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
		1315	.destroy = radeon_enc_destroy,
		1316	};
		1317
1179	serge	1318	struct radeon_encoder_atom_dac *
		1319	radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
		1320	{
		1321	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
		1322
		1323	if (!dac)
		1324	return NULL;
		1325
		1326	dac->tv_std = TV_STD_NTSC;
		1327	return dac;
		1328	}
		1329
1125	serge	1330	struct radeon_encoder_atom_dig *
		1331	radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
		1332	{
		1333	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1334
		1335	if (!dig)
		1336	return NULL;
		1337
		1338	/* coherent mode by default */
		1339	dig->coherent_mode = true;
		1340
		1341	return dig;
		1342	}
		1343
		1344	void
		1345	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1346	{
		1347	struct drm_encoder *encoder;
		1348	struct radeon_encoder *radeon_encoder;
		1349
		1350	/* see if we already added it */
		1351	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1352	radeon_encoder = to_radeon_encoder(encoder);
		1353	if (radeon_encoder->encoder_id == encoder_id) {
		1354	radeon_encoder->devices \|= supported_device;
		1355	return;
		1356	}
		1357
		1358	}
		1359
		1360	/* add a new one */
		1361	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1362	if (!radeon_encoder)
		1363	return;
		1364
		1365	encoder = &radeon_encoder->base;
		1366	encoder->possible_crtcs = 0x3;
		1367	encoder->possible_clones = 0;
		1368
		1369	radeon_encoder->enc_priv = NULL;
		1370
		1371	radeon_encoder->encoder_id = encoder_id;
		1372	radeon_encoder->devices = supported_device;
1179	serge	1373	radeon_encoder->rmx_type = RMX_OFF;
1125	serge	1374
		1375	switch (radeon_encoder->encoder_id) {
		1376	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1377	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1378	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1379	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1380	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1381	radeon_encoder->rmx_type = RMX_FULL;
		1382	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1383	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1384	} else {
		1385	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1386	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		1387	}
		1388	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1389	break;
		1390	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1391	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		1392	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1393	break;
		1394	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1395	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1396	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1397	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1179	serge	1398	radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1125	serge	1399	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1400	break;
		1401	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1402	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1403	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1404	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1405	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1406	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1407	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1179	serge	1408	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1409	radeon_encoder->rmx_type = RMX_FULL;
		1410	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1411	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1412	} else {
1125	serge	1413	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1414	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1179	serge	1415	}
1125	serge	1416	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1417	break;
		1418	}
		1419	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_encoders.c – Rev 1179