WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_encoders.c

Rev	Author	Line No.	Line
1125	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	//#include
		28	//#include
		29	//#include
		30
		31	#include "drm_crtc.h"
		32	#include "drm_crtc_helper.h"
		33	#include "radeon_drm.h"
		34	#include "radeon.h"
		35	#include "atom.h"
		36
		37	extern int atom_debug;
		38
		39	uint32_t
		40	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
		41	{
		42	struct radeon_device *rdev = dev->dev_private;
		43	uint32_t ret = 0;
		44
		45	switch (supported_device) {
		46	case ATOM_DEVICE_CRT1_SUPPORT:
		47	case ATOM_DEVICE_TV1_SUPPORT:
		48	case ATOM_DEVICE_TV2_SUPPORT:
		49	case ATOM_DEVICE_CRT2_SUPPORT:
		50	case ATOM_DEVICE_CV_SUPPORT:
		51	switch (dac) {
		52	case 1: /* dac a */
		53	if ((rdev->family == CHIP_RS300) \|\|
		54	(rdev->family == CHIP_RS400) \|\|
		55	(rdev->family == CHIP_RS480))
		56	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		57	else if (ASIC_IS_AVIVO(rdev))
		58	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
		59	else
		60	ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
		61	break;
		62	case 2: /* dac b */
		63	if (ASIC_IS_AVIVO(rdev))
		64	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
		65	else {
		66	/*if (rdev->family == CHIP_R200)
		67	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		68	else*/
		69	ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
		70	}
		71	break;
		72	case 3: /* external dac */
		73	if (ASIC_IS_AVIVO(rdev))
		74	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		75	else
		76	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		77	break;
		78	}
		79	break;
		80	case ATOM_DEVICE_LCD1_SUPPORT:
		81	if (ASIC_IS_AVIVO(rdev))
		82	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		83	else
		84	ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
		85	break;
		86	case ATOM_DEVICE_DFP1_SUPPORT:
		87	if ((rdev->family == CHIP_RS300) \|\|
		88	(rdev->family == CHIP_RS400) \|\|
		89	(rdev->family == CHIP_RS480))
		90	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		91	else if (ASIC_IS_AVIVO(rdev))
		92	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
		93	else
		94	ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
		95	break;
		96	case ATOM_DEVICE_LCD2_SUPPORT:
		97	case ATOM_DEVICE_DFP2_SUPPORT:
		98	if ((rdev->family == CHIP_RS600) \|\|
		99	(rdev->family == CHIP_RS690) \|\|
		100	(rdev->family == CHIP_RS740))
		101	ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
		102	else if (ASIC_IS_AVIVO(rdev))
		103	ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
		104	else
		105	ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
		106	break;
		107	case ATOM_DEVICE_DFP3_SUPPORT:
		108	ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
		109	break;
		110	}
		111
		112	return ret;
		113	}
		114
		115	void
		116	radeon_link_encoder_connector(struct drm_device *dev)
		117	{
		118	struct drm_connector *connector;
		119	struct radeon_connector *radeon_connector;
		120	struct drm_encoder *encoder;
		121	struct radeon_encoder *radeon_encoder;
		122
		123	/* walk the list and link encoders to connectors */
		124	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		125	radeon_connector = to_radeon_connector(connector);
		126	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		127	radeon_encoder = to_radeon_encoder(encoder);
		128	if (radeon_encoder->devices & radeon_connector->devices)
		129	drm_mode_connector_attach_encoder(connector, encoder);
		130	}
		131	}
		132	}
		133
		134	static struct drm_connector *
		135	radeon_get_connector_for_encoder(struct drm_encoder *encoder)
		136	{
		137	struct drm_device *dev = encoder->dev;
		138	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		139	struct drm_connector *connector;
		140	struct radeon_connector *radeon_connector;
		141
		142	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		143	radeon_connector = to_radeon_connector(connector);
		144	if (radeon_encoder->devices & radeon_connector->devices)
		145	return connector;
		146	}
		147	return NULL;
		148	}
		149
		150	/* used for both atom and legacy */
		151	void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
		152	struct drm_display_mode *mode,
		153	struct drm_display_mode *adjusted_mode)
		154	{
		155	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		156	struct drm_device *dev = encoder->dev;
		157	struct radeon_device *rdev = dev->dev_private;
		158	struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
		159
		160	if (mode->hdisplay < native_mode->panel_xres \|\|
		161	mode->vdisplay < native_mode->panel_yres) {
		162	radeon_encoder->flags \|= RADEON_USE_RMX;
		163	if (ASIC_IS_AVIVO(rdev)) {
		164	adjusted_mode->hdisplay = native_mode->panel_xres;
		165	adjusted_mode->vdisplay = native_mode->panel_yres;
		166	adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
		167	adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
		168	adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
		169	adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
		170	adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
		171	adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
		172	/* update crtc values */
		173	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
		174	/* adjust crtc values */
		175	adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
		176	adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
		177	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
		178	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
		179	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
		180	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
		181	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
		182	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
		183	} else {
		184	adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
		185	adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
		186	adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
		187	adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
		188	adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
		189	adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
		190	/* update crtc values */
		191	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
		192	/* adjust crtc values */
		193	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
		194	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
		195	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
		196	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
		197	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
		198	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
		199	}
		200	adjusted_mode->flags = native_mode->flags;
		201	adjusted_mode->clock = native_mode->dotclock;
		202	}
		203	}
		204
		205	static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
		206	struct drm_display_mode *mode,
		207	struct drm_display_mode *adjusted_mode)
		208	{
		209
		210	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		211
		212	radeon_encoder->flags &= ~RADEON_USE_RMX;
		213
		214	drm_mode_set_crtcinfo(adjusted_mode, 0);
		215
		216	if (radeon_encoder->rmx_type != RMX_OFF)
		217	radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
		218
		219	/* hw bug */
		220	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
		221	&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
		222	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
		223
		224	return true;
		225	}
		226
		227	static void
		228	atombios_dac_setup(struct drm_encoder *encoder, int action)
		229	{
		230	struct drm_device *dev = encoder->dev;
		231	struct radeon_device *rdev = dev->dev_private;
		232	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		233	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
		234	int index = 0, num = 0;
		235	/* fixme - fill in enc_priv for atom dac */
		236	enum radeon_tv_std tv_std = TV_STD_NTSC;
		237
		238	memset(&args, 0, sizeof(args));
		239
		240	switch (radeon_encoder->encoder_id) {
		241	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		242	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		243	index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
		244	num = 1;
		245	break;
		246	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		247	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		248	index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
		249	num = 2;
		250	break;
		251	}
		252
		253	args.ucAction = action;
		254
		255	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
		256	args.ucDacStandard = ATOM_DAC1_PS2;
		257	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		258	args.ucDacStandard = ATOM_DAC1_CV;
		259	else {
		260	switch (tv_std) {
		261	case TV_STD_PAL:
		262	case TV_STD_PAL_M:
		263	case TV_STD_SCART_PAL:
		264	case TV_STD_SECAM:
		265	case TV_STD_PAL_CN:
		266	args.ucDacStandard = ATOM_DAC1_PAL;
		267	break;
		268	case TV_STD_NTSC:
		269	case TV_STD_NTSC_J:
		270	case TV_STD_PAL_60:
		271	default:
		272	args.ucDacStandard = ATOM_DAC1_NTSC;
		273	break;
		274	}
		275	}
		276	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		277
		278	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		279
		280	}
		281
		282	static void
		283	atombios_tv_setup(struct drm_encoder *encoder, int action)
		284	{
		285	struct drm_device *dev = encoder->dev;
		286	struct radeon_device *rdev = dev->dev_private;
		287	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		288	TV_ENCODER_CONTROL_PS_ALLOCATION args;
		289	int index = 0;
		290	/* fixme - fill in enc_priv for atom dac */
		291	enum radeon_tv_std tv_std = TV_STD_NTSC;
		292
		293	memset(&args, 0, sizeof(args));
		294
		295	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
		296
		297	args.sTVEncoder.ucAction = action;
		298
		299	if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		300	args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
		301	else {
		302	switch (tv_std) {
		303	case TV_STD_NTSC:
		304	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		305	break;
		306	case TV_STD_PAL:
		307	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
		308	break;
		309	case TV_STD_PAL_M:
		310	args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
		311	break;
		312	case TV_STD_PAL_60:
		313	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
		314	break;
		315	case TV_STD_NTSC_J:
		316	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
		317	break;
		318	case TV_STD_SCART_PAL:
		319	args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
		320	break;
		321	case TV_STD_SECAM:
		322	args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
		323	break;
		324	case TV_STD_PAL_CN:
		325	args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
		326	break;
		327	default:
		328	args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
		329	break;
		330	}
		331	}
		332
		333	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		334
		335	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		336
		337	}
		338
		339	void
		340	atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
		341	{
		342	struct drm_device *dev = encoder->dev;
		343	struct radeon_device *rdev = dev->dev_private;
		344	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		345	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
		346	int index = 0;
		347
		348	memset(&args, 0, sizeof(args));
		349
		350	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		351
		352	args.sXTmdsEncoder.ucEnable = action;
		353
		354	if (radeon_encoder->pixel_clock > 165000)
		355	args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
		356
		357	/if (pScrn->rgbBits == 8)/
		358	args.sXTmdsEncoder.ucMisc \|= (1 << 1);
		359
		360	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		361
		362	}
		363
		364	static void
		365	atombios_ddia_setup(struct drm_encoder *encoder, int action)
		366	{
		367	struct drm_device *dev = encoder->dev;
		368	struct radeon_device *rdev = dev->dev_private;
		369	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		370	DVO_ENCODER_CONTROL_PS_ALLOCATION args;
		371	int index = 0;
		372
		373	memset(&args, 0, sizeof(args));
		374
		375	index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
		376
		377	args.sDVOEncoder.ucAction = action;
		378	args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		379
		380	if (radeon_encoder->pixel_clock > 165000)
		381	args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
		382
		383	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		384
		385	}
		386
		387	union lvds_encoder_control {
		388	LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
		389	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
		390	};
		391
		392	static void
		393	atombios_digital_setup(struct drm_encoder *encoder, int action)
		394	{
		395	struct drm_device *dev = encoder->dev;
		396	struct radeon_device *rdev = dev->dev_private;
		397	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		398	union lvds_encoder_control args;
		399	int index = 0;
		400	uint8_t frev, crev;
		401	struct radeon_encoder_atom_dig *dig;
		402	struct drm_connector *connector;
		403	struct radeon_connector *radeon_connector;
		404	struct radeon_connector_atom_dig *dig_connector;
		405
		406	connector = radeon_get_connector_for_encoder(encoder);
		407	if (!connector)
		408	return;
		409
		410	radeon_connector = to_radeon_connector(connector);
		411
		412	if (!radeon_encoder->enc_priv)
		413	return;
		414
		415	dig = radeon_encoder->enc_priv;
		416
		417	if (!radeon_connector->con_priv)
		418	return;
		419
		420	dig_connector = radeon_connector->con_priv;
		421
		422	memset(&args, 0, sizeof(args));
		423
		424	switch (radeon_encoder->encoder_id) {
		425	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		426	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		427	break;
		428	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		429	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		430	index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
		431	break;
		432	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		433	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		434	index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
		435	else
		436	index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
		437	break;
		438	}
		439
		440	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		441
		442	switch (frev) {
		443	case 1:
		444	case 2:
		445	switch (crev) {
		446	case 1:
		447	args.v1.ucMisc = 0;
		448	args.v1.ucAction = action;
		449	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		450	args.v1.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		451	args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		452	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		453	if (dig->lvds_misc & (1 << 0))
		454	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		455	if (dig->lvds_misc & (1 << 1))
		456	args.v1.ucMisc \|= (1 << 1);
		457	} else {
		458	if (dig_connector->linkb)
		459	args.v1.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		460	if (radeon_encoder->pixel_clock > 165000)
		461	args.v1.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		462	/if (pScrn->rgbBits == 8) /
		463	args.v1.ucMisc \|= (1 << 1);
		464	}
		465	break;
		466	case 2:
		467	case 3:
		468	args.v2.ucMisc = 0;
		469	args.v2.ucAction = action;
		470	if (crev == 3) {
		471	if (dig->coherent_mode)
		472	args.v2.ucMisc \|= PANEL_ENCODER_MISC_COHERENT;
		473	}
		474	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		475	args.v2.ucMisc \|= PANEL_ENCODER_MISC_HDMI_TYPE;
		476	args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		477	args.v2.ucTruncate = 0;
		478	args.v2.ucSpatial = 0;
		479	args.v2.ucTemporal = 0;
		480	args.v2.ucFRC = 0;
		481	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		482	if (dig->lvds_misc & (1 << 0))
		483	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		484	if (dig->lvds_misc & (1 << 5)) {
		485	args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
		486	if (dig->lvds_misc & (1 << 1))
		487	args.v2.ucSpatial \|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
		488	}
		489	if (dig->lvds_misc & (1 << 6)) {
		490	args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
		491	if (dig->lvds_misc & (1 << 1))
		492	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
		493	if (((dig->lvds_misc >> 2) & 0x3) == 2)
		494	args.v2.ucTemporal \|= PANEL_ENCODER_TEMPORAL_LEVEL_4;
		495	}
		496	} else {
		497	if (dig_connector->linkb)
		498	args.v2.ucMisc \|= PANEL_ENCODER_MISC_TMDS_LINKB;
		499	if (radeon_encoder->pixel_clock > 165000)
		500	args.v2.ucMisc \|= PANEL_ENCODER_MISC_DUAL;
		501	}
		502	break;
		503	default:
		504	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		505	break;
		506	}
		507	break;
		508	default:
		509	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		510	break;
		511	}
		512
		513	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		514
		515	}
		516
		517	int
		518	atombios_get_encoder_mode(struct drm_encoder *encoder)
		519	{
		520	struct drm_connector *connector;
		521	struct radeon_connector *radeon_connector;
		522
		523	connector = radeon_get_connector_for_encoder(encoder);
		524	if (!connector)
		525	return 0;
		526
		527	radeon_connector = to_radeon_connector(connector);
		528
		529	switch (connector->connector_type) {
		530	case DRM_MODE_CONNECTOR_DVII:
		531	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		532	return ATOM_ENCODER_MODE_HDMI;
		533	else if (radeon_connector->use_digital)
		534	return ATOM_ENCODER_MODE_DVI;
		535	else
		536	return ATOM_ENCODER_MODE_CRT;
		537	break;
		538	case DRM_MODE_CONNECTOR_DVID:
		539	case DRM_MODE_CONNECTOR_HDMIA:
		540	case DRM_MODE_CONNECTOR_HDMIB:
		541	default:
		542	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		543	return ATOM_ENCODER_MODE_HDMI;
		544	else
		545	return ATOM_ENCODER_MODE_DVI;
		546	break;
		547	case DRM_MODE_CONNECTOR_LVDS:
		548	return ATOM_ENCODER_MODE_LVDS;
		549	break;
		550	case DRM_MODE_CONNECTOR_DisplayPort:
		551	/*if (radeon_output->MonType == MT_DP)
		552	return ATOM_ENCODER_MODE_DP;
		553	else*/
		554	if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
		555	return ATOM_ENCODER_MODE_HDMI;
		556	else
		557	return ATOM_ENCODER_MODE_DVI;
		558	break;
		559	case CONNECTOR_DVI_A:
		560	case CONNECTOR_VGA:
		561	return ATOM_ENCODER_MODE_CRT;
		562	break;
		563	case CONNECTOR_STV:
		564	case CONNECTOR_CTV:
		565	case CONNECTOR_DIN:
		566	/* fix me */
		567	return ATOM_ENCODER_MODE_TV;
		568	/return ATOM_ENCODER_MODE_CV;/
		569	break;
		570	}
		571	}
		572
		573	static void
		574	atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
		575	{
		576	struct drm_device *dev = encoder->dev;
		577	struct radeon_device *rdev = dev->dev_private;
		578	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		579	DIG_ENCODER_CONTROL_PS_ALLOCATION args;
		580	int index = 0, num = 0;
		581	uint8_t frev, crev;
		582	struct radeon_encoder_atom_dig *dig;
		583	struct drm_connector *connector;
		584	struct radeon_connector *radeon_connector;
		585	struct radeon_connector_atom_dig *dig_connector;
		586
		587	connector = radeon_get_connector_for_encoder(encoder);
		588	if (!connector)
		589	return;
		590
		591	radeon_connector = to_radeon_connector(connector);
		592
		593	if (!radeon_connector->con_priv)
		594	return;
		595
		596	dig_connector = radeon_connector->con_priv;
		597
		598	if (!radeon_encoder->enc_priv)
		599	return;
		600
		601	dig = radeon_encoder->enc_priv;
		602
		603	memset(&args, 0, sizeof(args));
		604
		605	if (ASIC_IS_DCE32(rdev)) {
		606	if (dig->dig_block)
		607	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		608	else
		609	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
		610	num = dig->dig_block + 1;
		611	} else {
		612	switch (radeon_encoder->encoder_id) {
		613	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		614	index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
		615	num = 1;
		616	break;
		617	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		618	index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
		619	num = 2;
		620	break;
		621	}
		622	}
		623
		624	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		625
		626	args.ucAction = action;
		627	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
		628
		629	if (ASIC_IS_DCE32(rdev)) {
		630	switch (radeon_encoder->encoder_id) {
		631	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		632	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
		633	break;
		634	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		635	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
		636	break;
		637	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		638	args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
		639	break;
		640	}
		641	} else {
		642	switch (radeon_encoder->encoder_id) {
		643	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		644	args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
		645	break;
		646	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		647	args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
		648	break;
		649	}
		650	}
		651
		652	if (radeon_encoder->pixel_clock > 165000) {
		653	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA_B;
		654	args.ucLaneNum = 8;
		655	} else {
		656	if (dig_connector->linkb)
		657	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKB;
		658	else
		659	args.ucConfig \|= ATOM_ENCODER_CONFIG_LINKA;
		660	args.ucLaneNum = 4;
		661	}
		662
		663	args.ucEncoderMode = atombios_get_encoder_mode(encoder);
		664
		665	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		666
		667	}
		668
		669	union dig_transmitter_control {
		670	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
		671	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
		672	};
		673
		674	static void
		675	atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
		676	{
		677	struct drm_device *dev = encoder->dev;
		678	struct radeon_device *rdev = dev->dev_private;
		679	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		680	union dig_transmitter_control args;
		681	int index = 0, num = 0;
		682	uint8_t frev, crev;
		683	struct radeon_encoder_atom_dig *dig;
		684	struct drm_connector *connector;
		685	struct radeon_connector *radeon_connector;
		686	struct radeon_connector_atom_dig *dig_connector;
		687
		688	connector = radeon_get_connector_for_encoder(encoder);
		689	if (!connector)
		690	return;
		691
		692	radeon_connector = to_radeon_connector(connector);
		693
		694	if (!radeon_encoder->enc_priv)
		695	return;
		696
		697	dig = radeon_encoder->enc_priv;
		698
		699	if (!radeon_connector->con_priv)
		700	return;
		701
		702	dig_connector = radeon_connector->con_priv;
		703
		704	memset(&args, 0, sizeof(args));
		705
		706	if (ASIC_IS_DCE32(rdev))
		707	index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
		708	else {
		709	switch (radeon_encoder->encoder_id) {
		710	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		711	index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
		712	break;
		713	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		714	index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
		715	break;
		716	}
		717	}
		718
		719	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		720
		721	args.v1.ucAction = action;
		722
		723	if (ASIC_IS_DCE32(rdev)) {
		724	if (radeon_encoder->pixel_clock > 165000) {
		725	args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
		726	args.v2.acConfig.fDualLinkConnector = 1;
		727	} else {
		728	args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
		729	}
		730	if (dig->dig_block)
		731	args.v2.acConfig.ucEncoderSel = 1;
		732
		733	switch (radeon_encoder->encoder_id) {
		734	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		735	args.v2.acConfig.ucTransmitterSel = 0;
		736	num = 0;
		737	break;
		738	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		739	args.v2.acConfig.ucTransmitterSel = 1;
		740	num = 1;
		741	break;
		742	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		743	args.v2.acConfig.ucTransmitterSel = 2;
		744	num = 2;
		745	break;
		746	}
		747
		748	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		749	if (dig->coherent_mode)
		750	args.v2.acConfig.fCoherentMode = 1;
		751	}
		752	} else {
		753	args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
		754	args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
		755
		756	switch (radeon_encoder->encoder_id) {
		757	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		758	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
		759	if (rdev->flags & RADEON_IS_IGP) {
		760	if (radeon_encoder->pixel_clock > 165000) {
		761	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		762	ATOM_TRANSMITTER_CONFIG_LINKA_B);
		763	if (dig_connector->igp_lane_info & 0x3)
		764	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
		765	else if (dig_connector->igp_lane_info & 0xc)
		766	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
		767	} else {
		768	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA;
		769	if (dig_connector->igp_lane_info & 0x1)
		770	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		771	else if (dig_connector->igp_lane_info & 0x2)
		772	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
		773	else if (dig_connector->igp_lane_info & 0x4)
		774	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
		775	else if (dig_connector->igp_lane_info & 0x8)
		776	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
		777	}
		778	} else {
		779	if (radeon_encoder->pixel_clock > 165000)
		780	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		781	ATOM_TRANSMITTER_CONFIG_LINKA_B \|
		782	ATOM_TRANSMITTER_CONFIG_LANE_0_7);
		783	else {
		784	if (dig_connector->linkb)
		785	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		786	else
		787	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		788	}
		789	}
		790	break;
		791	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		792	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
		793	if (radeon_encoder->pixel_clock > 165000)
		794	args.v1.ucConfig \|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK \|
		795	ATOM_TRANSMITTER_CONFIG_LINKA_B \|
		796	ATOM_TRANSMITTER_CONFIG_LANE_0_7);
		797	else {
		798	if (dig_connector->linkb)
		799	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKB \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		800	else
		801	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_LINKA \| ATOM_TRANSMITTER_CONFIG_LANE_0_3;
		802	}
		803	break;
		804	}
		805
		806	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		807	if (dig->coherent_mode)
		808	args.v1.ucConfig \|= ATOM_TRANSMITTER_CONFIG_COHERENT;
		809	}
		810	}
		811
		812	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		813
		814	}
		815
		816	static void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
		817	{
		818
		819	WREG32(0x659C, 0x0);
		820	WREG32(0x6594, 0x705);
		821	WREG32(0x65A4, 0x10001);
		822	WREG32(0x65D8, 0x0);
		823	WREG32(0x65B0, 0x0);
		824	WREG32(0x65C0, 0x0);
		825	WREG32(0x65D4, 0x0);
		826	WREG32(0x6578, 0x0);
		827	WREG32(0x657C, 0x841880A8);
		828	WREG32(0x6578, 0x1);
		829	WREG32(0x657C, 0x84208680);
		830	WREG32(0x6578, 0x2);
		831	WREG32(0x657C, 0xBFF880B0);
		832	WREG32(0x6578, 0x100);
		833	WREG32(0x657C, 0x83D88088);
		834	WREG32(0x6578, 0x101);
		835	WREG32(0x657C, 0x84608680);
		836	WREG32(0x6578, 0x102);
		837	WREG32(0x657C, 0xBFF080D0);
		838	WREG32(0x6578, 0x200);
		839	WREG32(0x657C, 0x83988068);
		840	WREG32(0x6578, 0x201);
		841	WREG32(0x657C, 0x84A08680);
		842	WREG32(0x6578, 0x202);
		843	WREG32(0x657C, 0xBFF080F8);
		844	WREG32(0x6578, 0x300);
		845	WREG32(0x657C, 0x83588058);
		846	WREG32(0x6578, 0x301);
		847	WREG32(0x657C, 0x84E08660);
		848	WREG32(0x6578, 0x302);
		849	WREG32(0x657C, 0xBFF88120);
		850	WREG32(0x6578, 0x400);
		851	WREG32(0x657C, 0x83188040);
		852	WREG32(0x6578, 0x401);
		853	WREG32(0x657C, 0x85008660);
		854	WREG32(0x6578, 0x402);
		855	WREG32(0x657C, 0xBFF88150);
		856	WREG32(0x6578, 0x500);
		857	WREG32(0x657C, 0x82D88030);
		858	WREG32(0x6578, 0x501);
		859	WREG32(0x657C, 0x85408640);
		860	WREG32(0x6578, 0x502);
		861	WREG32(0x657C, 0xBFF88180);
		862	WREG32(0x6578, 0x600);
		863	WREG32(0x657C, 0x82A08018);
		864	WREG32(0x6578, 0x601);
		865	WREG32(0x657C, 0x85808620);
		866	WREG32(0x6578, 0x602);
		867	WREG32(0x657C, 0xBFF081B8);
		868	WREG32(0x6578, 0x700);
		869	WREG32(0x657C, 0x82608010);
		870	WREG32(0x6578, 0x701);
		871	WREG32(0x657C, 0x85A08600);
		872	WREG32(0x6578, 0x702);
		873	WREG32(0x657C, 0x800081F0);
		874	WREG32(0x6578, 0x800);
		875	WREG32(0x657C, 0x8228BFF8);
		876	WREG32(0x6578, 0x801);
		877	WREG32(0x657C, 0x85E085E0);
		878	WREG32(0x6578, 0x802);
		879	WREG32(0x657C, 0xBFF88228);
		880	WREG32(0x6578, 0x10000);
		881	WREG32(0x657C, 0x82A8BF00);
		882	WREG32(0x6578, 0x10001);
		883	WREG32(0x657C, 0x82A08CC0);
		884	WREG32(0x6578, 0x10002);
		885	WREG32(0x657C, 0x8008BEF8);
		886	WREG32(0x6578, 0x10100);
		887	WREG32(0x657C, 0x81F0BF28);
		888	WREG32(0x6578, 0x10101);
		889	WREG32(0x657C, 0x83608CA0);
		890	WREG32(0x6578, 0x10102);
		891	WREG32(0x657C, 0x8018BED0);
		892	WREG32(0x6578, 0x10200);
		893	WREG32(0x657C, 0x8148BF38);
		894	WREG32(0x6578, 0x10201);
		895	WREG32(0x657C, 0x84408C80);
		896	WREG32(0x6578, 0x10202);
		897	WREG32(0x657C, 0x8008BEB8);
		898	WREG32(0x6578, 0x10300);
		899	WREG32(0x657C, 0x80B0BF78);
		900	WREG32(0x6578, 0x10301);
		901	WREG32(0x657C, 0x85008C20);
		902	WREG32(0x6578, 0x10302);
		903	WREG32(0x657C, 0x8020BEA0);
		904	WREG32(0x6578, 0x10400);
		905	WREG32(0x657C, 0x8028BF90);
		906	WREG32(0x6578, 0x10401);
		907	WREG32(0x657C, 0x85E08BC0);
		908	WREG32(0x6578, 0x10402);
		909	WREG32(0x657C, 0x8018BE90);
		910	WREG32(0x6578, 0x10500);
		911	WREG32(0x657C, 0xBFB8BFB0);
		912	WREG32(0x6578, 0x10501);
		913	WREG32(0x657C, 0x86C08B40);
		914	WREG32(0x6578, 0x10502);
		915	WREG32(0x657C, 0x8010BE90);
		916	WREG32(0x6578, 0x10600);
		917	WREG32(0x657C, 0xBF58BFC8);
		918	WREG32(0x6578, 0x10601);
		919	WREG32(0x657C, 0x87A08AA0);
		920	WREG32(0x6578, 0x10602);
		921	WREG32(0x657C, 0x8010BE98);
		922	WREG32(0x6578, 0x10700);
		923	WREG32(0x657C, 0xBF10BFF0);
		924	WREG32(0x6578, 0x10701);
		925	WREG32(0x657C, 0x886089E0);
		926	WREG32(0x6578, 0x10702);
		927	WREG32(0x657C, 0x8018BEB0);
		928	WREG32(0x6578, 0x10800);
		929	WREG32(0x657C, 0xBED8BFE8);
		930	WREG32(0x6578, 0x10801);
		931	WREG32(0x657C, 0x89408940);
		932	WREG32(0x6578, 0x10802);
		933	WREG32(0x657C, 0xBFE8BED8);
		934	WREG32(0x6578, 0x20000);
		935	WREG32(0x657C, 0x80008000);
		936	WREG32(0x6578, 0x20001);
		937	WREG32(0x657C, 0x90008000);
		938	WREG32(0x6578, 0x20002);
		939	WREG32(0x657C, 0x80008000);
		940	WREG32(0x6578, 0x20003);
		941	WREG32(0x657C, 0x80008000);
		942	WREG32(0x6578, 0x20100);
		943	WREG32(0x657C, 0x80108000);
		944	WREG32(0x6578, 0x20101);
		945	WREG32(0x657C, 0x8FE0BF70);
		946	WREG32(0x6578, 0x20102);
		947	WREG32(0x657C, 0xBFE880C0);
		948	WREG32(0x6578, 0x20103);
		949	WREG32(0x657C, 0x80008000);
		950	WREG32(0x6578, 0x20200);
		951	WREG32(0x657C, 0x8018BFF8);
		952	WREG32(0x6578, 0x20201);
		953	WREG32(0x657C, 0x8F80BF08);
		954	WREG32(0x6578, 0x20202);
		955	WREG32(0x657C, 0xBFD081A0);
		956	WREG32(0x6578, 0x20203);
		957	WREG32(0x657C, 0xBFF88000);
		958	WREG32(0x6578, 0x20300);
		959	WREG32(0x657C, 0x80188000);
		960	WREG32(0x6578, 0x20301);
		961	WREG32(0x657C, 0x8EE0BEC0);
		962	WREG32(0x6578, 0x20302);
		963	WREG32(0x657C, 0xBFB082A0);
		964	WREG32(0x6578, 0x20303);
		965	WREG32(0x657C, 0x80008000);
		966	WREG32(0x6578, 0x20400);
		967	WREG32(0x657C, 0x80188000);
		968	WREG32(0x6578, 0x20401);
		969	WREG32(0x657C, 0x8E00BEA0);
		970	WREG32(0x6578, 0x20402);
		971	WREG32(0x657C, 0xBF8883C0);
		972	WREG32(0x6578, 0x20403);
		973	WREG32(0x657C, 0x80008000);
		974	WREG32(0x6578, 0x20500);
		975	WREG32(0x657C, 0x80188000);
		976	WREG32(0x6578, 0x20501);
		977	WREG32(0x657C, 0x8D00BE90);
		978	WREG32(0x6578, 0x20502);
		979	WREG32(0x657C, 0xBF588500);
		980	WREG32(0x6578, 0x20503);
		981	WREG32(0x657C, 0x80008008);
		982	WREG32(0x6578, 0x20600);
		983	WREG32(0x657C, 0x80188000);
		984	WREG32(0x6578, 0x20601);
		985	WREG32(0x657C, 0x8BC0BE98);
		986	WREG32(0x6578, 0x20602);
		987	WREG32(0x657C, 0xBF308660);
		988	WREG32(0x6578, 0x20603);
		989	WREG32(0x657C, 0x80008008);
		990	WREG32(0x6578, 0x20700);
		991	WREG32(0x657C, 0x80108000);
		992	WREG32(0x6578, 0x20701);
		993	WREG32(0x657C, 0x8A80BEB0);
		994	WREG32(0x6578, 0x20702);
		995	WREG32(0x657C, 0xBF0087C0);
		996	WREG32(0x6578, 0x20703);
		997	WREG32(0x657C, 0x80008008);
		998	WREG32(0x6578, 0x20800);
		999	WREG32(0x657C, 0x80108000);
		1000	WREG32(0x6578, 0x20801);
		1001	WREG32(0x657C, 0x8920BED0);
		1002	WREG32(0x6578, 0x20802);
		1003	WREG32(0x657C, 0xBED08920);
		1004	WREG32(0x6578, 0x20803);
		1005	WREG32(0x657C, 0x80008010);
		1006	WREG32(0x6578, 0x30000);
		1007	WREG32(0x657C, 0x90008000);
		1008	WREG32(0x6578, 0x30001);
		1009	WREG32(0x657C, 0x80008000);
		1010	WREG32(0x6578, 0x30100);
		1011	WREG32(0x657C, 0x8FE0BF90);
		1012	WREG32(0x6578, 0x30101);
		1013	WREG32(0x657C, 0xBFF880A0);
		1014	WREG32(0x6578, 0x30200);
		1015	WREG32(0x657C, 0x8F60BF40);
		1016	WREG32(0x6578, 0x30201);
		1017	WREG32(0x657C, 0xBFE88180);
		1018	WREG32(0x6578, 0x30300);
		1019	WREG32(0x657C, 0x8EC0BF00);
		1020	WREG32(0x6578, 0x30301);
		1021	WREG32(0x657C, 0xBFC88280);
		1022	WREG32(0x6578, 0x30400);
		1023	WREG32(0x657C, 0x8DE0BEE0);
		1024	WREG32(0x6578, 0x30401);
		1025	WREG32(0x657C, 0xBFA083A0);
		1026	WREG32(0x6578, 0x30500);
		1027	WREG32(0x657C, 0x8CE0BED0);
		1028	WREG32(0x6578, 0x30501);
		1029	WREG32(0x657C, 0xBF7884E0);
		1030	WREG32(0x6578, 0x30600);
		1031	WREG32(0x657C, 0x8BA0BED8);
		1032	WREG32(0x6578, 0x30601);
		1033	WREG32(0x657C, 0xBF508640);
		1034	WREG32(0x6578, 0x30700);
		1035	WREG32(0x657C, 0x8A60BEE8);
		1036	WREG32(0x6578, 0x30701);
		1037	WREG32(0x657C, 0xBF2087A0);
		1038	WREG32(0x6578, 0x30800);
		1039	WREG32(0x657C, 0x8900BF00);
		1040	WREG32(0x6578, 0x30801);
		1041	WREG32(0x657C, 0xBF008900);
		1042	}
		1043
		1044	static void
		1045	atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
		1046	{
		1047	struct drm_device *dev = encoder->dev;
		1048	struct radeon_device *rdev = dev->dev_private;
		1049	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1050	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1051	ENABLE_YUV_PS_ALLOCATION args;
		1052	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
		1053	uint32_t temp, reg;
		1054
		1055	memset(&args, 0, sizeof(args));
		1056
		1057	if (rdev->family >= CHIP_R600)
		1058	reg = R600_BIOS_3_SCRATCH;
		1059	else
		1060	reg = RADEON_BIOS_3_SCRATCH;
		1061
		1062	/* XXX: fix up scratch reg handling */
		1063	temp = RREG32(reg);
		1064	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1065	WREG32(reg, (ATOM_S3_TV1_ACTIVE \|
		1066	(radeon_crtc->crtc_id << 18)));
		1067	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1068	WREG32(reg, (ATOM_S3_CV_ACTIVE \| (radeon_crtc->crtc_id << 24)));
		1069	else
		1070	WREG32(reg, 0);
		1071
		1072	if (enable)
		1073	args.ucEnable = ATOM_ENABLE;
		1074	args.ucCRTC = radeon_crtc->crtc_id;
		1075
		1076	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1077
		1078	WREG32(reg, temp);
		1079	}
		1080
		1081	static void
		1082	atombios_overscan_setup(struct drm_encoder *encoder,
		1083	struct drm_display_mode *mode,
		1084	struct drm_display_mode *adjusted_mode)
		1085	{
		1086	struct drm_device *dev = encoder->dev;
		1087	struct radeon_device *rdev = dev->dev_private;
		1088	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1089	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1090	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
		1091	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
		1092
		1093	memset(&args, 0, sizeof(args));
		1094
		1095	args.usOverscanRight = 0;
		1096	args.usOverscanLeft = 0;
		1097	args.usOverscanBottom = 0;
		1098	args.usOverscanTop = 0;
		1099	args.ucCRTC = radeon_crtc->crtc_id;
		1100
		1101	if (radeon_encoder->flags & RADEON_USE_RMX) {
		1102	if (radeon_encoder->rmx_type == RMX_FULL) {
		1103	args.usOverscanRight = 0;
		1104	args.usOverscanLeft = 0;
		1105	args.usOverscanBottom = 0;
		1106	args.usOverscanTop = 0;
		1107	} else if (radeon_encoder->rmx_type == RMX_CENTER) {
		1108	args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
		1109	args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
		1110	args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
		1111	args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
		1112	} else if (radeon_encoder->rmx_type == RMX_ASPECT) {
		1113	int a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
		1114	int a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
		1115
		1116	if (a1 > a2) {
		1117	args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
		1118	args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
		1119	} else if (a2 > a1) {
		1120	args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
		1121	args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
		1122	}
		1123	}
		1124	}
		1125
		1126	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1127
		1128	}
		1129
		1130	static void
		1131	atombios_scaler_setup(struct drm_encoder *encoder)
		1132	{
		1133	struct drm_device *dev = encoder->dev;
		1134	struct radeon_device *rdev = dev->dev_private;
		1135	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1136	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1137	ENABLE_SCALER_PS_ALLOCATION args;
		1138	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
		1139	/* fixme - fill in enc_priv for atom dac */
		1140	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1141
		1142	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
		1143	return;
		1144
		1145	memset(&args, 0, sizeof(args));
		1146
		1147	args.ucScaler = radeon_crtc->crtc_id;
		1148
		1149	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		1150	switch (tv_std) {
		1151	case TV_STD_NTSC:
		1152	default:
		1153	args.ucTVStandard = ATOM_TV_NTSC;
		1154	break;
		1155	case TV_STD_PAL:
		1156	args.ucTVStandard = ATOM_TV_PAL;
		1157	break;
		1158	case TV_STD_PAL_M:
		1159	args.ucTVStandard = ATOM_TV_PALM;
		1160	break;
		1161	case TV_STD_PAL_60:
		1162	args.ucTVStandard = ATOM_TV_PAL60;
		1163	break;
		1164	case TV_STD_NTSC_J:
		1165	args.ucTVStandard = ATOM_TV_NTSCJ;
		1166	break;
		1167	case TV_STD_SCART_PAL:
		1168	args.ucTVStandard = ATOM_TV_PAL; /* ??? */
		1169	break;
		1170	case TV_STD_SECAM:
		1171	args.ucTVStandard = ATOM_TV_SECAM;
		1172	break;
		1173	case TV_STD_PAL_CN:
		1174	args.ucTVStandard = ATOM_TV_PALCN;
		1175	break;
		1176	}
		1177	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		1178	} else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) {
		1179	args.ucTVStandard = ATOM_TV_CV;
		1180	args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
		1181	} else if (radeon_encoder->flags & RADEON_USE_RMX) {
		1182	if (radeon_encoder->rmx_type == RMX_FULL)
		1183	args.ucEnable = ATOM_SCALER_EXPANSION;
		1184	else if (radeon_encoder->rmx_type == RMX_CENTER)
		1185	args.ucEnable = ATOM_SCALER_CENTER;
		1186	else if (radeon_encoder->rmx_type == RMX_ASPECT)
		1187	args.ucEnable = ATOM_SCALER_EXPANSION;
		1188	} else {
		1189	if (ASIC_IS_AVIVO(rdev))
		1190	args.ucEnable = ATOM_SCALER_DISABLE;
		1191	else
		1192	args.ucEnable = ATOM_SCALER_CENTER;
		1193	}
		1194
		1195	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1196
		1197	if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT \| ATOM_DEVICE_TV_SUPPORT)
		1198	&& rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
		1199	atom_rv515_force_tv_scaler(rdev);
		1200	}
		1201
		1202	}
		1203
		1204	static void
		1205	radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
		1206	{
		1207	struct drm_device *dev = encoder->dev;
		1208	struct radeon_device *rdev = dev->dev_private;
		1209	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1210	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
		1211	int index = 0;
		1212	bool is_dig = false;
		1213
		1214	memset(&args, 0, sizeof(args));
		1215
		1216	switch (radeon_encoder->encoder_id) {
		1217	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1218	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1219	index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
		1220	break;
		1221	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1222	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1223	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1224	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1225	is_dig = true;
		1226	break;
		1227	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1228	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1229	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1230	index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
		1231	break;
		1232	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1233	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1234	break;
		1235	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1236	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
		1237	index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
		1238	else
		1239	index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
		1240	break;
		1241	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1242	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1243	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1244	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
		1245	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1246	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1247	else
		1248	index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
		1249	break;
		1250	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1251	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1252	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1253	index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
		1254	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1255	index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
		1256	else
		1257	index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
		1258	break;
		1259	}
		1260
		1261	if (is_dig) {
		1262	switch (mode) {
		1263	case DRM_MODE_DPMS_ON:
		1264	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
		1265	break;
		1266	case DRM_MODE_DPMS_STANDBY:
		1267	case DRM_MODE_DPMS_SUSPEND:
		1268	case DRM_MODE_DPMS_OFF:
		1269	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
		1270	break;
		1271	}
		1272	} else {
		1273	switch (mode) {
		1274	case DRM_MODE_DPMS_ON:
		1275	args.ucAction = ATOM_ENABLE;
		1276	break;
		1277	case DRM_MODE_DPMS_STANDBY:
		1278	case DRM_MODE_DPMS_SUSPEND:
		1279	case DRM_MODE_DPMS_OFF:
		1280	args.ucAction = ATOM_DISABLE;
		1281	break;
		1282	}
		1283	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1284	}
		1285	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
		1286	}
		1287
		1288	union crtc_sourc_param {
		1289	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
		1290	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
		1291	};
		1292
		1293	static void
		1294	atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
		1295	{
		1296	struct drm_device *dev = encoder->dev;
		1297	struct radeon_device *rdev = dev->dev_private;
		1298	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1299	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1300	union crtc_sourc_param args;
		1301	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
		1302	uint8_t frev, crev;
		1303
		1304	memset(&args, 0, sizeof(args));
		1305
		1306	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		1307
		1308	switch (frev) {
		1309	case 1:
		1310	switch (crev) {
		1311	case 1:
		1312	default:
		1313	if (ASIC_IS_AVIVO(rdev))
		1314	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1315	else {
		1316	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
		1317	args.v1.ucCRTC = radeon_crtc->crtc_id;
		1318	} else {
		1319	args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
		1320	}
		1321	}
		1322	switch (radeon_encoder->encoder_id) {
		1323	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1324	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1325	args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
		1326	break;
		1327	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1328	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1329	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
		1330	args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
		1331	else
		1332	args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
		1333	break;
		1334	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1335	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1336	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1337	args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
		1338	break;
		1339	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1340	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1341	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1342	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
		1343	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1344	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1345	else
		1346	args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
		1347	break;
		1348	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1349	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1350	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1351	args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
		1352	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1353	args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
		1354	else
		1355	args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
		1356	break;
		1357	}
		1358	break;
		1359	case 2:
		1360	args.v2.ucCRTC = radeon_crtc->crtc_id;
		1361	args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
		1362	switch (radeon_encoder->encoder_id) {
		1363	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1364	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1365	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1366	if (ASIC_IS_DCE32(rdev)) {
		1367	if (radeon_crtc->crtc_id)
		1368	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
		1369	else
		1370	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1371	} else
		1372	args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
		1373	break;
		1374	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1375	args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
		1376	break;
		1377	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1378	args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
		1379	break;
		1380	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1381	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1382	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1383	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1384	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1385	else
		1386	args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
		1387	break;
		1388	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1389	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
		1390	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1391	else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
		1392	args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
		1393	else
		1394	args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
		1395	break;
		1396	}
		1397	break;
		1398	}
		1399	break;
		1400	default:
		1401	DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
		1402	break;
		1403	}
		1404
		1405	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1406
		1407	}
		1408
		1409	static void
		1410	atombios_apply_encoder_quirks(struct drm_encoder *encoder,
		1411	struct drm_display_mode *mode)
		1412	{
		1413	struct drm_device *dev = encoder->dev;
		1414	struct radeon_device *rdev = dev->dev_private;
		1415	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1416	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1417
		1418	/* Funky macbooks */
		1419	if ((dev->pdev->device == 0x71C5) &&
		1420	(dev->pdev->subsystem_vendor == 0x106b) &&
		1421	(dev->pdev->subsystem_device == 0x0080)) {
		1422	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1423	uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
		1424
		1425	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
		1426	lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
		1427
		1428	WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
		1429	}
		1430	}
		1431
		1432	/* set scaler clears this on some chips */
		1433	if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
		1434	WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
		1435	}
		1436
		1437	static void
		1438	radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
		1439	struct drm_display_mode *mode,
		1440	struct drm_display_mode *adjusted_mode)
		1441	{
		1442	struct drm_device *dev = encoder->dev;
		1443	struct radeon_device *rdev = dev->dev_private;
		1444	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1445	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
		1446
		1447	if (radeon_encoder->enc_priv) {
		1448	struct radeon_encoder_atom_dig *dig;
		1449
		1450	dig = radeon_encoder->enc_priv;
		1451	dig->dig_block = radeon_crtc->crtc_id;
		1452	}
		1453	radeon_encoder->pixel_clock = adjusted_mode->clock;
		1454
		1455	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
		1456	atombios_overscan_setup(encoder, mode, adjusted_mode);
		1457	atombios_scaler_setup(encoder);
		1458	atombios_set_encoder_crtc_source(encoder);
		1459
		1460	if (ASIC_IS_AVIVO(rdev)) {
		1461	if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT \| ATOM_DEVICE_TV_SUPPORT))
		1462	atombios_yuv_setup(encoder, true);
		1463	else
		1464	atombios_yuv_setup(encoder, false);
		1465	}
		1466
		1467	switch (radeon_encoder->encoder_id) {
		1468	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1469	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1470	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1471	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1472	atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
		1473	break;
		1474	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1475	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1476	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1477	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1478	/* disable the encoder and transmitter */
		1479	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
		1480	atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
		1481
		1482	/* setup and enable the encoder and transmitter */
		1483	atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
		1484	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
		1485	atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
		1486	break;
		1487	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1488	atombios_ddia_setup(encoder, ATOM_ENABLE);
		1489	break;
		1490	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1491	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1492	atombios_external_tmds_setup(encoder, ATOM_ENABLE);
		1493	break;
		1494	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1495	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1496	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1497	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1498	atombios_dac_setup(encoder, ATOM_ENABLE);
		1499	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		1500	atombios_tv_setup(encoder, ATOM_ENABLE);
		1501	break;
		1502	}
		1503	atombios_apply_encoder_quirks(encoder, adjusted_mode);
		1504	}
		1505
		1506	static bool
		1507	atombios_dac_load_detect(struct drm_encoder *encoder)
		1508	{
		1509	struct drm_device *dev = encoder->dev;
		1510	struct radeon_device *rdev = dev->dev_private;
		1511	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1512
		1513	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT \|
		1514	ATOM_DEVICE_CV_SUPPORT \|
		1515	ATOM_DEVICE_CRT_SUPPORT)) {
		1516	DAC_LOAD_DETECTION_PS_ALLOCATION args;
		1517	int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
		1518	uint8_t frev, crev;
		1519
		1520	memset(&args, 0, sizeof(args));
		1521
		1522	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
		1523
		1524	args.sDacload.ucMisc = 0;
		1525
		1526	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) \|\|
		1527	(radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
		1528	args.sDacload.ucDacType = ATOM_DAC_A;
		1529	else
		1530	args.sDacload.ucDacType = ATOM_DAC_B;
		1531
		1532	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT)
		1533	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
		1534	else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT)
		1535	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
		1536	else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1537	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
		1538	if (crev >= 3)
		1539	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		1540	} else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1541	args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
		1542	if (crev >= 3)
		1543	args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
		1544	}
		1545
		1546	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1547
		1548	return true;
		1549	} else
		1550	return false;
		1551	}
		1552
		1553	static enum drm_connector_status
		1554	radeon_atom_dac_detect(struct drm_encoder encoder, struct drm_connector connector)
		1555	{
		1556	struct drm_device *dev = encoder->dev;
		1557	struct radeon_device *rdev = dev->dev_private;
		1558	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1559	uint32_t bios_0_scratch;
		1560
		1561	if (!atombios_dac_load_detect(encoder)) {
		1562	DRM_DEBUG("detect returned false \n");
		1563	return connector_status_unknown;
		1564	}
		1565
		1566	if (rdev->family >= CHIP_R600)
		1567	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1568	else
		1569	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1570
		1571	DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
		1572	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1573	if (bios_0_scratch & ATOM_S0_CRT1_MASK)
		1574	return connector_status_connected;
		1575	} else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1576	if (bios_0_scratch & ATOM_S0_CRT2_MASK)
		1577	return connector_status_connected;
		1578	} else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1579	if (bios_0_scratch & (ATOM_S0_CV_MASK\|ATOM_S0_CV_MASK_A))
		1580	return connector_status_connected;
		1581	} else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1582	if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE \| ATOM_S0_TV1_COMPOSITE_A))
		1583	return connector_status_connected; /* CTV */
		1584	else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO \| ATOM_S0_TV1_SVIDEO_A))
		1585	return connector_status_connected; /* STV */
		1586	}
		1587	return connector_status_disconnected;
		1588	}
		1589
		1590	static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
		1591	{
		1592	radeon_atom_output_lock(encoder, true);
		1593	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
		1594	}
		1595
		1596	static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
		1597	{
		1598	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
		1599	radeon_atom_output_lock(encoder, false);
		1600	}
		1601
		1602	static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
		1603	.dpms = radeon_atom_encoder_dpms,
		1604	.mode_fixup = radeon_atom_mode_fixup,
		1605	.prepare = radeon_atom_encoder_prepare,
		1606	.mode_set = radeon_atom_encoder_mode_set,
		1607	.commit = radeon_atom_encoder_commit,
		1608	/* no detect for TMDS/LVDS yet */
		1609	};
		1610
		1611	static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
		1612	.dpms = radeon_atom_encoder_dpms,
		1613	.mode_fixup = radeon_atom_mode_fixup,
		1614	.prepare = radeon_atom_encoder_prepare,
		1615	.mode_set = radeon_atom_encoder_mode_set,
		1616	.commit = radeon_atom_encoder_commit,
		1617	.detect = radeon_atom_dac_detect,
		1618	};
		1619
		1620	void radeon_enc_destroy(struct drm_encoder *encoder)
		1621	{
		1622	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1623	kfree(radeon_encoder->enc_priv);
		1624	drm_encoder_cleanup(encoder);
		1625	kfree(radeon_encoder);
		1626	}
		1627
		1628	static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
		1629	.destroy = radeon_enc_destroy,
		1630	};
		1631
		1632	struct radeon_encoder_atom_dig *
		1633	radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
		1634	{
		1635	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1636
		1637	if (!dig)
		1638	return NULL;
		1639
		1640	/* coherent mode by default */
		1641	dig->coherent_mode = true;
		1642
		1643	return dig;
		1644	}
		1645
		1646	void
		1647	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
		1648	{
		1649	struct drm_encoder *encoder;
		1650	struct radeon_encoder *radeon_encoder;
		1651
		1652	/* see if we already added it */
		1653	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1654	radeon_encoder = to_radeon_encoder(encoder);
		1655	if (radeon_encoder->encoder_id == encoder_id) {
		1656	radeon_encoder->devices \|= supported_device;
		1657	return;
		1658	}
		1659
		1660	}
		1661
		1662	/* add a new one */
		1663	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
		1664	if (!radeon_encoder)
		1665	return;
		1666
		1667	encoder = &radeon_encoder->base;
		1668	encoder->possible_crtcs = 0x3;
		1669	encoder->possible_clones = 0;
		1670
		1671	radeon_encoder->enc_priv = NULL;
		1672
		1673	radeon_encoder->encoder_id = encoder_id;
		1674	radeon_encoder->devices = supported_device;
		1675
		1676	switch (radeon_encoder->encoder_id) {
		1677	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
		1678	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
		1679	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
		1680	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
		1681	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1682	radeon_encoder->rmx_type = RMX_FULL;
		1683	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
		1684	radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
		1685	} else {
		1686	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1687	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		1688	}
		1689	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1690	break;
		1691	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
		1692	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
		1693	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1694	break;
		1695	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
		1696	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
		1697	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
		1698	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
		1699	drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
		1700	break;
		1701	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
		1702	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
		1703	case ENCODER_OBJECT_ID_INTERNAL_DDI:
		1704	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
		1705	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
		1706	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
		1707	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
		1708	drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
		1709	radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
		1710	drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
		1711	break;
		1712	}
		1713	}
		1714

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_encoders.c @ 1268 – Rev 1125