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Rev | Author | Line No. | Line |
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6105 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | |||
5 | |||
6 | #include "atom.h" |
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7 | #include "ni_reg.h" |
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8 | |||
9 | |||
10 | |||
11 | |||
12 | { |
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13 | static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, |
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14 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
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15 | EVERGREEN_CRTC2_REGISTER_OFFSET, |
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16 | EVERGREEN_CRTC3_REGISTER_OFFSET, |
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17 | EVERGREEN_CRTC4_REGISTER_OFFSET, |
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18 | EVERGREEN_CRTC5_REGISTER_OFFSET, |
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19 | 0x13830 - 0x7030 }; |
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20 | |||
21 | |||
22 | } |
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23 | |||
24 | |||
25 | struct radeon_encoder_mst *mst_enc, |
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26 | enum radeon_hpd_id hpd, bool enable) |
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27 | { |
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28 | struct drm_device *dev = primary->base.dev; |
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29 | struct radeon_device *rdev = dev->dev_private; |
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30 | uint32_t reg; |
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31 | int retries = 0; |
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32 | uint32_t temp; |
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33 | |||
34 | |||
35 | |||
36 | |||
37 | reg &= ~NI_DIG_FE_DIG_MODE(7); |
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38 | reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); |
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39 | |||
40 | |||
41 | reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
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42 | else |
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43 | reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
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44 | |||
45 | |||
46 | DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); |
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47 | WREG32(NI_DIG_BE_CNTL + primary->offset, reg); |
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48 | |||
49 | |||
50 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
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51 | |||
52 | |||
53 | temp = RREG32(NI_DIG_FE_CNTL + offset); |
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54 | } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); |
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55 | if (retries == 10000) |
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56 | DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); |
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57 | } |
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58 | return 0; |
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59 | } |
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60 | |||
61 | |||
62 | int stream_number, |
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63 | int fe, |
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64 | int slots) |
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65 | { |
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66 | struct drm_device *dev = primary->base.dev; |
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67 | struct radeon_device *rdev = dev->dev_private; |
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68 | u32 temp, val; |
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69 | int retries = 0; |
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70 | int satreg, satidx; |
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71 | |||
72 | |||
73 | satidx = stream_number & 1; |
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74 | |||
75 | |||
76 | |||
77 | |||
78 | |||
79 | |||
80 | |||
81 | |||
82 | |||
83 | |||
84 | |||
85 | |||
86 | WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); |
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87 | |||
88 | |||
89 | |||
90 | |||
91 | unsigned value1, value2; |
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7146 | serge | 92 | udelay(10); |
93 | temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); |
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6105 | serge | 94 | |
95 | |||
7146 | serge | 96 | value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT; |
97 | |||
98 | |||
99 | break; |
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100 | } while (retries++ < 50); |
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101 | |||
102 | |||
6105 | serge | 103 | DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); |
104 | |||
105 | |||
106 | return 0; |
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107 | } |
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108 | |||
109 | |||
110 | struct radeon_encoder *primary) |
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111 | { |
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112 | struct drm_device *dev = mst_conn->base.dev; |
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113 | struct stream_attribs new_attribs[6]; |
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114 | int i; |
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115 | int idx = 0; |
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116 | struct radeon_connector *radeon_connector; |
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117 | struct drm_connector *connector; |
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118 | |||
119 | |||
120 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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121 | struct radeon_encoder *subenc; |
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122 | struct radeon_encoder_mst *mst_enc; |
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123 | |||
124 | |||
125 | if (!radeon_connector->is_mst_connector) |
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126 | continue; |
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127 | |||
128 | |||
129 | continue; |
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130 | |||
131 | |||
132 | mst_enc = subenc->enc_priv; |
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133 | |||
134 | |||
135 | continue; |
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136 | |||
137 | |||
138 | new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); |
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139 | idx++; |
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140 | } |
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141 | |||
142 | |||
143 | if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || |
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144 | new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { |
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145 | radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); |
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146 | mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; |
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147 | mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; |
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148 | } |
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149 | } |
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150 | |||
151 | |||
152 | radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); |
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153 | mst_conn->cur_stream_attribs[i].fe = 0; |
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154 | mst_conn->cur_stream_attribs[i].slots = 0; |
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155 | } |
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156 | mst_conn->enabled_attribs = idx; |
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157 | return 0; |
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158 | } |
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159 | |||
160 | |||
7146 | serge | 161 | { |
6105 | serge | 162 | struct drm_device *dev = mst->base.dev; |
163 | struct radeon_device *rdev = dev->dev_private; |
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164 | struct radeon_encoder_mst *mst_enc = mst->enc_priv; |
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165 | uint32_t val, temp; |
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166 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
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167 | int retries = 0; |
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168 | uint32_t x = drm_fixp2int(avg_time_slots_per_mtp); |
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7146 | serge | 169 | uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26); |
170 | |||
6105 | serge | 171 | |
172 | |||
173 | |||
174 | |||
175 | |||
176 | temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); |
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177 | udelay(10); |
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7146 | serge | 178 | } while ((temp & 0x1) && (retries++ < 10000)); |
6105 | serge | 179 | |
180 | |||
181 | DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); |
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182 | return 0; |
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183 | } |
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184 | |||
185 | |||
186 | { |
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187 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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188 | struct radeon_connector *master = radeon_connector->mst_port; |
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189 | struct edid *edid; |
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190 | int ret = 0; |
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191 | |||
192 | |||
193 | radeon_connector->edid = edid; |
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194 | DRM_DEBUG_KMS("edid retrieved %p\n", edid); |
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195 | if (radeon_connector->edid) { |
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196 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
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197 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
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198 | drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); |
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199 | return ret; |
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200 | } |
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201 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
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202 | |||
203 | |||
204 | } |
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205 | |||
206 | |||
207 | { |
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208 | return radeon_dp_mst_get_ddc_modes(connector); |
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209 | } |
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210 | |||
211 | |||
212 | radeon_dp_mst_mode_valid(struct drm_connector *connector, |
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213 | struct drm_display_mode *mode) |
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214 | { |
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215 | /* TODO - validate mode against available PBN for link */ |
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216 | if (mode->clock < 10000) |
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217 | return MODE_CLOCK_LOW; |
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218 | |||
219 | |||
220 | return MODE_H_ILLEGAL; |
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221 | |||
222 | |||
223 | } |
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224 | |||
225 | |||
226 | { |
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227 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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228 | |||
229 | |||
230 | } |
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231 | |||
232 | |||
233 | .get_modes = radeon_dp_mst_get_modes, |
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234 | .mode_valid = radeon_dp_mst_mode_valid, |
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235 | .best_encoder = radeon_mst_best_encoder, |
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236 | }; |
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237 | |||
238 | |||
239 | radeon_dp_mst_detect(struct drm_connector *connector, bool force) |
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240 | { |
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241 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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242 | struct radeon_connector *master = radeon_connector->mst_port; |
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243 | |||
244 | |||
245 | } |
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246 | |||
247 | |||
248 | radeon_dp_mst_connector_destroy(struct drm_connector *connector) |
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249 | { |
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250 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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251 | struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; |
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252 | |||
253 | |||
254 | kfree(radeon_encoder); |
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255 | drm_connector_cleanup(connector); |
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256 | kfree(radeon_connector); |
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257 | } |
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258 | |||
259 | |||
260 | .dpms = drm_helper_connector_dpms, |
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7146 | serge | 261 | .detect = radeon_dp_mst_detect, |
6105 | serge | 262 | .fill_modes = drm_helper_probe_single_connector_modes, |
263 | .destroy = radeon_dp_mst_connector_destroy, |
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264 | }; |
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265 | |||
266 | |||
267 | struct drm_dp_mst_port *port, |
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268 | const char *pathprop) |
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269 | { |
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270 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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271 | struct drm_device *dev = master->base.dev; |
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272 | struct radeon_connector *radeon_connector; |
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273 | struct drm_connector *connector; |
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274 | |||
275 | |||
276 | if (!radeon_connector) |
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277 | return NULL; |
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278 | |||
279 | |||
280 | connector = &radeon_connector->base; |
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281 | radeon_connector->port = port; |
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282 | radeon_connector->mst_port = master; |
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283 | DRM_DEBUG_KMS("\n"); |
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284 | |||
285 | |||
286 | drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); |
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287 | radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); |
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288 | |||
289 | |||
290 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
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291 | drm_mode_connector_set_path_property(connector, pathprop); |
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292 | |||
293 | |||
294 | } |
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295 | |||
296 | |||
297 | { |
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298 | struct drm_device *dev = connector->dev; |
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299 | struct radeon_device *rdev = dev->dev_private; |
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300 | |||
301 | |||
302 | radeon_fb_add_connector(rdev, connector); |
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303 | drm_modeset_unlock_all(dev); |
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304 | |||
305 | |||
306 | } |
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307 | |||
308 | |||
309 | struct drm_connector *connector) |
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310 | { |
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311 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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312 | struct drm_device *dev = master->base.dev; |
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313 | struct radeon_device *rdev = dev->dev_private; |
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314 | |||
315 | |||
316 | /* need to nuke the connector */ |
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317 | drm_modeset_lock_all(dev); |
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318 | /* dpms off */ |
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319 | radeon_fb_remove_connector(rdev, connector); |
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320 | |||
321 | |||
322 | drm_modeset_unlock_all(dev); |
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323 | |||
324 | |||
325 | DRM_DEBUG_KMS("\n"); |
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326 | } |
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327 | |||
328 | |||
329 | { |
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330 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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331 | struct drm_device *dev = master->base.dev; |
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332 | |||
333 | |||
334 | } |
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335 | |||
336 | |||
6938 | serge | 337 | .add_connector = radeon_dp_add_mst_connector, |
6105 | serge | 338 | .register_connector = radeon_dp_register_mst_connector, |
339 | .destroy_connector = radeon_dp_destroy_mst_connector, |
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340 | .hotplug = radeon_dp_mst_hotplug, |
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341 | }; |
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342 | |||
343 | |||
344 | { |
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345 | struct drm_device *dev = encoder->dev; |
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346 | struct drm_connector *connector; |
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347 | |||
348 | |||
349 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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350 | if (!connector->encoder) |
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351 | continue; |
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352 | if (!radeon_connector->is_mst_connector) |
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353 | continue; |
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354 | |||
355 | |||
356 | if (connector->encoder == encoder) |
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357 | return radeon_connector; |
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358 | } |
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359 | return NULL; |
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360 | } |
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361 | |||
362 | |||
363 | { |
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364 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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365 | struct drm_device *dev = crtc->dev; |
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366 | struct radeon_device *rdev = dev->dev_private; |
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367 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); |
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368 | struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
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369 | struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); |
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370 | int dp_clock; |
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371 | struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
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372 | |||
373 | |||
374 | radeon_connector->pixelclock_for_modeset = mode->clock; |
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375 | if (radeon_connector->base.display_info.bpc) |
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376 | radeon_crtc->bpc = radeon_connector->base.display_info.bpc; |
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377 | else |
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378 | radeon_crtc->bpc = 8; |
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379 | } |
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380 | |||
381 | |||
382 | dp_clock = dig_connector->dp_clock; |
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383 | radeon_crtc->ss_enabled = |
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384 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
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385 | ASIC_INTERNAL_SS_ON_DP, |
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386 | dp_clock); |
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387 | } |
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388 | |||
389 | |||
390 | radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) |
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391 | { |
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392 | struct drm_device *dev = encoder->dev; |
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393 | struct radeon_device *rdev = dev->dev_private; |
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394 | struct radeon_encoder *radeon_encoder, *primary; |
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395 | struct radeon_encoder_mst *mst_enc; |
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396 | struct radeon_encoder_atom_dig *dig_enc; |
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397 | struct radeon_connector *radeon_connector; |
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398 | struct drm_crtc *crtc; |
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399 | struct radeon_crtc *radeon_crtc; |
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400 | int ret, slots; |
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401 | s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp; |
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7146 | serge | 402 | if (!ASIC_IS_DCE5(rdev)) { |
6105 | serge | 403 | DRM_ERROR("got mst dpms on non-DCE5\n"); |
404 | return; |
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405 | } |
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406 | |||
407 | |||
408 | if (!radeon_connector) |
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409 | return; |
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410 | |||
411 | |||
412 | |||
413 | |||
414 | |||
415 | |||
416 | |||
417 | |||
418 | |||
419 | |||
420 | DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); |
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421 | |||
422 | |||
423 | case DRM_MODE_DPMS_ON: |
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424 | dig_enc->active_mst_links++; |
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425 | |||
426 | |||
427 | |||
428 | |||
429 | mst_enc->fe = dig_enc->dig_encoder; |
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430 | mst_enc->fe_from_be = true; |
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431 | atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
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432 | |||
433 | |||
434 | atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, |
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435 | 0, 0, dig_enc->dig_encoder); |
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436 | |||
437 | |||
438 | dig_enc->active_mst_links == 1) { |
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439 | radeon_dp_link_train(&primary->base, &mst_enc->connector->base); |
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440 | } |
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441 | |||
442 | |||
443 | mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); |
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444 | if (mst_enc->fe == -1) |
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445 | DRM_ERROR("failed to get frontend for dig encoder\n"); |
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446 | mst_enc->fe_from_be = false; |
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447 | atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
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448 | } |
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449 | |||
450 | |||
451 | dig_enc->linkb, radeon_crtc->crtc_id); |
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452 | |||
453 | |||
454 | radeon_connector->port, |
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455 | mst_enc->pbn, &slots); |
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456 | ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
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457 | |||
458 | |||
459 | radeon_connector->mst_port->hpd.hpd, true); |
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460 | |||
461 | |||
462 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
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463 | |||
464 | |||
7146 | serge | 465 | fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div); |
466 | avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot); |
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467 | radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp); |
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468 | |||
469 | |||
6105 | serge | 470 | mst_enc->fe); |
471 | ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); |
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472 | |||
473 | |||
474 | |||
475 | |||
476 | case DRM_MODE_DPMS_STANDBY: |
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477 | case DRM_MODE_DPMS_SUSPEND: |
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478 | case DRM_MODE_DPMS_OFF: |
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479 | DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); |
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480 | |||
481 | |||
482 | return; |
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483 | |||
484 | |||
485 | ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
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486 | |||
487 | |||
488 | /* and this can also fail */ |
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489 | drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); |
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490 | |||
491 | |||
492 | |||
493 | |||
494 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
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495 | |||
496 | |||
497 | radeon_connector->mst_port->hpd.hpd, false); |
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498 | atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, |
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499 | mst_enc->fe); |
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500 | |||
501 | |||
502 | radeon_atom_release_dig_encoder(rdev, mst_enc->fe); |
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503 | |||
504 | |||
505 | dig_enc->active_mst_links--; |
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506 | if (dig_enc->active_mst_links == 0) { |
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507 | /* drop link */ |
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508 | } |
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509 | |||
510 | |||
511 | } |
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512 | |||
513 | |||
514 | |||
515 | |||
516 | const struct drm_display_mode *mode, |
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517 | struct drm_display_mode *adjusted_mode) |
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518 | { |
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519 | struct radeon_encoder_mst *mst_enc; |
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520 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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521 | struct radeon_connector_atom_dig *dig_connector; |
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7146 | serge | 522 | int bpp = 24; |
6105 | serge | 523 | |
524 | |||
525 | |||
526 | |||
527 | |||
528 | |||
529 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
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530 | mst_enc->primary->active_device, mst_enc->primary->devices, |
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531 | mst_enc->connector->devices, mst_enc->primary->base.encoder_type); |
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532 | |||
533 | |||
534 | |||
535 | dig_connector = mst_enc->connector->con_priv; |
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7146 | serge | 536 | dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); |
537 | dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); |
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538 | DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, |
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539 | dig_connector->dp_lane_count, dig_connector->dp_clock); |
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540 | return true; |
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6105 | serge | 541 | } |
542 | |||
543 | |||
544 | { |
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545 | struct radeon_connector *radeon_connector; |
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546 | struct radeon_encoder *radeon_encoder, *primary; |
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547 | struct radeon_encoder_mst *mst_enc; |
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548 | struct radeon_encoder_atom_dig *dig_enc; |
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549 | |||
550 | |||
551 | if (!radeon_connector) { |
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552 | DRM_DEBUG_KMS("failed to find connector %p\n", encoder); |
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553 | return; |
||
554 | } |
||
555 | radeon_encoder = to_radeon_encoder(encoder); |
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556 | |||
557 | |||
558 | |||
559 | |||
560 | |||
561 | |||
562 | |||
563 | |||
564 | |||
565 | |||
566 | |||
567 | |||
568 | dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); |
||
569 | primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); |
||
570 | atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); |
||
571 | |||
572 | |||
573 | |||
574 | DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); |
||
575 | } |
||
576 | |||
577 | |||
578 | radeon_mst_encoder_mode_set(struct drm_encoder *encoder, |
||
579 | struct drm_display_mode *mode, |
||
580 | struct drm_display_mode *adjusted_mode) |
||
581 | { |
||
582 | DRM_DEBUG_KMS("\n"); |
||
583 | } |
||
584 | |||
585 | |||
586 | { |
||
587 | radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
||
588 | DRM_DEBUG_KMS("\n"); |
||
589 | } |
||
590 | |||
591 | |||
592 | .dpms = radeon_mst_encoder_dpms, |
||
593 | .mode_fixup = radeon_mst_mode_fixup, |
||
594 | .prepare = radeon_mst_encoder_prepare, |
||
595 | .mode_set = radeon_mst_encoder_mode_set, |
||
596 | .commit = radeon_mst_encoder_commit, |
||
597 | }; |
||
598 | |||
599 | |||
600 | { |
||
601 | drm_encoder_cleanup(encoder); |
||
602 | kfree(encoder); |
||
603 | } |
||
604 | |||
605 | |||
606 | .destroy = radeon_dp_mst_encoder_destroy, |
||
607 | }; |
||
608 | |||
609 | |||
610 | radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) |
||
611 | { |
||
612 | struct drm_device *dev = connector->base.dev; |
||
613 | struct radeon_device *rdev = dev->dev_private; |
||
614 | struct radeon_encoder *radeon_encoder; |
||
615 | struct radeon_encoder_mst *mst_enc; |
||
616 | struct drm_encoder *encoder; |
||
617 | const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; |
||
618 | struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); |
||
619 | |||
620 | |||
621 | radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); |
||
622 | if (!radeon_encoder) |
||
623 | return NULL; |
||
624 | |||
625 | |||
626 | if (!radeon_encoder->enc_priv) { |
||
627 | kfree(radeon_encoder); |
||
628 | return NULL; |
||
629 | } |
||
630 | encoder = &radeon_encoder->base; |
||
631 | switch (rdev->num_crtc) { |
||
632 | case 1: |
||
633 | encoder->possible_crtcs = 0x1; |
||
634 | break; |
||
635 | case 2: |
||
636 | default: |
||
637 | encoder->possible_crtcs = 0x3; |
||
638 | break; |
||
639 | case 4: |
||
640 | encoder->possible_crtcs = 0xf; |
||
641 | break; |
||
642 | case 6: |
||
643 | encoder->possible_crtcs = 0x3f; |
||
644 | break; |
||
645 | } |
||
646 | |||
647 | |||
648 | DRM_MODE_ENCODER_DPMST, NULL); |
||
6938 | serge | 649 | drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); |
6105 | serge | 650 | |
651 | |||
652 | mst_enc->connector = connector; |
||
653 | mst_enc->primary = to_radeon_encoder(enc_master); |
||
654 | radeon_encoder->is_mst_encoder = true; |
||
655 | return radeon_encoder; |
||
656 | } |
||
657 | |||
658 | |||
659 | radeon_dp_mst_init(struct radeon_connector *radeon_connector) |
||
660 | { |
||
661 | struct drm_device *dev = radeon_connector->base.dev; |
||
662 | |||
663 | |||
664 | return 0; |
||
665 | |||
666 | |||
667 | return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev, |
||
668 | &radeon_connector->ddc_bus->aux, 16, 6, |
||
669 | radeon_connector->base.base.id); |
||
670 | } |
||
671 | |||
672 | |||
673 | radeon_dp_mst_probe(struct radeon_connector *radeon_connector) |
||
674 | { |
||
675 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
676 | struct drm_device *dev = radeon_connector->base.dev; |
||
677 | struct radeon_device *rdev = dev->dev_private; |
||
678 | int ret; |
||
679 | u8 msg[1]; |
||
680 | |||
681 | |||
682 | return 0; |
||
683 | |||
684 | |||
685 | return 0; |
||
686 | |||
687 | |||
688 | return 0; |
||
689 | |||
690 | |||
691 | 1); |
||
692 | if (ret) { |
||
693 | if (msg[0] & DP_MST_CAP) { |
||
694 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
||
695 | dig_connector->is_mst = true; |
||
696 | } else { |
||
697 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
||
698 | dig_connector->is_mst = false; |
||
699 | } |
||
700 | |||
701 | |||
702 | drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
||
703 | dig_connector->is_mst); |
||
704 | return dig_connector->is_mst; |
||
705 | } |
||
706 | |||
707 | |||
708 | radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) |
||
709 | { |
||
710 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
711 | int retry; |
||
712 | |||
713 | |||
714 | u8 esi[16] = { 0 }; |
||
715 | int dret; |
||
716 | int ret = 0; |
||
717 | bool handled; |
||
718 | |||
719 | |||
720 | DP_SINK_COUNT_ESI, esi, 8); |
||
721 | go_again: |
||
722 | if (dret == 8) { |
||
723 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
724 | ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); |
||
725 | |||
726 | |||
727 | for (retry = 0; retry < 3; retry++) { |
||
728 | int wret; |
||
729 | wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, |
||
730 | DP_SINK_COUNT_ESI + 1, &esi[1], 3); |
||
731 | if (wret == 3) |
||
732 | break; |
||
733 | } |
||
734 | |||
735 | |||
736 | DP_SINK_COUNT_ESI, esi, 8); |
||
737 | if (dret == 8) { |
||
738 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
739 | goto go_again; |
||
740 | } |
||
741 | } else |
||
742 | ret = 0; |
||
743 | |||
744 | |||
745 | } else { |
||
746 | DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); |
||
747 | dig_connector->is_mst = false; |
||
748 | drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
||
749 | dig_connector->is_mst); |
||
750 | /* send a hotplug event */ |
||
751 | } |
||
752 | } |
||
753 | return -EINVAL; |
||
754 | } |
||
755 | |||
756 | |||
757 | |||
758 | |||
759 | { |
||
760 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
||
761 | struct drm_device *dev = node->minor->dev; |
||
762 | struct drm_connector *connector; |
||
763 | struct radeon_connector *radeon_connector; |
||
764 | struct radeon_connector_atom_dig *dig_connector; |
||
765 | int i; |
||
766 | |||
767 | |||
768 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
769 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
||
770 | continue; |
||
771 | |||
772 | |||
773 | dig_connector = radeon_connector->con_priv; |
||
774 | if (radeon_connector->is_mst_connector) |
||
775 | continue; |
||
776 | if (!dig_connector->is_mst) |
||
777 | continue; |
||
778 | drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); |
||
779 | |||
780 | |||
781 | seq_printf(m, "attrib %d: %d %d\n", i, |
||
782 | radeon_connector->cur_stream_attribs[i].fe, |
||
783 | radeon_connector->cur_stream_attribs[i].slots); |
||
784 | } |
||
785 | drm_modeset_unlock_all(dev); |
||
786 | return 0; |
||
787 | } |
||
788 | |||
789 | |||
790 | {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL}, |
||
791 | }; |
||
792 | #endif |
||
793 | |||
794 | |||
795 | { |
||
796 | #if defined(CONFIG_DEBUG_FS) |
||
797 | return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1); |
||
798 | #endif |
||
799 | return 0; |
||
800 | }>>>>>><>>>>><>=><=>>><>><> |
||
801 |