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Rev | Author | Line No. | Line |
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6105 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | |||
5 | |||
6 | #include "atom.h" |
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7 | #include "ni_reg.h" |
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8 | |||
9 | |||
10 | |||
11 | |||
12 | { |
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13 | static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET, |
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14 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
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15 | EVERGREEN_CRTC2_REGISTER_OFFSET, |
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16 | EVERGREEN_CRTC3_REGISTER_OFFSET, |
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17 | EVERGREEN_CRTC4_REGISTER_OFFSET, |
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18 | EVERGREEN_CRTC5_REGISTER_OFFSET, |
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19 | 0x13830 - 0x7030 }; |
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20 | |||
21 | |||
22 | } |
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23 | |||
24 | |||
25 | struct radeon_encoder_mst *mst_enc, |
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26 | enum radeon_hpd_id hpd, bool enable) |
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27 | { |
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28 | struct drm_device *dev = primary->base.dev; |
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29 | struct radeon_device *rdev = dev->dev_private; |
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30 | uint32_t reg; |
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31 | int retries = 0; |
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32 | uint32_t temp; |
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33 | |||
34 | |||
35 | |||
36 | |||
37 | reg &= ~NI_DIG_FE_DIG_MODE(7); |
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38 | reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST); |
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39 | |||
40 | |||
41 | reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
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42 | else |
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43 | reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe); |
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44 | |||
45 | |||
46 | DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg); |
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47 | WREG32(NI_DIG_BE_CNTL + primary->offset, reg); |
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48 | |||
49 | |||
50 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
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51 | |||
52 | |||
53 | temp = RREG32(NI_DIG_FE_CNTL + offset); |
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54 | } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000); |
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55 | if (retries == 10000) |
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56 | DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe); |
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57 | } |
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58 | return 0; |
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59 | } |
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60 | |||
61 | |||
62 | int stream_number, |
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63 | int fe, |
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64 | int slots) |
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65 | { |
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66 | struct drm_device *dev = primary->base.dev; |
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67 | struct radeon_device *rdev = dev->dev_private; |
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68 | u32 temp, val; |
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69 | int retries = 0; |
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70 | int satreg, satidx; |
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71 | |||
72 | |||
73 | satidx = stream_number & 1; |
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74 | |||
75 | |||
76 | |||
77 | |||
78 | |||
79 | |||
80 | |||
81 | |||
82 | |||
83 | |||
84 | |||
85 | |||
86 | WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp); |
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87 | |||
88 | |||
89 | |||
90 | |||
91 | temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset); |
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92 | } while ((temp & 0x1) && retries++ < 10000); |
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93 | |||
94 | |||
95 | DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset); |
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96 | |||
97 | |||
98 | return 0; |
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99 | } |
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100 | |||
101 | |||
102 | struct radeon_encoder *primary) |
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103 | { |
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104 | struct drm_device *dev = mst_conn->base.dev; |
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105 | struct stream_attribs new_attribs[6]; |
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106 | int i; |
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107 | int idx = 0; |
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108 | struct radeon_connector *radeon_connector; |
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109 | struct drm_connector *connector; |
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110 | |||
111 | |||
112 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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113 | struct radeon_encoder *subenc; |
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114 | struct radeon_encoder_mst *mst_enc; |
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115 | |||
116 | |||
117 | if (!radeon_connector->is_mst_connector) |
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118 | continue; |
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119 | |||
120 | |||
121 | continue; |
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122 | |||
123 | |||
124 | mst_enc = subenc->enc_priv; |
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125 | |||
126 | |||
127 | continue; |
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128 | |||
129 | |||
130 | new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port); |
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131 | idx++; |
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132 | } |
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133 | |||
134 | |||
135 | if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe || |
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136 | new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) { |
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137 | radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots); |
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138 | mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe; |
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139 | mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots; |
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140 | } |
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141 | } |
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142 | |||
143 | |||
144 | radeon_dp_mst_set_stream_attrib(primary, i, 0, 0); |
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145 | mst_conn->cur_stream_attribs[i].fe = 0; |
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146 | mst_conn->cur_stream_attribs[i].slots = 0; |
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147 | } |
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148 | mst_conn->enabled_attribs = idx; |
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149 | return 0; |
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150 | } |
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151 | |||
152 | |||
153 | { |
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154 | struct drm_device *dev = mst->base.dev; |
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155 | struct radeon_device *rdev = dev->dev_private; |
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156 | struct radeon_encoder_mst *mst_enc = mst->enc_priv; |
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157 | uint32_t val, temp; |
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158 | uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe); |
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159 | int retries = 0; |
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160 | |||
161 | |||
162 | |||
163 | |||
164 | |||
165 | |||
166 | temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset); |
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167 | } while ((temp & 0x1) && (retries++ < 10000)); |
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168 | |||
169 | |||
170 | DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); |
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171 | return 0; |
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172 | } |
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173 | |||
174 | |||
175 | { |
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176 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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177 | struct radeon_connector *master = radeon_connector->mst_port; |
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178 | struct edid *edid; |
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179 | int ret = 0; |
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180 | |||
181 | |||
182 | radeon_connector->edid = edid; |
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183 | DRM_DEBUG_KMS("edid retrieved %p\n", edid); |
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184 | if (radeon_connector->edid) { |
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185 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
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186 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
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187 | drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid); |
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188 | return ret; |
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189 | } |
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190 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
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191 | |||
192 | |||
193 | } |
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194 | |||
195 | |||
196 | { |
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197 | return radeon_dp_mst_get_ddc_modes(connector); |
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198 | } |
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199 | |||
200 | |||
201 | radeon_dp_mst_mode_valid(struct drm_connector *connector, |
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202 | struct drm_display_mode *mode) |
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203 | { |
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204 | /* TODO - validate mode against available PBN for link */ |
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205 | if (mode->clock < 10000) |
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206 | return MODE_CLOCK_LOW; |
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207 | |||
208 | |||
209 | return MODE_H_ILLEGAL; |
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210 | |||
211 | |||
212 | } |
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213 | |||
214 | |||
215 | { |
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216 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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217 | |||
218 | |||
219 | } |
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220 | |||
221 | |||
222 | .get_modes = radeon_dp_mst_get_modes, |
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223 | .mode_valid = radeon_dp_mst_mode_valid, |
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224 | .best_encoder = radeon_mst_best_encoder, |
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225 | }; |
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226 | |||
227 | |||
228 | radeon_dp_mst_detect(struct drm_connector *connector, bool force) |
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229 | { |
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230 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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231 | struct radeon_connector *master = radeon_connector->mst_port; |
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232 | |||
233 | |||
234 | } |
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235 | |||
236 | |||
237 | radeon_dp_mst_connector_destroy(struct drm_connector *connector) |
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238 | { |
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239 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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240 | struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder; |
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241 | |||
242 | |||
243 | kfree(radeon_encoder); |
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244 | drm_connector_cleanup(connector); |
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245 | kfree(radeon_connector); |
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246 | } |
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247 | |||
248 | |||
249 | { |
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250 | DRM_DEBUG_KMS("\n"); |
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251 | return 0; |
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252 | } |
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253 | |||
254 | |||
255 | .dpms = radeon_connector_dpms, |
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256 | .detect = radeon_dp_mst_detect, |
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257 | .fill_modes = drm_helper_probe_single_connector_modes, |
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258 | .destroy = radeon_dp_mst_connector_destroy, |
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259 | }; |
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260 | |||
261 | |||
262 | struct drm_dp_mst_port *port, |
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263 | const char *pathprop) |
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264 | { |
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265 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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266 | struct drm_device *dev = master->base.dev; |
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267 | struct radeon_connector *radeon_connector; |
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268 | struct drm_connector *connector; |
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269 | |||
270 | |||
271 | if (!radeon_connector) |
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272 | return NULL; |
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273 | |||
274 | |||
275 | connector = &radeon_connector->base; |
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276 | radeon_connector->port = port; |
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277 | radeon_connector->mst_port = master; |
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278 | DRM_DEBUG_KMS("\n"); |
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279 | |||
280 | |||
281 | drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs); |
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282 | radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master); |
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283 | |||
284 | |||
285 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
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286 | drm_mode_connector_set_path_property(connector, pathprop); |
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287 | |||
288 | |||
289 | } |
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290 | |||
291 | |||
292 | { |
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293 | struct drm_device *dev = connector->dev; |
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294 | struct radeon_device *rdev = dev->dev_private; |
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295 | |||
296 | |||
297 | radeon_fb_add_connector(rdev, connector); |
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298 | drm_modeset_unlock_all(dev); |
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299 | |||
300 | |||
301 | } |
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302 | |||
303 | |||
304 | struct drm_connector *connector) |
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305 | { |
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306 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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307 | struct drm_device *dev = master->base.dev; |
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308 | struct radeon_device *rdev = dev->dev_private; |
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309 | |||
310 | |||
311 | /* need to nuke the connector */ |
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312 | drm_modeset_lock_all(dev); |
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313 | /* dpms off */ |
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314 | radeon_fb_remove_connector(rdev, connector); |
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315 | |||
316 | |||
317 | drm_modeset_unlock_all(dev); |
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318 | |||
319 | |||
320 | DRM_DEBUG_KMS("\n"); |
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321 | } |
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322 | |||
323 | |||
324 | { |
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325 | struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); |
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326 | struct drm_device *dev = master->base.dev; |
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327 | |||
328 | |||
329 | } |
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330 | |||
331 | |||
332 | .add_connector = radeon_dp_add_mst_connector, |
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333 | .register_connector = radeon_dp_register_mst_connector, |
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334 | .destroy_connector = radeon_dp_destroy_mst_connector, |
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335 | .hotplug = radeon_dp_mst_hotplug, |
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336 | }; |
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337 | |||
338 | |||
339 | { |
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340 | struct drm_device *dev = encoder->dev; |
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341 | struct drm_connector *connector; |
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342 | |||
343 | |||
344 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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345 | if (!connector->encoder) |
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346 | continue; |
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347 | if (!radeon_connector->is_mst_connector) |
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348 | continue; |
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349 | |||
350 | |||
351 | if (connector->encoder == encoder) |
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352 | return radeon_connector; |
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353 | } |
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354 | return NULL; |
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355 | } |
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356 | |||
357 | |||
358 | { |
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359 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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360 | struct drm_device *dev = crtc->dev; |
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361 | struct radeon_device *rdev = dev->dev_private; |
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362 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); |
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363 | struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
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364 | struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base); |
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365 | int dp_clock; |
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366 | struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
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367 | |||
368 | |||
369 | radeon_connector->pixelclock_for_modeset = mode->clock; |
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370 | if (radeon_connector->base.display_info.bpc) |
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371 | radeon_crtc->bpc = radeon_connector->base.display_info.bpc; |
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372 | else |
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373 | radeon_crtc->bpc = 8; |
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374 | } |
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375 | |||
376 | |||
377 | dp_clock = dig_connector->dp_clock; |
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378 | radeon_crtc->ss_enabled = |
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379 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, |
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380 | ASIC_INTERNAL_SS_ON_DP, |
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381 | dp_clock); |
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382 | } |
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383 | |||
384 | |||
385 | radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode) |
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386 | { |
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387 | struct drm_device *dev = encoder->dev; |
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388 | struct radeon_device *rdev = dev->dev_private; |
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389 | struct radeon_encoder *radeon_encoder, *primary; |
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390 | struct radeon_encoder_mst *mst_enc; |
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391 | struct radeon_encoder_atom_dig *dig_enc; |
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392 | struct radeon_connector *radeon_connector; |
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393 | struct drm_crtc *crtc; |
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394 | struct radeon_crtc *radeon_crtc; |
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395 | int ret, slots; |
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396 | |||
397 | |||
398 | DRM_ERROR("got mst dpms on non-DCE5\n"); |
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399 | return; |
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400 | } |
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401 | |||
402 | |||
403 | if (!radeon_connector) |
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404 | return; |
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405 | |||
406 | |||
407 | |||
408 | |||
409 | |||
410 | |||
411 | |||
412 | |||
413 | |||
414 | |||
415 | DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links); |
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416 | |||
417 | |||
418 | case DRM_MODE_DPMS_ON: |
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419 | dig_enc->active_mst_links++; |
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420 | |||
421 | |||
422 | |||
423 | |||
424 | mst_enc->fe = dig_enc->dig_encoder; |
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425 | mst_enc->fe_from_be = true; |
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426 | atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
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427 | |||
428 | |||
429 | atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE, |
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430 | 0, 0, dig_enc->dig_encoder); |
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431 | |||
432 | |||
433 | dig_enc->active_mst_links == 1) { |
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434 | radeon_dp_link_train(&primary->base, &mst_enc->connector->base); |
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435 | } |
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436 | |||
437 | |||
438 | mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); |
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439 | if (mst_enc->fe == -1) |
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440 | DRM_ERROR("failed to get frontend for dig encoder\n"); |
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441 | mst_enc->fe_from_be = false; |
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442 | atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe); |
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443 | } |
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444 | |||
445 | |||
446 | dig_enc->linkb, radeon_crtc->crtc_id); |
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447 | |||
448 | |||
449 | radeon_connector->port, |
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450 | mst_enc->pbn, &slots); |
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451 | ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
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452 | |||
453 | |||
454 | radeon_connector->mst_port->hpd.hpd, true); |
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455 | |||
456 | |||
457 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
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458 | radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0); |
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459 | |||
460 | |||
461 | mst_enc->fe); |
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462 | ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr); |
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463 | |||
464 | |||
465 | |||
466 | |||
467 | case DRM_MODE_DPMS_STANDBY: |
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468 | case DRM_MODE_DPMS_SUSPEND: |
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469 | case DRM_MODE_DPMS_OFF: |
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470 | DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links); |
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471 | |||
472 | |||
473 | return; |
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474 | |||
475 | |||
476 | ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr); |
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477 | |||
478 | |||
479 | /* and this can also fail */ |
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480 | drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr); |
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481 | |||
482 | |||
483 | |||
484 | |||
485 | radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary); |
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486 | |||
487 | |||
488 | radeon_connector->mst_port->hpd.hpd, false); |
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489 | atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0, |
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490 | mst_enc->fe); |
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491 | |||
492 | |||
493 | radeon_atom_release_dig_encoder(rdev, mst_enc->fe); |
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494 | |||
495 | |||
496 | dig_enc->active_mst_links--; |
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497 | if (dig_enc->active_mst_links == 0) { |
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498 | /* drop link */ |
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499 | } |
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500 | |||
501 | |||
502 | } |
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503 | |||
504 | |||
505 | |||
506 | |||
507 | const struct drm_display_mode *mode, |
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508 | struct drm_display_mode *adjusted_mode) |
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509 | { |
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510 | struct radeon_encoder_mst *mst_enc; |
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511 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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512 | int bpp = 24; |
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513 | |||
514 | |||
515 | |||
516 | |||
517 | |||
518 | |||
519 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
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520 | mst_enc->primary->active_device, mst_enc->primary->devices, |
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521 | mst_enc->connector->devices, mst_enc->primary->base.encoder_type); |
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522 | |||
523 | |||
524 | |||
525 | { |
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526 | struct radeon_connector_atom_dig *dig_connector; |
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527 | dig_connector = mst_enc->connector->con_priv; |
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528 | dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); |
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529 | dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); |
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6661 | serge | 530 | DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector, |
6105 | serge | 531 | dig_connector->dp_lane_count, dig_connector->dp_clock); |
532 | } |
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533 | return true; |
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534 | } |
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535 | |||
536 | |||
537 | { |
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538 | struct radeon_connector *radeon_connector; |
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539 | struct radeon_encoder *radeon_encoder, *primary; |
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540 | struct radeon_encoder_mst *mst_enc; |
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541 | struct radeon_encoder_atom_dig *dig_enc; |
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542 | |||
543 | |||
544 | if (!radeon_connector) { |
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545 | DRM_DEBUG_KMS("failed to find connector %p\n", encoder); |
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546 | return; |
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547 | } |
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548 | radeon_encoder = to_radeon_encoder(encoder); |
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549 | |||
550 | |||
551 | |||
552 | |||
553 | |||
554 | |||
555 | |||
556 | |||
557 | |||
558 | |||
559 | |||
560 | |||
561 | dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1); |
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562 | primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder); |
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563 | atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder); |
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564 | |||
565 | |||
566 | |||
567 | DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset); |
||
568 | } |
||
569 | |||
570 | |||
571 | radeon_mst_encoder_mode_set(struct drm_encoder *encoder, |
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572 | struct drm_display_mode *mode, |
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573 | struct drm_display_mode *adjusted_mode) |
||
574 | { |
||
575 | DRM_DEBUG_KMS("\n"); |
||
576 | } |
||
577 | |||
578 | |||
579 | { |
||
580 | radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
||
581 | DRM_DEBUG_KMS("\n"); |
||
582 | } |
||
583 | |||
584 | |||
585 | .dpms = radeon_mst_encoder_dpms, |
||
586 | .mode_fixup = radeon_mst_mode_fixup, |
||
587 | .prepare = radeon_mst_encoder_prepare, |
||
588 | .mode_set = radeon_mst_encoder_mode_set, |
||
589 | .commit = radeon_mst_encoder_commit, |
||
590 | }; |
||
591 | |||
592 | |||
593 | { |
||
594 | drm_encoder_cleanup(encoder); |
||
595 | kfree(encoder); |
||
596 | } |
||
597 | |||
598 | |||
599 | .destroy = radeon_dp_mst_encoder_destroy, |
||
600 | }; |
||
601 | |||
602 | |||
603 | radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector) |
||
604 | { |
||
605 | struct drm_device *dev = connector->base.dev; |
||
606 | struct radeon_device *rdev = dev->dev_private; |
||
607 | struct radeon_encoder *radeon_encoder; |
||
608 | struct radeon_encoder_mst *mst_enc; |
||
609 | struct drm_encoder *encoder; |
||
610 | const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private; |
||
611 | struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base); |
||
612 | |||
613 | |||
614 | radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL); |
||
615 | if (!radeon_encoder) |
||
616 | return NULL; |
||
617 | |||
618 | |||
619 | if (!radeon_encoder->enc_priv) { |
||
620 | kfree(radeon_encoder); |
||
621 | return NULL; |
||
622 | } |
||
623 | encoder = &radeon_encoder->base; |
||
624 | switch (rdev->num_crtc) { |
||
625 | case 1: |
||
626 | encoder->possible_crtcs = 0x1; |
||
627 | break; |
||
628 | case 2: |
||
629 | default: |
||
630 | encoder->possible_crtcs = 0x3; |
||
631 | break; |
||
632 | case 4: |
||
633 | encoder->possible_crtcs = 0xf; |
||
634 | break; |
||
635 | case 6: |
||
636 | encoder->possible_crtcs = 0x3f; |
||
637 | break; |
||
638 | } |
||
639 | |||
640 | |||
641 | DRM_MODE_ENCODER_DPMST); |
||
642 | drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs); |
||
643 | |||
644 | |||
645 | mst_enc->connector = connector; |
||
646 | mst_enc->primary = to_radeon_encoder(enc_master); |
||
647 | radeon_encoder->is_mst_encoder = true; |
||
648 | return radeon_encoder; |
||
649 | } |
||
650 | |||
651 | |||
652 | radeon_dp_mst_init(struct radeon_connector *radeon_connector) |
||
653 | { |
||
654 | struct drm_device *dev = radeon_connector->base.dev; |
||
655 | |||
656 | |||
657 | return 0; |
||
658 | |||
659 | |||
660 | return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev->dev, |
||
661 | &radeon_connector->ddc_bus->aux, 16, 6, |
||
662 | radeon_connector->base.base.id); |
||
663 | } |
||
664 | |||
665 | |||
666 | radeon_dp_mst_probe(struct radeon_connector *radeon_connector) |
||
667 | { |
||
668 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
669 | struct drm_device *dev = radeon_connector->base.dev; |
||
670 | struct radeon_device *rdev = dev->dev_private; |
||
671 | int ret; |
||
672 | u8 msg[1]; |
||
673 | |||
674 | |||
675 | return 0; |
||
676 | |||
677 | |||
678 | return 0; |
||
679 | |||
680 | |||
681 | return 0; |
||
682 | |||
683 | |||
684 | 1); |
||
685 | if (ret) { |
||
686 | if (msg[0] & DP_MST_CAP) { |
||
687 | DRM_DEBUG_KMS("Sink is MST capable\n"); |
||
688 | dig_connector->is_mst = true; |
||
689 | } else { |
||
690 | DRM_DEBUG_KMS("Sink is not MST capable\n"); |
||
691 | dig_connector->is_mst = false; |
||
692 | } |
||
693 | |||
694 | |||
695 | drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
||
696 | dig_connector->is_mst); |
||
697 | return dig_connector->is_mst; |
||
698 | } |
||
699 | |||
700 | |||
701 | radeon_dp_mst_check_status(struct radeon_connector *radeon_connector) |
||
702 | { |
||
703 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
||
704 | int retry; |
||
705 | |||
706 | |||
707 | u8 esi[16] = { 0 }; |
||
708 | int dret; |
||
709 | int ret = 0; |
||
710 | bool handled; |
||
711 | |||
712 | |||
713 | DP_SINK_COUNT_ESI, esi, 8); |
||
714 | go_again: |
||
715 | if (dret == 8) { |
||
716 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
717 | ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled); |
||
718 | |||
719 | |||
720 | for (retry = 0; retry < 3; retry++) { |
||
721 | int wret; |
||
722 | wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux, |
||
723 | DP_SINK_COUNT_ESI + 1, &esi[1], 3); |
||
724 | if (wret == 3) |
||
725 | break; |
||
726 | } |
||
727 | |||
728 | |||
729 | DP_SINK_COUNT_ESI, esi, 8); |
||
730 | if (dret == 8) { |
||
731 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); |
||
732 | goto go_again; |
||
733 | } |
||
734 | } else |
||
735 | ret = 0; |
||
736 | |||
737 | |||
738 | } else { |
||
739 | DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret); |
||
740 | dig_connector->is_mst = false; |
||
741 | drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr, |
||
742 | dig_connector->is_mst); |
||
743 | /* send a hotplug event */ |
||
744 | } |
||
745 | } |
||
746 | return -EINVAL; |
||
747 | } |
||
748 | |||
749 | |||
750 | |||
751 | |||
752 | { |
||
753 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
||
754 | struct drm_device *dev = node->minor->dev; |
||
755 | struct drm_connector *connector; |
||
756 | struct radeon_connector *radeon_connector; |
||
757 | struct radeon_connector_atom_dig *dig_connector; |
||
758 | int i; |
||
759 | |||
760 | |||
761 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
762 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) |
||
763 | continue; |
||
764 | |||
765 | |||
766 | dig_connector = radeon_connector->con_priv; |
||
767 | if (radeon_connector->is_mst_connector) |
||
768 | continue; |
||
769 | if (!dig_connector->is_mst) |
||
770 | continue; |
||
771 | drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr); |
||
772 | |||
773 | |||
774 | seq_printf(m, "attrib %d: %d %d\n", i, |
||
775 | radeon_connector->cur_stream_attribs[i].fe, |
||
776 | radeon_connector->cur_stream_attribs[i].slots); |
||
777 | } |
||
778 | drm_modeset_unlock_all(dev); |
||
779 | return 0; |
||
780 | } |
||
781 | |||
782 | |||
783 | {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL}, |
||
784 | }; |
||
785 | #endif |
||
786 | |||
787 | |||
788 | { |
||
789 | #if defined(CONFIG_DEBUG_FS) |
||
790 | return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1); |
||
791 | #endif |
||
792 | return 0; |
||
793 | }>>>>>>>>><>=><=>>><>><> |
||
794 |