Rev 6105 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
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| 6105 | serge | 1 | /* |
| 2 | * Copyright 2015 Red Hat Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: Dave Airlie |
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| 23 | */ |
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| 24 | #include |
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| 25 | #include |
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| 26 | #include "radeon.h" |
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| 27 | #include "nid.h" |
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| 28 | |||
| 29 | #define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ |
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| 30 | AUX_SW_RX_HPD_DISCON | \ |
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| 31 | AUX_SW_RX_PARTIAL_BYTE | \ |
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| 32 | AUX_SW_NON_AUX_MODE | \ |
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| 33 | AUX_SW_RX_SYNC_INVALID_L | \ |
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| 34 | AUX_SW_RX_SYNC_INVALID_H | \ |
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| 35 | AUX_SW_RX_INVALID_START | \ |
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| 36 | AUX_SW_RX_RECV_NO_DET | \ |
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| 37 | AUX_SW_RX_RECV_INVALID_H | \ |
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| 38 | AUX_SW_RX_RECV_INVALID_V) |
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| 39 | |||
| 40 | #define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) |
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| 41 | |||
| 42 | #define BARE_ADDRESS_SIZE 3 |
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| 43 | |||
| 44 | static const u32 aux_offset[] = |
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| 45 | { |
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| 46 | 0x6200 - 0x6200, |
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| 47 | 0x6250 - 0x6200, |
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| 48 | 0x62a0 - 0x6200, |
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| 49 | 0x6300 - 0x6200, |
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| 50 | 0x6350 - 0x6200, |
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| 51 | 0x63a0 - 0x6200, |
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| 52 | }; |
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| 53 | |||
| 54 | ssize_t |
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| 55 | radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
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| 56 | { |
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| 57 | struct radeon_i2c_chan *chan = |
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| 58 | container_of(aux, struct radeon_i2c_chan, aux); |
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| 59 | struct drm_device *dev = chan->dev; |
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| 60 | struct radeon_device *rdev = dev->dev_private; |
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| 61 | int ret = 0, i; |
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| 62 | uint32_t tmp, ack = 0; |
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| 63 | int instance = chan->rec.i2c_id & 0xf; |
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| 64 | u8 byte; |
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| 65 | u8 *buf = msg->buffer; |
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| 66 | int retry_count = 0; |
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| 67 | int bytes; |
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| 68 | int msize; |
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| 69 | bool is_write = false; |
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| 70 | |||
| 71 | if (WARN_ON(msg->size > 16)) |
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| 72 | return -E2BIG; |
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| 73 | |||
| 74 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
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| 75 | case DP_AUX_NATIVE_WRITE: |
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| 76 | case DP_AUX_I2C_WRITE: |
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| 77 | is_write = true; |
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| 78 | break; |
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| 79 | case DP_AUX_NATIVE_READ: |
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| 80 | case DP_AUX_I2C_READ: |
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| 81 | break; |
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| 82 | default: |
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| 83 | return -EINVAL; |
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| 84 | } |
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| 85 | |||
| 86 | /* work out two sizes required */ |
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| 87 | msize = 0; |
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| 88 | bytes = BARE_ADDRESS_SIZE; |
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| 89 | if (msg->size) { |
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| 90 | msize = msg->size - 1; |
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| 91 | bytes++; |
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| 92 | if (is_write) |
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| 93 | bytes += msg->size; |
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| 94 | } |
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| 95 | |||
| 96 | mutex_lock(&chan->mutex); |
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| 97 | |||
| 98 | /* switch the pad to aux mode */ |
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| 99 | tmp = RREG32(chan->rec.mask_clk_reg); |
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| 100 | tmp |= (1 << 16); |
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| 101 | WREG32(chan->rec.mask_clk_reg, tmp); |
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| 102 | |||
| 103 | /* setup AUX control register with correct HPD pin */ |
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| 104 | tmp = RREG32(AUX_CONTROL + aux_offset[instance]); |
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| 105 | |||
| 106 | tmp &= AUX_HPD_SEL(0x7); |
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| 107 | tmp |= AUX_HPD_SEL(chan->rec.hpd); |
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| 6661 | serge | 108 | tmp |= AUX_EN | AUX_LS_READ_EN | AUX_HPD_DISCON(0x1); |
| 6105 | serge | 109 | |
| 110 | WREG32(AUX_CONTROL + aux_offset[instance], tmp); |
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| 111 | |||
| 112 | /* atombios appears to write this twice lets copy it */ |
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| 113 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
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| 114 | AUX_SW_WR_BYTES(bytes)); |
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| 115 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
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| 116 | AUX_SW_WR_BYTES(bytes)); |
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| 117 | |||
| 118 | /* write the data header into the registers */ |
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| 119 | /* request, address, msg size */ |
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| 120 | byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
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| 121 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 122 | AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); |
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| 123 | |||
| 124 | byte = (msg->address >> 8) & 0xff; |
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| 125 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 126 | AUX_SW_DATA_MASK(byte)); |
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| 127 | |||
| 128 | byte = msg->address & 0xff; |
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| 129 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 130 | AUX_SW_DATA_MASK(byte)); |
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| 131 | |||
| 132 | byte = msize; |
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| 133 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 134 | AUX_SW_DATA_MASK(byte)); |
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| 135 | |||
| 136 | /* if we are writing - write the msg buffer */ |
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| 137 | if (is_write) { |
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| 138 | for (i = 0; i < msg->size; i++) { |
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| 139 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 140 | AUX_SW_DATA_MASK(buf[i])); |
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| 141 | } |
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| 142 | } |
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| 143 | |||
| 144 | /* clear the ACK */ |
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| 145 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
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| 146 | |||
| 147 | /* write the size and GO bits */ |
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| 148 | WREG32(AUX_SW_CONTROL + aux_offset[instance], |
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| 149 | AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); |
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| 150 | |||
| 151 | /* poll the status registers - TODO irq support */ |
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| 152 | do { |
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| 153 | tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); |
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| 154 | if (tmp & AUX_SW_DONE) { |
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| 155 | break; |
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| 156 | } |
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| 157 | usleep_range(100, 200); |
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| 158 | } while (retry_count++ < 1000); |
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| 159 | |||
| 160 | if (retry_count >= 1000) { |
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| 161 | DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); |
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| 162 | ret = -EIO; |
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| 163 | goto done; |
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| 164 | } |
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| 165 | |||
| 166 | if (tmp & AUX_SW_RX_TIMEOUT) { |
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| 167 | DRM_DEBUG_KMS("dp_aux_ch timed out\n"); |
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| 168 | ret = -ETIMEDOUT; |
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| 169 | goto done; |
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| 170 | } |
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| 171 | if (tmp & AUX_RX_ERROR_FLAGS) { |
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| 172 | DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); |
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| 173 | ret = -EIO; |
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| 174 | goto done; |
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| 175 | } |
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| 176 | |||
| 177 | bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); |
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| 178 | if (bytes) { |
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| 179 | WREG32(AUX_SW_DATA + aux_offset[instance], |
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| 180 | AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); |
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| 181 | |||
| 182 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
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| 183 | ack = (tmp >> 8) & 0xff; |
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| 184 | |||
| 185 | for (i = 0; i < bytes - 1; i++) { |
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| 186 | tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); |
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| 187 | if (buf) |
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| 188 | buf[i] = (tmp >> 8) & 0xff; |
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| 189 | } |
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| 190 | if (buf) |
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| 191 | ret = bytes - 1; |
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| 192 | } |
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| 193 | |||
| 194 | WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); |
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| 195 | |||
| 196 | if (is_write) |
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| 197 | ret = msg->size; |
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| 198 | done: |
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| 199 | mutex_unlock(&chan->mutex); |
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| 200 | |||
| 201 | if (ret >= 0) |
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| 202 | msg->reply = ack >> 4; |
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| 203 | return ret; |
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| 204 | } |