Rev 5271 | Rev 6321 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * |
||
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
6 | * copy of this software and associated documentation files (the "Software"), |
||
7 | * to deal in the Software without restriction, including without limitation |
||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
9 | * and/or sell copies of the Software, and to permit persons to whom the |
||
10 | * Software is furnished to do so, subject to the following conditions: |
||
11 | * |
||
12 | * The above copyright notice and this permission notice shall be included in |
||
13 | * all copies or substantial portions of the Software. |
||
14 | * |
||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
21 | * OTHER DEALINGS IN THE SOFTWARE. |
||
22 | * |
||
23 | * Authors: Dave Airlie |
||
24 | * Alex Deucher |
||
25 | */ |
||
2997 | Serge | 26 | #include |
27 | #include |
||
1123 | serge | 28 | #include "radeon.h" |
29 | |||
30 | #include "atom.h" |
||
1963 | serge | 31 | #include |
1123 | serge | 32 | |
6104 | serge | 33 | #include |
2997 | Serge | 34 | #include |
6104 | serge | 35 | #include |
2997 | Serge | 36 | #include |
1123 | serge | 37 | |
6104 | serge | 38 | #include |
5078 | serge | 39 | |
1123 | serge | 40 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
41 | { |
||
42 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
43 | struct drm_device *dev = crtc->dev; |
||
44 | struct radeon_device *rdev = dev->dev_private; |
||
45 | int i; |
||
46 | |||
1963 | serge | 47 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
1123 | serge | 48 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
49 | |||
50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
||
51 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
||
52 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
||
53 | |||
54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
||
55 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
||
56 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
||
57 | |||
58 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
||
59 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
||
60 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
||
61 | |||
62 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
||
63 | for (i = 0; i < 256; i++) { |
||
64 | WREG32(AVIVO_DC_LUT_30_COLOR, |
||
65 | (radeon_crtc->lut_r[i] << 20) | |
||
66 | (radeon_crtc->lut_g[i] << 10) | |
||
67 | (radeon_crtc->lut_b[i] << 0)); |
||
68 | } |
||
69 | |||
5078 | serge | 70 | /* Only change bit 0 of LUT_SEL, other bits are set elsewhere */ |
71 | WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); |
||
1123 | serge | 72 | } |
73 | |||
1963 | serge | 74 | static void dce4_crtc_load_lut(struct drm_crtc *crtc) |
1430 | serge | 75 | { |
76 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
77 | struct drm_device *dev = crtc->dev; |
||
78 | struct radeon_device *rdev = dev->dev_private; |
||
79 | int i; |
||
80 | |||
1963 | serge | 81 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
1430 | serge | 82 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
83 | |||
84 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
||
85 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
||
86 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
||
87 | |||
88 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
||
89 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
||
90 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
||
91 | |||
1963 | serge | 92 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
93 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
||
1430 | serge | 94 | |
1963 | serge | 95 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
1430 | serge | 96 | for (i = 0; i < 256; i++) { |
1963 | serge | 97 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
1430 | serge | 98 | (radeon_crtc->lut_r[i] << 20) | |
99 | (radeon_crtc->lut_g[i] << 10) | |
||
100 | (radeon_crtc->lut_b[i] << 0)); |
||
101 | } |
||
102 | } |
||
103 | |||
1963 | serge | 104 | static void dce5_crtc_load_lut(struct drm_crtc *crtc) |
105 | { |
||
106 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
107 | struct drm_device *dev = crtc->dev; |
||
108 | struct radeon_device *rdev = dev->dev_private; |
||
109 | int i; |
||
110 | |||
111 | DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); |
||
112 | |||
113 | WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
||
114 | (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | |
||
115 | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); |
||
116 | WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, |
||
117 | NI_GRPH_PRESCALE_BYPASS); |
||
118 | WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, |
||
119 | NI_OVL_PRESCALE_BYPASS); |
||
120 | WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, |
||
121 | (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) | |
||
122 | NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT))); |
||
123 | |||
124 | WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); |
||
125 | |||
126 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
||
127 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
||
128 | WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
||
129 | |||
130 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
||
131 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
||
132 | WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
||
133 | |||
134 | WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); |
||
135 | WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); |
||
136 | |||
137 | WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); |
||
138 | for (i = 0; i < 256; i++) { |
||
139 | WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, |
||
140 | (radeon_crtc->lut_r[i] << 20) | |
||
141 | (radeon_crtc->lut_g[i] << 10) | |
||
142 | (radeon_crtc->lut_b[i] << 0)); |
||
143 | } |
||
144 | |||
145 | WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, |
||
146 | (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
||
147 | NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
||
148 | NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) | |
||
149 | NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS))); |
||
150 | WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, |
||
151 | (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) | |
||
152 | NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS))); |
||
153 | WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, |
||
154 | (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) | |
||
155 | NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS))); |
||
156 | WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, |
||
6104 | serge | 157 | (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | |
1963 | serge | 158 | NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS))); |
159 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
||
160 | WREG32(0x6940 + radeon_crtc->crtc_offset, 0); |
||
5078 | serge | 161 | if (ASIC_IS_DCE8(rdev)) { |
162 | /* XXX this only needs to be programmed once per crtc at startup, |
||
163 | * not sure where the best place for it is |
||
164 | */ |
||
165 | WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, |
||
166 | CIK_CURSOR_ALPHA_BLND_ENA); |
||
167 | } |
||
1963 | serge | 168 | } |
169 | |||
1123 | serge | 170 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
171 | { |
||
172 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
173 | struct drm_device *dev = crtc->dev; |
||
174 | struct radeon_device *rdev = dev->dev_private; |
||
175 | int i; |
||
176 | uint32_t dac2_cntl; |
||
177 | |||
178 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
||
179 | if (radeon_crtc->crtc_id == 0) |
||
180 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
||
181 | else |
||
182 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
||
183 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
||
184 | |||
185 | WREG8(RADEON_PALETTE_INDEX, 0); |
||
186 | for (i = 0; i < 256; i++) { |
||
187 | WREG32(RADEON_PALETTE_30_DATA, |
||
188 | (radeon_crtc->lut_r[i] << 20) | |
||
189 | (radeon_crtc->lut_g[i] << 10) | |
||
190 | (radeon_crtc->lut_b[i] << 0)); |
||
191 | } |
||
192 | } |
||
193 | |||
194 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
||
195 | { |
||
196 | struct drm_device *dev = crtc->dev; |
||
197 | struct radeon_device *rdev = dev->dev_private; |
||
198 | |||
199 | if (!crtc->enabled) |
||
200 | return; |
||
201 | |||
1963 | serge | 202 | if (ASIC_IS_DCE5(rdev)) |
203 | dce5_crtc_load_lut(crtc); |
||
204 | else if (ASIC_IS_DCE4(rdev)) |
||
205 | dce4_crtc_load_lut(crtc); |
||
1430 | serge | 206 | else if (ASIC_IS_AVIVO(rdev)) |
1123 | serge | 207 | avivo_crtc_load_lut(crtc); |
208 | else |
||
209 | legacy_crtc_load_lut(crtc); |
||
210 | } |
||
211 | |||
1221 | serge | 212 | /** Sets the color ramps on behalf of fbcon */ |
1123 | serge | 213 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
214 | u16 blue, int regno) |
||
215 | { |
||
216 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
217 | |||
218 | radeon_crtc->lut_r[regno] = red >> 6; |
||
219 | radeon_crtc->lut_g[regno] = green >> 6; |
||
220 | radeon_crtc->lut_b[regno] = blue >> 6; |
||
221 | } |
||
222 | |||
1221 | serge | 223 | /** Gets the color ramps on behalf of fbcon */ |
224 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
||
225 | u16 *blue, int regno) |
||
226 | { |
||
227 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
228 | |||
229 | *red = radeon_crtc->lut_r[regno] << 6; |
||
230 | *green = radeon_crtc->lut_g[regno] << 6; |
||
231 | *blue = radeon_crtc->lut_b[regno] << 6; |
||
232 | } |
||
233 | |||
1123 | serge | 234 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
1963 | serge | 235 | u16 *blue, uint32_t start, uint32_t size) |
1123 | serge | 236 | { |
237 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
1963 | serge | 238 | int end = (start + size > 256) ? 256 : start + size, i; |
1123 | serge | 239 | |
1221 | serge | 240 | /* userspace palettes are always correct as is */ |
1963 | serge | 241 | for (i = start; i < end; i++) { |
6104 | serge | 242 | radeon_crtc->lut_r[i] = red[i] >> 6; |
243 | radeon_crtc->lut_g[i] = green[i] >> 6; |
||
244 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
||
245 | } |
||
1123 | serge | 246 | radeon_crtc_load_lut(crtc); |
247 | } |
||
248 | |||
249 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
||
250 | { |
||
251 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
252 | |||
253 | drm_crtc_cleanup(crtc); |
||
254 | kfree(radeon_crtc); |
||
255 | } |
||
256 | |||
6104 | serge | 257 | void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id) |
258 | { |
||
259 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
||
260 | unsigned long flags; |
||
261 | u32 update_pending; |
||
262 | int vpos, hpos; |
||
263 | |||
264 | /* can happen during initialization */ |
||
265 | if (radeon_crtc == NULL) |
||
266 | return; |
||
267 | |||
268 | /* Skip the pageflip completion check below (based on polling) on |
||
269 | * asics which reliably support hw pageflip completion irqs. pflip |
||
270 | * irqs are a reliable and race-free method of handling pageflip |
||
271 | * completion detection. A use_pflipirq module parameter < 2 allows |
||
272 | * to override this in case of asics with faulty pflip irqs. |
||
273 | * A module parameter of 0 would only use this polling based path, |
||
274 | * a parameter of 1 would use pflip irq only as a backup to this |
||
275 | * path, as in Linux 3.16. |
||
276 | */ |
||
277 | if ((radeon_use_pflipirq == 2) && ASIC_IS_DCE4(rdev)) |
||
278 | return; |
||
279 | |||
280 | spin_lock_irqsave(&rdev->ddev->event_lock, flags); |
||
281 | if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { |
||
282 | DRM_DEBUG_DRIVER("radeon_crtc->flip_status = %d != " |
||
283 | "RADEON_FLIP_SUBMITTED(%d)\n", |
||
284 | radeon_crtc->flip_status, |
||
285 | RADEON_FLIP_SUBMITTED); |
||
286 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
||
287 | return; |
||
288 | } |
||
289 | |||
290 | update_pending = radeon_page_flip_pending(rdev, crtc_id); |
||
291 | |||
292 | /* Has the pageflip already completed in crtc, or is it certain |
||
293 | * to complete in this vblank? |
||
294 | */ |
||
295 | if (update_pending && |
||
296 | (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, |
||
297 | crtc_id, |
||
298 | USE_REAL_VBLANKSTART, |
||
299 | &vpos, &hpos, NULL, NULL, |
||
300 | &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && |
||
301 | ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) || |
||
302 | (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) { |
||
303 | /* crtc didn't flip in this target vblank interval, |
||
304 | * but flip is pending in crtc. Based on the current |
||
305 | * scanout position we know that the current frame is |
||
306 | * (nearly) complete and the flip will (likely) |
||
307 | * complete before the start of the next frame. |
||
308 | */ |
||
309 | update_pending = 0; |
||
310 | } |
||
311 | spin_unlock_irqrestore(&rdev->ddev->event_lock, flags); |
||
312 | // if (!update_pending) |
||
313 | // radeon_crtc_handle_flip(rdev, crtc_id); |
||
314 | } |
||
315 | |||
5078 | serge | 316 | static int |
317 | radeon_crtc_set_config(struct drm_mode_set *set) |
||
318 | { |
||
319 | struct drm_device *dev; |
||
320 | struct radeon_device *rdev; |
||
321 | struct drm_crtc *crtc; |
||
322 | bool active = false; |
||
323 | int ret; |
||
324 | |||
325 | if (!set || !set->crtc) |
||
326 | return -EINVAL; |
||
327 | |||
328 | dev = set->crtc->dev; |
||
329 | |||
330 | ret = drm_crtc_helper_set_config(set); |
||
331 | |||
332 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
||
333 | if (crtc->enabled) |
||
334 | active = true; |
||
335 | |||
336 | // pm_runtime_mark_last_busy(dev->dev); |
||
337 | |||
338 | rdev = dev->dev_private; |
||
339 | /* if we have active crtcs and we don't have a power ref, |
||
340 | take the current one */ |
||
341 | if (active && !rdev->have_disp_power_ref) { |
||
342 | rdev->have_disp_power_ref = true; |
||
343 | return ret; |
||
344 | } |
||
345 | /* if we have no active crtcs, then drop the power ref |
||
346 | we got before */ |
||
347 | if (!active && rdev->have_disp_power_ref) { |
||
348 | // pm_runtime_put_autosuspend(dev->dev); |
||
349 | rdev->have_disp_power_ref = false; |
||
350 | } |
||
351 | |||
352 | /* drop the power reference we got coming in here */ |
||
353 | // pm_runtime_put_autosuspend(dev->dev); |
||
354 | return ret; |
||
355 | } |
||
1123 | serge | 356 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
1221 | serge | 357 | .cursor_set = NULL, |
358 | .cursor_move = NULL, |
||
1123 | serge | 359 | .gamma_set = radeon_crtc_gamma_set, |
5078 | serge | 360 | .set_config = radeon_crtc_set_config, |
1123 | serge | 361 | .destroy = radeon_crtc_destroy, |
1963 | serge | 362 | .page_flip = NULL, |
1123 | serge | 363 | }; |
364 | |||
365 | static void radeon_crtc_init(struct drm_device *dev, int index) |
||
366 | { |
||
367 | struct radeon_device *rdev = dev->dev_private; |
||
368 | struct radeon_crtc *radeon_crtc; |
||
369 | int i; |
||
370 | |||
371 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
||
372 | if (radeon_crtc == NULL) |
||
373 | return; |
||
374 | |||
375 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
||
376 | |||
377 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
||
378 | radeon_crtc->crtc_id = index; |
||
1179 | serge | 379 | rdev->mode_info.crtcs[index] = radeon_crtc; |
1123 | serge | 380 | |
5078 | serge | 381 | if (rdev->family >= CHIP_BONAIRE) { |
382 | radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; |
||
383 | radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; |
||
384 | } else { |
||
385 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; |
||
386 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; |
||
387 | } |
||
388 | dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; |
||
389 | dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; |
||
390 | |||
1179 | serge | 391 | #if 0 |
1123 | serge | 392 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
393 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
||
394 | radeon_crtc->mode_set.num_connectors = 0; |
||
1179 | serge | 395 | #endif |
1123 | serge | 396 | |
397 | for (i = 0; i < 256; i++) { |
||
398 | radeon_crtc->lut_r[i] = i << 2; |
||
399 | radeon_crtc->lut_g[i] = i << 2; |
||
400 | radeon_crtc->lut_b[i] = i << 2; |
||
401 | } |
||
402 | |||
403 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
||
404 | radeon_atombios_init_crtc(dev, radeon_crtc); |
||
405 | else |
||
406 | radeon_legacy_init_crtc(dev, radeon_crtc); |
||
407 | } |
||
408 | |||
5078 | serge | 409 | static const char *encoder_names[38] = { |
1123 | serge | 410 | "NONE", |
411 | "INTERNAL_LVDS", |
||
412 | "INTERNAL_TMDS1", |
||
413 | "INTERNAL_TMDS2", |
||
414 | "INTERNAL_DAC1", |
||
415 | "INTERNAL_DAC2", |
||
416 | "INTERNAL_SDVOA", |
||
417 | "INTERNAL_SDVOB", |
||
418 | "SI170B", |
||
419 | "CH7303", |
||
420 | "CH7301", |
||
421 | "INTERNAL_DVO1", |
||
422 | "EXTERNAL_SDVOA", |
||
423 | "EXTERNAL_SDVOB", |
||
424 | "TITFP513", |
||
425 | "INTERNAL_LVTM1", |
||
426 | "VT1623", |
||
427 | "HDMI_SI1930", |
||
428 | "HDMI_INTERNAL", |
||
429 | "INTERNAL_KLDSCP_TMDS1", |
||
430 | "INTERNAL_KLDSCP_DVO1", |
||
431 | "INTERNAL_KLDSCP_DAC1", |
||
432 | "INTERNAL_KLDSCP_DAC2", |
||
433 | "SI178", |
||
434 | "MVPU_FPGA", |
||
435 | "INTERNAL_DDI", |
||
436 | "VT1625", |
||
437 | "HDMI_SI1932", |
||
438 | "DP_AN9801", |
||
439 | "DP_DP501", |
||
440 | "INTERNAL_UNIPHY", |
||
441 | "INTERNAL_KLDSCP_LVTMA", |
||
442 | "INTERNAL_UNIPHY1", |
||
443 | "INTERNAL_UNIPHY2", |
||
1963 | serge | 444 | "NUTMEG", |
445 | "TRAVIS", |
||
5078 | serge | 446 | "INTERNAL_VCE", |
447 | "INTERNAL_UNIPHY3", |
||
1123 | serge | 448 | }; |
449 | |||
1963 | serge | 450 | static const char *hpd_names[6] = { |
1404 | serge | 451 | "HPD1", |
452 | "HPD2", |
||
453 | "HPD3", |
||
454 | "HPD4", |
||
455 | "HPD5", |
||
456 | "HPD6", |
||
457 | }; |
||
458 | |||
1123 | serge | 459 | static void radeon_print_display_setup(struct drm_device *dev) |
460 | { |
||
461 | struct drm_connector *connector; |
||
462 | struct radeon_connector *radeon_connector; |
||
463 | struct drm_encoder *encoder; |
||
464 | struct radeon_encoder *radeon_encoder; |
||
465 | uint32_t devices; |
||
466 | int i = 0; |
||
467 | |||
468 | DRM_INFO("Radeon Display Connectors\n"); |
||
469 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
||
470 | radeon_connector = to_radeon_connector(connector); |
||
471 | DRM_INFO("Connector %d:\n", i); |
||
5078 | serge | 472 | DRM_INFO(" %s\n", connector->name); |
1404 | serge | 473 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
474 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
||
475 | if (radeon_connector->ddc_bus) { |
||
1123 | serge | 476 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
477 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
||
478 | radeon_connector->ddc_bus->rec.mask_data_reg, |
||
479 | radeon_connector->ddc_bus->rec.a_clk_reg, |
||
480 | radeon_connector->ddc_bus->rec.a_data_reg, |
||
1404 | serge | 481 | radeon_connector->ddc_bus->rec.en_clk_reg, |
482 | radeon_connector->ddc_bus->rec.en_data_reg, |
||
483 | radeon_connector->ddc_bus->rec.y_clk_reg, |
||
484 | radeon_connector->ddc_bus->rec.y_data_reg); |
||
1963 | serge | 485 | if (radeon_connector->router.ddc_valid) |
486 | DRM_INFO(" DDC Router 0x%x/0x%x\n", |
||
487 | radeon_connector->router.ddc_mux_control_pin, |
||
488 | radeon_connector->router.ddc_mux_state); |
||
489 | if (radeon_connector->router.cd_valid) |
||
490 | DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", |
||
491 | radeon_connector->router.cd_mux_control_pin, |
||
492 | radeon_connector->router.cd_mux_state); |
||
1404 | serge | 493 | } else { |
494 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
||
495 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
||
496 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
||
497 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
||
498 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
||
499 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
||
500 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
||
501 | } |
||
1123 | serge | 502 | DRM_INFO(" Encoders:\n"); |
503 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
504 | radeon_encoder = to_radeon_encoder(encoder); |
||
505 | devices = radeon_encoder->devices & radeon_connector->devices; |
||
506 | if (devices) { |
||
507 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
||
508 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
509 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
||
510 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
511 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
||
512 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
513 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
||
514 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
515 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
||
516 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
517 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
||
518 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
519 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
||
520 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
521 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
||
522 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
1963 | serge | 523 | if (devices & ATOM_DEVICE_DFP6_SUPPORT) |
524 | DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
1123 | serge | 525 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
526 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
527 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
||
528 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
||
529 | } |
||
530 | } |
||
531 | i++; |
||
532 | } |
||
533 | } |
||
534 | |||
1179 | serge | 535 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
1123 | serge | 536 | { |
537 | struct radeon_device *rdev = dev->dev_private; |
||
538 | bool ret = false; |
||
539 | |||
540 | if (rdev->bios) { |
||
541 | if (rdev->is_atom_bios) { |
||
1963 | serge | 542 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
543 | if (ret == false) |
||
1123 | serge | 544 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
1404 | serge | 545 | } else { |
1123 | serge | 546 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
1404 | serge | 547 | if (ret == false) |
548 | ret = radeon_get_legacy_connector_info_from_table(dev); |
||
549 | } |
||
1123 | serge | 550 | } else { |
551 | if (!ASIC_IS_AVIVO(rdev)) |
||
552 | ret = radeon_get_legacy_connector_info_from_table(dev); |
||
553 | } |
||
554 | if (ret) { |
||
1404 | serge | 555 | radeon_setup_encoder_clones(dev); |
1123 | serge | 556 | radeon_print_display_setup(dev); |
557 | } |
||
558 | |||
559 | return ret; |
||
560 | } |
||
561 | |||
5078 | serge | 562 | /* avivo */ |
563 | |||
564 | /** |
||
565 | * avivo_reduce_ratio - fractional number reduction |
||
566 | * |
||
567 | * @nom: nominator |
||
568 | * @den: denominator |
||
569 | * @nom_min: minimum value for nominator |
||
570 | * @den_min: minimum value for denominator |
||
571 | * |
||
572 | * Find the greatest common divisor and apply it on both nominator and |
||
573 | * denominator, but make nominator and denominator are at least as large |
||
574 | * as their minimum values. |
||
575 | */ |
||
576 | static void avivo_reduce_ratio(unsigned *nom, unsigned *den, |
||
577 | unsigned nom_min, unsigned den_min) |
||
1123 | serge | 578 | { |
5078 | serge | 579 | unsigned tmp; |
1123 | serge | 580 | |
5078 | serge | 581 | /* reduce the numbers to a simpler ratio */ |
582 | tmp = gcd(*nom, *den); |
||
583 | *nom /= tmp; |
||
584 | *den /= tmp; |
||
1963 | serge | 585 | |
5078 | serge | 586 | /* make sure nominator is large enough */ |
587 | if (*nom < nom_min) { |
||
588 | tmp = DIV_ROUND_UP(nom_min, *nom); |
||
589 | *nom *= tmp; |
||
590 | *den *= tmp; |
||
1404 | serge | 591 | } |
1963 | serge | 592 | |
5078 | serge | 593 | /* make sure the denominator is large enough */ |
594 | if (*den < den_min) { |
||
595 | tmp = DIV_ROUND_UP(den_min, *den); |
||
596 | *nom *= tmp; |
||
597 | *den *= tmp; |
||
1963 | serge | 598 | } |
1123 | serge | 599 | } |
600 | |||
5078 | serge | 601 | /** |
602 | * avivo_get_fb_ref_div - feedback and ref divider calculation |
||
603 | * |
||
604 | * @nom: nominator |
||
605 | * @den: denominator |
||
606 | * @post_div: post divider |
||
607 | * @fb_div_max: feedback divider maximum |
||
608 | * @ref_div_max: reference divider maximum |
||
609 | * @fb_div: resulting feedback divider |
||
610 | * @ref_div: resulting reference divider |
||
611 | * |
||
612 | * Calculate feedback and reference divider for a given post divider. Makes |
||
613 | * sure we stay within the limits. |
||
614 | */ |
||
615 | static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, |
||
616 | unsigned fb_div_max, unsigned ref_div_max, |
||
617 | unsigned *fb_div, unsigned *ref_div) |
||
1963 | serge | 618 | { |
5078 | serge | 619 | /* limit reference * post divider to a maximum */ |
620 | ref_div_max = max(min(100 / post_div, ref_div_max), 1u); |
||
1963 | serge | 621 | |
5078 | serge | 622 | /* get matching reference and feedback divider */ |
623 | *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); |
||
624 | *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); |
||
1963 | serge | 625 | |
5078 | serge | 626 | /* limit fb divider to its maximum */ |
627 | if (*fb_div > fb_div_max) { |
||
628 | *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); |
||
629 | *fb_div = fb_div_max; |
||
630 | } |
||
1963 | serge | 631 | } |
632 | |||
5078 | serge | 633 | /** |
634 | * radeon_compute_pll_avivo - compute PLL paramaters |
||
635 | * |
||
636 | * @pll: information about the PLL |
||
637 | * @dot_clock_p: resulting pixel clock |
||
638 | * fb_div_p: resulting feedback divider |
||
639 | * frac_fb_div_p: fractional part of the feedback divider |
||
640 | * ref_div_p: resulting reference divider |
||
641 | * post_div_p: resulting reference divider |
||
642 | * |
||
643 | * Try to calculate the PLL parameters to generate the given frequency: |
||
644 | * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) |
||
645 | */ |
||
646 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
||
647 | u32 freq, |
||
648 | u32 *dot_clock_p, |
||
649 | u32 *fb_div_p, |
||
650 | u32 *frac_fb_div_p, |
||
651 | u32 *ref_div_p, |
||
652 | u32 *post_div_p) |
||
1963 | serge | 653 | { |
5078 | serge | 654 | unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? |
655 | freq : freq / 10; |
||
1963 | serge | 656 | |
5078 | serge | 657 | unsigned fb_div_min, fb_div_max, fb_div; |
658 | unsigned post_div_min, post_div_max, post_div; |
||
659 | unsigned ref_div_min, ref_div_max, ref_div; |
||
660 | unsigned post_div_best, diff_best; |
||
661 | unsigned nom, den; |
||
1963 | serge | 662 | |
5078 | serge | 663 | /* determine allowed feedback divider range */ |
664 | fb_div_min = pll->min_feedback_div; |
||
665 | fb_div_max = pll->max_feedback_div; |
||
666 | |||
667 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
668 | fb_div_min *= 10; |
||
669 | fb_div_max *= 10; |
||
670 | } |
||
671 | |||
672 | /* determine allowed ref divider range */ |
||
673 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
||
674 | ref_div_min = pll->reference_div; |
||
675 | else |
||
676 | ref_div_min = pll->min_ref_div; |
||
677 | |||
678 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && |
||
679 | pll->flags & RADEON_PLL_USE_REF_DIV) |
||
680 | ref_div_max = pll->reference_div; |
||
6104 | serge | 681 | else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
682 | /* fix for problems on RS880 */ |
||
683 | ref_div_max = min(pll->max_ref_div, 7u); |
||
1963 | serge | 684 | else |
5078 | serge | 685 | ref_div_max = pll->max_ref_div; |
686 | |||
687 | /* determine allowed post divider range */ |
||
688 | if (pll->flags & RADEON_PLL_USE_POST_DIV) { |
||
689 | post_div_min = pll->post_div; |
||
690 | post_div_max = pll->post_div; |
||
1963 | serge | 691 | } else { |
5078 | serge | 692 | unsigned vco_min, vco_max; |
693 | |||
694 | if (pll->flags & RADEON_PLL_IS_LCD) { |
||
695 | vco_min = pll->lcd_pll_out_min; |
||
696 | vco_max = pll->lcd_pll_out_max; |
||
697 | } else { |
||
698 | vco_min = pll->pll_out_min; |
||
699 | vco_max = pll->pll_out_max; |
||
700 | } |
||
701 | |||
702 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
703 | vco_min *= 10; |
||
704 | vco_max *= 10; |
||
6104 | serge | 705 | } |
1963 | serge | 706 | |
5078 | serge | 707 | post_div_min = vco_min / target_clock; |
708 | if ((target_clock * post_div_min) < vco_min) |
||
709 | ++post_div_min; |
||
710 | if (post_div_min < pll->min_post_div) |
||
711 | post_div_min = pll->min_post_div; |
||
1963 | serge | 712 | |
5078 | serge | 713 | post_div_max = vco_max / target_clock; |
714 | if ((target_clock * post_div_max) > vco_max) |
||
715 | --post_div_max; |
||
716 | if (post_div_max > pll->max_post_div) |
||
717 | post_div_max = pll->max_post_div; |
||
1963 | serge | 718 | } |
719 | |||
5078 | serge | 720 | /* represent the searched ratio as fractional number */ |
721 | nom = target_clock; |
||
722 | den = pll->reference_freq; |
||
1963 | serge | 723 | |
5078 | serge | 724 | /* reduce the numbers to a simpler ratio */ |
725 | avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min); |
||
1963 | serge | 726 | |
5078 | serge | 727 | /* now search for a post divider */ |
728 | if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) |
||
729 | post_div_best = post_div_min; |
||
730 | else |
||
731 | post_div_best = post_div_max; |
||
732 | diff_best = ~0; |
||
1963 | serge | 733 | |
5078 | serge | 734 | for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { |
735 | unsigned diff; |
||
736 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, |
||
737 | ref_div_max, &fb_div, &ref_div); |
||
738 | diff = abs(target_clock - (pll->reference_freq * fb_div) / |
||
739 | (ref_div * post_div)); |
||
1963 | serge | 740 | |
5078 | serge | 741 | if (diff < diff_best || (diff == diff_best && |
742 | !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { |
||
1963 | serge | 743 | |
5078 | serge | 744 | post_div_best = post_div; |
745 | diff_best = diff; |
||
1963 | serge | 746 | } |
5078 | serge | 747 | } |
748 | post_div = post_div_best; |
||
1963 | serge | 749 | |
5078 | serge | 750 | /* get the feedback and reference divider for the optimal value */ |
751 | avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, |
||
752 | &fb_div, &ref_div); |
||
753 | |||
754 | /* reduce the numbers to a simpler ratio once more */ |
||
755 | /* this also makes sure that the reference divider is large enough */ |
||
756 | avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); |
||
757 | |||
758 | /* avoid high jitter with small fractional dividers */ |
||
759 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { |
||
760 | fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); |
||
761 | if (fb_div < fb_div_min) { |
||
762 | unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); |
||
763 | fb_div *= tmp; |
||
764 | ref_div *= tmp; |
||
1963 | serge | 765 | } |
766 | } |
||
767 | |||
5078 | serge | 768 | /* and finally save the result */ |
769 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
770 | *fb_div_p = fb_div / 10; |
||
771 | *frac_fb_div_p = fb_div % 10; |
||
772 | } else { |
||
773 | *fb_div_p = fb_div; |
||
774 | *frac_fb_div_p = 0; |
||
775 | } |
||
776 | |||
777 | *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + |
||
778 | (pll->reference_freq * *frac_fb_div_p)) / |
||
6104 | serge | 779 | (ref_div * post_div * 10); |
1963 | serge | 780 | *ref_div_p = ref_div; |
781 | *post_div_p = post_div; |
||
5078 | serge | 782 | |
783 | DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
||
784 | freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, |
||
785 | ref_div, post_div); |
||
1963 | serge | 786 | } |
787 | |||
788 | /* pre-avivo */ |
||
1123 | serge | 789 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
790 | { |
||
791 | uint64_t mod; |
||
792 | |||
793 | n += d / 2; |
||
794 | |||
795 | mod = do_div(n, d); |
||
796 | return n; |
||
797 | } |
||
798 | |||
1963 | serge | 799 | void radeon_compute_pll_legacy(struct radeon_pll *pll, |
6104 | serge | 800 | uint64_t freq, |
801 | uint32_t *dot_clock_p, |
||
802 | uint32_t *fb_div_p, |
||
803 | uint32_t *frac_fb_div_p, |
||
804 | uint32_t *ref_div_p, |
||
805 | uint32_t *post_div_p) |
||
1123 | serge | 806 | { |
807 | uint32_t min_ref_div = pll->min_ref_div; |
||
808 | uint32_t max_ref_div = pll->max_ref_div; |
||
1404 | serge | 809 | uint32_t min_post_div = pll->min_post_div; |
810 | uint32_t max_post_div = pll->max_post_div; |
||
1123 | serge | 811 | uint32_t min_fractional_feed_div = 0; |
812 | uint32_t max_fractional_feed_div = 0; |
||
813 | uint32_t best_vco = pll->best_vco; |
||
814 | uint32_t best_post_div = 1; |
||
815 | uint32_t best_ref_div = 1; |
||
816 | uint32_t best_feedback_div = 1; |
||
817 | uint32_t best_frac_feedback_div = 0; |
||
818 | uint32_t best_freq = -1; |
||
819 | uint32_t best_error = 0xffffffff; |
||
820 | uint32_t best_vco_diff = 1; |
||
821 | uint32_t post_div; |
||
1963 | serge | 822 | u32 pll_out_min, pll_out_max; |
1123 | serge | 823 | |
1963 | serge | 824 | DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
1123 | serge | 825 | freq = freq * 1000; |
826 | |||
1963 | serge | 827 | if (pll->flags & RADEON_PLL_IS_LCD) { |
828 | pll_out_min = pll->lcd_pll_out_min; |
||
829 | pll_out_max = pll->lcd_pll_out_max; |
||
830 | } else { |
||
831 | pll_out_min = pll->pll_out_min; |
||
832 | pll_out_max = pll->pll_out_max; |
||
833 | } |
||
834 | |||
835 | if (pll_out_min > 64800) |
||
836 | pll_out_min = 64800; |
||
837 | |||
1404 | serge | 838 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
1123 | serge | 839 | min_ref_div = max_ref_div = pll->reference_div; |
840 | else { |
||
841 | while (min_ref_div < max_ref_div-1) { |
||
842 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
||
843 | uint32_t pll_in = pll->reference_freq / mid; |
||
844 | if (pll_in < pll->pll_in_min) |
||
845 | max_ref_div = mid; |
||
846 | else if (pll_in > pll->pll_in_max) |
||
847 | min_ref_div = mid; |
||
848 | else |
||
849 | break; |
||
850 | } |
||
851 | } |
||
852 | |||
1404 | serge | 853 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
854 | min_post_div = max_post_div = pll->post_div; |
||
855 | |||
856 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
1123 | serge | 857 | min_fractional_feed_div = pll->min_frac_feedback_div; |
858 | max_fractional_feed_div = pll->max_frac_feedback_div; |
||
859 | } |
||
860 | |||
1963 | serge | 861 | for (post_div = max_post_div; post_div >= min_post_div; --post_div) { |
1123 | serge | 862 | uint32_t ref_div; |
863 | |||
1404 | serge | 864 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
1123 | serge | 865 | continue; |
866 | |||
867 | /* legacy radeons only have a few post_divs */ |
||
1404 | serge | 868 | if (pll->flags & RADEON_PLL_LEGACY) { |
1123 | serge | 869 | if ((post_div == 5) || |
870 | (post_div == 7) || |
||
871 | (post_div == 9) || |
||
872 | (post_div == 10) || |
||
873 | (post_div == 11) || |
||
874 | (post_div == 13) || |
||
875 | (post_div == 14) || |
||
876 | (post_div == 15)) |
||
877 | continue; |
||
878 | } |
||
879 | |||
880 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
||
881 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
||
882 | uint32_t pll_in = pll->reference_freq / ref_div; |
||
883 | uint32_t min_feed_div = pll->min_feedback_div; |
||
884 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
||
885 | |||
886 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
||
887 | continue; |
||
888 | |||
889 | while (min_feed_div < max_feed_div) { |
||
890 | uint32_t vco; |
||
891 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
||
892 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
||
893 | uint32_t frac_feedback_div; |
||
894 | uint64_t tmp; |
||
895 | |||
896 | feedback_div = (min_feed_div + max_feed_div) / 2; |
||
897 | |||
898 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
||
899 | vco = radeon_div(tmp, ref_div); |
||
900 | |||
1963 | serge | 901 | if (vco < pll_out_min) { |
1123 | serge | 902 | min_feed_div = feedback_div + 1; |
903 | continue; |
||
1963 | serge | 904 | } else if (vco > pll_out_max) { |
1123 | serge | 905 | max_feed_div = feedback_div; |
906 | continue; |
||
907 | } |
||
908 | |||
909 | while (min_frac_feed_div < max_frac_feed_div) { |
||
910 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
||
911 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
||
912 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
||
913 | current_freq = radeon_div(tmp, ref_div * post_div); |
||
914 | |||
1404 | serge | 915 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
1963 | serge | 916 | if (freq < current_freq) |
917 | error = 0xffffffff; |
||
918 | else |
||
6104 | serge | 919 | error = freq - current_freq; |
1179 | serge | 920 | } else |
6104 | serge | 921 | error = abs(current_freq - freq); |
1123 | serge | 922 | vco_diff = abs(vco - best_vco); |
923 | |||
924 | if ((best_vco == 0 && error < best_error) || |
||
925 | (best_vco != 0 && |
||
1963 | serge | 926 | ((best_error > 100 && error < best_error - 100) || |
1123 | serge | 927 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
928 | best_post_div = post_div; |
||
929 | best_ref_div = ref_div; |
||
930 | best_feedback_div = feedback_div; |
||
931 | best_frac_feedback_div = frac_feedback_div; |
||
932 | best_freq = current_freq; |
||
933 | best_error = error; |
||
934 | best_vco_diff = vco_diff; |
||
935 | } else if (current_freq == freq) { |
||
936 | if (best_freq == -1) { |
||
937 | best_post_div = post_div; |
||
938 | best_ref_div = ref_div; |
||
939 | best_feedback_div = feedback_div; |
||
940 | best_frac_feedback_div = frac_feedback_div; |
||
941 | best_freq = current_freq; |
||
942 | best_error = error; |
||
943 | best_vco_diff = vco_diff; |
||
1404 | serge | 944 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
945 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
||
946 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
||
947 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
||
948 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
||
949 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
||
1123 | serge | 950 | best_post_div = post_div; |
951 | best_ref_div = ref_div; |
||
952 | best_feedback_div = feedback_div; |
||
953 | best_frac_feedback_div = frac_feedback_div; |
||
954 | best_freq = current_freq; |
||
955 | best_error = error; |
||
956 | best_vco_diff = vco_diff; |
||
957 | } |
||
958 | } |
||
959 | if (current_freq < freq) |
||
960 | min_frac_feed_div = frac_feedback_div + 1; |
||
961 | else |
||
962 | max_frac_feed_div = frac_feedback_div; |
||
963 | } |
||
964 | if (current_freq < freq) |
||
965 | min_feed_div = feedback_div + 1; |
||
966 | else |
||
967 | max_feed_div = feedback_div; |
||
968 | } |
||
969 | } |
||
970 | } |
||
971 | |||
972 | *dot_clock_p = best_freq / 10000; |
||
973 | *fb_div_p = best_feedback_div; |
||
974 | *frac_fb_div_p = best_frac_feedback_div; |
||
975 | *ref_div_p = best_ref_div; |
||
976 | *post_div_p = best_post_div; |
||
1963 | serge | 977 | DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n", |
978 | (long long)freq, |
||
979 | best_freq / 1000, best_feedback_div, best_frac_feedback_div, |
||
980 | best_ref_div, best_post_div); |
||
1123 | serge | 981 | |
1430 | serge | 982 | } |
983 | |||
1123 | serge | 984 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
985 | { |
||
986 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
987 | |||
5078 | serge | 988 | if (radeon_fb->obj) { |
989 | drm_gem_object_unreference_unlocked(radeon_fb->obj); |
||
990 | } |
||
1123 | serge | 991 | drm_framebuffer_cleanup(fb); |
992 | kfree(radeon_fb); |
||
993 | } |
||
994 | |||
995 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
||
6104 | serge | 996 | struct drm_file *file_priv, |
997 | unsigned int *handle) |
||
1123 | serge | 998 | { |
6104 | serge | 999 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
1123 | serge | 1000 | |
1001 | return NULL; |
||
1002 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
||
1003 | } |
||
1004 | |||
1005 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
||
1006 | .destroy = radeon_user_framebuffer_destroy, |
||
6104 | serge | 1007 | .create_handle = radeon_user_framebuffer_create_handle, |
1123 | serge | 1008 | }; |
1009 | |||
2997 | Serge | 1010 | int |
1963 | serge | 1011 | radeon_framebuffer_init(struct drm_device *dev, |
1012 | struct radeon_framebuffer *rfb, |
||
2997 | Serge | 1013 | struct drm_mode_fb_cmd2 *mode_cmd, |
6104 | serge | 1014 | struct drm_gem_object *obj) |
1123 | serge | 1015 | { |
2997 | Serge | 1016 | int ret; |
1963 | serge | 1017 | rfb->obj = obj; |
3764 | Serge | 1018 | drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); |
2997 | Serge | 1019 | ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs); |
1020 | if (ret) { |
||
1021 | rfb->obj = NULL; |
||
1022 | return ret; |
||
1023 | } |
||
1024 | return 0; |
||
1123 | serge | 1025 | } |
1026 | |||
1027 | |||
1028 | |||
1029 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
||
1963 | serge | 1030 | // .fb_create = radeon_user_framebuffer_create, |
1031 | // .output_poll_changed = radeon_output_poll_changed |
||
1123 | serge | 1032 | }; |
1033 | |||
1179 | serge | 1034 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
1035 | { { 0, "driver" }, |
||
1036 | { 1, "bios" }, |
||
1037 | }; |
||
1038 | |||
1039 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
||
1040 | { { TV_STD_NTSC, "ntsc" }, |
||
1041 | { TV_STD_PAL, "pal" }, |
||
1042 | { TV_STD_PAL_M, "pal-m" }, |
||
1043 | { TV_STD_PAL_60, "pal-60" }, |
||
1044 | { TV_STD_NTSC_J, "ntsc-j" }, |
||
1045 | { TV_STD_SCART_PAL, "scart-pal" }, |
||
1046 | { TV_STD_PAL_CN, "pal-cn" }, |
||
1047 | { TV_STD_SECAM, "secam" }, |
||
1048 | }; |
||
1049 | |||
1963 | serge | 1050 | static struct drm_prop_enum_list radeon_underscan_enum_list[] = |
1051 | { { UNDERSCAN_OFF, "off" }, |
||
1052 | { UNDERSCAN_ON, "on" }, |
||
1053 | { UNDERSCAN_AUTO, "auto" }, |
||
1054 | }; |
||
1055 | |||
5078 | serge | 1056 | static struct drm_prop_enum_list radeon_audio_enum_list[] = |
1057 | { { RADEON_AUDIO_DISABLE, "off" }, |
||
1058 | { RADEON_AUDIO_ENABLE, "on" }, |
||
1059 | { RADEON_AUDIO_AUTO, "auto" }, |
||
1060 | }; |
||
1061 | |||
1062 | /* XXX support different dither options? spatial, temporal, both, etc. */ |
||
1063 | static struct drm_prop_enum_list radeon_dither_enum_list[] = |
||
1064 | { { RADEON_FMT_DITHER_DISABLE, "off" }, |
||
1065 | { RADEON_FMT_DITHER_ENABLE, "on" }, |
||
1066 | }; |
||
1067 | |||
6104 | serge | 1068 | static struct drm_prop_enum_list radeon_output_csc_enum_list[] = |
1069 | { { RADEON_OUTPUT_CSC_BYPASS, "bypass" }, |
||
1070 | { RADEON_OUTPUT_CSC_TVRGB, "tvrgb" }, |
||
1071 | { RADEON_OUTPUT_CSC_YCBCR601, "ycbcr601" }, |
||
1072 | { RADEON_OUTPUT_CSC_YCBCR709, "ycbcr709" }, |
||
1073 | }; |
||
1074 | |||
1404 | serge | 1075 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
1123 | serge | 1076 | { |
2997 | Serge | 1077 | int sz; |
1125 | serge | 1078 | |
1179 | serge | 1079 | if (rdev->is_atom_bios) { |
1080 | rdev->mode_info.coherent_mode_property = |
||
2997 | Serge | 1081 | drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1); |
1179 | serge | 1082 | if (!rdev->mode_info.coherent_mode_property) |
1083 | return -ENOMEM; |
||
1084 | } |
||
1085 | |||
1086 | if (!ASIC_IS_AVIVO(rdev)) { |
||
1087 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
||
1088 | rdev->mode_info.tmds_pll_property = |
||
2997 | Serge | 1089 | drm_property_create_enum(rdev->ddev, 0, |
1090 | "tmds_pll", |
||
1091 | radeon_tmds_pll_enum_list, sz); |
||
1179 | serge | 1092 | } |
1093 | |||
1094 | rdev->mode_info.load_detect_property = |
||
2997 | Serge | 1095 | drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1); |
1179 | serge | 1096 | if (!rdev->mode_info.load_detect_property) |
1097 | return -ENOMEM; |
||
1098 | |||
1099 | drm_mode_create_scaling_mode_property(rdev->ddev); |
||
1100 | |||
1101 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
||
1102 | rdev->mode_info.tv_std_property = |
||
2997 | Serge | 1103 | drm_property_create_enum(rdev->ddev, 0, |
1104 | "tv standard", |
||
1105 | radeon_tv_std_enum_list, sz); |
||
1179 | serge | 1106 | |
1963 | serge | 1107 | sz = ARRAY_SIZE(radeon_underscan_enum_list); |
1108 | rdev->mode_info.underscan_property = |
||
2997 | Serge | 1109 | drm_property_create_enum(rdev->ddev, 0, |
1110 | "underscan", |
||
1111 | radeon_underscan_enum_list, sz); |
||
1963 | serge | 1112 | |
1113 | rdev->mode_info.underscan_hborder_property = |
||
2997 | Serge | 1114 | drm_property_create_range(rdev->ddev, 0, |
1115 | "underscan hborder", 0, 128); |
||
1963 | serge | 1116 | if (!rdev->mode_info.underscan_hborder_property) |
1117 | return -ENOMEM; |
||
1118 | |||
1119 | rdev->mode_info.underscan_vborder_property = |
||
2997 | Serge | 1120 | drm_property_create_range(rdev->ddev, 0, |
1121 | "underscan vborder", 0, 128); |
||
1963 | serge | 1122 | if (!rdev->mode_info.underscan_vborder_property) |
1123 | return -ENOMEM; |
||
1124 | |||
5078 | serge | 1125 | sz = ARRAY_SIZE(radeon_audio_enum_list); |
1126 | rdev->mode_info.audio_property = |
||
1127 | drm_property_create_enum(rdev->ddev, 0, |
||
1128 | "audio", |
||
1129 | radeon_audio_enum_list, sz); |
||
1130 | |||
1131 | sz = ARRAY_SIZE(radeon_dither_enum_list); |
||
1132 | rdev->mode_info.dither_property = |
||
1133 | drm_property_create_enum(rdev->ddev, 0, |
||
1134 | "dither", |
||
1135 | radeon_dither_enum_list, sz); |
||
1136 | |||
6104 | serge | 1137 | sz = ARRAY_SIZE(radeon_output_csc_enum_list); |
1138 | rdev->mode_info.output_csc_property = |
||
1139 | drm_property_create_enum(rdev->ddev, 0, |
||
1140 | "output_csc", |
||
1141 | radeon_output_csc_enum_list, sz); |
||
1142 | |||
1179 | serge | 1143 | return 0; |
1144 | } |
||
1145 | |||
1963 | serge | 1146 | void radeon_update_display_priority(struct radeon_device *rdev) |
1147 | { |
||
1148 | /* adjustment options for the display watermarks */ |
||
1149 | if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) { |
||
1150 | /* set display priority to high for r3xx, rv515 chips |
||
1151 | * this avoids flickering due to underflow to the |
||
1152 | * display controllers during heavy acceleration. |
||
1153 | * Don't force high on rs4xx igp chips as it seems to |
||
1154 | * affect the sound card. See kernel bug 15982. |
||
1155 | */ |
||
1156 | if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) && |
||
1157 | !(rdev->flags & RADEON_IS_IGP)) |
||
1158 | rdev->disp_priority = 2; |
||
1159 | else |
||
1160 | rdev->disp_priority = 0; |
||
1161 | } else |
||
1162 | rdev->disp_priority = radeon_disp_priority; |
||
1163 | |||
1164 | } |
||
1165 | |||
2997 | Serge | 1166 | /* |
1167 | * Allocate hdmi structs and determine register offsets |
||
1168 | */ |
||
1169 | static void radeon_afmt_init(struct radeon_device *rdev) |
||
1170 | { |
||
1171 | int i; |
||
1172 | |||
1173 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) |
||
1174 | rdev->mode_info.afmt[i] = NULL; |
||
1175 | |||
5078 | serge | 1176 | if (ASIC_IS_NODCE(rdev)) { |
1177 | /* nothing to do */ |
||
2997 | Serge | 1178 | } else if (ASIC_IS_DCE4(rdev)) { |
5078 | serge | 1179 | static uint32_t eg_offsets[] = { |
1180 | EVERGREEN_CRTC0_REGISTER_OFFSET, |
||
1181 | EVERGREEN_CRTC1_REGISTER_OFFSET, |
||
1182 | EVERGREEN_CRTC2_REGISTER_OFFSET, |
||
1183 | EVERGREEN_CRTC3_REGISTER_OFFSET, |
||
1184 | EVERGREEN_CRTC4_REGISTER_OFFSET, |
||
1185 | EVERGREEN_CRTC5_REGISTER_OFFSET, |
||
1186 | 0x13830 - 0x7030, |
||
1187 | }; |
||
1188 | int num_afmt; |
||
1189 | |||
1190 | /* DCE8 has 7 audio blocks tied to DIG encoders */ |
||
1191 | /* DCE6 has 6 audio blocks tied to DIG encoders */ |
||
2997 | Serge | 1192 | /* DCE4/5 has 6 audio blocks tied to DIG encoders */ |
1193 | /* DCE4.1 has 2 audio blocks tied to DIG encoders */ |
||
5078 | serge | 1194 | if (ASIC_IS_DCE8(rdev)) |
1195 | num_afmt = 7; |
||
1196 | else if (ASIC_IS_DCE6(rdev)) |
||
1197 | num_afmt = 6; |
||
1198 | else if (ASIC_IS_DCE5(rdev)) |
||
1199 | num_afmt = 6; |
||
1200 | else if (ASIC_IS_DCE41(rdev)) |
||
1201 | num_afmt = 2; |
||
1202 | else /* DCE4 */ |
||
1203 | num_afmt = 6; |
||
1204 | |||
1205 | BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets)); |
||
1206 | for (i = 0; i < num_afmt; i++) { |
||
1207 | rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1208 | if (rdev->mode_info.afmt[i]) { |
||
1209 | rdev->mode_info.afmt[i]->offset = eg_offsets[i]; |
||
1210 | rdev->mode_info.afmt[i]->id = i; |
||
2997 | Serge | 1211 | } |
1212 | } |
||
1213 | } else if (ASIC_IS_DCE3(rdev)) { |
||
1214 | /* DCE3.x has 2 audio blocks tied to DIG encoders */ |
||
1215 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1216 | if (rdev->mode_info.afmt[0]) { |
||
1217 | rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0; |
||
1218 | rdev->mode_info.afmt[0]->id = 0; |
||
1219 | } |
||
1220 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1221 | if (rdev->mode_info.afmt[1]) { |
||
1222 | rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1; |
||
1223 | rdev->mode_info.afmt[1]->id = 1; |
||
1224 | } |
||
1225 | } else if (ASIC_IS_DCE2(rdev)) { |
||
1226 | /* DCE2 has at least 1 routable audio block */ |
||
1227 | rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1228 | if (rdev->mode_info.afmt[0]) { |
||
1229 | rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0; |
||
1230 | rdev->mode_info.afmt[0]->id = 0; |
||
1231 | } |
||
1232 | /* r6xx has 2 routable audio blocks */ |
||
1233 | if (rdev->family >= CHIP_R600) { |
||
1234 | rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL); |
||
1235 | if (rdev->mode_info.afmt[1]) { |
||
1236 | rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1; |
||
1237 | rdev->mode_info.afmt[1]->id = 1; |
||
1238 | } |
||
1239 | } |
||
1240 | } |
||
1241 | } |
||
1242 | |||
1243 | static void radeon_afmt_fini(struct radeon_device *rdev) |
||
1244 | { |
||
1245 | int i; |
||
1246 | |||
1247 | for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) { |
||
1248 | kfree(rdev->mode_info.afmt[i]); |
||
1249 | rdev->mode_info.afmt[i] = NULL; |
||
1250 | } |
||
1251 | } |
||
1252 | |||
1179 | serge | 1253 | int radeon_modeset_init(struct radeon_device *rdev) |
1254 | { |
||
1430 | serge | 1255 | int i; |
1123 | serge | 1256 | int ret; |
1257 | |||
5078 | serge | 1258 | ENTER(); |
1259 | |||
1123 | serge | 1260 | drm_mode_config_init(rdev->ddev); |
1261 | rdev->mode_info.mode_config_initialized = true; |
||
1262 | |||
2997 | Serge | 1263 | rdev->ddev->mode_config.funcs = &radeon_mode_funcs; |
1123 | serge | 1264 | |
1963 | serge | 1265 | if (ASIC_IS_DCE5(rdev)) { |
1266 | rdev->ddev->mode_config.max_width = 16384; |
||
1267 | rdev->ddev->mode_config.max_height = 16384; |
||
1268 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
1123 | serge | 1269 | rdev->ddev->mode_config.max_width = 8192; |
1270 | rdev->ddev->mode_config.max_height = 8192; |
||
1271 | } else { |
||
1272 | rdev->ddev->mode_config.max_width = 4096; |
||
1273 | rdev->ddev->mode_config.max_height = 4096; |
||
1274 | } |
||
1275 | |||
2997 | Serge | 1276 | rdev->ddev->mode_config.preferred_depth = 24; |
1277 | rdev->ddev->mode_config.prefer_shadow = 1; |
||
1278 | |||
1123 | serge | 1279 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
1280 | |||
1179 | serge | 1281 | ret = radeon_modeset_create_props(rdev); |
1282 | if (ret) { |
||
1283 | return ret; |
||
1284 | } |
||
1221 | serge | 1285 | |
1963 | serge | 1286 | /* init i2c buses */ |
1287 | radeon_i2c_init(rdev); |
||
1288 | |||
1430 | serge | 1289 | /* check combios for a valid hardcoded EDID - Sun servers */ |
1290 | if (!rdev->is_atom_bios) { |
||
1291 | /* check for hardcoded EDID in BIOS */ |
||
1292 | radeon_combios_check_hardcoded_edid(rdev); |
||
1293 | } |
||
1294 | |||
1221 | serge | 1295 | /* allocate crtcs */ |
1430 | serge | 1296 | for (i = 0; i < rdev->num_crtc; i++) { |
1123 | serge | 1297 | radeon_crtc_init(rdev->ddev, i); |
1298 | } |
||
1299 | |||
1300 | /* okay we should have all the bios connectors */ |
||
1301 | ret = radeon_setup_enc_conn(rdev->ddev); |
||
1302 | if (!ret) { |
||
1303 | return ret; |
||
1304 | } |
||
1963 | serge | 1305 | |
2997 | Serge | 1306 | /* init dig PHYs, disp eng pll */ |
1307 | if (rdev->is_atom_bios) { |
||
1963 | serge | 1308 | radeon_atom_encoder_init(rdev); |
2997 | Serge | 1309 | radeon_atom_disp_eng_pll_init(rdev); |
1310 | } |
||
1963 | serge | 1311 | |
1404 | serge | 1312 | /* initialize hpd */ |
1963 | serge | 1313 | // radeon_hpd_init(rdev); |
1314 | |||
2997 | Serge | 1315 | /* setup afmt */ |
5078 | serge | 1316 | radeon_afmt_init(rdev); |
2997 | Serge | 1317 | |
1963 | serge | 1318 | radeon_fbdev_init(rdev); |
1319 | |||
5078 | serge | 1320 | LEAVE(); |
1321 | |||
1123 | serge | 1322 | return 0; |
1323 | } |
||
1324 | |||
1325 | void radeon_modeset_fini(struct radeon_device *rdev) |
||
1326 | { |
||
1430 | serge | 1327 | kfree(rdev->mode_info.bios_hardcoded_edid); |
1328 | |||
1123 | serge | 1329 | if (rdev->mode_info.mode_config_initialized) { |
2997 | Serge | 1330 | // radeon_afmt_fini(rdev); |
1963 | serge | 1331 | // drm_kms_helper_poll_fini(rdev->ddev); |
1332 | // radeon_hpd_fini(rdev); |
||
3764 | Serge | 1333 | // drm_mode_config_cleanup(rdev->ddev); |
1123 | serge | 1334 | rdev->mode_info.mode_config_initialized = false; |
1335 | } |
||
1963 | serge | 1336 | /* free i2c buses */ |
1337 | radeon_i2c_fini(rdev); |
||
1123 | serge | 1338 | } |
1339 | |||
2997 | Serge | 1340 | static bool is_hdtv_mode(const struct drm_display_mode *mode) |
1963 | serge | 1341 | { |
1342 | /* try and guess if this is a tv or a monitor */ |
||
1343 | if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ |
||
1344 | (mode->vdisplay == 576) || /* 576p */ |
||
1345 | (mode->vdisplay == 720) || /* 720p */ |
||
1346 | (mode->vdisplay == 1080)) /* 1080p */ |
||
1347 | return true; |
||
1348 | else |
||
1349 | return false; |
||
1350 | } |
||
1351 | |||
1179 | serge | 1352 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
2997 | Serge | 1353 | const struct drm_display_mode *mode, |
1179 | serge | 1354 | struct drm_display_mode *adjusted_mode) |
1123 | serge | 1355 | { |
1179 | serge | 1356 | struct drm_device *dev = crtc->dev; |
1963 | serge | 1357 | struct radeon_device *rdev = dev->dev_private; |
1179 | serge | 1358 | struct drm_encoder *encoder; |
1123 | serge | 1359 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1179 | serge | 1360 | struct radeon_encoder *radeon_encoder; |
1963 | serge | 1361 | struct drm_connector *connector; |
1362 | struct radeon_connector *radeon_connector; |
||
1179 | serge | 1363 | bool first = true; |
1963 | serge | 1364 | u32 src_v = 1, dst_v = 1; |
1365 | u32 src_h = 1, dst_h = 1; |
||
1123 | serge | 1366 | |
1963 | serge | 1367 | radeon_crtc->h_border = 0; |
1368 | radeon_crtc->v_border = 0; |
||
1369 | |||
1179 | serge | 1370 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
1371 | if (encoder->crtc != crtc) |
||
1372 | continue; |
||
1963 | serge | 1373 | radeon_encoder = to_radeon_encoder(encoder); |
1374 | connector = radeon_get_connector_for_encoder(encoder); |
||
1375 | radeon_connector = to_radeon_connector(connector); |
||
1376 | |||
1179 | serge | 1377 | if (first) { |
1404 | serge | 1378 | /* set scaling */ |
1379 | if (radeon_encoder->rmx_type == RMX_OFF) |
||
1380 | radeon_crtc->rmx_type = RMX_OFF; |
||
1381 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
||
1382 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
||
1179 | serge | 1383 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1404 | serge | 1384 | else |
1385 | radeon_crtc->rmx_type = RMX_OFF; |
||
1386 | /* copy native mode */ |
||
1179 | serge | 1387 | memcpy(&radeon_crtc->native_mode, |
1388 | &radeon_encoder->native_mode, |
||
1268 | serge | 1389 | sizeof(struct drm_display_mode)); |
1963 | serge | 1390 | src_v = crtc->mode.vdisplay; |
1391 | dst_v = radeon_crtc->native_mode.vdisplay; |
||
1392 | src_h = crtc->mode.hdisplay; |
||
1393 | dst_h = radeon_crtc->native_mode.hdisplay; |
||
1394 | |||
1395 | /* fix up for overscan on hdmi */ |
||
1396 | if (ASIC_IS_AVIVO(rdev) && |
||
1397 | (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && |
||
1398 | ((radeon_encoder->underscan_type == UNDERSCAN_ON) || |
||
1399 | ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) && |
||
5078 | serge | 1400 | drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
1963 | serge | 1401 | is_hdtv_mode(mode)))) { |
1402 | if (radeon_encoder->underscan_hborder != 0) |
||
1403 | radeon_crtc->h_border = radeon_encoder->underscan_hborder; |
||
1404 | else |
||
1405 | radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; |
||
1406 | if (radeon_encoder->underscan_vborder != 0) |
||
1407 | radeon_crtc->v_border = radeon_encoder->underscan_vborder; |
||
1408 | else |
||
1409 | radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; |
||
1410 | radeon_crtc->rmx_type = RMX_FULL; |
||
1411 | src_v = crtc->mode.vdisplay; |
||
1412 | dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); |
||
1413 | src_h = crtc->mode.hdisplay; |
||
1414 | dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); |
||
1415 | } |
||
1179 | serge | 1416 | first = false; |
1417 | } else { |
||
1418 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
||
1419 | /* WARNING: Right now this can't happen but |
||
1420 | * in the future we need to check that scaling |
||
1963 | serge | 1421 | * are consistent across different encoder |
1179 | serge | 1422 | * (ie all encoder can work with the same |
1423 | * scaling). |
||
1424 | */ |
||
1963 | serge | 1425 | DRM_ERROR("Scaling not consistent across encoder.\n"); |
1179 | serge | 1426 | return false; |
1427 | } |
||
1123 | serge | 1428 | } |
1429 | } |
||
1179 | serge | 1430 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1221 | serge | 1431 | fixed20_12 a, b; |
1963 | serge | 1432 | a.full = dfixed_const(src_v); |
1433 | b.full = dfixed_const(dst_v); |
||
1434 | radeon_crtc->vsc.full = dfixed_div(a, b); |
||
1435 | a.full = dfixed_const(src_h); |
||
1436 | b.full = dfixed_const(dst_h); |
||
1437 | radeon_crtc->hsc.full = dfixed_div(a, b); |
||
1123 | serge | 1438 | } else { |
1963 | serge | 1439 | radeon_crtc->vsc.full = dfixed_const(1); |
1440 | radeon_crtc->hsc.full = dfixed_const(1); |
||
1123 | serge | 1441 | } |
1179 | serge | 1442 | return true; |
1123 | serge | 1443 | } |
1963 | serge | 1444 | |
1445 | /* |
||
5078 | serge | 1446 | * Retrieve current video scanout position of crtc on a given gpu, and |
1447 | * an optional accurate timestamp of when query happened. |
||
1963 | serge | 1448 | * |
1449 | * \param dev Device to query. |
||
1450 | * \param crtc Crtc to query. |
||
5078 | serge | 1451 | * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). |
1963 | serge | 1452 | * \param *vpos Location where vertical scanout position should be stored. |
1453 | * \param *hpos Location where horizontal scanout position should go. |
||
5078 | serge | 1454 | * \param *stime Target location for timestamp taken immediately before |
1455 | * scanout position query. Can be NULL to skip timestamp. |
||
1456 | * \param *etime Target location for timestamp taken immediately after |
||
1457 | * scanout position query. Can be NULL to skip timestamp. |
||
1963 | serge | 1458 | * |
1459 | * Returns vpos as a positive number while in active scanout area. |
||
1460 | * Returns vpos as a negative number inside vblank, counting the number |
||
1461 | * of scanlines to go until end of vblank, e.g., -1 means "one scanline |
||
1462 | * until start of active scanout / end of vblank." |
||
1463 | * |
||
1464 | * \return Flags, or'ed together as follows: |
||
1465 | * |
||
1466 | * DRM_SCANOUTPOS_VALID = Query successful. |
||
1467 | * DRM_SCANOUTPOS_INVBL = Inside vblank. |
||
1468 | * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of |
||
1469 | * this flag means that returned position may be offset by a constant but |
||
1470 | * unknown small number of scanlines wrt. real scanout position. |
||
1471 | * |
||
1472 | */ |
||
6104 | serge | 1473 | int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, |
1474 | unsigned int flags, int *vpos, int *hpos, |
||
1475 | ktime_t *stime, ktime_t *etime, |
||
1476 | const struct drm_display_mode *mode) |
||
1963 | serge | 1477 | { |
1478 | u32 stat_crtc = 0, vbl = 0, position = 0; |
||
1479 | int vbl_start, vbl_end, vtotal, ret = 0; |
||
1480 | bool in_vbl = true; |
||
1481 | |||
1482 | struct radeon_device *rdev = dev->dev_private; |
||
1483 | |||
6104 | serge | 1484 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
1485 | |||
1486 | /* Get optional system timestamp before query. */ |
||
1487 | if (stime) |
||
1488 | *stime = ktime_get(); |
||
1489 | |||
1963 | serge | 1490 | if (ASIC_IS_DCE4(rdev)) { |
6104 | serge | 1491 | if (pipe == 0) { |
1963 | serge | 1492 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1493 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
||
1494 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1495 | EVERGREEN_CRTC0_REGISTER_OFFSET); |
||
1496 | ret |= DRM_SCANOUTPOS_VALID; |
||
1497 | } |
||
6104 | serge | 1498 | if (pipe == 1) { |
1963 | serge | 1499 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1500 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
||
1501 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1502 | EVERGREEN_CRTC1_REGISTER_OFFSET); |
||
1503 | ret |= DRM_SCANOUTPOS_VALID; |
||
1504 | } |
||
6104 | serge | 1505 | if (pipe == 2) { |
1963 | serge | 1506 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1507 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
||
1508 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1509 | EVERGREEN_CRTC2_REGISTER_OFFSET); |
||
1510 | ret |= DRM_SCANOUTPOS_VALID; |
||
1511 | } |
||
6104 | serge | 1512 | if (pipe == 3) { |
1963 | serge | 1513 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1514 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
1515 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1516 | EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
1517 | ret |= DRM_SCANOUTPOS_VALID; |
||
1518 | } |
||
6104 | serge | 1519 | if (pipe == 4) { |
1963 | serge | 1520 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1521 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
||
1522 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1523 | EVERGREEN_CRTC4_REGISTER_OFFSET); |
||
1524 | ret |= DRM_SCANOUTPOS_VALID; |
||
1525 | } |
||
6104 | serge | 1526 | if (pipe == 5) { |
1963 | serge | 1527 | vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + |
1528 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1529 | position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + |
||
1530 | EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
1531 | ret |= DRM_SCANOUTPOS_VALID; |
||
1532 | } |
||
1533 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
6104 | serge | 1534 | if (pipe == 0) { |
1963 | serge | 1535 | vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); |
1536 | position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); |
||
1537 | ret |= DRM_SCANOUTPOS_VALID; |
||
1538 | } |
||
6104 | serge | 1539 | if (pipe == 1) { |
1963 | serge | 1540 | vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); |
1541 | position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); |
||
1542 | ret |= DRM_SCANOUTPOS_VALID; |
||
1543 | } |
||
1544 | } else { |
||
1545 | /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ |
||
6104 | serge | 1546 | if (pipe == 0) { |
1963 | serge | 1547 | /* Assume vbl_end == 0, get vbl_start from |
1548 | * upper 16 bits. |
||
1549 | */ |
||
1550 | vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) & |
||
1551 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
||
1552 | /* Only retrieve vpos from upper 16 bits, set hpos == 0. */ |
||
1553 | position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
||
1554 | stat_crtc = RREG32(RADEON_CRTC_STATUS); |
||
1555 | if (!(stat_crtc & 1)) |
||
1556 | in_vbl = false; |
||
1557 | |||
1558 | ret |= DRM_SCANOUTPOS_VALID; |
||
1559 | } |
||
6104 | serge | 1560 | if (pipe == 1) { |
1963 | serge | 1561 | vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & |
1562 | RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; |
||
1563 | position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; |
||
1564 | stat_crtc = RREG32(RADEON_CRTC2_STATUS); |
||
1565 | if (!(stat_crtc & 1)) |
||
1566 | in_vbl = false; |
||
1567 | |||
1568 | ret |= DRM_SCANOUTPOS_VALID; |
||
1569 | } |
||
1570 | } |
||
1571 | |||
6104 | serge | 1572 | /* Get optional system timestamp after query. */ |
1573 | if (etime) |
||
1574 | *etime = ktime_get(); |
||
1575 | |||
1576 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ |
||
1577 | |||
1963 | serge | 1578 | /* Decode into vertical and horizontal scanout position. */ |
1579 | *vpos = position & 0x1fff; |
||
1580 | *hpos = (position >> 16) & 0x1fff; |
||
1581 | |||
1582 | /* Valid vblank area boundaries from gpu retrieved? */ |
||
1583 | if (vbl > 0) { |
||
1584 | /* Yes: Decode. */ |
||
1585 | ret |= DRM_SCANOUTPOS_ACCURATE; |
||
1586 | vbl_start = vbl & 0x1fff; |
||
1587 | vbl_end = (vbl >> 16) & 0x1fff; |
||
1588 | } |
||
1589 | else { |
||
1590 | /* No: Fake something reasonable which gives at least ok results. */ |
||
6104 | serge | 1591 | vbl_start = mode->crtc_vdisplay; |
1963 | serge | 1592 | vbl_end = 0; |
1593 | } |
||
1594 | |||
1595 | /* Test scanout position against vblank region. */ |
||
1596 | if ((*vpos < vbl_start) && (*vpos >= vbl_end)) |
||
1597 | in_vbl = false; |
||
1598 | |||
1599 | /* Check if inside vblank area and apply corrective offsets: |
||
1600 | * vpos will then be >=0 in video scanout area, but negative |
||
1601 | * within vblank area, counting down the number of lines until |
||
1602 | * start of scanout. |
||
1603 | */ |
||
1604 | |||
1605 | /* Inside "upper part" of vblank area? Apply corrective offset if so: */ |
||
1606 | if (in_vbl && (*vpos >= vbl_start)) { |
||
6104 | serge | 1607 | vtotal = mode->crtc_vtotal; |
1963 | serge | 1608 | *vpos = *vpos - vtotal; |
1609 | } |
||
1610 | |||
1611 | /* Correct for shifted end of vbl at vbl_end. */ |
||
1612 | *vpos = *vpos - vbl_end; |
||
1613 | |||
1614 | /* In vblank? */ |
||
1615 | if (in_vbl) |
||
5271 | serge | 1616 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
1963 | serge | 1617 | |
5078 | serge | 1618 | /* Is vpos outside nominal vblank area, but less than |
1619 | * 1/100 of a frame height away from start of vblank? |
||
1620 | * If so, assume this isn't a massively delayed vblank |
||
1621 | * interrupt, but a vblank interrupt that fired a few |
||
1622 | * microseconds before true start of vblank. Compensate |
||
1623 | * by adding a full frame duration to the final timestamp. |
||
1624 | * Happens, e.g., on ATI R500, R600. |
||
1625 | * |
||
1626 | * We only do this if DRM_CALLED_FROM_VBLIRQ. |
||
1627 | */ |
||
1628 | if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) { |
||
6104 | serge | 1629 | vbl_start = mode->crtc_vdisplay; |
1630 | vtotal = mode->crtc_vtotal; |
||
5078 | serge | 1631 | |
1632 | if (vbl_start - *vpos < vtotal / 100) { |
||
1633 | *vpos -= vtotal; |
||
1634 | |||
1635 | /* Signal this correction as "applied". */ |
||
1636 | ret |= 0x8; |
||
1637 | } |
||
1638 | } |
||
1639 | |||
1963 | serge | 1640 | return ret; |
1641 | }>>>>>>>>>>>>>>>>>>>>>>=>>>>>=>>>>>><>><>><>>>>>><>><>><>><>><>><>>><>><>><>>><>><>><>>><>><>><>> |