WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_display.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
1123	serge	28	#include "radeon.h"
		29
		30	#include "atom.h"
1963	serge	31	#include
1123	serge	32
2997	Serge	33	#include
		34	#include
1123	serge	35
		36	static void avivo_crtc_load_lut(struct drm_crtc *crtc)
		37	{
		38	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		39	struct drm_device *dev = crtc->dev;
		40	struct radeon_device *rdev = dev->dev_private;
		41	int i;
		42
1963	serge	43	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1123	serge	44	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
		45
		46	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		47	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		48	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		49
		50	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		51	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		52	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		53
		54	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
		55	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
		56	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
		57
		58	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
		59	for (i = 0; i < 256; i++) {
		60	WREG32(AVIVO_DC_LUT_30_COLOR,
		61	(radeon_crtc->lut_r[i] << 20) \|
		62	(radeon_crtc->lut_g[i] << 10) \|
		63	(radeon_crtc->lut_b[i] << 0));
		64	}
		65
		66	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
		67	}
		68
1963	serge	69	static void dce4_crtc_load_lut(struct drm_crtc *crtc)
1430	serge	70	{
		71	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		72	struct drm_device *dev = crtc->dev;
		73	struct radeon_device *rdev = dev->dev_private;
		74	int i;
		75
1963	serge	76	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1430	serge	77	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		78
		79	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		80	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		81	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		82
		83	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		84	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		85	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		86
1963	serge	87	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		88	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
1430	serge	89
1963	serge	90	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
1430	serge	91	for (i = 0; i < 256; i++) {
1963	serge	92	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
1430	serge	93	(radeon_crtc->lut_r[i] << 20) \|
		94	(radeon_crtc->lut_g[i] << 10) \|
		95	(radeon_crtc->lut_b[i] << 0));
		96	}
		97	}
		98
1963	serge	99	static void dce5_crtc_load_lut(struct drm_crtc *crtc)
		100	{
		101	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		102	struct drm_device *dev = crtc->dev;
		103	struct radeon_device *rdev = dev->dev_private;
		104	int i;
		105
		106	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
		107
		108	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		109	(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) \|
		110	NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
		111	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
		112	NI_GRPH_PRESCALE_BYPASS);
		113	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
		114	NI_OVL_PRESCALE_BYPASS);
		115	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
		116	(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) \|
		117	NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
		118
		119	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		120
		121	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		122	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		123	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		124
		125	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		126	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		127	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		128
		129	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		130	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
		131
		132	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
		133	for (i = 0; i < 256; i++) {
		134	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
		135	(radeon_crtc->lut_r[i] << 20) \|
		136	(radeon_crtc->lut_g[i] << 10) \|
		137	(radeon_crtc->lut_b[i] << 0));
		138	}
		139
		140	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
		141	(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		142	NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		143	NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		144	NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
		145	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
		146	(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) \|
		147	NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
		148	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
		149	(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) \|
		150	NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
		151	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		152	(NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) \|
		153	NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
		154	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
		155	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
		156
		157	}
		158
1123	serge	159	static void legacy_crtc_load_lut(struct drm_crtc *crtc)
		160	{
		161	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		162	struct drm_device *dev = crtc->dev;
		163	struct radeon_device *rdev = dev->dev_private;
		164	int i;
		165	uint32_t dac2_cntl;
		166
		167	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		168	if (radeon_crtc->crtc_id == 0)
		169	dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
		170	else
		171	dac2_cntl \|= RADEON_DAC2_PALETTE_ACC_CTL;
		172	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		173
		174	WREG8(RADEON_PALETTE_INDEX, 0);
		175	for (i = 0; i < 256; i++) {
		176	WREG32(RADEON_PALETTE_30_DATA,
		177	(radeon_crtc->lut_r[i] << 20) \|
		178	(radeon_crtc->lut_g[i] << 10) \|
		179	(radeon_crtc->lut_b[i] << 0));
		180	}
		181	}
		182
		183	void radeon_crtc_load_lut(struct drm_crtc *crtc)
		184	{
		185	struct drm_device *dev = crtc->dev;
		186	struct radeon_device *rdev = dev->dev_private;
		187
		188	if (!crtc->enabled)
		189	return;
		190
1963	serge	191	if (ASIC_IS_DCE5(rdev))
		192	dce5_crtc_load_lut(crtc);
		193	else if (ASIC_IS_DCE4(rdev))
		194	dce4_crtc_load_lut(crtc);
1430	serge	195	else if (ASIC_IS_AVIVO(rdev))
1123	serge	196	avivo_crtc_load_lut(crtc);
		197	else
		198	legacy_crtc_load_lut(crtc);
		199	}
		200
1221	serge	201	/** Sets the color ramps on behalf of fbcon */
1123	serge	202	void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		203	u16 blue, int regno)
		204	{
		205	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		206
		207	radeon_crtc->lut_r[regno] = red >> 6;
		208	radeon_crtc->lut_g[regno] = green >> 6;
		209	radeon_crtc->lut_b[regno] = blue >> 6;
		210	}
		211
1221	serge	212	/** Gets the color ramps on behalf of fbcon */
		213	void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		214	u16 *blue, int regno)
		215	{
		216	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		217
		218	*red = radeon_crtc->lut_r[regno] << 6;
		219	*green = radeon_crtc->lut_g[regno] << 6;
		220	*blue = radeon_crtc->lut_b[regno] << 6;
		221	}
		222
1123	serge	223	static void radeon_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
1963	serge	224	u16 *blue, uint32_t start, uint32_t size)
1123	serge	225	{
		226	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	227	int end = (start + size > 256) ? 256 : start + size, i;
1123	serge	228
1221	serge	229	/* userspace palettes are always correct as is */
1963	serge	230	for (i = start; i < end; i++) {
1123	serge	231	radeon_crtc->lut_r[i] = red[i] >> 6;
		232	radeon_crtc->lut_g[i] = green[i] >> 6;
		233	radeon_crtc->lut_b[i] = blue[i] >> 6;
		234	}
		235	radeon_crtc_load_lut(crtc);
		236	}
		237
		238	static void radeon_crtc_destroy(struct drm_crtc *crtc)
		239	{
		240	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		241
		242	drm_crtc_cleanup(crtc);
		243	kfree(radeon_crtc);
		244	}
		245
		246	static const struct drm_crtc_funcs radeon_crtc_funcs = {
1221	serge	247	.cursor_set = NULL,
		248	.cursor_move = NULL,
1123	serge	249	.gamma_set = radeon_crtc_gamma_set,
1126	serge	250	.set_config = drm_crtc_helper_set_config,
1123	serge	251	.destroy = radeon_crtc_destroy,
1963	serge	252	.page_flip = NULL,
1123	serge	253	};
		254
		255	static void radeon_crtc_init(struct drm_device *dev, int index)
		256	{
		257	struct radeon_device *rdev = dev->dev_private;
		258	struct radeon_crtc *radeon_crtc;
		259	int i;
		260
		261	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		262	if (radeon_crtc == NULL)
		263	return;
		264
		265	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
		266
		267	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
		268	radeon_crtc->crtc_id = index;
1179	serge	269	rdev->mode_info.crtcs[index] = radeon_crtc;
1123	serge	270
1179	serge	271	#if 0
1123	serge	272	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
		273	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
		274	radeon_crtc->mode_set.num_connectors = 0;
1179	serge	275	#endif
1123	serge	276
		277	for (i = 0; i < 256; i++) {
		278	radeon_crtc->lut_r[i] = i << 2;
		279	radeon_crtc->lut_g[i] = i << 2;
		280	radeon_crtc->lut_b[i] = i << 2;
		281	}
		282
		283	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom))
		284	radeon_atombios_init_crtc(dev, radeon_crtc);
		285	else
		286	radeon_legacy_init_crtc(dev, radeon_crtc);
		287	}
		288
2997	Serge	289	static const char *encoder_names[37] = {
1123	serge	290	"NONE",
		291	"INTERNAL_LVDS",
		292	"INTERNAL_TMDS1",
		293	"INTERNAL_TMDS2",
		294	"INTERNAL_DAC1",
		295	"INTERNAL_DAC2",
		296	"INTERNAL_SDVOA",
		297	"INTERNAL_SDVOB",
		298	"SI170B",
		299	"CH7303",
		300	"CH7301",
		301	"INTERNAL_DVO1",
		302	"EXTERNAL_SDVOA",
		303	"EXTERNAL_SDVOB",
		304	"TITFP513",
		305	"INTERNAL_LVTM1",
		306	"VT1623",
		307	"HDMI_SI1930",
		308	"HDMI_INTERNAL",
		309	"INTERNAL_KLDSCP_TMDS1",
		310	"INTERNAL_KLDSCP_DVO1",
		311	"INTERNAL_KLDSCP_DAC1",
		312	"INTERNAL_KLDSCP_DAC2",
		313	"SI178",
		314	"MVPU_FPGA",
		315	"INTERNAL_DDI",
		316	"VT1625",
		317	"HDMI_SI1932",
		318	"DP_AN9801",
		319	"DP_DP501",
		320	"INTERNAL_UNIPHY",
		321	"INTERNAL_KLDSCP_LVTMA",
		322	"INTERNAL_UNIPHY1",
		323	"INTERNAL_UNIPHY2",
1963	serge	324	"NUTMEG",
		325	"TRAVIS",
2997	Serge	326	"INTERNAL_VCE"
1123	serge	327	};
		328
1963	serge	329	static const char *hpd_names[6] = {
1404	serge	330	"HPD1",
		331	"HPD2",
		332	"HPD3",
		333	"HPD4",
		334	"HPD5",
		335	"HPD6",
		336	};
		337
1123	serge	338	static void radeon_print_display_setup(struct drm_device *dev)
		339	{
		340	struct drm_connector *connector;
		341	struct radeon_connector *radeon_connector;
		342	struct drm_encoder *encoder;
		343	struct radeon_encoder *radeon_encoder;
		344	uint32_t devices;
		345	int i = 0;
		346
		347	DRM_INFO("Radeon Display Connectors\n");
		348	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		349	radeon_connector = to_radeon_connector(connector);
		350	DRM_INFO("Connector %d:\n", i);
2997	Serge	351	DRM_INFO(" %s\n", drm_get_connector_name(connector));
1404	serge	352	if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
		353	DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
		354	if (radeon_connector->ddc_bus) {
1123	serge	355	DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		356	radeon_connector->ddc_bus->rec.mask_clk_reg,
		357	radeon_connector->ddc_bus->rec.mask_data_reg,
		358	radeon_connector->ddc_bus->rec.a_clk_reg,
		359	radeon_connector->ddc_bus->rec.a_data_reg,
1404	serge	360	radeon_connector->ddc_bus->rec.en_clk_reg,
		361	radeon_connector->ddc_bus->rec.en_data_reg,
		362	radeon_connector->ddc_bus->rec.y_clk_reg,
		363	radeon_connector->ddc_bus->rec.y_data_reg);
1963	serge	364	if (radeon_connector->router.ddc_valid)
		365	DRM_INFO(" DDC Router 0x%x/0x%x\n",
		366	radeon_connector->router.ddc_mux_control_pin,
		367	radeon_connector->router.ddc_mux_state);
		368	if (radeon_connector->router.cd_valid)
		369	DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
		370	radeon_connector->router.cd_mux_control_pin,
		371	radeon_connector->router.cd_mux_state);
1404	serge	372	} else {
		373	if (connector->connector_type == DRM_MODE_CONNECTOR_VGA \|\|
		374	connector->connector_type == DRM_MODE_CONNECTOR_DVII \|\|
		375	connector->connector_type == DRM_MODE_CONNECTOR_DVID \|\|
		376	connector->connector_type == DRM_MODE_CONNECTOR_DVIA \|\|
		377	connector->connector_type == DRM_MODE_CONNECTOR_HDMIA \|\|
		378	connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
		379	DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
		380	}
1123	serge	381	DRM_INFO(" Encoders:\n");
		382	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		383	radeon_encoder = to_radeon_encoder(encoder);
		384	devices = radeon_encoder->devices & radeon_connector->devices;
		385	if (devices) {
		386	if (devices & ATOM_DEVICE_CRT1_SUPPORT)
		387	DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		388	if (devices & ATOM_DEVICE_CRT2_SUPPORT)
		389	DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		390	if (devices & ATOM_DEVICE_LCD1_SUPPORT)
		391	DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		392	if (devices & ATOM_DEVICE_DFP1_SUPPORT)
		393	DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		394	if (devices & ATOM_DEVICE_DFP2_SUPPORT)
		395	DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		396	if (devices & ATOM_DEVICE_DFP3_SUPPORT)
		397	DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
		398	if (devices & ATOM_DEVICE_DFP4_SUPPORT)
		399	DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
		400	if (devices & ATOM_DEVICE_DFP5_SUPPORT)
		401	DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
1963	serge	402	if (devices & ATOM_DEVICE_DFP6_SUPPORT)
		403	DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
1123	serge	404	if (devices & ATOM_DEVICE_TV1_SUPPORT)
		405	DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		406	if (devices & ATOM_DEVICE_CV_SUPPORT)
		407	DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
		408	}
		409	}
		410	i++;
		411	}
		412	}
		413
1179	serge	414	static bool radeon_setup_enc_conn(struct drm_device *dev)
1123	serge	415	{
		416	struct radeon_device *rdev = dev->dev_private;
		417	bool ret = false;
		418
		419	if (rdev->bios) {
		420	if (rdev->is_atom_bios) {
1963	serge	421	ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
		422	if (ret == false)
1123	serge	423	ret = radeon_get_atom_connector_info_from_object_table(dev);
1404	serge	424	} else {
1123	serge	425	ret = radeon_get_legacy_connector_info_from_bios(dev);
1404	serge	426	if (ret == false)
		427	ret = radeon_get_legacy_connector_info_from_table(dev);
		428	}
1123	serge	429	} else {
		430	if (!ASIC_IS_AVIVO(rdev))
		431	ret = radeon_get_legacy_connector_info_from_table(dev);
		432	}
		433	if (ret) {
1404	serge	434	radeon_setup_encoder_clones(dev);
1123	serge	435	radeon_print_display_setup(dev);
		436	}
		437
		438	return ret;
		439	}
		440
		441	int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
		442	{
1430	serge	443	struct drm_device *dev = radeon_connector->base.dev;
		444	struct radeon_device *rdev = dev->dev_private;
1123	serge	445	int ret = 0;
		446
1963	serge	447	/* on hw with routers, select right port */
		448	if (radeon_connector->router.ddc_valid)
		449	radeon_router_select_ddc_port(radeon_connector);
		450
1404	serge	451	if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
2997	Serge	452	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) \|\|
		453	(radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
		454	ENCODER_OBJECT_ID_NONE)) {
1404	serge	455	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
2997	Serge	456
1404	serge	457	if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT \|\|
		458	dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
2997	Serge	459	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		460	&dig->dp_i2c_bus->adapter);
		461	else if (radeon_connector->ddc_bus && !radeon_connector->edid)
		462	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		463	&radeon_connector->ddc_bus->adapter);
		464	} else {
		465	if (radeon_connector->ddc_bus && !radeon_connector->edid)
		466	radeon_connector->edid = drm_get_edid(&radeon_connector->base,
		467	&radeon_connector->ddc_bus->adapter);
1404	serge	468	}
1963	serge	469
		470	if (!radeon_connector->edid) {
		471	if (rdev->is_atom_bios) {
		472	/* some laptops provide a hardcoded edid in rom for LCDs */
		473	if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) \|\|
		474	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
		475	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		476	} else
1430	serge	477	/* some servers provide a hardcoded edid in rom for KVMs */
1963	serge	478	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		479	}
1268	serge	480	if (radeon_connector->edid) {
		481	drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
		482	ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
1123	serge	483	return ret;
		484	}
		485	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
1179	serge	486	return 0;
1123	serge	487	}
		488
1963	serge	489	/* avivo */
		490	static void avivo_get_fb_div(struct radeon_pll *pll,
		491	u32 target_clock,
		492	u32 post_div,
		493	u32 ref_div,
		494	u32 *fb_div,
		495	u32 *frac_fb_div)
		496	{
		497	u32 tmp = post_div * ref_div;
		498
		499	tmp *= target_clock;
		500	*fb_div = tmp / pll->reference_freq;
		501	*frac_fb_div = tmp % pll->reference_freq;
		502
		503	if (*fb_div > pll->max_feedback_div)
		504	*fb_div = pll->max_feedback_div;
		505	else if (*fb_div < pll->min_feedback_div)
		506	*fb_div = pll->min_feedback_div;
		507	}
		508
		509	static u32 avivo_get_post_div(struct radeon_pll *pll,
		510	u32 target_clock)
		511	{
		512	u32 vco, post_div, tmp;
		513
		514	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		515	return pll->post_div;
		516
		517	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		518	if (pll->flags & RADEON_PLL_IS_LCD)
		519	vco = pll->lcd_pll_out_min;
		520	else
		521	vco = pll->pll_out_min;
		522	} else {
		523	if (pll->flags & RADEON_PLL_IS_LCD)
		524	vco = pll->lcd_pll_out_max;
		525	else
		526	vco = pll->pll_out_max;
		527	}
		528
		529	post_div = vco / target_clock;
		530	tmp = vco % target_clock;
		531
		532	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		533	if (tmp)
		534	post_div++;
		535	} else {
		536	if (!tmp)
		537	post_div--;
		538	}
		539
		540	if (post_div > pll->max_post_div)
		541	post_div = pll->max_post_div;
		542	else if (post_div < pll->min_post_div)
		543	post_div = pll->min_post_div;
		544
		545	return post_div;
		546	}
		547
		548	#define MAX_TOLERANCE 10
		549
		550	void radeon_compute_pll_avivo(struct radeon_pll *pll,
		551	u32 freq,
		552	u32 *dot_clock_p,
		553	u32 *fb_div_p,
		554	u32 *frac_fb_div_p,
		555	u32 *ref_div_p,
		556	u32 *post_div_p)
		557	{
		558	u32 target_clock = freq / 10;
		559	u32 post_div = avivo_get_post_div(pll, target_clock);
		560	u32 ref_div = pll->min_ref_div;
		561	u32 fb_div = 0, frac_fb_div = 0, tmp;
		562
		563	if (pll->flags & RADEON_PLL_USE_REF_DIV)
		564	ref_div = pll->reference_div;
		565
		566	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		567	avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
		568	frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
		569	if (frac_fb_div >= 5) {
		570	frac_fb_div -= 5;
		571	frac_fb_div = frac_fb_div / 10;
		572	frac_fb_div++;
		573	}
		574	if (frac_fb_div >= 10) {
		575	fb_div++;
		576	frac_fb_div = 0;
		577	}
		578	} else {
		579	while (ref_div <= pll->max_ref_div) {
		580	avivo_get_fb_div(pll, target_clock, post_div, ref_div,
		581	&fb_div, &frac_fb_div);
		582	if (frac_fb_div >= (pll->reference_freq / 2))
		583	fb_div++;
		584	frac_fb_div = 0;
		585	tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
		586	tmp = (tmp * 10000) / target_clock;
		587
		588	if (tmp > (10000 + MAX_TOLERANCE))
		589	ref_div++;
		590	else if (tmp >= (10000 - MAX_TOLERANCE))
		591	break;
		592	else
		593	ref_div++;
		594	}
		595	}
		596
		597	dot_clock_p = ((pll->reference_freq fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
		598	(ref_div * post_div * 10);
		599	*fb_div_p = fb_div;
		600	*frac_fb_div_p = frac_fb_div;
		601	*ref_div_p = ref_div;
		602	*post_div_p = post_div;
		603	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		604	*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
		605	}
		606
		607	/* pre-avivo */
1123	serge	608	static inline uint32_t radeon_div(uint64_t n, uint32_t d)
		609	{
		610	uint64_t mod;
		611
		612	n += d / 2;
		613
		614	mod = do_div(n, d);
		615	return n;
		616	}
		617
1963	serge	618	void radeon_compute_pll_legacy(struct radeon_pll *pll,
1123	serge	619	uint64_t freq,
		620	uint32_t *dot_clock_p,
		621	uint32_t *fb_div_p,
		622	uint32_t *frac_fb_div_p,
		623	uint32_t *ref_div_p,
1404	serge	624	uint32_t *post_div_p)
1123	serge	625	{
		626	uint32_t min_ref_div = pll->min_ref_div;
		627	uint32_t max_ref_div = pll->max_ref_div;
1404	serge	628	uint32_t min_post_div = pll->min_post_div;
		629	uint32_t max_post_div = pll->max_post_div;
1123	serge	630	uint32_t min_fractional_feed_div = 0;
		631	uint32_t max_fractional_feed_div = 0;
		632	uint32_t best_vco = pll->best_vco;
		633	uint32_t best_post_div = 1;
		634	uint32_t best_ref_div = 1;
		635	uint32_t best_feedback_div = 1;
		636	uint32_t best_frac_feedback_div = 0;
		637	uint32_t best_freq = -1;
		638	uint32_t best_error = 0xffffffff;
		639	uint32_t best_vco_diff = 1;
		640	uint32_t post_div;
1963	serge	641	u32 pll_out_min, pll_out_max;
1123	serge	642
1963	serge	643	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1123	serge	644	freq = freq * 1000;
		645
1963	serge	646	if (pll->flags & RADEON_PLL_IS_LCD) {
		647	pll_out_min = pll->lcd_pll_out_min;
		648	pll_out_max = pll->lcd_pll_out_max;
		649	} else {
		650	pll_out_min = pll->pll_out_min;
		651	pll_out_max = pll->pll_out_max;
		652	}
		653
		654	if (pll_out_min > 64800)
		655	pll_out_min = 64800;
		656
1404	serge	657	if (pll->flags & RADEON_PLL_USE_REF_DIV)
1123	serge	658	min_ref_div = max_ref_div = pll->reference_div;
		659	else {
		660	while (min_ref_div < max_ref_div-1) {
		661	uint32_t mid = (min_ref_div + max_ref_div) / 2;
		662	uint32_t pll_in = pll->reference_freq / mid;
		663	if (pll_in < pll->pll_in_min)
		664	max_ref_div = mid;
		665	else if (pll_in > pll->pll_in_max)
		666	min_ref_div = mid;
		667	else
		668	break;
		669	}
		670	}
		671
1404	serge	672	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		673	min_post_div = max_post_div = pll->post_div;
		674
		675	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1123	serge	676	min_fractional_feed_div = pll->min_frac_feedback_div;
		677	max_fractional_feed_div = pll->max_frac_feedback_div;
		678	}
		679
1963	serge	680	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1123	serge	681	uint32_t ref_div;
		682
1404	serge	683	if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1123	serge	684	continue;
		685
		686	/* legacy radeons only have a few post_divs */
1404	serge	687	if (pll->flags & RADEON_PLL_LEGACY) {
1123	serge	688	if ((post_div == 5) \|\|
		689	(post_div == 7) \|\|
		690	(post_div == 9) \|\|
		691	(post_div == 10) \|\|
		692	(post_div == 11) \|\|
		693	(post_div == 13) \|\|
		694	(post_div == 14) \|\|
		695	(post_div == 15))
		696	continue;
		697	}
		698
		699	for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
		700	uint32_t feedback_div, current_freq = 0, error, vco_diff;
		701	uint32_t pll_in = pll->reference_freq / ref_div;
		702	uint32_t min_feed_div = pll->min_feedback_div;
		703	uint32_t max_feed_div = pll->max_feedback_div + 1;
		704
		705	if (pll_in < pll->pll_in_min \|\| pll_in > pll->pll_in_max)
		706	continue;
		707
		708	while (min_feed_div < max_feed_div) {
		709	uint32_t vco;
		710	uint32_t min_frac_feed_div = min_fractional_feed_div;
		711	uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
		712	uint32_t frac_feedback_div;
		713	uint64_t tmp;
		714
		715	feedback_div = (min_feed_div + max_feed_div) / 2;
		716
		717	tmp = (uint64_t)pll->reference_freq * feedback_div;
		718	vco = radeon_div(tmp, ref_div);
		719
1963	serge	720	if (vco < pll_out_min) {
1123	serge	721	min_feed_div = feedback_div + 1;
		722	continue;
1963	serge	723	} else if (vco > pll_out_max) {
1123	serge	724	max_feed_div = feedback_div;
		725	continue;
		726	}
		727
		728	while (min_frac_feed_div < max_frac_feed_div) {
		729	frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
		730	tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
		731	tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
		732	current_freq = radeon_div(tmp, ref_div * post_div);
		733
1404	serge	734	if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1963	serge	735	if (freq < current_freq)
		736	error = 0xffffffff;
		737	else
1179	serge	738	error = freq - current_freq;
		739	} else
1123	serge	740	error = abs(current_freq - freq);
		741	vco_diff = abs(vco - best_vco);
		742
		743	if ((best_vco == 0 && error < best_error) \|\|
		744	(best_vco != 0 &&
1963	serge	745	((best_error > 100 && error < best_error - 100) \|\|
1123	serge	746	(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
		747	best_post_div = post_div;
		748	best_ref_div = ref_div;
		749	best_feedback_div = feedback_div;
		750	best_frac_feedback_div = frac_feedback_div;
		751	best_freq = current_freq;
		752	best_error = error;
		753	best_vco_diff = vco_diff;
		754	} else if (current_freq == freq) {
		755	if (best_freq == -1) {
		756	best_post_div = post_div;
		757	best_ref_div = ref_div;
		758	best_feedback_div = feedback_div;
		759	best_frac_feedback_div = frac_feedback_div;
		760	best_freq = current_freq;
		761	best_error = error;
		762	best_vco_diff = vco_diff;
1404	serge	763	} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) \|\|
		764	((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) \|\|
		765	((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) \|\|
		766	((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) \|\|
		767	((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) \|\|
		768	((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1123	serge	769	best_post_div = post_div;
		770	best_ref_div = ref_div;
		771	best_feedback_div = feedback_div;
		772	best_frac_feedback_div = frac_feedback_div;
		773	best_freq = current_freq;
		774	best_error = error;
		775	best_vco_diff = vco_diff;
		776	}
		777	}
		778	if (current_freq < freq)
		779	min_frac_feed_div = frac_feedback_div + 1;
		780	else
		781	max_frac_feed_div = frac_feedback_div;
		782	}
		783	if (current_freq < freq)
		784	min_feed_div = feedback_div + 1;
		785	else
		786	max_feed_div = feedback_div;
		787	}
		788	}
		789	}
		790
		791	*dot_clock_p = best_freq / 10000;
		792	*fb_div_p = best_feedback_div;
		793	*frac_fb_div_p = best_frac_feedback_div;
		794	*ref_div_p = best_ref_div;
		795	*post_div_p = best_post_div;
1963	serge	796	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		797	(long long)freq,
		798	best_freq / 1000, best_feedback_div, best_frac_feedback_div,
		799	best_ref_div, best_post_div);
1123	serge	800
1430	serge	801	}
		802
1123	serge	803	static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
		804	{
		805	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		806
		807	drm_framebuffer_cleanup(fb);
		808	kfree(radeon_fb);
		809	}
		810
		811	static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
		812	struct drm_file *file_priv,
		813	unsigned int *handle)
		814	{
		815	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		816
		817	return NULL;
		818	// return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
		819	}
		820
		821	static const struct drm_framebuffer_funcs radeon_fb_funcs = {
		822	.destroy = radeon_user_framebuffer_destroy,
		823	.create_handle = radeon_user_framebuffer_create_handle,
		824	};
		825
2997	Serge	826	int
1963	serge	827	radeon_framebuffer_init(struct drm_device *dev,
		828	struct radeon_framebuffer *rfb,
2997	Serge	829	struct drm_mode_fb_cmd2 *mode_cmd,
1123	serge	830	struct drm_gem_object *obj)
		831	{
2997	Serge	832	int ret;
		833
		834	ENTER();
		835
1963	serge	836	rfb->obj = obj;
2997	Serge	837	ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
		838	if (ret) {
		839	rfb->obj = NULL;
		840	return ret;
		841	}
1963	serge	842	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
2997	Serge	843	LEAVE();
		844	return 0;
1123	serge	845	}
		846
		847
		848
		849	static const struct drm_mode_config_funcs radeon_mode_funcs = {
1963	serge	850	// .fb_create = radeon_user_framebuffer_create,
		851	// .output_poll_changed = radeon_output_poll_changed
1123	serge	852	};
		853
1179	serge	854	static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
		855	{ { 0, "driver" },
		856	{ 1, "bios" },
		857	};
		858
		859	static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
		860	{ { TV_STD_NTSC, "ntsc" },
		861	{ TV_STD_PAL, "pal" },
		862	{ TV_STD_PAL_M, "pal-m" },
		863	{ TV_STD_PAL_60, "pal-60" },
		864	{ TV_STD_NTSC_J, "ntsc-j" },
		865	{ TV_STD_SCART_PAL, "scart-pal" },
		866	{ TV_STD_PAL_CN, "pal-cn" },
		867	{ TV_STD_SECAM, "secam" },
		868	};
		869
1963	serge	870	static struct drm_prop_enum_list radeon_underscan_enum_list[] =
		871	{ { UNDERSCAN_OFF, "off" },
		872	{ UNDERSCAN_ON, "on" },
		873	{ UNDERSCAN_AUTO, "auto" },
		874	};
		875
1404	serge	876	static int radeon_modeset_create_props(struct radeon_device *rdev)
1123	serge	877	{
2997	Serge	878	int sz;
1125	serge	879
1179	serge	880	if (rdev->is_atom_bios) {
		881	rdev->mode_info.coherent_mode_property =
2997	Serge	882	drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1179	serge	883	if (!rdev->mode_info.coherent_mode_property)
		884	return -ENOMEM;
		885	}
		886
		887	if (!ASIC_IS_AVIVO(rdev)) {
		888	sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
		889	rdev->mode_info.tmds_pll_property =
2997	Serge	890	drm_property_create_enum(rdev->ddev, 0,
		891	"tmds_pll",
		892	radeon_tmds_pll_enum_list, sz);
1179	serge	893	}
		894
		895	rdev->mode_info.load_detect_property =
2997	Serge	896	drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1179	serge	897	if (!rdev->mode_info.load_detect_property)
		898	return -ENOMEM;
		899
		900	drm_mode_create_scaling_mode_property(rdev->ddev);
		901
		902	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
		903	rdev->mode_info.tv_std_property =
2997	Serge	904	drm_property_create_enum(rdev->ddev, 0,
		905	"tv standard",
		906	radeon_tv_std_enum_list, sz);
1179	serge	907
1963	serge	908	sz = ARRAY_SIZE(radeon_underscan_enum_list);
		909	rdev->mode_info.underscan_property =
2997	Serge	910	drm_property_create_enum(rdev->ddev, 0,
		911	"underscan",
		912	radeon_underscan_enum_list, sz);
1963	serge	913
		914	rdev->mode_info.underscan_hborder_property =
2997	Serge	915	drm_property_create_range(rdev->ddev, 0,
		916	"underscan hborder", 0, 128);
1963	serge	917	if (!rdev->mode_info.underscan_hborder_property)
		918	return -ENOMEM;
		919
		920	rdev->mode_info.underscan_vborder_property =
2997	Serge	921	drm_property_create_range(rdev->ddev, 0,
		922	"underscan vborder", 0, 128);
1963	serge	923	if (!rdev->mode_info.underscan_vborder_property)
		924	return -ENOMEM;
		925
1179	serge	926	return 0;
		927	}
		928
1963	serge	929	void radeon_update_display_priority(struct radeon_device *rdev)
		930	{
		931	/* adjustment options for the display watermarks */
		932	if ((radeon_disp_priority == 0) \|\| (radeon_disp_priority > 2)) {
		933	/* set display priority to high for r3xx, rv515 chips
		934	* this avoids flickering due to underflow to the
		935	* display controllers during heavy acceleration.
		936	* Don't force high on rs4xx igp chips as it seems to
		937	* affect the sound card. See kernel bug 15982.
		938	*/
		939	if ((ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV515)) &&
		940	!(rdev->flags & RADEON_IS_IGP))
		941	rdev->disp_priority = 2;
		942	else
		943	rdev->disp_priority = 0;
		944	} else
		945	rdev->disp_priority = radeon_disp_priority;
		946
		947	}
		948
2997	Serge	949	/*
		950	* Allocate hdmi structs and determine register offsets
		951	*/
		952	static void radeon_afmt_init(struct radeon_device *rdev)
		953	{
		954	int i;
		955
		956	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
		957	rdev->mode_info.afmt[i] = NULL;
		958
		959	if (ASIC_IS_DCE6(rdev)) {
		960	/* todo */
		961	} else if (ASIC_IS_DCE4(rdev)) {
		962	/* DCE4/5 has 6 audio blocks tied to DIG encoders */
		963	/* DCE4.1 has 2 audio blocks tied to DIG encoders */
		964	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		965	if (rdev->mode_info.afmt[0]) {
		966	rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
		967	rdev->mode_info.afmt[0]->id = 0;
		968	}
		969	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		970	if (rdev->mode_info.afmt[1]) {
		971	rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
		972	rdev->mode_info.afmt[1]->id = 1;
		973	}
		974	if (!ASIC_IS_DCE41(rdev)) {
		975	rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		976	if (rdev->mode_info.afmt[2]) {
		977	rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
		978	rdev->mode_info.afmt[2]->id = 2;
		979	}
		980	rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		981	if (rdev->mode_info.afmt[3]) {
		982	rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
		983	rdev->mode_info.afmt[3]->id = 3;
		984	}
		985	rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		986	if (rdev->mode_info.afmt[4]) {
		987	rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
		988	rdev->mode_info.afmt[4]->id = 4;
		989	}
		990	rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		991	if (rdev->mode_info.afmt[5]) {
		992	rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
		993	rdev->mode_info.afmt[5]->id = 5;
		994	}
		995	}
		996	} else if (ASIC_IS_DCE3(rdev)) {
		997	/* DCE3.x has 2 audio blocks tied to DIG encoders */
		998	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		999	if (rdev->mode_info.afmt[0]) {
		1000	rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
		1001	rdev->mode_info.afmt[0]->id = 0;
		1002	}
		1003	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1004	if (rdev->mode_info.afmt[1]) {
		1005	rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
		1006	rdev->mode_info.afmt[1]->id = 1;
		1007	}
		1008	} else if (ASIC_IS_DCE2(rdev)) {
		1009	/* DCE2 has at least 1 routable audio block */
		1010	rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1011	if (rdev->mode_info.afmt[0]) {
		1012	rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
		1013	rdev->mode_info.afmt[0]->id = 0;
		1014	}
		1015	/* r6xx has 2 routable audio blocks */
		1016	if (rdev->family >= CHIP_R600) {
		1017	rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
		1018	if (rdev->mode_info.afmt[1]) {
		1019	rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
		1020	rdev->mode_info.afmt[1]->id = 1;
		1021	}
		1022	}
		1023	}
		1024	}
		1025
		1026	static void radeon_afmt_fini(struct radeon_device *rdev)
		1027	{
		1028	int i;
		1029
		1030	for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
		1031	kfree(rdev->mode_info.afmt[i]);
		1032	rdev->mode_info.afmt[i] = NULL;
		1033	}
		1034	}
		1035
1179	serge	1036	int radeon_modeset_init(struct radeon_device *rdev)
		1037	{
1430	serge	1038	int i;
1123	serge	1039	int ret;
		1040
		1041	drm_mode_config_init(rdev->ddev);
		1042	rdev->mode_info.mode_config_initialized = true;
		1043
2997	Serge	1044	rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1123	serge	1045
1963	serge	1046	if (ASIC_IS_DCE5(rdev)) {
		1047	rdev->ddev->mode_config.max_width = 16384;
		1048	rdev->ddev->mode_config.max_height = 16384;
		1049	} else if (ASIC_IS_AVIVO(rdev)) {
1123	serge	1050	rdev->ddev->mode_config.max_width = 8192;
		1051	rdev->ddev->mode_config.max_height = 8192;
		1052	} else {
		1053	rdev->ddev->mode_config.max_width = 4096;
		1054	rdev->ddev->mode_config.max_height = 4096;
		1055	}
		1056
2997	Serge	1057	rdev->ddev->mode_config.preferred_depth = 24;
		1058	rdev->ddev->mode_config.prefer_shadow = 1;
		1059
1123	serge	1060	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
		1061
1179	serge	1062	ret = radeon_modeset_create_props(rdev);
		1063	if (ret) {
		1064	return ret;
		1065	}
1221	serge	1066
1963	serge	1067	/* init i2c buses */
		1068	radeon_i2c_init(rdev);
		1069
1430	serge	1070	/* check combios for a valid hardcoded EDID - Sun servers */
		1071	if (!rdev->is_atom_bios) {
		1072	/* check for hardcoded EDID in BIOS */
		1073	radeon_combios_check_hardcoded_edid(rdev);
		1074	}
		1075
1221	serge	1076	/* allocate crtcs */
1430	serge	1077	for (i = 0; i < rdev->num_crtc; i++) {
1123	serge	1078	radeon_crtc_init(rdev->ddev, i);
		1079	}
		1080
		1081	/* okay we should have all the bios connectors */
		1082	ret = radeon_setup_enc_conn(rdev->ddev);
		1083	if (!ret) {
		1084	return ret;
		1085	}
1963	serge	1086
2997	Serge	1087	/* init dig PHYs, disp eng pll */
		1088	if (rdev->is_atom_bios) {
1963	serge	1089	radeon_atom_encoder_init(rdev);
2997	Serge	1090	radeon_atom_disp_eng_pll_init(rdev);
		1091	}
1963	serge	1092
1404	serge	1093	/* initialize hpd */
1963	serge	1094	// radeon_hpd_init(rdev);
		1095
2997	Serge	1096	/* setup afmt */
		1097	// radeon_afmt_init(rdev);
		1098
1963	serge	1099	/* Initialize power management */
		1100	// radeon_pm_init(rdev);
		1101
		1102	radeon_fbdev_init(rdev);
		1103	// drm_kms_helper_poll_init(rdev->ddev);
		1104
1123	serge	1105	return 0;
		1106	}
		1107
		1108	void radeon_modeset_fini(struct radeon_device *rdev)
		1109	{
1430	serge	1110	kfree(rdev->mode_info.bios_hardcoded_edid);
		1111
1123	serge	1112	if (rdev->mode_info.mode_config_initialized) {
2997	Serge	1113	// radeon_afmt_fini(rdev);
1963	serge	1114	// drm_kms_helper_poll_fini(rdev->ddev);
		1115	// radeon_hpd_fini(rdev);
1123	serge	1116	drm_mode_config_cleanup(rdev->ddev);
		1117	rdev->mode_info.mode_config_initialized = false;
		1118	}
1963	serge	1119	/* free i2c buses */
		1120	radeon_i2c_fini(rdev);
1123	serge	1121	}
		1122
2997	Serge	1123	static bool is_hdtv_mode(const struct drm_display_mode *mode)
1963	serge	1124	{
		1125	/* try and guess if this is a tv or a monitor */
		1126	if ((mode->vdisplay == 480 && mode->hdisplay == 720) \|\| /* 480p */
		1127	(mode->vdisplay == 576) \|\| /* 576p */
		1128	(mode->vdisplay == 720) \|\| /* 720p */
		1129	(mode->vdisplay == 1080)) /* 1080p */
		1130	return true;
		1131	else
		1132	return false;
		1133	}
		1134
1179	serge	1135	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
2997	Serge	1136	const struct drm_display_mode *mode,
1179	serge	1137	struct drm_display_mode *adjusted_mode)
1123	serge	1138	{
1179	serge	1139	struct drm_device *dev = crtc->dev;
1963	serge	1140	struct radeon_device *rdev = dev->dev_private;
1179	serge	1141	struct drm_encoder *encoder;
1123	serge	1142	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1179	serge	1143	struct radeon_encoder *radeon_encoder;
1963	serge	1144	struct drm_connector *connector;
		1145	struct radeon_connector *radeon_connector;
1179	serge	1146	bool first = true;
1963	serge	1147	u32 src_v = 1, dst_v = 1;
		1148	u32 src_h = 1, dst_h = 1;
1123	serge	1149
1963	serge	1150	radeon_crtc->h_border = 0;
		1151	radeon_crtc->v_border = 0;
		1152
2997	Serge	1153	ENTER();
		1154
1179	serge	1155	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1156	if (encoder->crtc != crtc)
		1157	continue;
1963	serge	1158	radeon_encoder = to_radeon_encoder(encoder);
		1159	connector = radeon_get_connector_for_encoder(encoder);
		1160	radeon_connector = to_radeon_connector(connector);
		1161
2997	Serge	1162	dbgprintf("native_hdisplay %d vdisplay %d\n",
		1163	radeon_encoder->native_mode.hdisplay,
		1164	radeon_encoder->native_mode.vdisplay);
		1165
1179	serge	1166	if (first) {
1404	serge	1167	/* set scaling */
		1168	if (radeon_encoder->rmx_type == RMX_OFF)
		1169	radeon_crtc->rmx_type = RMX_OFF;
		1170	else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay \|\|
		1171	mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1179	serge	1172	radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1404	serge	1173	else
		1174	radeon_crtc->rmx_type = RMX_OFF;
		1175	/* copy native mode */
1179	serge	1176	memcpy(&radeon_crtc->native_mode,
		1177	&radeon_encoder->native_mode,
1268	serge	1178	sizeof(struct drm_display_mode));
1963	serge	1179	src_v = crtc->mode.vdisplay;
		1180	dst_v = radeon_crtc->native_mode.vdisplay;
		1181	src_h = crtc->mode.hdisplay;
		1182	dst_h = radeon_crtc->native_mode.hdisplay;
		1183
		1184	/* fix up for overscan on hdmi */
		1185	if (ASIC_IS_AVIVO(rdev) &&
		1186	(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
		1187	((radeon_encoder->underscan_type == UNDERSCAN_ON) \|\|
		1188	((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
		1189	drm_detect_hdmi_monitor(radeon_connector->edid) &&
		1190	is_hdtv_mode(mode)))) {
		1191	if (radeon_encoder->underscan_hborder != 0)
		1192	radeon_crtc->h_border = radeon_encoder->underscan_hborder;
		1193	else
		1194	radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
		1195	if (radeon_encoder->underscan_vborder != 0)
		1196	radeon_crtc->v_border = radeon_encoder->underscan_vborder;
		1197	else
		1198	radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
		1199	radeon_crtc->rmx_type = RMX_FULL;
		1200	src_v = crtc->mode.vdisplay;
		1201	dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
		1202	src_h = crtc->mode.hdisplay;
		1203	dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
		1204	}
1179	serge	1205	first = false;
		1206	} else {
		1207	if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
		1208	/* WARNING: Right now this can't happen but
		1209	* in the future we need to check that scaling
1963	serge	1210	* are consistent across different encoder
1179	serge	1211	* (ie all encoder can work with the same
		1212	* scaling).
		1213	*/
1963	serge	1214	DRM_ERROR("Scaling not consistent across encoder.\n");
1179	serge	1215	return false;
		1216	}
1123	serge	1217	}
		1218	}
1179	serge	1219	if (radeon_crtc->rmx_type != RMX_OFF) {
1221	serge	1220	fixed20_12 a, b;
1963	serge	1221	a.full = dfixed_const(src_v);
		1222	b.full = dfixed_const(dst_v);
		1223	radeon_crtc->vsc.full = dfixed_div(a, b);
		1224	a.full = dfixed_const(src_h);
		1225	b.full = dfixed_const(dst_h);
		1226	radeon_crtc->hsc.full = dfixed_div(a, b);
1123	serge	1227	} else {
1963	serge	1228	radeon_crtc->vsc.full = dfixed_const(1);
		1229	radeon_crtc->hsc.full = dfixed_const(1);
1123	serge	1230	}
2997	Serge	1231
		1232	LEAVE();
		1233
1179	serge	1234	return true;
1123	serge	1235	}
1963	serge	1236
		1237	/*
		1238	* Retrieve current video scanout position of crtc on a given gpu.
		1239	*
		1240	* \param dev Device to query.
		1241	* \param crtc Crtc to query.
		1242	* \param *vpos Location where vertical scanout position should be stored.
		1243	* \param *hpos Location where horizontal scanout position should go.
		1244	*
		1245	* Returns vpos as a positive number while in active scanout area.
		1246	* Returns vpos as a negative number inside vblank, counting the number
		1247	* of scanlines to go until end of vblank, e.g., -1 means "one scanline
		1248	* until start of active scanout / end of vblank."
		1249	*
		1250	* \return Flags, or'ed together as follows:
		1251	*
		1252	* DRM_SCANOUTPOS_VALID = Query successful.
		1253	* DRM_SCANOUTPOS_INVBL = Inside vblank.
		1254	* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
		1255	* this flag means that returned position may be offset by a constant but
		1256	* unknown small number of scanlines wrt. real scanout position.
		1257	*
		1258	*/
		1259	int radeon_get_crtc_scanoutpos(struct drm_device dev, int crtc, int vpos, int *hpos)
		1260	{
		1261	u32 stat_crtc = 0, vbl = 0, position = 0;
		1262	int vbl_start, vbl_end, vtotal, ret = 0;
		1263	bool in_vbl = true;
		1264
		1265	struct radeon_device *rdev = dev->dev_private;
		1266
		1267	if (ASIC_IS_DCE4(rdev)) {
		1268	if (crtc == 0) {
		1269	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1270	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1271	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1272	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1273	ret \|= DRM_SCANOUTPOS_VALID;
		1274	}
		1275	if (crtc == 1) {
		1276	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1277	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1278	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1279	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1280	ret \|= DRM_SCANOUTPOS_VALID;
		1281	}
		1282	if (crtc == 2) {
		1283	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1284	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1285	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1286	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1287	ret \|= DRM_SCANOUTPOS_VALID;
		1288	}
		1289	if (crtc == 3) {
		1290	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1291	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1292	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1293	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1294	ret \|= DRM_SCANOUTPOS_VALID;
		1295	}
		1296	if (crtc == 4) {
		1297	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1298	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1299	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1300	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1301	ret \|= DRM_SCANOUTPOS_VALID;
		1302	}
		1303	if (crtc == 5) {
		1304	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1305	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1306	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1307	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1308	ret \|= DRM_SCANOUTPOS_VALID;
		1309	}
		1310	} else if (ASIC_IS_AVIVO(rdev)) {
		1311	if (crtc == 0) {
		1312	vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
		1313	position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
		1314	ret \|= DRM_SCANOUTPOS_VALID;
		1315	}
		1316	if (crtc == 1) {
		1317	vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
		1318	position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
		1319	ret \|= DRM_SCANOUTPOS_VALID;
		1320	}
		1321	} else {
		1322	/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
		1323	if (crtc == 0) {
		1324	/* Assume vbl_end == 0, get vbl_start from
		1325	* upper 16 bits.
		1326	*/
		1327	vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
		1328	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1329	/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
		1330	position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1331	stat_crtc = RREG32(RADEON_CRTC_STATUS);
		1332	if (!(stat_crtc & 1))
		1333	in_vbl = false;
		1334
		1335	ret \|= DRM_SCANOUTPOS_VALID;
		1336	}
		1337	if (crtc == 1) {
		1338	vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
		1339	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1340	position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1341	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
		1342	if (!(stat_crtc & 1))
		1343	in_vbl = false;
		1344
		1345	ret \|= DRM_SCANOUTPOS_VALID;
		1346	}
		1347	}
		1348
		1349	/* Decode into vertical and horizontal scanout position. */
		1350	*vpos = position & 0x1fff;
		1351	*hpos = (position >> 16) & 0x1fff;
		1352
		1353	/* Valid vblank area boundaries from gpu retrieved? */
		1354	if (vbl > 0) {
		1355	/* Yes: Decode. */
		1356	ret \|= DRM_SCANOUTPOS_ACCURATE;
		1357	vbl_start = vbl & 0x1fff;
		1358	vbl_end = (vbl >> 16) & 0x1fff;
		1359	}
		1360	else {
		1361	/* No: Fake something reasonable which gives at least ok results. */
		1362	vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
		1363	vbl_end = 0;
		1364	}
		1365
		1366	/* Test scanout position against vblank region. */
		1367	if ((vpos < vbl_start) && (vpos >= vbl_end))
		1368	in_vbl = false;
		1369
		1370	/* Check if inside vblank area and apply corrective offsets:
		1371	* vpos will then be >=0 in video scanout area, but negative
		1372	* within vblank area, counting down the number of lines until
		1373	* start of scanout.
		1374	*/
		1375
		1376	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
		1377	if (in_vbl && (*vpos >= vbl_start)) {
		1378	vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
		1379	vpos = vpos - vtotal;
		1380	}
		1381
		1382	/* Correct for shifted end of vbl at vbl_end. */
		1383	vpos = vpos - vbl_end;
		1384
		1385	/* In vblank? */
		1386	if (in_vbl)
		1387	ret \|= DRM_SCANOUTPOS_INVBL;
		1388
		1389	return ret;
		1390	}

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(root)/drivers/video/drm/radeon/radeon_display.c @ 3192 – Rev 2997