WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_display.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
		26	#include "drmP.h"
		27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
1963	serge	31	#include
1123	serge	32
		33	#include "drm_crtc_helper.h"
		34	#include "drm_edid.h"
		35
		36	static int radeon_ddc_dump(struct drm_connector *connector);
		37
		38	static void avivo_crtc_load_lut(struct drm_crtc *crtc)
		39	{
		40	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		41	struct drm_device *dev = crtc->dev;
		42	struct radeon_device *rdev = dev->dev_private;
		43	int i;
		44
1963	serge	45	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1123	serge	46	WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
		47
		48	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		49	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		50	WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		51
		52	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		53	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		54	WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		55
		56	WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
		57	WREG32(AVIVO_DC_LUT_RW_MODE, 0);
		58	WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
		59
		60	WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
		61	for (i = 0; i < 256; i++) {
		62	WREG32(AVIVO_DC_LUT_30_COLOR,
		63	(radeon_crtc->lut_r[i] << 20) \|
		64	(radeon_crtc->lut_g[i] << 10) \|
		65	(radeon_crtc->lut_b[i] << 0));
		66	}
		67
		68	WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
		69	}
		70
1963	serge	71	static void dce4_crtc_load_lut(struct drm_crtc *crtc)
1430	serge	72	{
		73	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		74	struct drm_device *dev = crtc->dev;
		75	struct radeon_device *rdev = dev->dev_private;
		76	int i;
		77
1963	serge	78	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
1430	serge	79	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		80
		81	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		82	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		83	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		84
		85	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		86	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		87	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		88
1963	serge	89	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		90	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
1430	serge	91
1963	serge	92	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
1430	serge	93	for (i = 0; i < 256; i++) {
1963	serge	94	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
1430	serge	95	(radeon_crtc->lut_r[i] << 20) \|
		96	(radeon_crtc->lut_g[i] << 10) \|
		97	(radeon_crtc->lut_b[i] << 0));
		98	}
		99	}
		100
1963	serge	101	static void dce5_crtc_load_lut(struct drm_crtc *crtc)
		102	{
		103	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		104	struct drm_device *dev = crtc->dev;
		105	struct radeon_device *rdev = dev->dev_private;
		106	int i;
		107
		108	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
		109
		110	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		111	(NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) \|
		112	NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
		113	WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
		114	NI_GRPH_PRESCALE_BYPASS);
		115	WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
		116	NI_OVL_PRESCALE_BYPASS);
		117	WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
		118	(NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) \|
		119	NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
		120
		121	WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
		122
		123	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
		124	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
		125	WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
		126
		127	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
		128	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
		129	WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
		130
		131	WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
		132	WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
		133
		134	WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
		135	for (i = 0; i < 256; i++) {
		136	WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
		137	(radeon_crtc->lut_r[i] << 20) \|
		138	(radeon_crtc->lut_g[i] << 10) \|
		139	(radeon_crtc->lut_b[i] << 0));
		140	}
		141
		142	WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
		143	(NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		144	NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		145	NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) \|
		146	NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
		147	WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
		148	(NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) \|
		149	NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
		150	WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
		151	(NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) \|
		152	NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
		153	WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
		154	(NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) \|
		155	NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
		156	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
		157	WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
		158
		159	}
		160
1123	serge	161	static void legacy_crtc_load_lut(struct drm_crtc *crtc)
		162	{
		163	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		164	struct drm_device *dev = crtc->dev;
		165	struct radeon_device *rdev = dev->dev_private;
		166	int i;
		167	uint32_t dac2_cntl;
		168
		169	dac2_cntl = RREG32(RADEON_DAC_CNTL2);
		170	if (radeon_crtc->crtc_id == 0)
		171	dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
		172	else
		173	dac2_cntl \|= RADEON_DAC2_PALETTE_ACC_CTL;
		174	WREG32(RADEON_DAC_CNTL2, dac2_cntl);
		175
		176	WREG8(RADEON_PALETTE_INDEX, 0);
		177	for (i = 0; i < 256; i++) {
		178	WREG32(RADEON_PALETTE_30_DATA,
		179	(radeon_crtc->lut_r[i] << 20) \|
		180	(radeon_crtc->lut_g[i] << 10) \|
		181	(radeon_crtc->lut_b[i] << 0));
		182	}
		183	}
		184
		185	void radeon_crtc_load_lut(struct drm_crtc *crtc)
		186	{
		187	struct drm_device *dev = crtc->dev;
		188	struct radeon_device *rdev = dev->dev_private;
		189
		190	if (!crtc->enabled)
		191	return;
		192
1963	serge	193	if (ASIC_IS_DCE5(rdev))
		194	dce5_crtc_load_lut(crtc);
		195	else if (ASIC_IS_DCE4(rdev))
		196	dce4_crtc_load_lut(crtc);
1430	serge	197	else if (ASIC_IS_AVIVO(rdev))
1123	serge	198	avivo_crtc_load_lut(crtc);
		199	else
		200	legacy_crtc_load_lut(crtc);
		201	}
		202
1221	serge	203	/** Sets the color ramps on behalf of fbcon */
1123	serge	204	void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
		205	u16 blue, int regno)
		206	{
		207	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		208
		209	radeon_crtc->lut_r[regno] = red >> 6;
		210	radeon_crtc->lut_g[regno] = green >> 6;
		211	radeon_crtc->lut_b[regno] = blue >> 6;
		212	}
		213
1221	serge	214	/** Gets the color ramps on behalf of fbcon */
		215	void radeon_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
		216	u16 *blue, int regno)
		217	{
		218	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		219
		220	*red = radeon_crtc->lut_r[regno] << 6;
		221	*green = radeon_crtc->lut_g[regno] << 6;
		222	*blue = radeon_crtc->lut_b[regno] << 6;
		223	}
		224
1123	serge	225	static void radeon_crtc_gamma_set(struct drm_crtc crtc, u16 red, u16 *green,
1963	serge	226	u16 *blue, uint32_t start, uint32_t size)
1123	serge	227	{
		228	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1963	serge	229	int end = (start + size > 256) ? 256 : start + size, i;
1123	serge	230
1221	serge	231	/* userspace palettes are always correct as is */
1963	serge	232	for (i = start; i < end; i++) {
1123	serge	233	radeon_crtc->lut_r[i] = red[i] >> 6;
		234	radeon_crtc->lut_g[i] = green[i] >> 6;
		235	radeon_crtc->lut_b[i] = blue[i] >> 6;
		236	}
		237	radeon_crtc_load_lut(crtc);
		238	}
		239
		240	static void radeon_crtc_destroy(struct drm_crtc *crtc)
		241	{
		242	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
		243
		244	drm_crtc_cleanup(crtc);
		245	kfree(radeon_crtc);
		246	}
		247
		248	static const struct drm_crtc_funcs radeon_crtc_funcs = {
1221	serge	249	.cursor_set = NULL,
		250	.cursor_move = NULL,
1123	serge	251	.gamma_set = radeon_crtc_gamma_set,
1126	serge	252	.set_config = drm_crtc_helper_set_config,
1123	serge	253	.destroy = radeon_crtc_destroy,
1963	serge	254	.page_flip = NULL,
1123	serge	255	};
		256
		257	static void radeon_crtc_init(struct drm_device *dev, int index)
		258	{
		259	struct radeon_device *rdev = dev->dev_private;
		260	struct radeon_crtc *radeon_crtc;
		261	int i;
		262
		263	radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
		264	if (radeon_crtc == NULL)
		265	return;
		266
		267	drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
		268
		269	drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
		270	radeon_crtc->crtc_id = index;
1179	serge	271	rdev->mode_info.crtcs[index] = radeon_crtc;
1123	serge	272
1179	serge	273	#if 0
1123	serge	274	radeon_crtc->mode_set.crtc = &radeon_crtc->base;
		275	radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
		276	radeon_crtc->mode_set.num_connectors = 0;
1179	serge	277	#endif
1123	serge	278
		279	for (i = 0; i < 256; i++) {
		280	radeon_crtc->lut_r[i] = i << 2;
		281	radeon_crtc->lut_g[i] = i << 2;
		282	radeon_crtc->lut_b[i] = i << 2;
		283	}
		284
		285	if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom))
		286	radeon_atombios_init_crtc(dev, radeon_crtc);
		287	else
		288	radeon_legacy_init_crtc(dev, radeon_crtc);
		289	}
		290
1963	serge	291	static const char *encoder_names[36] = {
1123	serge	292	"NONE",
		293	"INTERNAL_LVDS",
		294	"INTERNAL_TMDS1",
		295	"INTERNAL_TMDS2",
		296	"INTERNAL_DAC1",
		297	"INTERNAL_DAC2",
		298	"INTERNAL_SDVOA",
		299	"INTERNAL_SDVOB",
		300	"SI170B",
		301	"CH7303",
		302	"CH7301",
		303	"INTERNAL_DVO1",
		304	"EXTERNAL_SDVOA",
		305	"EXTERNAL_SDVOB",
		306	"TITFP513",
		307	"INTERNAL_LVTM1",
		308	"VT1623",
		309	"HDMI_SI1930",
		310	"HDMI_INTERNAL",
		311	"INTERNAL_KLDSCP_TMDS1",
		312	"INTERNAL_KLDSCP_DVO1",
		313	"INTERNAL_KLDSCP_DAC1",
		314	"INTERNAL_KLDSCP_DAC2",
		315	"SI178",
		316	"MVPU_FPGA",
		317	"INTERNAL_DDI",
		318	"VT1625",
		319	"HDMI_SI1932",
		320	"DP_AN9801",
		321	"DP_DP501",
		322	"INTERNAL_UNIPHY",
		323	"INTERNAL_KLDSCP_LVTMA",
		324	"INTERNAL_UNIPHY1",
		325	"INTERNAL_UNIPHY2",
1963	serge	326	"NUTMEG",
		327	"TRAVIS",
1123	serge	328	};
		329
1404	serge	330	static const char *connector_names[15] = {
1123	serge	331	"Unknown",
		332	"VGA",
		333	"DVI-I",
		334	"DVI-D",
		335	"DVI-A",
		336	"Composite",
		337	"S-video",
		338	"LVDS",
		339	"Component",
		340	"DIN",
		341	"DisplayPort",
		342	"HDMI-A",
		343	"HDMI-B",
1404	serge	344	"TV",
		345	"eDP",
1123	serge	346	};
		347
1963	serge	348	static const char *hpd_names[6] = {
1404	serge	349	"HPD1",
		350	"HPD2",
		351	"HPD3",
		352	"HPD4",
		353	"HPD5",
		354	"HPD6",
		355	};
		356
1123	serge	357	static void radeon_print_display_setup(struct drm_device *dev)
		358	{
		359	struct drm_connector *connector;
		360	struct radeon_connector *radeon_connector;
		361	struct drm_encoder *encoder;
		362	struct radeon_encoder *radeon_encoder;
		363	uint32_t devices;
		364	int i = 0;
		365
		366	DRM_INFO("Radeon Display Connectors\n");
		367	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		368	radeon_connector = to_radeon_connector(connector);
		369	DRM_INFO("Connector %d:\n", i);
		370	DRM_INFO(" %s\n", connector_names[connector->connector_type]);
1404	serge	371	if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
		372	DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
		373	if (radeon_connector->ddc_bus) {
1123	serge	374	DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		375	radeon_connector->ddc_bus->rec.mask_clk_reg,
		376	radeon_connector->ddc_bus->rec.mask_data_reg,
		377	radeon_connector->ddc_bus->rec.a_clk_reg,
		378	radeon_connector->ddc_bus->rec.a_data_reg,
1404	serge	379	radeon_connector->ddc_bus->rec.en_clk_reg,
		380	radeon_connector->ddc_bus->rec.en_data_reg,
		381	radeon_connector->ddc_bus->rec.y_clk_reg,
		382	radeon_connector->ddc_bus->rec.y_data_reg);
1963	serge	383	if (radeon_connector->router.ddc_valid)
		384	DRM_INFO(" DDC Router 0x%x/0x%x\n",
		385	radeon_connector->router.ddc_mux_control_pin,
		386	radeon_connector->router.ddc_mux_state);
		387	if (radeon_connector->router.cd_valid)
		388	DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
		389	radeon_connector->router.cd_mux_control_pin,
		390	radeon_connector->router.cd_mux_state);
1404	serge	391	} else {
		392	if (connector->connector_type == DRM_MODE_CONNECTOR_VGA \|\|
		393	connector->connector_type == DRM_MODE_CONNECTOR_DVII \|\|
		394	connector->connector_type == DRM_MODE_CONNECTOR_DVID \|\|
		395	connector->connector_type == DRM_MODE_CONNECTOR_DVIA \|\|
		396	connector->connector_type == DRM_MODE_CONNECTOR_HDMIA \|\|
		397	connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
		398	DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
		399	}
1123	serge	400	DRM_INFO(" Encoders:\n");
		401	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		402	radeon_encoder = to_radeon_encoder(encoder);
		403	devices = radeon_encoder->devices & radeon_connector->devices;
		404	if (devices) {
		405	if (devices & ATOM_DEVICE_CRT1_SUPPORT)
		406	DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		407	if (devices & ATOM_DEVICE_CRT2_SUPPORT)
		408	DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		409	if (devices & ATOM_DEVICE_LCD1_SUPPORT)
		410	DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		411	if (devices & ATOM_DEVICE_DFP1_SUPPORT)
		412	DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		413	if (devices & ATOM_DEVICE_DFP2_SUPPORT)
		414	DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
		415	if (devices & ATOM_DEVICE_DFP3_SUPPORT)
		416	DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
		417	if (devices & ATOM_DEVICE_DFP4_SUPPORT)
		418	DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
		419	if (devices & ATOM_DEVICE_DFP5_SUPPORT)
		420	DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
1963	serge	421	if (devices & ATOM_DEVICE_DFP6_SUPPORT)
		422	DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
1123	serge	423	if (devices & ATOM_DEVICE_TV1_SUPPORT)
		424	DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
		425	if (devices & ATOM_DEVICE_CV_SUPPORT)
		426	DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
		427	}
		428	}
		429	i++;
		430	}
		431	}
		432
1179	serge	433	static bool radeon_setup_enc_conn(struct drm_device *dev)
1123	serge	434	{
		435	struct radeon_device *rdev = dev->dev_private;
		436	struct drm_connector *drm_connector;
		437	bool ret = false;
		438
		439	if (rdev->bios) {
		440	if (rdev->is_atom_bios) {
1963	serge	441	ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
		442	if (ret == false)
1123	serge	443	ret = radeon_get_atom_connector_info_from_object_table(dev);
1404	serge	444	} else {
1123	serge	445	ret = radeon_get_legacy_connector_info_from_bios(dev);
1404	serge	446	if (ret == false)
		447	ret = radeon_get_legacy_connector_info_from_table(dev);
		448	}
1123	serge	449	} else {
		450	if (!ASIC_IS_AVIVO(rdev))
		451	ret = radeon_get_legacy_connector_info_from_table(dev);
		452	}
		453	if (ret) {
1404	serge	454	radeon_setup_encoder_clones(dev);
1123	serge	455	radeon_print_display_setup(dev);
2004	serge	456	list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
		457	radeon_ddc_dump(drm_connector);
1123	serge	458	}
		459
		460	return ret;
		461	}
		462
		463	int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
		464	{
1430	serge	465	struct drm_device *dev = radeon_connector->base.dev;
		466	struct radeon_device *rdev = dev->dev_private;
1123	serge	467	int ret = 0;
		468
1963	serge	469	/* on hw with routers, select right port */
		470	if (radeon_connector->router.ddc_valid)
		471	radeon_router_select_ddc_port(radeon_connector);
		472
1404	serge	473	if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
		474	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
		475	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
		476	if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT \|\|
		477	dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
		478	radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
		479	}
1123	serge	480	if (!radeon_connector->ddc_bus)
		481	return -1;
1179	serge	482	if (!radeon_connector->edid) {
1268	serge	483	radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
		484	}
1963	serge	485
		486	if (!radeon_connector->edid) {
		487	if (rdev->is_atom_bios) {
		488	/* some laptops provide a hardcoded edid in rom for LCDs */
		489	if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) \|\|
		490	(radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
		491	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		492	} else
1430	serge	493	/* some servers provide a hardcoded edid in rom for KVMs */
1963	serge	494	radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
		495	}
1268	serge	496	if (radeon_connector->edid) {
		497	drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
		498	ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
1123	serge	499	return ret;
		500	}
		501	drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
1179	serge	502	return 0;
1123	serge	503	}
		504
		505	static int radeon_ddc_dump(struct drm_connector *connector)
		506	{
		507	struct edid *edid;
		508	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
		509	int ret = 0;
		510
1963	serge	511	/* on hw with routers, select right port */
		512	if (radeon_connector->router.ddc_valid)
		513	radeon_router_select_ddc_port(radeon_connector);
		514
1123	serge	515	if (!radeon_connector->ddc_bus)
		516	return -1;
		517	edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
		518	if (edid) {
		519	kfree(edid);
		520	}
		521	return ret;
		522	}
		523
1963	serge	524	/* avivo */
		525	static void avivo_get_fb_div(struct radeon_pll *pll,
		526	u32 target_clock,
		527	u32 post_div,
		528	u32 ref_div,
		529	u32 *fb_div,
		530	u32 *frac_fb_div)
		531	{
		532	u32 tmp = post_div * ref_div;
		533
		534	tmp *= target_clock;
		535	*fb_div = tmp / pll->reference_freq;
		536	*frac_fb_div = tmp % pll->reference_freq;
		537
		538	if (*fb_div > pll->max_feedback_div)
		539	*fb_div = pll->max_feedback_div;
		540	else if (*fb_div < pll->min_feedback_div)
		541	*fb_div = pll->min_feedback_div;
		542	}
		543
		544	static u32 avivo_get_post_div(struct radeon_pll *pll,
		545	u32 target_clock)
		546	{
		547	u32 vco, post_div, tmp;
		548
		549	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		550	return pll->post_div;
		551
		552	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		553	if (pll->flags & RADEON_PLL_IS_LCD)
		554	vco = pll->lcd_pll_out_min;
		555	else
		556	vco = pll->pll_out_min;
		557	} else {
		558	if (pll->flags & RADEON_PLL_IS_LCD)
		559	vco = pll->lcd_pll_out_max;
		560	else
		561	vco = pll->pll_out_max;
		562	}
		563
		564	post_div = vco / target_clock;
		565	tmp = vco % target_clock;
		566
		567	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
		568	if (tmp)
		569	post_div++;
		570	} else {
		571	if (!tmp)
		572	post_div--;
		573	}
		574
		575	if (post_div > pll->max_post_div)
		576	post_div = pll->max_post_div;
		577	else if (post_div < pll->min_post_div)
		578	post_div = pll->min_post_div;
		579
		580	return post_div;
		581	}
		582
		583	#define MAX_TOLERANCE 10
		584
		585	void radeon_compute_pll_avivo(struct radeon_pll *pll,
		586	u32 freq,
		587	u32 *dot_clock_p,
		588	u32 *fb_div_p,
		589	u32 *frac_fb_div_p,
		590	u32 *ref_div_p,
		591	u32 *post_div_p)
		592	{
		593	u32 target_clock = freq / 10;
		594	u32 post_div = avivo_get_post_div(pll, target_clock);
		595	u32 ref_div = pll->min_ref_div;
		596	u32 fb_div = 0, frac_fb_div = 0, tmp;
		597
		598	if (pll->flags & RADEON_PLL_USE_REF_DIV)
		599	ref_div = pll->reference_div;
		600
		601	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
		602	avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
		603	frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
		604	if (frac_fb_div >= 5) {
		605	frac_fb_div -= 5;
		606	frac_fb_div = frac_fb_div / 10;
		607	frac_fb_div++;
		608	}
		609	if (frac_fb_div >= 10) {
		610	fb_div++;
		611	frac_fb_div = 0;
		612	}
		613	} else {
		614	while (ref_div <= pll->max_ref_div) {
		615	avivo_get_fb_div(pll, target_clock, post_div, ref_div,
		616	&fb_div, &frac_fb_div);
		617	if (frac_fb_div >= (pll->reference_freq / 2))
		618	fb_div++;
		619	frac_fb_div = 0;
		620	tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
		621	tmp = (tmp * 10000) / target_clock;
		622
		623	if (tmp > (10000 + MAX_TOLERANCE))
		624	ref_div++;
		625	else if (tmp >= (10000 - MAX_TOLERANCE))
		626	break;
		627	else
		628	ref_div++;
		629	}
		630	}
		631
		632	dot_clock_p = ((pll->reference_freq fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
		633	(ref_div * post_div * 10);
		634	*fb_div_p = fb_div;
		635	*frac_fb_div_p = frac_fb_div;
		636	*ref_div_p = ref_div;
		637	*post_div_p = post_div;
		638	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		639	*dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
		640	}
		641
		642	/* pre-avivo */
1123	serge	643	static inline uint32_t radeon_div(uint64_t n, uint32_t d)
		644	{
		645	uint64_t mod;
		646
		647	n += d / 2;
		648
		649	mod = do_div(n, d);
		650	return n;
		651	}
		652
1963	serge	653	void radeon_compute_pll_legacy(struct radeon_pll *pll,
1123	serge	654	uint64_t freq,
		655	uint32_t *dot_clock_p,
		656	uint32_t *fb_div_p,
		657	uint32_t *frac_fb_div_p,
		658	uint32_t *ref_div_p,
1404	serge	659	uint32_t *post_div_p)
1123	serge	660	{
		661	uint32_t min_ref_div = pll->min_ref_div;
		662	uint32_t max_ref_div = pll->max_ref_div;
1404	serge	663	uint32_t min_post_div = pll->min_post_div;
		664	uint32_t max_post_div = pll->max_post_div;
1123	serge	665	uint32_t min_fractional_feed_div = 0;
		666	uint32_t max_fractional_feed_div = 0;
		667	uint32_t best_vco = pll->best_vco;
		668	uint32_t best_post_div = 1;
		669	uint32_t best_ref_div = 1;
		670	uint32_t best_feedback_div = 1;
		671	uint32_t best_frac_feedback_div = 0;
		672	uint32_t best_freq = -1;
		673	uint32_t best_error = 0xffffffff;
		674	uint32_t best_vco_diff = 1;
		675	uint32_t post_div;
1963	serge	676	u32 pll_out_min, pll_out_max;
1123	serge	677
1963	serge	678	DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1123	serge	679	freq = freq * 1000;
		680
1963	serge	681	if (pll->flags & RADEON_PLL_IS_LCD) {
		682	pll_out_min = pll->lcd_pll_out_min;
		683	pll_out_max = pll->lcd_pll_out_max;
		684	} else {
		685	pll_out_min = pll->pll_out_min;
		686	pll_out_max = pll->pll_out_max;
		687	}
		688
		689	if (pll_out_min > 64800)
		690	pll_out_min = 64800;
		691
1404	serge	692	if (pll->flags & RADEON_PLL_USE_REF_DIV)
1123	serge	693	min_ref_div = max_ref_div = pll->reference_div;
		694	else {
		695	while (min_ref_div < max_ref_div-1) {
		696	uint32_t mid = (min_ref_div + max_ref_div) / 2;
		697	uint32_t pll_in = pll->reference_freq / mid;
		698	if (pll_in < pll->pll_in_min)
		699	max_ref_div = mid;
		700	else if (pll_in > pll->pll_in_max)
		701	min_ref_div = mid;
		702	else
		703	break;
		704	}
		705	}
		706
1404	serge	707	if (pll->flags & RADEON_PLL_USE_POST_DIV)
		708	min_post_div = max_post_div = pll->post_div;
		709
		710	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1123	serge	711	min_fractional_feed_div = pll->min_frac_feedback_div;
		712	max_fractional_feed_div = pll->max_frac_feedback_div;
		713	}
		714
1963	serge	715	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1123	serge	716	uint32_t ref_div;
		717
1404	serge	718	if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1123	serge	719	continue;
		720
		721	/* legacy radeons only have a few post_divs */
1404	serge	722	if (pll->flags & RADEON_PLL_LEGACY) {
1123	serge	723	if ((post_div == 5) \|\|
		724	(post_div == 7) \|\|
		725	(post_div == 9) \|\|
		726	(post_div == 10) \|\|
		727	(post_div == 11) \|\|
		728	(post_div == 13) \|\|
		729	(post_div == 14) \|\|
		730	(post_div == 15))
		731	continue;
		732	}
		733
		734	for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
		735	uint32_t feedback_div, current_freq = 0, error, vco_diff;
		736	uint32_t pll_in = pll->reference_freq / ref_div;
		737	uint32_t min_feed_div = pll->min_feedback_div;
		738	uint32_t max_feed_div = pll->max_feedback_div + 1;
		739
		740	if (pll_in < pll->pll_in_min \|\| pll_in > pll->pll_in_max)
		741	continue;
		742
		743	while (min_feed_div < max_feed_div) {
		744	uint32_t vco;
		745	uint32_t min_frac_feed_div = min_fractional_feed_div;
		746	uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
		747	uint32_t frac_feedback_div;
		748	uint64_t tmp;
		749
		750	feedback_div = (min_feed_div + max_feed_div) / 2;
		751
		752	tmp = (uint64_t)pll->reference_freq * feedback_div;
		753	vco = radeon_div(tmp, ref_div);
		754
1963	serge	755	if (vco < pll_out_min) {
1123	serge	756	min_feed_div = feedback_div + 1;
		757	continue;
1963	serge	758	} else if (vco > pll_out_max) {
1123	serge	759	max_feed_div = feedback_div;
		760	continue;
		761	}
		762
		763	while (min_frac_feed_div < max_frac_feed_div) {
		764	frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
		765	tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
		766	tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
		767	current_freq = radeon_div(tmp, ref_div * post_div);
		768
1404	serge	769	if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1963	serge	770	if (freq < current_freq)
		771	error = 0xffffffff;
		772	else
1179	serge	773	error = freq - current_freq;
		774	} else
1123	serge	775	error = abs(current_freq - freq);
		776	vco_diff = abs(vco - best_vco);
		777
		778	if ((best_vco == 0 && error < best_error) \|\|
		779	(best_vco != 0 &&
1963	serge	780	((best_error > 100 && error < best_error - 100) \|\|
1123	serge	781	(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
		782	best_post_div = post_div;
		783	best_ref_div = ref_div;
		784	best_feedback_div = feedback_div;
		785	best_frac_feedback_div = frac_feedback_div;
		786	best_freq = current_freq;
		787	best_error = error;
		788	best_vco_diff = vco_diff;
		789	} else if (current_freq == freq) {
		790	if (best_freq == -1) {
		791	best_post_div = post_div;
		792	best_ref_div = ref_div;
		793	best_feedback_div = feedback_div;
		794	best_frac_feedback_div = frac_feedback_div;
		795	best_freq = current_freq;
		796	best_error = error;
		797	best_vco_diff = vco_diff;
1404	serge	798	} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) \|\|
		799	((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) \|\|
		800	((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) \|\|
		801	((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) \|\|
		802	((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) \|\|
		803	((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1123	serge	804	best_post_div = post_div;
		805	best_ref_div = ref_div;
		806	best_feedback_div = feedback_div;
		807	best_frac_feedback_div = frac_feedback_div;
		808	best_freq = current_freq;
		809	best_error = error;
		810	best_vco_diff = vco_diff;
		811	}
		812	}
		813	if (current_freq < freq)
		814	min_frac_feed_div = frac_feedback_div + 1;
		815	else
		816	max_frac_feed_div = frac_feedback_div;
		817	}
		818	if (current_freq < freq)
		819	min_feed_div = feedback_div + 1;
		820	else
		821	max_feed_div = feedback_div;
		822	}
		823	}
		824	}
		825
		826	*dot_clock_p = best_freq / 10000;
		827	*fb_div_p = best_feedback_div;
		828	*frac_fb_div_p = best_frac_feedback_div;
		829	*ref_div_p = best_ref_div;
		830	*post_div_p = best_post_div;
1963	serge	831	DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
		832	(long long)freq,
		833	best_freq / 1000, best_feedback_div, best_frac_feedback_div,
		834	best_ref_div, best_post_div);
1123	serge	835
1430	serge	836	}
		837
1123	serge	838	static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
		839	{
		840	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		841
		842	drm_framebuffer_cleanup(fb);
		843	kfree(radeon_fb);
		844	}
		845
		846	static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
		847	struct drm_file *file_priv,
		848	unsigned int *handle)
		849	{
		850	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
		851
		852	return NULL;
		853	// return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
		854	}
		855
		856	static const struct drm_framebuffer_funcs radeon_fb_funcs = {
		857	.destroy = radeon_user_framebuffer_destroy,
		858	.create_handle = radeon_user_framebuffer_create_handle,
		859	};
		860
1963	serge	861	void
		862	radeon_framebuffer_init(struct drm_device *dev,
		863	struct radeon_framebuffer *rfb,
1123	serge	864	struct drm_mode_fb_cmd *mode_cmd,
		865	struct drm_gem_object *obj)
		866	{
1963	serge	867	rfb->obj = obj;
		868	drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
		869	drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1123	serge	870	}
		871
		872
		873
		874	static const struct drm_mode_config_funcs radeon_mode_funcs = {
1963	serge	875	// .fb_create = radeon_user_framebuffer_create,
		876	// .output_poll_changed = radeon_output_poll_changed
1123	serge	877	};
		878
1179	serge	879	struct drm_prop_enum_list {
		880	int type;
		881	char *name;
		882	};
		883
		884	static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
		885	{ { 0, "driver" },
		886	{ 1, "bios" },
		887	};
		888
		889	static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
		890	{ { TV_STD_NTSC, "ntsc" },
		891	{ TV_STD_PAL, "pal" },
		892	{ TV_STD_PAL_M, "pal-m" },
		893	{ TV_STD_PAL_60, "pal-60" },
		894	{ TV_STD_NTSC_J, "ntsc-j" },
		895	{ TV_STD_SCART_PAL, "scart-pal" },
		896	{ TV_STD_PAL_CN, "pal-cn" },
		897	{ TV_STD_SECAM, "secam" },
		898	};
		899
1963	serge	900	static struct drm_prop_enum_list radeon_underscan_enum_list[] =
		901	{ { UNDERSCAN_OFF, "off" },
		902	{ UNDERSCAN_ON, "on" },
		903	{ UNDERSCAN_AUTO, "auto" },
		904	};
		905
1404	serge	906	static int radeon_modeset_create_props(struct radeon_device *rdev)
1123	serge	907	{
1179	serge	908	int i, sz;
1125	serge	909
1179	serge	910	if (rdev->is_atom_bios) {
		911	rdev->mode_info.coherent_mode_property =
		912	drm_property_create(rdev->ddev,
		913	DRM_MODE_PROP_RANGE,
		914	"coherent", 2);
		915	if (!rdev->mode_info.coherent_mode_property)
		916	return -ENOMEM;
1125	serge	917
1179	serge	918	rdev->mode_info.coherent_mode_property->values[0] = 0;
1404	serge	919	rdev->mode_info.coherent_mode_property->values[1] = 1;
1179	serge	920	}
		921
		922	if (!ASIC_IS_AVIVO(rdev)) {
		923	sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
		924	rdev->mode_info.tmds_pll_property =
		925	drm_property_create(rdev->ddev,
		926	DRM_MODE_PROP_ENUM,
		927	"tmds_pll", sz);
		928	for (i = 0; i < sz; i++) {
		929	drm_property_add_enum(rdev->mode_info.tmds_pll_property,
		930	i,
		931	radeon_tmds_pll_enum_list[i].type,
		932	radeon_tmds_pll_enum_list[i].name);
		933	}
		934	}
		935
		936	rdev->mode_info.load_detect_property =
		937	drm_property_create(rdev->ddev,
		938	DRM_MODE_PROP_RANGE,
		939	"load detection", 2);
		940	if (!rdev->mode_info.load_detect_property)
		941	return -ENOMEM;
		942	rdev->mode_info.load_detect_property->values[0] = 0;
1404	serge	943	rdev->mode_info.load_detect_property->values[1] = 1;
1179	serge	944
		945	drm_mode_create_scaling_mode_property(rdev->ddev);
		946
		947	sz = ARRAY_SIZE(radeon_tv_std_enum_list);
		948	rdev->mode_info.tv_std_property =
		949	drm_property_create(rdev->ddev,
		950	DRM_MODE_PROP_ENUM,
		951	"tv standard", sz);
		952	for (i = 0; i < sz; i++) {
		953	drm_property_add_enum(rdev->mode_info.tv_std_property,
		954	i,
		955	radeon_tv_std_enum_list[i].type,
		956	radeon_tv_std_enum_list[i].name);
		957	}
		958
1963	serge	959	sz = ARRAY_SIZE(radeon_underscan_enum_list);
		960	rdev->mode_info.underscan_property =
		961	drm_property_create(rdev->ddev,
		962	DRM_MODE_PROP_ENUM,
		963	"underscan", sz);
		964	for (i = 0; i < sz; i++) {
		965	drm_property_add_enum(rdev->mode_info.underscan_property,
		966	i,
		967	radeon_underscan_enum_list[i].type,
		968	radeon_underscan_enum_list[i].name);
		969	}
		970
		971	rdev->mode_info.underscan_hborder_property =
		972	drm_property_create(rdev->ddev,
		973	DRM_MODE_PROP_RANGE,
		974	"underscan hborder", 2);
		975	if (!rdev->mode_info.underscan_hborder_property)
		976	return -ENOMEM;
		977	rdev->mode_info.underscan_hborder_property->values[0] = 0;
		978	rdev->mode_info.underscan_hborder_property->values[1] = 128;
		979
		980	rdev->mode_info.underscan_vborder_property =
		981	drm_property_create(rdev->ddev,
		982	DRM_MODE_PROP_RANGE,
		983	"underscan vborder", 2);
		984	if (!rdev->mode_info.underscan_vborder_property)
		985	return -ENOMEM;
		986	rdev->mode_info.underscan_vborder_property->values[0] = 0;
		987	rdev->mode_info.underscan_vborder_property->values[1] = 128;
		988
1179	serge	989	return 0;
		990	}
		991
1963	serge	992	void radeon_update_display_priority(struct radeon_device *rdev)
		993	{
		994	/* adjustment options for the display watermarks */
		995	if ((radeon_disp_priority == 0) \|\| (radeon_disp_priority > 2)) {
		996	/* set display priority to high for r3xx, rv515 chips
		997	* this avoids flickering due to underflow to the
		998	* display controllers during heavy acceleration.
		999	* Don't force high on rs4xx igp chips as it seems to
		1000	* affect the sound card. See kernel bug 15982.
		1001	*/
		1002	if ((ASIC_IS_R300(rdev) \|\| (rdev->family == CHIP_RV515)) &&
		1003	!(rdev->flags & RADEON_IS_IGP))
		1004	rdev->disp_priority = 2;
		1005	else
		1006	rdev->disp_priority = 0;
		1007	} else
		1008	rdev->disp_priority = radeon_disp_priority;
		1009
		1010	}
		1011
1179	serge	1012	int radeon_modeset_init(struct radeon_device *rdev)
		1013	{
1430	serge	1014	int i;
1123	serge	1015	int ret;
		1016
1963	serge	1017	ENTER();
		1018
1123	serge	1019	drm_mode_config_init(rdev->ddev);
		1020	rdev->mode_info.mode_config_initialized = true;
		1021
1125	serge	1022	rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1123	serge	1023
1963	serge	1024	if (ASIC_IS_DCE5(rdev)) {
		1025	rdev->ddev->mode_config.max_width = 16384;
		1026	rdev->ddev->mode_config.max_height = 16384;
		1027	} else if (ASIC_IS_AVIVO(rdev)) {
1123	serge	1028	rdev->ddev->mode_config.max_width = 8192;
		1029	rdev->ddev->mode_config.max_height = 8192;
		1030	} else {
		1031	rdev->ddev->mode_config.max_width = 4096;
		1032	rdev->ddev->mode_config.max_height = 4096;
		1033	}
		1034
		1035	rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
		1036
1179	serge	1037	ret = radeon_modeset_create_props(rdev);
		1038	if (ret) {
		1039	return ret;
		1040	}
1221	serge	1041
1963	serge	1042	/* init i2c buses */
		1043	radeon_i2c_init(rdev);
		1044
1430	serge	1045	/* check combios for a valid hardcoded EDID - Sun servers */
		1046	if (!rdev->is_atom_bios) {
		1047	/* check for hardcoded EDID in BIOS */
		1048	radeon_combios_check_hardcoded_edid(rdev);
		1049	}
		1050
1221	serge	1051	/* allocate crtcs */
1430	serge	1052	for (i = 0; i < rdev->num_crtc; i++) {
1123	serge	1053	radeon_crtc_init(rdev->ddev, i);
		1054	}
		1055
		1056	/* okay we should have all the bios connectors */
		1057	ret = radeon_setup_enc_conn(rdev->ddev);
		1058	if (!ret) {
		1059	return ret;
		1060	}
1963	serge	1061
		1062	/* init dig PHYs */
		1063	if (rdev->is_atom_bios)
		1064	radeon_atom_encoder_init(rdev);
		1065
1404	serge	1066	/* initialize hpd */
1963	serge	1067	// radeon_hpd_init(rdev);
		1068
		1069	/* Initialize power management */
		1070	// radeon_pm_init(rdev);
		1071
		1072	radeon_fbdev_init(rdev);
		1073	// drm_kms_helper_poll_init(rdev->ddev);
		1074
		1075	LEAVE();
		1076
1123	serge	1077	return 0;
		1078	}
		1079
		1080	void radeon_modeset_fini(struct radeon_device *rdev)
		1081	{
1430	serge	1082	kfree(rdev->mode_info.bios_hardcoded_edid);
		1083
1123	serge	1084	if (rdev->mode_info.mode_config_initialized) {
1963	serge	1085	// drm_kms_helper_poll_fini(rdev->ddev);
		1086	// radeon_hpd_fini(rdev);
1123	serge	1087	drm_mode_config_cleanup(rdev->ddev);
		1088	rdev->mode_info.mode_config_initialized = false;
		1089	}
1963	serge	1090	/* free i2c buses */
		1091	radeon_i2c_fini(rdev);
1123	serge	1092	}
		1093
1963	serge	1094	static bool is_hdtv_mode(struct drm_display_mode *mode)
		1095	{
		1096	/* try and guess if this is a tv or a monitor */
		1097	if ((mode->vdisplay == 480 && mode->hdisplay == 720) \|\| /* 480p */
		1098	(mode->vdisplay == 576) \|\| /* 576p */
		1099	(mode->vdisplay == 720) \|\| /* 720p */
		1100	(mode->vdisplay == 1080)) /* 1080p */
		1101	return true;
		1102	else
		1103	return false;
		1104	}
		1105
1179	serge	1106	bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
		1107	struct drm_display_mode *mode,
		1108	struct drm_display_mode *adjusted_mode)
1123	serge	1109	{
1179	serge	1110	struct drm_device *dev = crtc->dev;
1963	serge	1111	struct radeon_device *rdev = dev->dev_private;
1179	serge	1112	struct drm_encoder *encoder;
1123	serge	1113	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1179	serge	1114	struct radeon_encoder *radeon_encoder;
1963	serge	1115	struct drm_connector *connector;
		1116	struct radeon_connector *radeon_connector;
1179	serge	1117	bool first = true;
1963	serge	1118	u32 src_v = 1, dst_v = 1;
		1119	u32 src_h = 1, dst_h = 1;
1123	serge	1120
1963	serge	1121	radeon_crtc->h_border = 0;
		1122	radeon_crtc->v_border = 0;
		1123
1179	serge	1124	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		1125	if (encoder->crtc != crtc)
		1126	continue;
1963	serge	1127	radeon_encoder = to_radeon_encoder(encoder);
		1128	connector = radeon_get_connector_for_encoder(encoder);
		1129	radeon_connector = to_radeon_connector(connector);
		1130
1179	serge	1131	if (first) {
1404	serge	1132	/* set scaling */
		1133	if (radeon_encoder->rmx_type == RMX_OFF)
		1134	radeon_crtc->rmx_type = RMX_OFF;
		1135	else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay \|\|
		1136	mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1179	serge	1137	radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1404	serge	1138	else
		1139	radeon_crtc->rmx_type = RMX_OFF;
		1140	/* copy native mode */
1179	serge	1141	memcpy(&radeon_crtc->native_mode,
		1142	&radeon_encoder->native_mode,
1268	serge	1143	sizeof(struct drm_display_mode));
1963	serge	1144	src_v = crtc->mode.vdisplay;
		1145	dst_v = radeon_crtc->native_mode.vdisplay;
		1146	src_h = crtc->mode.hdisplay;
		1147	dst_h = radeon_crtc->native_mode.hdisplay;
		1148
		1149	/* fix up for overscan on hdmi */
		1150	if (ASIC_IS_AVIVO(rdev) &&
		1151	(!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
		1152	((radeon_encoder->underscan_type == UNDERSCAN_ON) \|\|
		1153	((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
		1154	drm_detect_hdmi_monitor(radeon_connector->edid) &&
		1155	is_hdtv_mode(mode)))) {
		1156	if (radeon_encoder->underscan_hborder != 0)
		1157	radeon_crtc->h_border = radeon_encoder->underscan_hborder;
		1158	else
		1159	radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
		1160	if (radeon_encoder->underscan_vborder != 0)
		1161	radeon_crtc->v_border = radeon_encoder->underscan_vborder;
		1162	else
		1163	radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
		1164	radeon_crtc->rmx_type = RMX_FULL;
		1165	src_v = crtc->mode.vdisplay;
		1166	dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
		1167	src_h = crtc->mode.hdisplay;
		1168	dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
		1169	}
1179	serge	1170	first = false;
		1171	} else {
		1172	if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
		1173	/* WARNING: Right now this can't happen but
		1174	* in the future we need to check that scaling
1963	serge	1175	* are consistent across different encoder
1179	serge	1176	* (ie all encoder can work with the same
		1177	* scaling).
		1178	*/
1963	serge	1179	DRM_ERROR("Scaling not consistent across encoder.\n");
1179	serge	1180	return false;
		1181	}
1123	serge	1182	}
		1183	}
1179	serge	1184	if (radeon_crtc->rmx_type != RMX_OFF) {
1221	serge	1185	fixed20_12 a, b;
1963	serge	1186	a.full = dfixed_const(src_v);
		1187	b.full = dfixed_const(dst_v);
		1188	radeon_crtc->vsc.full = dfixed_div(a, b);
		1189	a.full = dfixed_const(src_h);
		1190	b.full = dfixed_const(dst_h);
		1191	radeon_crtc->hsc.full = dfixed_div(a, b);
1123	serge	1192	} else {
1963	serge	1193	radeon_crtc->vsc.full = dfixed_const(1);
		1194	radeon_crtc->hsc.full = dfixed_const(1);
1123	serge	1195	}
1179	serge	1196	return true;
1123	serge	1197	}
1963	serge	1198
		1199	/*
		1200	* Retrieve current video scanout position of crtc on a given gpu.
		1201	*
		1202	* \param dev Device to query.
		1203	* \param crtc Crtc to query.
		1204	* \param *vpos Location where vertical scanout position should be stored.
		1205	* \param *hpos Location where horizontal scanout position should go.
		1206	*
		1207	* Returns vpos as a positive number while in active scanout area.
		1208	* Returns vpos as a negative number inside vblank, counting the number
		1209	* of scanlines to go until end of vblank, e.g., -1 means "one scanline
		1210	* until start of active scanout / end of vblank."
		1211	*
		1212	* \return Flags, or'ed together as follows:
		1213	*
		1214	* DRM_SCANOUTPOS_VALID = Query successful.
		1215	* DRM_SCANOUTPOS_INVBL = Inside vblank.
		1216	* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
		1217	* this flag means that returned position may be offset by a constant but
		1218	* unknown small number of scanlines wrt. real scanout position.
		1219	*
		1220	*/
		1221	int radeon_get_crtc_scanoutpos(struct drm_device dev, int crtc, int vpos, int *hpos)
		1222	{
		1223	u32 stat_crtc = 0, vbl = 0, position = 0;
		1224	int vbl_start, vbl_end, vtotal, ret = 0;
		1225	bool in_vbl = true;
		1226
		1227	struct radeon_device *rdev = dev->dev_private;
		1228
		1229	if (ASIC_IS_DCE4(rdev)) {
		1230	if (crtc == 0) {
		1231	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1232	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1233	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1234	EVERGREEN_CRTC0_REGISTER_OFFSET);
		1235	ret \|= DRM_SCANOUTPOS_VALID;
		1236	}
		1237	if (crtc == 1) {
		1238	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1239	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1240	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1241	EVERGREEN_CRTC1_REGISTER_OFFSET);
		1242	ret \|= DRM_SCANOUTPOS_VALID;
		1243	}
		1244	if (crtc == 2) {
		1245	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1246	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1247	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1248	EVERGREEN_CRTC2_REGISTER_OFFSET);
		1249	ret \|= DRM_SCANOUTPOS_VALID;
		1250	}
		1251	if (crtc == 3) {
		1252	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1253	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1254	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1255	EVERGREEN_CRTC3_REGISTER_OFFSET);
		1256	ret \|= DRM_SCANOUTPOS_VALID;
		1257	}
		1258	if (crtc == 4) {
		1259	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1260	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1261	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1262	EVERGREEN_CRTC4_REGISTER_OFFSET);
		1263	ret \|= DRM_SCANOUTPOS_VALID;
		1264	}
		1265	if (crtc == 5) {
		1266	vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
		1267	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1268	position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
		1269	EVERGREEN_CRTC5_REGISTER_OFFSET);
		1270	ret \|= DRM_SCANOUTPOS_VALID;
		1271	}
		1272	} else if (ASIC_IS_AVIVO(rdev)) {
		1273	if (crtc == 0) {
		1274	vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
		1275	position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
		1276	ret \|= DRM_SCANOUTPOS_VALID;
		1277	}
		1278	if (crtc == 1) {
		1279	vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
		1280	position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
		1281	ret \|= DRM_SCANOUTPOS_VALID;
		1282	}
		1283	} else {
		1284	/* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
		1285	if (crtc == 0) {
		1286	/* Assume vbl_end == 0, get vbl_start from
		1287	* upper 16 bits.
		1288	*/
		1289	vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
		1290	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1291	/* Only retrieve vpos from upper 16 bits, set hpos == 0. */
		1292	position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1293	stat_crtc = RREG32(RADEON_CRTC_STATUS);
		1294	if (!(stat_crtc & 1))
		1295	in_vbl = false;
		1296
		1297	ret \|= DRM_SCANOUTPOS_VALID;
		1298	}
		1299	if (crtc == 1) {
		1300	vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
		1301	RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
		1302	position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
		1303	stat_crtc = RREG32(RADEON_CRTC2_STATUS);
		1304	if (!(stat_crtc & 1))
		1305	in_vbl = false;
		1306
		1307	ret \|= DRM_SCANOUTPOS_VALID;
		1308	}
		1309	}
		1310
		1311	/* Decode into vertical and horizontal scanout position. */
		1312	*vpos = position & 0x1fff;
		1313	*hpos = (position >> 16) & 0x1fff;
		1314
		1315	/* Valid vblank area boundaries from gpu retrieved? */
		1316	if (vbl > 0) {
		1317	/* Yes: Decode. */
		1318	ret \|= DRM_SCANOUTPOS_ACCURATE;
		1319	vbl_start = vbl & 0x1fff;
		1320	vbl_end = (vbl >> 16) & 0x1fff;
		1321	}
		1322	else {
		1323	/* No: Fake something reasonable which gives at least ok results. */
		1324	vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
		1325	vbl_end = 0;
		1326	}
		1327
		1328	/* Test scanout position against vblank region. */
		1329	if ((vpos < vbl_start) && (vpos >= vbl_end))
		1330	in_vbl = false;
		1331
		1332	/* Check if inside vblank area and apply corrective offsets:
		1333	* vpos will then be >=0 in video scanout area, but negative
		1334	* within vblank area, counting down the number of lines until
		1335	* start of scanout.
		1336	*/
		1337
		1338	/* Inside "upper part" of vblank area? Apply corrective offset if so: */
		1339	if (in_vbl && (*vpos >= vbl_start)) {
		1340	vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
		1341	vpos = vpos - vtotal;
		1342	}
		1343
		1344	/* Correct for shifted end of vbl at vbl_end. */
		1345	vpos = vpos - vbl_end;
		1346
		1347	/* In vblank? */
		1348	if (in_vbl)
		1349	ret \|= DRM_SCANOUTPOS_INVBL;
		1350
		1351	return ret;
		1352	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_display.c – Rev 2004