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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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26 | #include "drmP.h" |
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27 | #include "radeon_drm.h" |
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28 | #include "radeon.h" |
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29 | |||
30 | #include "atom.h" |
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31 | //#include |
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32 | |||
33 | #include "drm_crtc_helper.h" |
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34 | #include "drm_edid.h" |
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35 | |||
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
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37 | |||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
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39 | { |
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40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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41 | struct drm_device *dev = crtc->dev; |
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42 | struct radeon_device *rdev = dev->dev_private; |
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43 | int i; |
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44 | |||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
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46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
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47 | |||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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51 | |||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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55 | |||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
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57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
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58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
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59 | |||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
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61 | for (i = 0; i < 256; i++) { |
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62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
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63 | (radeon_crtc->lut_r[i] << 20) | |
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64 | (radeon_crtc->lut_g[i] << 10) | |
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65 | (radeon_crtc->lut_b[i] << 0)); |
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66 | } |
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67 | |||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
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69 | } |
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70 | |||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
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72 | { |
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73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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74 | struct drm_device *dev = crtc->dev; |
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75 | struct radeon_device *rdev = dev->dev_private; |
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76 | int i; |
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77 | uint32_t dac2_cntl; |
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78 | |||
79 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
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80 | if (radeon_crtc->crtc_id == 0) |
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81 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
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82 | else |
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83 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
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84 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
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85 | |||
86 | WREG8(RADEON_PALETTE_INDEX, 0); |
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87 | for (i = 0; i < 256; i++) { |
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88 | WREG32(RADEON_PALETTE_30_DATA, |
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89 | (radeon_crtc->lut_r[i] << 20) | |
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90 | (radeon_crtc->lut_g[i] << 10) | |
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91 | (radeon_crtc->lut_b[i] << 0)); |
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92 | } |
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93 | } |
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94 | |||
95 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
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96 | { |
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97 | struct drm_device *dev = crtc->dev; |
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98 | struct radeon_device *rdev = dev->dev_private; |
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99 | |||
100 | if (!crtc->enabled) |
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101 | return; |
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102 | |||
103 | if (ASIC_IS_AVIVO(rdev)) |
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104 | avivo_crtc_load_lut(crtc); |
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105 | else |
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106 | legacy_crtc_load_lut(crtc); |
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107 | } |
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108 | |||
1221 | serge | 109 | /** Sets the color ramps on behalf of fbcon */ |
1123 | serge | 110 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
111 | u16 blue, int regno) |
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112 | { |
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113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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114 | |||
115 | radeon_crtc->lut_r[regno] = red >> 6; |
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116 | radeon_crtc->lut_g[regno] = green >> 6; |
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117 | radeon_crtc->lut_b[regno] = blue >> 6; |
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118 | } |
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119 | |||
1221 | serge | 120 | /** Gets the color ramps on behalf of fbcon */ |
121 | void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
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122 | u16 *blue, int regno) |
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123 | { |
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124 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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125 | |||
126 | *red = radeon_crtc->lut_r[regno] << 6; |
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127 | *green = radeon_crtc->lut_g[regno] << 6; |
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128 | *blue = radeon_crtc->lut_b[regno] << 6; |
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129 | } |
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130 | |||
1123 | serge | 131 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
132 | u16 *blue, uint32_t size) |
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133 | { |
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134 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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1221 | serge | 135 | int i; |
1123 | serge | 136 | |
137 | if (size != 256) { |
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138 | return; |
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139 | } |
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140 | |||
1221 | serge | 141 | /* userspace palettes are always correct as is */ |
1123 | serge | 142 | for (i = 0; i < 256; i++) { |
143 | radeon_crtc->lut_r[i] = red[i] >> 6; |
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144 | radeon_crtc->lut_g[i] = green[i] >> 6; |
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145 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
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146 | } |
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147 | radeon_crtc_load_lut(crtc); |
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148 | } |
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149 | |||
150 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
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151 | { |
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152 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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153 | |||
154 | drm_crtc_cleanup(crtc); |
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155 | kfree(radeon_crtc); |
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156 | } |
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157 | |||
158 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
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1221 | serge | 159 | .cursor_set = NULL, |
160 | .cursor_move = NULL, |
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1123 | serge | 161 | .gamma_set = radeon_crtc_gamma_set, |
1126 | serge | 162 | .set_config = drm_crtc_helper_set_config, |
1123 | serge | 163 | .destroy = radeon_crtc_destroy, |
164 | }; |
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165 | |||
166 | static void radeon_crtc_init(struct drm_device *dev, int index) |
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167 | { |
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168 | struct radeon_device *rdev = dev->dev_private; |
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169 | struct radeon_crtc *radeon_crtc; |
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170 | int i; |
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171 | |||
172 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
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173 | if (radeon_crtc == NULL) |
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174 | return; |
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175 | |||
176 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
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177 | |||
178 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
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179 | radeon_crtc->crtc_id = index; |
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1179 | serge | 180 | rdev->mode_info.crtcs[index] = radeon_crtc; |
1123 | serge | 181 | |
1179 | serge | 182 | #if 0 |
1123 | serge | 183 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
184 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
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185 | radeon_crtc->mode_set.num_connectors = 0; |
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1179 | serge | 186 | #endif |
1123 | serge | 187 | |
188 | for (i = 0; i < 256; i++) { |
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189 | radeon_crtc->lut_r[i] = i << 2; |
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190 | radeon_crtc->lut_g[i] = i << 2; |
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191 | radeon_crtc->lut_b[i] = i << 2; |
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192 | } |
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193 | |||
194 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
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195 | radeon_atombios_init_crtc(dev, radeon_crtc); |
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196 | else |
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197 | radeon_legacy_init_crtc(dev, radeon_crtc); |
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198 | } |
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199 | |||
200 | static const char *encoder_names[34] = { |
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201 | "NONE", |
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202 | "INTERNAL_LVDS", |
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203 | "INTERNAL_TMDS1", |
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204 | "INTERNAL_TMDS2", |
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205 | "INTERNAL_DAC1", |
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206 | "INTERNAL_DAC2", |
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207 | "INTERNAL_SDVOA", |
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208 | "INTERNAL_SDVOB", |
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209 | "SI170B", |
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210 | "CH7303", |
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211 | "CH7301", |
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212 | "INTERNAL_DVO1", |
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213 | "EXTERNAL_SDVOA", |
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214 | "EXTERNAL_SDVOB", |
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215 | "TITFP513", |
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216 | "INTERNAL_LVTM1", |
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217 | "VT1623", |
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218 | "HDMI_SI1930", |
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219 | "HDMI_INTERNAL", |
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220 | "INTERNAL_KLDSCP_TMDS1", |
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221 | "INTERNAL_KLDSCP_DVO1", |
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222 | "INTERNAL_KLDSCP_DAC1", |
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223 | "INTERNAL_KLDSCP_DAC2", |
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224 | "SI178", |
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225 | "MVPU_FPGA", |
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226 | "INTERNAL_DDI", |
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227 | "VT1625", |
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228 | "HDMI_SI1932", |
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229 | "DP_AN9801", |
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230 | "DP_DP501", |
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231 | "INTERNAL_UNIPHY", |
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232 | "INTERNAL_KLDSCP_LVTMA", |
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233 | "INTERNAL_UNIPHY1", |
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234 | "INTERNAL_UNIPHY2", |
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235 | }; |
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236 | |||
1404 | serge | 237 | static const char *connector_names[15] = { |
1123 | serge | 238 | "Unknown", |
239 | "VGA", |
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240 | "DVI-I", |
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241 | "DVI-D", |
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242 | "DVI-A", |
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243 | "Composite", |
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244 | "S-video", |
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245 | "LVDS", |
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246 | "Component", |
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247 | "DIN", |
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248 | "DisplayPort", |
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249 | "HDMI-A", |
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250 | "HDMI-B", |
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1404 | serge | 251 | "TV", |
252 | "eDP", |
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1123 | serge | 253 | }; |
254 | |||
1404 | serge | 255 | static const char *hpd_names[7] = { |
256 | "NONE", |
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257 | "HPD1", |
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258 | "HPD2", |
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259 | "HPD3", |
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260 | "HPD4", |
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261 | "HPD5", |
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262 | "HPD6", |
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263 | }; |
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264 | |||
1123 | serge | 265 | static void radeon_print_display_setup(struct drm_device *dev) |
266 | { |
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267 | struct drm_connector *connector; |
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268 | struct radeon_connector *radeon_connector; |
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269 | struct drm_encoder *encoder; |
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270 | struct radeon_encoder *radeon_encoder; |
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271 | uint32_t devices; |
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272 | int i = 0; |
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273 | |||
274 | DRM_INFO("Radeon Display Connectors\n"); |
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275 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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276 | radeon_connector = to_radeon_connector(connector); |
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277 | DRM_INFO("Connector %d:\n", i); |
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278 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
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1404 | serge | 279 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
280 | DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); |
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281 | if (radeon_connector->ddc_bus) { |
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1123 | serge | 282 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
283 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
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284 | radeon_connector->ddc_bus->rec.mask_data_reg, |
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285 | radeon_connector->ddc_bus->rec.a_clk_reg, |
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286 | radeon_connector->ddc_bus->rec.a_data_reg, |
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1404 | serge | 287 | radeon_connector->ddc_bus->rec.en_clk_reg, |
288 | radeon_connector->ddc_bus->rec.en_data_reg, |
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289 | radeon_connector->ddc_bus->rec.y_clk_reg, |
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290 | radeon_connector->ddc_bus->rec.y_data_reg); |
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291 | } else { |
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292 | if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || |
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293 | connector->connector_type == DRM_MODE_CONNECTOR_DVII || |
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294 | connector->connector_type == DRM_MODE_CONNECTOR_DVID || |
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295 | connector->connector_type == DRM_MODE_CONNECTOR_DVIA || |
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296 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || |
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297 | connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) |
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298 | DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); |
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299 | } |
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1123 | serge | 300 | DRM_INFO(" Encoders:\n"); |
301 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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302 | radeon_encoder = to_radeon_encoder(encoder); |
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303 | devices = radeon_encoder->devices & radeon_connector->devices; |
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304 | if (devices) { |
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305 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
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306 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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307 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
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308 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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309 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
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310 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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311 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
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312 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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313 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
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314 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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315 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
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316 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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317 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
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318 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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319 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
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320 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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321 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
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322 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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323 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
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324 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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325 | } |
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326 | } |
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327 | i++; |
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328 | } |
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329 | } |
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330 | |||
1179 | serge | 331 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
1123 | serge | 332 | { |
333 | struct radeon_device *rdev = dev->dev_private; |
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334 | struct drm_connector *drm_connector; |
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335 | bool ret = false; |
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336 | |||
337 | if (rdev->bios) { |
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338 | if (rdev->is_atom_bios) { |
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339 | if (rdev->family >= CHIP_R600) |
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340 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
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341 | else |
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342 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
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1404 | serge | 343 | } else { |
1123 | serge | 344 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
1404 | serge | 345 | if (ret == false) |
346 | ret = radeon_get_legacy_connector_info_from_table(dev); |
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347 | } |
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1123 | serge | 348 | } else { |
349 | if (!ASIC_IS_AVIVO(rdev)) |
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350 | ret = radeon_get_legacy_connector_info_from_table(dev); |
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351 | } |
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352 | if (ret) { |
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1404 | serge | 353 | radeon_setup_encoder_clones(dev); |
1123 | serge | 354 | radeon_print_display_setup(dev); |
355 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
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356 | radeon_ddc_dump(drm_connector); |
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357 | } |
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358 | |||
359 | return ret; |
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360 | } |
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361 | |||
362 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
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363 | { |
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364 | int ret = 0; |
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365 | |||
1404 | serge | 366 | if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || |
367 | (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { |
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368 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
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369 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || |
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370 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus) |
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371 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); |
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372 | } |
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1123 | serge | 373 | if (!radeon_connector->ddc_bus) |
374 | return -1; |
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1179 | serge | 375 | if (!radeon_connector->edid) { |
1404 | serge | 376 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
1268 | serge | 377 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
1404 | serge | 378 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
1268 | serge | 379 | } |
1179 | serge | 380 | |
1268 | serge | 381 | if (radeon_connector->edid) { |
382 | drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid); |
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383 | ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid); |
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1123 | serge | 384 | return ret; |
385 | } |
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386 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
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1179 | serge | 387 | return 0; |
1123 | serge | 388 | } |
389 | |||
390 | static int radeon_ddc_dump(struct drm_connector *connector) |
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391 | { |
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392 | struct edid *edid; |
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393 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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394 | int ret = 0; |
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395 | |||
396 | if (!radeon_connector->ddc_bus) |
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397 | return -1; |
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1404 | serge | 398 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); |
1123 | serge | 399 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
1404 | serge | 400 | radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); |
1123 | serge | 401 | if (edid) { |
402 | kfree(edid); |
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403 | } |
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404 | return ret; |
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405 | } |
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406 | |||
407 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
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408 | { |
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409 | uint64_t mod; |
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410 | |||
411 | n += d / 2; |
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412 | |||
413 | mod = do_div(n, d); |
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414 | return n; |
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415 | } |
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416 | |||
417 | void radeon_compute_pll(struct radeon_pll *pll, |
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418 | uint64_t freq, |
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419 | uint32_t *dot_clock_p, |
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420 | uint32_t *fb_div_p, |
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421 | uint32_t *frac_fb_div_p, |
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422 | uint32_t *ref_div_p, |
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1404 | serge | 423 | uint32_t *post_div_p) |
1123 | serge | 424 | { |
425 | uint32_t min_ref_div = pll->min_ref_div; |
||
426 | uint32_t max_ref_div = pll->max_ref_div; |
||
1404 | serge | 427 | uint32_t min_post_div = pll->min_post_div; |
428 | uint32_t max_post_div = pll->max_post_div; |
||
1123 | serge | 429 | uint32_t min_fractional_feed_div = 0; |
430 | uint32_t max_fractional_feed_div = 0; |
||
431 | uint32_t best_vco = pll->best_vco; |
||
432 | uint32_t best_post_div = 1; |
||
433 | uint32_t best_ref_div = 1; |
||
434 | uint32_t best_feedback_div = 1; |
||
435 | uint32_t best_frac_feedback_div = 0; |
||
436 | uint32_t best_freq = -1; |
||
437 | uint32_t best_error = 0xffffffff; |
||
438 | uint32_t best_vco_diff = 1; |
||
439 | uint32_t post_div; |
||
440 | |||
441 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
||
442 | freq = freq * 1000; |
||
443 | |||
1404 | serge | 444 | if (pll->flags & RADEON_PLL_USE_REF_DIV) |
1123 | serge | 445 | min_ref_div = max_ref_div = pll->reference_div; |
446 | else { |
||
447 | while (min_ref_div < max_ref_div-1) { |
||
448 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
||
449 | uint32_t pll_in = pll->reference_freq / mid; |
||
450 | if (pll_in < pll->pll_in_min) |
||
451 | max_ref_div = mid; |
||
452 | else if (pll_in > pll->pll_in_max) |
||
453 | min_ref_div = mid; |
||
454 | else |
||
455 | break; |
||
456 | } |
||
457 | } |
||
458 | |||
1404 | serge | 459 | if (pll->flags & RADEON_PLL_USE_POST_DIV) |
460 | min_post_div = max_post_div = pll->post_div; |
||
461 | |||
462 | if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
1123 | serge | 463 | min_fractional_feed_div = pll->min_frac_feedback_div; |
464 | max_fractional_feed_div = pll->max_frac_feedback_div; |
||
465 | } |
||
466 | |||
1404 | serge | 467 | for (post_div = min_post_div; post_div <= max_post_div; ++post_div) { |
1123 | serge | 468 | uint32_t ref_div; |
469 | |||
1404 | serge | 470 | if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
1123 | serge | 471 | continue; |
472 | |||
473 | /* legacy radeons only have a few post_divs */ |
||
1404 | serge | 474 | if (pll->flags & RADEON_PLL_LEGACY) { |
1123 | serge | 475 | if ((post_div == 5) || |
476 | (post_div == 7) || |
||
477 | (post_div == 9) || |
||
478 | (post_div == 10) || |
||
479 | (post_div == 11) || |
||
480 | (post_div == 13) || |
||
481 | (post_div == 14) || |
||
482 | (post_div == 15)) |
||
483 | continue; |
||
484 | } |
||
485 | |||
486 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
||
487 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
||
488 | uint32_t pll_in = pll->reference_freq / ref_div; |
||
489 | uint32_t min_feed_div = pll->min_feedback_div; |
||
490 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
||
491 | |||
492 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
||
493 | continue; |
||
494 | |||
495 | while (min_feed_div < max_feed_div) { |
||
496 | uint32_t vco; |
||
497 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
||
498 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
||
499 | uint32_t frac_feedback_div; |
||
500 | uint64_t tmp; |
||
501 | |||
502 | feedback_div = (min_feed_div + max_feed_div) / 2; |
||
503 | |||
504 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
||
505 | vco = radeon_div(tmp, ref_div); |
||
506 | |||
507 | if (vco < pll->pll_out_min) { |
||
508 | min_feed_div = feedback_div + 1; |
||
509 | continue; |
||
510 | } else if (vco > pll->pll_out_max) { |
||
511 | max_feed_div = feedback_div; |
||
512 | continue; |
||
513 | } |
||
514 | |||
515 | while (min_frac_feed_div < max_frac_feed_div) { |
||
516 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
||
517 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
||
518 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
||
519 | current_freq = radeon_div(tmp, ref_div * post_div); |
||
520 | |||
1404 | serge | 521 | if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
1179 | serge | 522 | error = freq - current_freq; |
523 | error = error < 0 ? 0xffffffff : error; |
||
524 | } else |
||
1123 | serge | 525 | error = abs(current_freq - freq); |
526 | vco_diff = abs(vco - best_vco); |
||
527 | |||
528 | if ((best_vco == 0 && error < best_error) || |
||
529 | (best_vco != 0 && |
||
530 | (error < best_error - 100 || |
||
531 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
||
532 | best_post_div = post_div; |
||
533 | best_ref_div = ref_div; |
||
534 | best_feedback_div = feedback_div; |
||
535 | best_frac_feedback_div = frac_feedback_div; |
||
536 | best_freq = current_freq; |
||
537 | best_error = error; |
||
538 | best_vco_diff = vco_diff; |
||
539 | } else if (current_freq == freq) { |
||
540 | if (best_freq == -1) { |
||
541 | best_post_div = post_div; |
||
542 | best_ref_div = ref_div; |
||
543 | best_feedback_div = feedback_div; |
||
544 | best_frac_feedback_div = frac_feedback_div; |
||
545 | best_freq = current_freq; |
||
546 | best_error = error; |
||
547 | best_vco_diff = vco_diff; |
||
1404 | serge | 548 | } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
549 | ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
||
550 | ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
||
551 | ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
||
552 | ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
||
553 | ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
||
1123 | serge | 554 | best_post_div = post_div; |
555 | best_ref_div = ref_div; |
||
556 | best_feedback_div = feedback_div; |
||
557 | best_frac_feedback_div = frac_feedback_div; |
||
558 | best_freq = current_freq; |
||
559 | best_error = error; |
||
560 | best_vco_diff = vco_diff; |
||
561 | } |
||
562 | } |
||
563 | if (current_freq < freq) |
||
564 | min_frac_feed_div = frac_feedback_div + 1; |
||
565 | else |
||
566 | max_frac_feed_div = frac_feedback_div; |
||
567 | } |
||
568 | if (current_freq < freq) |
||
569 | min_feed_div = feedback_div + 1; |
||
570 | else |
||
571 | max_feed_div = feedback_div; |
||
572 | } |
||
573 | } |
||
574 | } |
||
575 | |||
576 | *dot_clock_p = best_freq / 10000; |
||
577 | *fb_div_p = best_feedback_div; |
||
578 | *frac_fb_div_p = best_frac_feedback_div; |
||
579 | *ref_div_p = best_ref_div; |
||
580 | *post_div_p = best_post_div; |
||
581 | } |
||
582 | |||
1404 | serge | 583 | void radeon_compute_pll_avivo(struct radeon_pll *pll, |
584 | uint64_t freq, |
||
585 | uint32_t *dot_clock_p, |
||
586 | uint32_t *fb_div_p, |
||
587 | uint32_t *frac_fb_div_p, |
||
588 | uint32_t *ref_div_p, |
||
589 | uint32_t *post_div_p) |
||
590 | { |
||
591 | fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; |
||
592 | fixed20_12 pll_out_max, pll_out_min; |
||
593 | fixed20_12 pll_in_max, pll_in_min; |
||
594 | fixed20_12 reference_freq; |
||
595 | fixed20_12 error, ffreq, a, b; |
||
596 | |||
597 | pll_out_max.full = rfixed_const(pll->pll_out_max); |
||
598 | pll_out_min.full = rfixed_const(pll->pll_out_min); |
||
599 | pll_in_max.full = rfixed_const(pll->pll_in_max); |
||
600 | pll_in_min.full = rfixed_const(pll->pll_in_min); |
||
601 | reference_freq.full = rfixed_const(pll->reference_freq); |
||
602 | do_div(freq, 10); |
||
603 | ffreq.full = rfixed_const(freq); |
||
604 | error.full = rfixed_const(100 * 100); |
||
605 | |||
606 | /* max p */ |
||
607 | p.full = rfixed_div(pll_out_max, ffreq); |
||
608 | p.full = rfixed_floor(p); |
||
609 | |||
610 | /* min m */ |
||
611 | m.full = rfixed_div(reference_freq, pll_in_max); |
||
612 | m.full = rfixed_ceil(m); |
||
613 | |||
614 | while (1) { |
||
615 | n.full = rfixed_div(ffreq, reference_freq); |
||
616 | n.full = rfixed_mul(n, m); |
||
617 | n.full = rfixed_mul(n, p); |
||
618 | |||
619 | f_vco.full = rfixed_div(n, m); |
||
620 | f_vco.full = rfixed_mul(f_vco, reference_freq); |
||
621 | |||
622 | f_pclk.full = rfixed_div(f_vco, p); |
||
623 | |||
624 | if (f_pclk.full > ffreq.full) |
||
625 | error.full = f_pclk.full - ffreq.full; |
||
626 | else |
||
627 | error.full = ffreq.full - f_pclk.full; |
||
628 | error.full = rfixed_div(error, f_pclk); |
||
629 | a.full = rfixed_const(100 * 100); |
||
630 | error.full = rfixed_mul(error, a); |
||
631 | |||
632 | a.full = rfixed_mul(m, p); |
||
633 | a.full = rfixed_div(n, a); |
||
634 | best_freq.full = rfixed_mul(reference_freq, a); |
||
635 | |||
636 | if (rfixed_trunc(error) < 25) |
||
637 | break; |
||
638 | |||
639 | a.full = rfixed_const(1); |
||
640 | m.full = m.full + a.full; |
||
641 | a.full = rfixed_div(reference_freq, m); |
||
642 | if (a.full >= pll_in_min.full) |
||
643 | continue; |
||
644 | |||
645 | m.full = rfixed_div(reference_freq, pll_in_max); |
||
646 | m.full = rfixed_ceil(m); |
||
647 | a.full= rfixed_const(1); |
||
648 | p.full = p.full - a.full; |
||
649 | a.full = rfixed_mul(p, ffreq); |
||
650 | if (a.full >= pll_out_min.full) |
||
651 | continue; |
||
652 | else { |
||
653 | DRM_ERROR("Unable to find pll dividers\n"); |
||
654 | break; |
||
655 | } |
||
656 | } |
||
657 | |||
658 | a.full = rfixed_const(10); |
||
659 | b.full = rfixed_mul(n, a); |
||
660 | |||
661 | frac_n.full = rfixed_floor(n); |
||
662 | frac_n.full = rfixed_mul(frac_n, a); |
||
663 | frac_n.full = b.full - frac_n.full; |
||
664 | |||
665 | *dot_clock_p = rfixed_trunc(best_freq); |
||
666 | *fb_div_p = rfixed_trunc(n); |
||
667 | *frac_fb_div_p = rfixed_trunc(frac_n); |
||
668 | *ref_div_p = rfixed_trunc(m); |
||
669 | *post_div_p = rfixed_trunc(p); |
||
670 | |||
671 | DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p); |
||
672 | } |
||
673 | |||
1123 | serge | 674 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
675 | { |
||
676 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
677 | struct drm_device *dev = fb->dev; |
||
678 | |||
679 | if (fb->fbdev) |
||
680 | radeonfb_remove(dev, fb); |
||
681 | |||
682 | // if (radeon_fb->obj) { |
||
683 | // radeon_gem_object_unpin(radeon_fb->obj); |
||
684 | // mutex_lock(&dev->struct_mutex); |
||
685 | // drm_gem_object_unreference(radeon_fb->obj); |
||
686 | // mutex_unlock(&dev->struct_mutex); |
||
687 | // } |
||
688 | drm_framebuffer_cleanup(fb); |
||
689 | kfree(radeon_fb); |
||
690 | } |
||
691 | |||
692 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
||
693 | struct drm_file *file_priv, |
||
694 | unsigned int *handle) |
||
695 | { |
||
696 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
697 | |||
698 | return NULL; |
||
699 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
||
700 | } |
||
701 | |||
702 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
||
703 | .destroy = radeon_user_framebuffer_destroy, |
||
704 | .create_handle = radeon_user_framebuffer_create_handle, |
||
705 | }; |
||
706 | |||
707 | struct drm_framebuffer * |
||
708 | radeon_framebuffer_create(struct drm_device *dev, |
||
709 | struct drm_mode_fb_cmd *mode_cmd, |
||
710 | struct drm_gem_object *obj) |
||
711 | { |
||
712 | struct radeon_framebuffer *radeon_fb; |
||
713 | |||
1179 | serge | 714 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); |
1123 | serge | 715 | if (radeon_fb == NULL) { |
716 | return NULL; |
||
717 | } |
||
1126 | serge | 718 | drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); |
719 | drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); |
||
1123 | serge | 720 | radeon_fb->obj = obj; |
721 | return &radeon_fb->base; |
||
722 | } |
||
723 | |||
724 | static struct drm_framebuffer * |
||
725 | radeon_user_framebuffer_create(struct drm_device *dev, |
||
726 | struct drm_file *file_priv, |
||
727 | struct drm_mode_fb_cmd *mode_cmd) |
||
728 | { |
||
729 | struct drm_gem_object *obj; |
||
730 | |||
1125 | serge | 731 | return NULL; |
1123 | serge | 732 | |
1125 | serge | 733 | // obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); |
734 | // |
||
735 | // return radeon_framebuffer_create(dev, mode_cmd, obj); |
||
1123 | serge | 736 | } |
737 | |||
738 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
||
1125 | serge | 739 | // .fb_create = radeon_user_framebuffer_create, |
1126 | serge | 740 | .fb_changed = radeonfb_probe, |
1123 | serge | 741 | }; |
742 | |||
1179 | serge | 743 | struct drm_prop_enum_list { |
744 | int type; |
||
745 | char *name; |
||
746 | }; |
||
747 | |||
748 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
||
749 | { { 0, "driver" }, |
||
750 | { 1, "bios" }, |
||
751 | }; |
||
752 | |||
753 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
||
754 | { { TV_STD_NTSC, "ntsc" }, |
||
755 | { TV_STD_PAL, "pal" }, |
||
756 | { TV_STD_PAL_M, "pal-m" }, |
||
757 | { TV_STD_PAL_60, "pal-60" }, |
||
758 | { TV_STD_NTSC_J, "ntsc-j" }, |
||
759 | { TV_STD_SCART_PAL, "scart-pal" }, |
||
760 | { TV_STD_PAL_CN, "pal-cn" }, |
||
761 | { TV_STD_SECAM, "secam" }, |
||
762 | }; |
||
763 | |||
1404 | serge | 764 | static int radeon_modeset_create_props(struct radeon_device *rdev) |
1123 | serge | 765 | { |
1179 | serge | 766 | int i, sz; |
1125 | serge | 767 | |
1179 | serge | 768 | if (rdev->is_atom_bios) { |
769 | rdev->mode_info.coherent_mode_property = |
||
770 | drm_property_create(rdev->ddev, |
||
771 | DRM_MODE_PROP_RANGE, |
||
772 | "coherent", 2); |
||
773 | if (!rdev->mode_info.coherent_mode_property) |
||
774 | return -ENOMEM; |
||
1125 | serge | 775 | |
1179 | serge | 776 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
1404 | serge | 777 | rdev->mode_info.coherent_mode_property->values[1] = 1; |
1179 | serge | 778 | } |
779 | |||
780 | if (!ASIC_IS_AVIVO(rdev)) { |
||
781 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
||
782 | rdev->mode_info.tmds_pll_property = |
||
783 | drm_property_create(rdev->ddev, |
||
784 | DRM_MODE_PROP_ENUM, |
||
785 | "tmds_pll", sz); |
||
786 | for (i = 0; i < sz; i++) { |
||
787 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
||
788 | i, |
||
789 | radeon_tmds_pll_enum_list[i].type, |
||
790 | radeon_tmds_pll_enum_list[i].name); |
||
791 | } |
||
792 | } |
||
793 | |||
794 | rdev->mode_info.load_detect_property = |
||
795 | drm_property_create(rdev->ddev, |
||
796 | DRM_MODE_PROP_RANGE, |
||
797 | "load detection", 2); |
||
798 | if (!rdev->mode_info.load_detect_property) |
||
799 | return -ENOMEM; |
||
800 | rdev->mode_info.load_detect_property->values[0] = 0; |
||
1404 | serge | 801 | rdev->mode_info.load_detect_property->values[1] = 1; |
1179 | serge | 802 | |
803 | drm_mode_create_scaling_mode_property(rdev->ddev); |
||
804 | |||
805 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
||
806 | rdev->mode_info.tv_std_property = |
||
807 | drm_property_create(rdev->ddev, |
||
808 | DRM_MODE_PROP_ENUM, |
||
809 | "tv standard", sz); |
||
810 | for (i = 0; i < sz; i++) { |
||
811 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
||
812 | i, |
||
813 | radeon_tv_std_enum_list[i].type, |
||
814 | radeon_tv_std_enum_list[i].name); |
||
815 | } |
||
816 | |||
817 | return 0; |
||
818 | } |
||
819 | |||
820 | int radeon_modeset_init(struct radeon_device *rdev) |
||
821 | { |
||
1123 | serge | 822 | int num_crtc = 2, i; |
823 | int ret; |
||
824 | |||
825 | drm_mode_config_init(rdev->ddev); |
||
826 | rdev->mode_info.mode_config_initialized = true; |
||
827 | |||
1125 | serge | 828 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1123 | serge | 829 | |
830 | if (ASIC_IS_AVIVO(rdev)) { |
||
831 | rdev->ddev->mode_config.max_width = 8192; |
||
832 | rdev->ddev->mode_config.max_height = 8192; |
||
833 | } else { |
||
834 | rdev->ddev->mode_config.max_width = 4096; |
||
835 | rdev->ddev->mode_config.max_height = 4096; |
||
836 | } |
||
837 | |||
838 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
||
839 | |||
1179 | serge | 840 | ret = radeon_modeset_create_props(rdev); |
841 | if (ret) { |
||
842 | return ret; |
||
843 | } |
||
1221 | serge | 844 | |
845 | if (rdev->flags & RADEON_SINGLE_CRTC) |
||
846 | num_crtc = 1; |
||
847 | |||
848 | /* allocate crtcs */ |
||
1123 | serge | 849 | for (i = 0; i < num_crtc; i++) { |
850 | radeon_crtc_init(rdev->ddev, i); |
||
851 | } |
||
852 | |||
853 | /* okay we should have all the bios connectors */ |
||
854 | ret = radeon_setup_enc_conn(rdev->ddev); |
||
855 | if (!ret) { |
||
856 | return ret; |
||
857 | } |
||
1404 | serge | 858 | /* initialize hpd */ |
859 | radeon_hpd_init(rdev); |
||
1123 | serge | 860 | drm_helper_initial_config(rdev->ddev); |
861 | return 0; |
||
862 | } |
||
863 | |||
864 | void radeon_modeset_fini(struct radeon_device *rdev) |
||
865 | { |
||
866 | if (rdev->mode_info.mode_config_initialized) { |
||
1404 | serge | 867 | radeon_hpd_fini(rdev); |
1123 | serge | 868 | drm_mode_config_cleanup(rdev->ddev); |
869 | rdev->mode_info.mode_config_initialized = false; |
||
870 | } |
||
871 | } |
||
872 | |||
1179 | serge | 873 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
874 | struct drm_display_mode *mode, |
||
875 | struct drm_display_mode *adjusted_mode) |
||
1123 | serge | 876 | { |
1179 | serge | 877 | struct drm_device *dev = crtc->dev; |
878 | struct drm_encoder *encoder; |
||
1123 | serge | 879 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1179 | serge | 880 | struct radeon_encoder *radeon_encoder; |
881 | bool first = true; |
||
1123 | serge | 882 | |
1179 | serge | 883 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
884 | radeon_encoder = to_radeon_encoder(encoder); |
||
885 | if (encoder->crtc != crtc) |
||
886 | continue; |
||
887 | if (first) { |
||
1404 | serge | 888 | /* set scaling */ |
889 | if (radeon_encoder->rmx_type == RMX_OFF) |
||
890 | radeon_crtc->rmx_type = RMX_OFF; |
||
891 | else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay || |
||
892 | mode->vdisplay < radeon_encoder->native_mode.vdisplay) |
||
1179 | serge | 893 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
1404 | serge | 894 | else |
895 | radeon_crtc->rmx_type = RMX_OFF; |
||
896 | /* copy native mode */ |
||
1179 | serge | 897 | memcpy(&radeon_crtc->native_mode, |
898 | &radeon_encoder->native_mode, |
||
1268 | serge | 899 | sizeof(struct drm_display_mode)); |
1179 | serge | 900 | first = false; |
901 | } else { |
||
902 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
||
903 | /* WARNING: Right now this can't happen but |
||
904 | * in the future we need to check that scaling |
||
905 | * are consistent accross different encoder |
||
906 | * (ie all encoder can work with the same |
||
907 | * scaling). |
||
908 | */ |
||
909 | DRM_ERROR("Scaling not consistent accross encoder.\n"); |
||
910 | return false; |
||
911 | } |
||
1123 | serge | 912 | } |
913 | } |
||
1179 | serge | 914 | if (radeon_crtc->rmx_type != RMX_OFF) { |
1221 | serge | 915 | fixed20_12 a, b; |
1179 | serge | 916 | a.full = rfixed_const(crtc->mode.vdisplay); |
1268 | serge | 917 | b.full = rfixed_const(radeon_crtc->native_mode.hdisplay); |
1179 | serge | 918 | radeon_crtc->vsc.full = rfixed_div(a, b); |
919 | a.full = rfixed_const(crtc->mode.hdisplay); |
||
1268 | serge | 920 | b.full = rfixed_const(radeon_crtc->native_mode.vdisplay); |
1179 | serge | 921 | radeon_crtc->hsc.full = rfixed_div(a, b); |
1123 | serge | 922 | } else { |
1179 | serge | 923 | radeon_crtc->vsc.full = rfixed_const(1); |
924 | radeon_crtc->hsc.full = rfixed_const(1); |
||
1123 | serge | 925 | } |
1179 | serge | 926 | return true; |
1123 | serge | 927 | }>>>>>>>>>>>>>>>>>>>>=>=>>>><>><>><>>>><>><>><>><>><>><>>><>><>><>> |