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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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26 | #include "drmP.h" |
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27 | #include "radeon_drm.h" |
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28 | #include "radeon.h" |
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29 | |||
30 | #include "atom.h" |
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31 | //#include |
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32 | |||
33 | #include "drm_crtc_helper.h" |
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34 | #include "drm_edid.h" |
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35 | |||
36 | static int radeon_ddc_dump(struct drm_connector *connector); |
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37 | |||
38 | static void avivo_crtc_load_lut(struct drm_crtc *crtc) |
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39 | { |
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40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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41 | struct drm_device *dev = crtc->dev; |
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42 | struct radeon_device *rdev = dev->dev_private; |
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43 | int i; |
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44 | |||
45 | DRM_DEBUG("%d\n", radeon_crtc->crtc_id); |
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46 | WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); |
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47 | |||
48 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); |
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49 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); |
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50 | WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); |
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51 | |||
52 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); |
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53 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); |
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54 | WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); |
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55 | |||
56 | WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); |
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57 | WREG32(AVIVO_DC_LUT_RW_MODE, 0); |
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58 | WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f); |
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59 | |||
60 | WREG8(AVIVO_DC_LUT_RW_INDEX, 0); |
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61 | for (i = 0; i < 256; i++) { |
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62 | WREG32(AVIVO_DC_LUT_30_COLOR, |
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63 | (radeon_crtc->lut_r[i] << 20) | |
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64 | (radeon_crtc->lut_g[i] << 10) | |
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65 | (radeon_crtc->lut_b[i] << 0)); |
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66 | } |
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67 | |||
68 | WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); |
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69 | } |
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70 | |||
71 | static void legacy_crtc_load_lut(struct drm_crtc *crtc) |
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72 | { |
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73 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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74 | struct drm_device *dev = crtc->dev; |
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75 | struct radeon_device *rdev = dev->dev_private; |
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76 | int i; |
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77 | uint32_t dac2_cntl; |
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78 | |||
79 | dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
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80 | if (radeon_crtc->crtc_id == 0) |
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81 | dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL; |
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82 | else |
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83 | dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL; |
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84 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
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85 | |||
86 | WREG8(RADEON_PALETTE_INDEX, 0); |
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87 | for (i = 0; i < 256; i++) { |
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88 | WREG32(RADEON_PALETTE_30_DATA, |
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89 | (radeon_crtc->lut_r[i] << 20) | |
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90 | (radeon_crtc->lut_g[i] << 10) | |
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91 | (radeon_crtc->lut_b[i] << 0)); |
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92 | } |
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93 | } |
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94 | |||
95 | void radeon_crtc_load_lut(struct drm_crtc *crtc) |
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96 | { |
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97 | struct drm_device *dev = crtc->dev; |
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98 | struct radeon_device *rdev = dev->dev_private; |
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99 | |||
100 | if (!crtc->enabled) |
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101 | return; |
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102 | |||
103 | if (ASIC_IS_AVIVO(rdev)) |
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104 | avivo_crtc_load_lut(crtc); |
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105 | else |
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106 | legacy_crtc_load_lut(crtc); |
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107 | } |
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108 | |||
109 | /** Sets the color ramps on behalf of RandR */ |
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110 | void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
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111 | u16 blue, int regno) |
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112 | { |
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113 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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114 | |||
115 | if (regno == 0) |
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116 | DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id); |
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117 | radeon_crtc->lut_r[regno] = red >> 6; |
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118 | radeon_crtc->lut_g[regno] = green >> 6; |
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119 | radeon_crtc->lut_b[regno] = blue >> 6; |
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120 | } |
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121 | |||
122 | static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
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123 | u16 *blue, uint32_t size) |
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124 | { |
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125 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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126 | int i, j; |
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127 | |||
128 | if (size != 256) { |
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129 | return; |
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130 | } |
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131 | if (crtc->fb == NULL) { |
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132 | return; |
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133 | } |
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134 | |||
135 | if (crtc->fb->depth == 16) { |
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136 | for (i = 0; i < 64; i++) { |
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137 | if (i <= 31) { |
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138 | for (j = 0; j < 8; j++) { |
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139 | radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6; |
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140 | radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6; |
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141 | } |
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142 | } |
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143 | for (j = 0; j < 4; j++) |
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144 | radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6; |
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145 | } |
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146 | } else { |
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147 | for (i = 0; i < 256; i++) { |
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148 | radeon_crtc->lut_r[i] = red[i] >> 6; |
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149 | radeon_crtc->lut_g[i] = green[i] >> 6; |
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150 | radeon_crtc->lut_b[i] = blue[i] >> 6; |
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151 | } |
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152 | } |
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153 | |||
154 | radeon_crtc_load_lut(crtc); |
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155 | } |
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156 | |||
157 | static void radeon_crtc_destroy(struct drm_crtc *crtc) |
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158 | { |
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159 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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160 | |||
161 | drm_crtc_cleanup(crtc); |
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162 | kfree(radeon_crtc); |
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163 | } |
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164 | |||
165 | static const struct drm_crtc_funcs radeon_crtc_funcs = { |
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166 | // .cursor_set = radeon_crtc_cursor_set, |
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1179 | serge | 167 | .cursor_move = radeon_crtc_cursor_move, |
1123 | serge | 168 | .gamma_set = radeon_crtc_gamma_set, |
1126 | serge | 169 | .set_config = drm_crtc_helper_set_config, |
1123 | serge | 170 | .destroy = radeon_crtc_destroy, |
171 | }; |
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172 | |||
173 | static void radeon_crtc_init(struct drm_device *dev, int index) |
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174 | { |
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175 | struct radeon_device *rdev = dev->dev_private; |
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176 | struct radeon_crtc *radeon_crtc; |
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177 | int i; |
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178 | |||
179 | radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
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180 | if (radeon_crtc == NULL) |
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181 | return; |
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182 | |||
183 | drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); |
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184 | |||
185 | drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); |
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186 | radeon_crtc->crtc_id = index; |
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1179 | serge | 187 | rdev->mode_info.crtcs[index] = radeon_crtc; |
1123 | serge | 188 | |
1179 | serge | 189 | #if 0 |
1123 | serge | 190 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
191 | radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); |
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192 | radeon_crtc->mode_set.num_connectors = 0; |
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1179 | serge | 193 | #endif |
1123 | serge | 194 | |
195 | for (i = 0; i < 256; i++) { |
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196 | radeon_crtc->lut_r[i] = i << 2; |
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197 | radeon_crtc->lut_g[i] = i << 2; |
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198 | radeon_crtc->lut_b[i] = i << 2; |
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199 | } |
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200 | |||
201 | if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)) |
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202 | radeon_atombios_init_crtc(dev, radeon_crtc); |
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203 | else |
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204 | radeon_legacy_init_crtc(dev, radeon_crtc); |
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205 | } |
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206 | |||
207 | static const char *encoder_names[34] = { |
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208 | "NONE", |
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209 | "INTERNAL_LVDS", |
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210 | "INTERNAL_TMDS1", |
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211 | "INTERNAL_TMDS2", |
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212 | "INTERNAL_DAC1", |
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213 | "INTERNAL_DAC2", |
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214 | "INTERNAL_SDVOA", |
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215 | "INTERNAL_SDVOB", |
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216 | "SI170B", |
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217 | "CH7303", |
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218 | "CH7301", |
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219 | "INTERNAL_DVO1", |
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220 | "EXTERNAL_SDVOA", |
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221 | "EXTERNAL_SDVOB", |
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222 | "TITFP513", |
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223 | "INTERNAL_LVTM1", |
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224 | "VT1623", |
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225 | "HDMI_SI1930", |
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226 | "HDMI_INTERNAL", |
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227 | "INTERNAL_KLDSCP_TMDS1", |
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228 | "INTERNAL_KLDSCP_DVO1", |
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229 | "INTERNAL_KLDSCP_DAC1", |
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230 | "INTERNAL_KLDSCP_DAC2", |
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231 | "SI178", |
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232 | "MVPU_FPGA", |
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233 | "INTERNAL_DDI", |
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234 | "VT1625", |
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235 | "HDMI_SI1932", |
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236 | "DP_AN9801", |
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237 | "DP_DP501", |
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238 | "INTERNAL_UNIPHY", |
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239 | "INTERNAL_KLDSCP_LVTMA", |
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240 | "INTERNAL_UNIPHY1", |
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241 | "INTERNAL_UNIPHY2", |
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242 | }; |
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243 | |||
244 | static const char *connector_names[13] = { |
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245 | "Unknown", |
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246 | "VGA", |
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247 | "DVI-I", |
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248 | "DVI-D", |
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249 | "DVI-A", |
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250 | "Composite", |
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251 | "S-video", |
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252 | "LVDS", |
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253 | "Component", |
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254 | "DIN", |
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255 | "DisplayPort", |
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256 | "HDMI-A", |
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257 | "HDMI-B", |
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258 | }; |
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259 | |||
260 | static void radeon_print_display_setup(struct drm_device *dev) |
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261 | { |
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262 | struct drm_connector *connector; |
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263 | struct radeon_connector *radeon_connector; |
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264 | struct drm_encoder *encoder; |
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265 | struct radeon_encoder *radeon_encoder; |
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266 | uint32_t devices; |
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267 | int i = 0; |
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268 | |||
269 | DRM_INFO("Radeon Display Connectors\n"); |
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270 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
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271 | radeon_connector = to_radeon_connector(connector); |
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272 | DRM_INFO("Connector %d:\n", i); |
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273 | DRM_INFO(" %s\n", connector_names[connector->connector_type]); |
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274 | if (radeon_connector->ddc_bus) |
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275 | DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
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276 | radeon_connector->ddc_bus->rec.mask_clk_reg, |
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277 | radeon_connector->ddc_bus->rec.mask_data_reg, |
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278 | radeon_connector->ddc_bus->rec.a_clk_reg, |
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279 | radeon_connector->ddc_bus->rec.a_data_reg, |
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280 | radeon_connector->ddc_bus->rec.put_clk_reg, |
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281 | radeon_connector->ddc_bus->rec.put_data_reg, |
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282 | radeon_connector->ddc_bus->rec.get_clk_reg, |
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283 | radeon_connector->ddc_bus->rec.get_data_reg); |
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284 | DRM_INFO(" Encoders:\n"); |
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285 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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286 | radeon_encoder = to_radeon_encoder(encoder); |
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287 | devices = radeon_encoder->devices & radeon_connector->devices; |
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288 | if (devices) { |
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289 | if (devices & ATOM_DEVICE_CRT1_SUPPORT) |
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290 | DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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291 | if (devices & ATOM_DEVICE_CRT2_SUPPORT) |
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292 | DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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293 | if (devices & ATOM_DEVICE_LCD1_SUPPORT) |
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294 | DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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295 | if (devices & ATOM_DEVICE_DFP1_SUPPORT) |
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296 | DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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297 | if (devices & ATOM_DEVICE_DFP2_SUPPORT) |
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298 | DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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299 | if (devices & ATOM_DEVICE_DFP3_SUPPORT) |
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300 | DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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301 | if (devices & ATOM_DEVICE_DFP4_SUPPORT) |
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302 | DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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303 | if (devices & ATOM_DEVICE_DFP5_SUPPORT) |
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304 | DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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305 | if (devices & ATOM_DEVICE_TV1_SUPPORT) |
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306 | DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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307 | if (devices & ATOM_DEVICE_CV_SUPPORT) |
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308 | DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]); |
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309 | } |
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310 | } |
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311 | i++; |
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312 | } |
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313 | } |
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314 | |||
1179 | serge | 315 | static bool radeon_setup_enc_conn(struct drm_device *dev) |
1123 | serge | 316 | { |
317 | struct radeon_device *rdev = dev->dev_private; |
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318 | struct drm_connector *drm_connector; |
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319 | bool ret = false; |
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320 | |||
321 | if (rdev->bios) { |
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322 | if (rdev->is_atom_bios) { |
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323 | if (rdev->family >= CHIP_R600) |
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324 | ret = radeon_get_atom_connector_info_from_object_table(dev); |
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325 | else |
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326 | ret = radeon_get_atom_connector_info_from_supported_devices_table(dev); |
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327 | } else |
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328 | ret = radeon_get_legacy_connector_info_from_bios(dev); |
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329 | } else { |
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330 | if (!ASIC_IS_AVIVO(rdev)) |
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331 | ret = radeon_get_legacy_connector_info_from_table(dev); |
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332 | } |
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333 | if (ret) { |
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334 | radeon_print_display_setup(dev); |
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335 | list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) |
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336 | radeon_ddc_dump(drm_connector); |
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337 | } |
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338 | |||
339 | return ret; |
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340 | } |
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341 | |||
342 | int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) |
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343 | { |
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344 | struct edid *edid; |
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345 | int ret = 0; |
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346 | |||
347 | if (!radeon_connector->ddc_bus) |
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348 | return -1; |
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1179 | serge | 349 | if (!radeon_connector->edid) { |
1123 | serge | 350 | radeon_i2c_do_lock(radeon_connector, 1); |
351 | edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); |
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352 | radeon_i2c_do_lock(radeon_connector, 0); |
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1179 | serge | 353 | } else |
354 | edid = radeon_connector->edid; |
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355 | |||
1123 | serge | 356 | if (edid) { |
357 | /* update digital bits here */ |
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358 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
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359 | radeon_connector->use_digital = 1; |
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360 | else |
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361 | radeon_connector->use_digital = 0; |
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362 | drm_mode_connector_update_edid_property(&radeon_connector->base, edid); |
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363 | ret = drm_add_edid_modes(&radeon_connector->base, edid); |
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364 | kfree(edid); |
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365 | return ret; |
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366 | } |
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367 | drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); |
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1179 | serge | 368 | return 0; |
1123 | serge | 369 | } |
370 | |||
371 | static int radeon_ddc_dump(struct drm_connector *connector) |
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372 | { |
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373 | struct edid *edid; |
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374 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
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375 | int ret = 0; |
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376 | |||
377 | if (!radeon_connector->ddc_bus) |
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378 | return -1; |
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379 | radeon_i2c_do_lock(radeon_connector, 1); |
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380 | edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); |
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381 | radeon_i2c_do_lock(radeon_connector, 0); |
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382 | if (edid) { |
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383 | kfree(edid); |
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384 | } |
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385 | return ret; |
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386 | } |
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387 | |||
388 | static inline uint32_t radeon_div(uint64_t n, uint32_t d) |
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389 | { |
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390 | uint64_t mod; |
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391 | |||
392 | n += d / 2; |
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393 | |||
394 | mod = do_div(n, d); |
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395 | return n; |
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396 | } |
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397 | |||
398 | void radeon_compute_pll(struct radeon_pll *pll, |
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399 | uint64_t freq, |
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400 | uint32_t *dot_clock_p, |
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401 | uint32_t *fb_div_p, |
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402 | uint32_t *frac_fb_div_p, |
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403 | uint32_t *ref_div_p, |
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404 | uint32_t *post_div_p, |
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405 | int flags) |
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406 | { |
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407 | uint32_t min_ref_div = pll->min_ref_div; |
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408 | uint32_t max_ref_div = pll->max_ref_div; |
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409 | uint32_t min_fractional_feed_div = 0; |
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410 | uint32_t max_fractional_feed_div = 0; |
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411 | uint32_t best_vco = pll->best_vco; |
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412 | uint32_t best_post_div = 1; |
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413 | uint32_t best_ref_div = 1; |
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414 | uint32_t best_feedback_div = 1; |
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415 | uint32_t best_frac_feedback_div = 0; |
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416 | uint32_t best_freq = -1; |
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417 | uint32_t best_error = 0xffffffff; |
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418 | uint32_t best_vco_diff = 1; |
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419 | uint32_t post_div; |
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420 | |||
421 | DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); |
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422 | freq = freq * 1000; |
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423 | |||
424 | if (flags & RADEON_PLL_USE_REF_DIV) |
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425 | min_ref_div = max_ref_div = pll->reference_div; |
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426 | else { |
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427 | while (min_ref_div < max_ref_div-1) { |
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428 | uint32_t mid = (min_ref_div + max_ref_div) / 2; |
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429 | uint32_t pll_in = pll->reference_freq / mid; |
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430 | if (pll_in < pll->pll_in_min) |
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431 | max_ref_div = mid; |
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432 | else if (pll_in > pll->pll_in_max) |
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433 | min_ref_div = mid; |
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434 | else |
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435 | break; |
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436 | } |
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437 | } |
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438 | |||
439 | if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { |
||
440 | min_fractional_feed_div = pll->min_frac_feedback_div; |
||
441 | max_fractional_feed_div = pll->max_frac_feedback_div; |
||
442 | } |
||
443 | |||
444 | for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { |
||
445 | uint32_t ref_div; |
||
446 | |||
447 | if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) |
||
448 | continue; |
||
449 | |||
450 | /* legacy radeons only have a few post_divs */ |
||
451 | if (flags & RADEON_PLL_LEGACY) { |
||
452 | if ((post_div == 5) || |
||
453 | (post_div == 7) || |
||
454 | (post_div == 9) || |
||
455 | (post_div == 10) || |
||
456 | (post_div == 11) || |
||
457 | (post_div == 13) || |
||
458 | (post_div == 14) || |
||
459 | (post_div == 15)) |
||
460 | continue; |
||
461 | } |
||
462 | |||
463 | for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { |
||
464 | uint32_t feedback_div, current_freq = 0, error, vco_diff; |
||
465 | uint32_t pll_in = pll->reference_freq / ref_div; |
||
466 | uint32_t min_feed_div = pll->min_feedback_div; |
||
467 | uint32_t max_feed_div = pll->max_feedback_div + 1; |
||
468 | |||
469 | if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) |
||
470 | continue; |
||
471 | |||
472 | while (min_feed_div < max_feed_div) { |
||
473 | uint32_t vco; |
||
474 | uint32_t min_frac_feed_div = min_fractional_feed_div; |
||
475 | uint32_t max_frac_feed_div = max_fractional_feed_div + 1; |
||
476 | uint32_t frac_feedback_div; |
||
477 | uint64_t tmp; |
||
478 | |||
479 | feedback_div = (min_feed_div + max_feed_div) / 2; |
||
480 | |||
481 | tmp = (uint64_t)pll->reference_freq * feedback_div; |
||
482 | vco = radeon_div(tmp, ref_div); |
||
483 | |||
484 | if (vco < pll->pll_out_min) { |
||
485 | min_feed_div = feedback_div + 1; |
||
486 | continue; |
||
487 | } else if (vco > pll->pll_out_max) { |
||
488 | max_feed_div = feedback_div; |
||
489 | continue; |
||
490 | } |
||
491 | |||
492 | while (min_frac_feed_div < max_frac_feed_div) { |
||
493 | frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2; |
||
494 | tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; |
||
495 | tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; |
||
496 | current_freq = radeon_div(tmp, ref_div * post_div); |
||
497 | |||
1179 | serge | 498 | if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { |
499 | error = freq - current_freq; |
||
500 | error = error < 0 ? 0xffffffff : error; |
||
501 | } else |
||
1123 | serge | 502 | error = abs(current_freq - freq); |
503 | vco_diff = abs(vco - best_vco); |
||
504 | |||
505 | if ((best_vco == 0 && error < best_error) || |
||
506 | (best_vco != 0 && |
||
507 | (error < best_error - 100 || |
||
508 | (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) { |
||
509 | best_post_div = post_div; |
||
510 | best_ref_div = ref_div; |
||
511 | best_feedback_div = feedback_div; |
||
512 | best_frac_feedback_div = frac_feedback_div; |
||
513 | best_freq = current_freq; |
||
514 | best_error = error; |
||
515 | best_vco_diff = vco_diff; |
||
516 | } else if (current_freq == freq) { |
||
517 | if (best_freq == -1) { |
||
518 | best_post_div = post_div; |
||
519 | best_ref_div = ref_div; |
||
520 | best_feedback_div = feedback_div; |
||
521 | best_frac_feedback_div = frac_feedback_div; |
||
522 | best_freq = current_freq; |
||
523 | best_error = error; |
||
524 | best_vco_diff = vco_diff; |
||
525 | } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || |
||
526 | ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || |
||
527 | ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || |
||
528 | ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || |
||
529 | ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || |
||
530 | ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { |
||
531 | best_post_div = post_div; |
||
532 | best_ref_div = ref_div; |
||
533 | best_feedback_div = feedback_div; |
||
534 | best_frac_feedback_div = frac_feedback_div; |
||
535 | best_freq = current_freq; |
||
536 | best_error = error; |
||
537 | best_vco_diff = vco_diff; |
||
538 | } |
||
539 | } |
||
540 | if (current_freq < freq) |
||
541 | min_frac_feed_div = frac_feedback_div + 1; |
||
542 | else |
||
543 | max_frac_feed_div = frac_feedback_div; |
||
544 | } |
||
545 | if (current_freq < freq) |
||
546 | min_feed_div = feedback_div + 1; |
||
547 | else |
||
548 | max_feed_div = feedback_div; |
||
549 | } |
||
550 | } |
||
551 | } |
||
552 | |||
553 | *dot_clock_p = best_freq / 10000; |
||
554 | *fb_div_p = best_feedback_div; |
||
555 | *frac_fb_div_p = best_frac_feedback_div; |
||
556 | *ref_div_p = best_ref_div; |
||
557 | *post_div_p = best_post_div; |
||
558 | } |
||
559 | |||
560 | static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb) |
||
561 | { |
||
562 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
563 | struct drm_device *dev = fb->dev; |
||
564 | |||
565 | if (fb->fbdev) |
||
566 | radeonfb_remove(dev, fb); |
||
567 | |||
568 | // if (radeon_fb->obj) { |
||
569 | // radeon_gem_object_unpin(radeon_fb->obj); |
||
570 | // mutex_lock(&dev->struct_mutex); |
||
571 | // drm_gem_object_unreference(radeon_fb->obj); |
||
572 | // mutex_unlock(&dev->struct_mutex); |
||
573 | // } |
||
574 | drm_framebuffer_cleanup(fb); |
||
575 | kfree(radeon_fb); |
||
576 | } |
||
577 | |||
578 | static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
||
579 | struct drm_file *file_priv, |
||
580 | unsigned int *handle) |
||
581 | { |
||
582 | struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb); |
||
583 | |||
584 | return NULL; |
||
585 | // return drm_gem_handle_create(file_priv, radeon_fb->obj, handle); |
||
586 | } |
||
587 | |||
588 | static const struct drm_framebuffer_funcs radeon_fb_funcs = { |
||
589 | .destroy = radeon_user_framebuffer_destroy, |
||
590 | .create_handle = radeon_user_framebuffer_create_handle, |
||
591 | }; |
||
592 | |||
593 | struct drm_framebuffer * |
||
594 | radeon_framebuffer_create(struct drm_device *dev, |
||
595 | struct drm_mode_fb_cmd *mode_cmd, |
||
596 | struct drm_gem_object *obj) |
||
597 | { |
||
598 | struct radeon_framebuffer *radeon_fb; |
||
599 | |||
1179 | serge | 600 | radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); |
1123 | serge | 601 | if (radeon_fb == NULL) { |
602 | return NULL; |
||
603 | } |
||
1126 | serge | 604 | drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs); |
605 | drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd); |
||
1123 | serge | 606 | radeon_fb->obj = obj; |
607 | return &radeon_fb->base; |
||
608 | } |
||
609 | |||
610 | static struct drm_framebuffer * |
||
611 | radeon_user_framebuffer_create(struct drm_device *dev, |
||
612 | struct drm_file *file_priv, |
||
613 | struct drm_mode_fb_cmd *mode_cmd) |
||
614 | { |
||
615 | struct drm_gem_object *obj; |
||
616 | |||
1125 | serge | 617 | return NULL; |
1123 | serge | 618 | |
1125 | serge | 619 | // obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); |
620 | // |
||
621 | // return radeon_framebuffer_create(dev, mode_cmd, obj); |
||
1123 | serge | 622 | } |
623 | |||
624 | static const struct drm_mode_config_funcs radeon_mode_funcs = { |
||
1125 | serge | 625 | // .fb_create = radeon_user_framebuffer_create, |
1126 | serge | 626 | .fb_changed = radeonfb_probe, |
1123 | serge | 627 | }; |
628 | |||
1179 | serge | 629 | struct drm_prop_enum_list { |
630 | int type; |
||
631 | char *name; |
||
632 | }; |
||
633 | |||
634 | static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = |
||
635 | { { 0, "driver" }, |
||
636 | { 1, "bios" }, |
||
637 | }; |
||
638 | |||
639 | static struct drm_prop_enum_list radeon_tv_std_enum_list[] = |
||
640 | { { TV_STD_NTSC, "ntsc" }, |
||
641 | { TV_STD_PAL, "pal" }, |
||
642 | { TV_STD_PAL_M, "pal-m" }, |
||
643 | { TV_STD_PAL_60, "pal-60" }, |
||
644 | { TV_STD_NTSC_J, "ntsc-j" }, |
||
645 | { TV_STD_SCART_PAL, "scart-pal" }, |
||
646 | { TV_STD_PAL_CN, "pal-cn" }, |
||
647 | { TV_STD_SECAM, "secam" }, |
||
648 | }; |
||
649 | |||
650 | int radeon_modeset_create_props(struct radeon_device *rdev) |
||
1123 | serge | 651 | { |
1179 | serge | 652 | int i, sz; |
1125 | serge | 653 | |
1179 | serge | 654 | if (rdev->is_atom_bios) { |
655 | rdev->mode_info.coherent_mode_property = |
||
656 | drm_property_create(rdev->ddev, |
||
657 | DRM_MODE_PROP_RANGE, |
||
658 | "coherent", 2); |
||
659 | if (!rdev->mode_info.coherent_mode_property) |
||
660 | return -ENOMEM; |
||
1125 | serge | 661 | |
1179 | serge | 662 | rdev->mode_info.coherent_mode_property->values[0] = 0; |
663 | rdev->mode_info.coherent_mode_property->values[0] = 1; |
||
664 | } |
||
665 | |||
666 | if (!ASIC_IS_AVIVO(rdev)) { |
||
667 | sz = ARRAY_SIZE(radeon_tmds_pll_enum_list); |
||
668 | rdev->mode_info.tmds_pll_property = |
||
669 | drm_property_create(rdev->ddev, |
||
670 | DRM_MODE_PROP_ENUM, |
||
671 | "tmds_pll", sz); |
||
672 | for (i = 0; i < sz; i++) { |
||
673 | drm_property_add_enum(rdev->mode_info.tmds_pll_property, |
||
674 | i, |
||
675 | radeon_tmds_pll_enum_list[i].type, |
||
676 | radeon_tmds_pll_enum_list[i].name); |
||
677 | } |
||
678 | } |
||
679 | |||
680 | rdev->mode_info.load_detect_property = |
||
681 | drm_property_create(rdev->ddev, |
||
682 | DRM_MODE_PROP_RANGE, |
||
683 | "load detection", 2); |
||
684 | if (!rdev->mode_info.load_detect_property) |
||
685 | return -ENOMEM; |
||
686 | rdev->mode_info.load_detect_property->values[0] = 0; |
||
687 | rdev->mode_info.load_detect_property->values[0] = 1; |
||
688 | |||
689 | drm_mode_create_scaling_mode_property(rdev->ddev); |
||
690 | |||
691 | sz = ARRAY_SIZE(radeon_tv_std_enum_list); |
||
692 | rdev->mode_info.tv_std_property = |
||
693 | drm_property_create(rdev->ddev, |
||
694 | DRM_MODE_PROP_ENUM, |
||
695 | "tv standard", sz); |
||
696 | for (i = 0; i < sz; i++) { |
||
697 | drm_property_add_enum(rdev->mode_info.tv_std_property, |
||
698 | i, |
||
699 | radeon_tv_std_enum_list[i].type, |
||
700 | radeon_tv_std_enum_list[i].name); |
||
701 | } |
||
702 | |||
703 | return 0; |
||
704 | } |
||
705 | |||
706 | int radeon_modeset_init(struct radeon_device *rdev) |
||
707 | { |
||
1123 | serge | 708 | int num_crtc = 2, i; |
709 | int ret; |
||
710 | |||
711 | drm_mode_config_init(rdev->ddev); |
||
712 | rdev->mode_info.mode_config_initialized = true; |
||
713 | |||
1125 | serge | 714 | rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; |
1123 | serge | 715 | |
716 | if (ASIC_IS_AVIVO(rdev)) { |
||
717 | rdev->ddev->mode_config.max_width = 8192; |
||
718 | rdev->ddev->mode_config.max_height = 8192; |
||
719 | } else { |
||
720 | rdev->ddev->mode_config.max_width = 4096; |
||
721 | rdev->ddev->mode_config.max_height = 4096; |
||
722 | } |
||
723 | |||
724 | rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; |
||
725 | |||
1179 | serge | 726 | ret = radeon_modeset_create_props(rdev); |
727 | if (ret) { |
||
728 | return ret; |
||
729 | } |
||
1123 | serge | 730 | /* allocate crtcs - TODO single crtc */ |
731 | for (i = 0; i < num_crtc; i++) { |
||
732 | radeon_crtc_init(rdev->ddev, i); |
||
733 | } |
||
734 | |||
735 | /* okay we should have all the bios connectors */ |
||
736 | ret = radeon_setup_enc_conn(rdev->ddev); |
||
737 | if (!ret) { |
||
738 | return ret; |
||
739 | } |
||
740 | drm_helper_initial_config(rdev->ddev); |
||
741 | return 0; |
||
742 | } |
||
743 | |||
744 | void radeon_modeset_fini(struct radeon_device *rdev) |
||
745 | { |
||
746 | if (rdev->mode_info.mode_config_initialized) { |
||
747 | drm_mode_config_cleanup(rdev->ddev); |
||
748 | rdev->mode_info.mode_config_initialized = false; |
||
749 | } |
||
750 | } |
||
751 | |||
1179 | serge | 752 | bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, |
753 | struct drm_display_mode *mode, |
||
754 | struct drm_display_mode *adjusted_mode) |
||
1123 | serge | 755 | { |
1179 | serge | 756 | struct drm_device *dev = crtc->dev; |
757 | struct drm_encoder *encoder; |
||
1123 | serge | 758 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1179 | serge | 759 | struct radeon_encoder *radeon_encoder; |
760 | bool first = true; |
||
1123 | serge | 761 | |
1179 | serge | 762 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
763 | radeon_encoder = to_radeon_encoder(encoder); |
||
764 | if (encoder->crtc != crtc) |
||
765 | continue; |
||
766 | if (first) { |
||
767 | radeon_crtc->rmx_type = radeon_encoder->rmx_type; |
||
768 | memcpy(&radeon_crtc->native_mode, |
||
769 | &radeon_encoder->native_mode, |
||
770 | sizeof(struct radeon_native_mode)); |
||
771 | first = false; |
||
772 | } else { |
||
773 | if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { |
||
774 | /* WARNING: Right now this can't happen but |
||
775 | * in the future we need to check that scaling |
||
776 | * are consistent accross different encoder |
||
777 | * (ie all encoder can work with the same |
||
778 | * scaling). |
||
779 | */ |
||
780 | DRM_ERROR("Scaling not consistent accross encoder.\n"); |
||
781 | return false; |
||
782 | } |
||
1123 | serge | 783 | } |
784 | } |
||
1179 | serge | 785 | if (radeon_crtc->rmx_type != RMX_OFF) { |
786 | fixed20_12 a, b; |
||
787 | a.full = rfixed_const(crtc->mode.vdisplay); |
||
788 | b.full = rfixed_const(radeon_crtc->native_mode.panel_xres); |
||
789 | radeon_crtc->vsc.full = rfixed_div(a, b); |
||
790 | a.full = rfixed_const(crtc->mode.hdisplay); |
||
791 | b.full = rfixed_const(radeon_crtc->native_mode.panel_yres); |
||
792 | radeon_crtc->hsc.full = rfixed_div(a, b); |
||
1123 | serge | 793 | } else { |
1179 | serge | 794 | radeon_crtc->vsc.full = rfixed_const(1); |
795 | radeon_crtc->hsc.full = rfixed_const(1); |
||
1123 | serge | 796 | } |
1179 | serge | 797 | return true; |
1123 | serge | 798 | }>>>>>>>>>>>>>>>>>=>=>>>><>><>><>>>>>=>>><>><>><>>><>><>><>> |