Rev 5097 | Rev 5271 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * Copyright 2009 Jerome Glisse. |
||
5 | * |
||
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
7 | * copy of this software and associated documentation files (the "Software"), |
||
8 | * to deal in the Software without restriction, including without limitation |
||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
11 | * Software is furnished to do so, subject to the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice shall be included in |
||
14 | * all copies or substantial portions of the Software. |
||
15 | * |
||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
23 | * |
||
24 | * Authors: Dave Airlie |
||
25 | * Alex Deucher |
||
26 | * Jerome Glisse |
||
27 | */ |
||
28 | //#include |
||
2997 | Serge | 29 | #include |
1179 | serge | 30 | #include |
31 | #include |
||
1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
||
35 | #include "atom.h" |
||
3120 | serge | 36 | |
37 | #include "bitmap.h" |
||
1428 | serge | 38 | #include "display.h" |
1117 | serge | 39 | |
3120 | serge | 40 | |
1221 | serge | 41 | #include |
42 | |||
5078 | serge | 43 | #define PCI_VENDOR_ID_ATI 0x1002 |
44 | #define PCI_VENDOR_ID_APPLE 0x106b |
||
1117 | serge | 45 | |
5078 | serge | 46 | int radeon_no_wb; |
1430 | serge | 47 | int radeon_modeset = -1; |
48 | int radeon_dynclks = -1; |
||
49 | int radeon_r4xx_atom = 0; |
||
50 | int radeon_agpmode = 0; |
||
51 | int radeon_vram_limit = 0; |
||
5078 | serge | 52 | int radeon_gart_size = -1; /* auto */ |
1430 | serge | 53 | int radeon_benchmarking = 0; |
54 | int radeon_testing = 0; |
||
55 | int radeon_connector_table = 0; |
||
56 | int radeon_tv = 1; |
||
5078 | serge | 57 | int radeon_audio = -1; |
58 | int radeon_disp_priority = 0; |
||
1963 | serge | 59 | int radeon_hw_i2c = 0; |
5078 | serge | 60 | int radeon_pcie_gen2 = -1; |
61 | int radeon_msi = -1; |
||
2997 | Serge | 62 | int radeon_lockup_timeout = 10000; |
3764 | Serge | 63 | int radeon_fastfb = 0; |
5078 | serge | 64 | int radeon_dpm = -1; |
65 | int radeon_aspm = -1; |
||
66 | int radeon_runtime_pm = -1; |
||
67 | int radeon_hard_reset = 0; |
||
68 | int radeon_vm_size = 8; |
||
69 | int radeon_vm_block_size = -1; |
||
70 | int radeon_deep_color = 0; |
||
71 | int radeon_use_pflipirq = 2; |
||
2160 | serge | 72 | int irq_override = 0; |
5078 | serge | 73 | int radeon_bapm = -1; |
5179 | serge | 74 | int radeon_backlight = 0; |
1430 | serge | 75 | |
5078 | serge | 76 | extern display_t *os_display; |
77 | extern struct drm_device *main_device; |
||
78 | extern videomode_t usermode; |
||
1246 | serge | 79 | |
3120 | serge | 80 | |
1404 | serge | 81 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
82 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
||
5078 | serge | 83 | int init_display_kms(struct drm_device *dev, videomode_t *usermode); |
1117 | serge | 84 | |
2997 | Serge | 85 | int get_modes(videomode_t *mode, u32_t *count); |
1404 | serge | 86 | int set_user_mode(videomode_t *mode); |
1428 | serge | 87 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 88 | |
1404 | serge | 89 | |
1233 | serge | 90 | /* Legacy VGA regions */ |
91 | #define VGA_RSRC_NONE 0x00 |
||
92 | #define VGA_RSRC_LEGACY_IO 0x01 |
||
93 | #define VGA_RSRC_LEGACY_MEM 0x02 |
||
94 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
||
95 | /* Non-legacy access */ |
||
96 | #define VGA_RSRC_NORMAL_IO 0x04 |
||
97 | #define VGA_RSRC_NORMAL_MEM 0x08 |
||
98 | |||
99 | |||
1963 | serge | 100 | static const char radeon_family_name[][16] = { |
101 | "R100", |
||
102 | "RV100", |
||
103 | "RS100", |
||
104 | "RV200", |
||
105 | "RS200", |
||
106 | "R200", |
||
107 | "RV250", |
||
108 | "RS300", |
||
109 | "RV280", |
||
110 | "R300", |
||
111 | "R350", |
||
112 | "RV350", |
||
113 | "RV380", |
||
114 | "R420", |
||
115 | "R423", |
||
116 | "RV410", |
||
117 | "RS400", |
||
118 | "RS480", |
||
119 | "RS600", |
||
120 | "RS690", |
||
121 | "RS740", |
||
122 | "RV515", |
||
123 | "R520", |
||
124 | "RV530", |
||
125 | "RV560", |
||
126 | "RV570", |
||
127 | "R580", |
||
128 | "R600", |
||
129 | "RV610", |
||
130 | "RV630", |
||
131 | "RV670", |
||
132 | "RV620", |
||
133 | "RV635", |
||
134 | "RS780", |
||
135 | "RS880", |
||
136 | "RV770", |
||
137 | "RV730", |
||
138 | "RV710", |
||
139 | "RV740", |
||
140 | "CEDAR", |
||
141 | "REDWOOD", |
||
142 | "JUNIPER", |
||
143 | "CYPRESS", |
||
144 | "HEMLOCK", |
||
145 | "PALM", |
||
1986 | serge | 146 | "SUMO", |
147 | "SUMO2", |
||
1963 | serge | 148 | "BARTS", |
149 | "TURKS", |
||
150 | "CAICOS", |
||
151 | "CAYMAN", |
||
2997 | Serge | 152 | "ARUBA", |
153 | "TAHITI", |
||
154 | "PITCAIRN", |
||
155 | "VERDE", |
||
3764 | Serge | 156 | "OLAND", |
157 | "HAINAN", |
||
5078 | serge | 158 | "BONAIRE", |
159 | "KAVERI", |
||
160 | "KABINI", |
||
161 | "HAWAII", |
||
162 | "MULLINS", |
||
1963 | serge | 163 | "LAST", |
164 | }; |
||
1233 | serge | 165 | |
5078 | serge | 166 | #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) |
167 | #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) |
||
168 | |||
169 | struct radeon_px_quirk { |
||
170 | u32 chip_vendor; |
||
171 | u32 chip_device; |
||
172 | u32 subsys_vendor; |
||
173 | u32 subsys_device; |
||
174 | u32 px_quirk_flags; |
||
175 | }; |
||
176 | |||
177 | static struct radeon_px_quirk radeon_px_quirk_list[] = { |
||
178 | /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) |
||
179 | * https://bugzilla.kernel.org/show_bug.cgi?id=74551 |
||
180 | */ |
||
181 | { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, |
||
182 | /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU |
||
183 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
||
184 | */ |
||
185 | { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, |
||
5179 | serge | 186 | /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU |
187 | * https://bugzilla.kernel.org/show_bug.cgi?id=51381 |
||
188 | */ |
||
189 | { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, |
||
5078 | serge | 190 | /* macbook pro 8.2 */ |
191 | { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, |
||
192 | { 0, 0, 0, 0, 0 }, |
||
193 | }; |
||
194 | |||
195 | bool radeon_is_px(struct drm_device *dev) |
||
196 | { |
||
197 | struct radeon_device *rdev = dev->dev_private; |
||
198 | |||
199 | if (rdev->flags & RADEON_IS_PX) |
||
200 | return true; |
||
201 | return false; |
||
202 | } |
||
203 | |||
204 | static void radeon_device_handle_px_quirks(struct radeon_device *rdev) |
||
205 | { |
||
206 | struct radeon_px_quirk *p = radeon_px_quirk_list; |
||
207 | |||
208 | /* Apply PX quirks */ |
||
209 | while (p && p->chip_device != 0) { |
||
210 | if (rdev->pdev->vendor == p->chip_vendor && |
||
211 | rdev->pdev->device == p->chip_device && |
||
212 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
||
213 | rdev->pdev->subsystem_device == p->subsys_device) { |
||
214 | rdev->px_quirk_flags = p->px_quirk_flags; |
||
215 | break; |
||
216 | } |
||
217 | ++p; |
||
218 | } |
||
219 | |||
220 | if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) |
||
221 | rdev->flags &= ~RADEON_IS_PX; |
||
222 | } |
||
223 | |||
2997 | Serge | 224 | /** |
3764 | Serge | 225 | * radeon_program_register_sequence - program an array of registers. |
226 | * |
||
227 | * @rdev: radeon_device pointer |
||
228 | * @registers: pointer to the register array |
||
229 | * @array_size: size of the register array |
||
230 | * |
||
231 | * Programs an array or registers with and and or masks. |
||
232 | * This is a helper for setting golden registers. |
||
233 | */ |
||
234 | void radeon_program_register_sequence(struct radeon_device *rdev, |
||
235 | const u32 *registers, |
||
236 | const u32 array_size) |
||
237 | { |
||
238 | u32 tmp, reg, and_mask, or_mask; |
||
239 | int i; |
||
240 | |||
241 | if (array_size % 3) |
||
242 | return; |
||
243 | |||
244 | for (i = 0; i < array_size; i +=3) { |
||
245 | reg = registers[i + 0]; |
||
246 | and_mask = registers[i + 1]; |
||
247 | or_mask = registers[i + 2]; |
||
248 | |||
249 | if (and_mask == 0xffffffff) { |
||
250 | tmp = or_mask; |
||
251 | } else { |
||
252 | tmp = RREG32(reg); |
||
253 | tmp &= ~and_mask; |
||
254 | tmp |= or_mask; |
||
255 | } |
||
256 | WREG32(reg, tmp); |
||
257 | } |
||
258 | } |
||
259 | |||
5078 | serge | 260 | void radeon_pci_config_reset(struct radeon_device *rdev) |
261 | { |
||
262 | pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); |
||
263 | } |
||
264 | |||
3764 | Serge | 265 | /** |
2997 | Serge | 266 | * radeon_surface_init - Clear GPU surface registers. |
267 | * |
||
268 | * @rdev: radeon_device pointer |
||
269 | * |
||
270 | * Clear GPU surface registers (r1xx-r5xx). |
||
1117 | serge | 271 | */ |
1179 | serge | 272 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 273 | { |
274 | /* FIXME: check this out */ |
||
275 | if (rdev->family < CHIP_R600) { |
||
276 | int i; |
||
277 | |||
1321 | serge | 278 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
5078 | serge | 279 | if (rdev->surface_regs[i].bo) |
280 | radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); |
||
281 | else |
||
1404 | serge | 282 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 283 | } |
1179 | serge | 284 | /* enable surfaces */ |
285 | WREG32(RADEON_SURFACE_CNTL, 0); |
||
1117 | serge | 286 | } |
287 | } |
||
288 | |||
289 | /* |
||
290 | * GPU scratch registers helpers function. |
||
291 | */ |
||
2997 | Serge | 292 | /** |
293 | * radeon_scratch_init - Init scratch register driver information. |
||
294 | * |
||
295 | * @rdev: radeon_device pointer |
||
296 | * |
||
297 | * Init CP scratch register driver information (r1xx-r5xx) |
||
298 | */ |
||
1179 | serge | 299 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 300 | { |
301 | int i; |
||
302 | |||
303 | /* FIXME: check this out */ |
||
304 | if (rdev->family < CHIP_R300) { |
||
305 | rdev->scratch.num_reg = 5; |
||
306 | } else { |
||
307 | rdev->scratch.num_reg = 7; |
||
308 | } |
||
1963 | serge | 309 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
1117 | serge | 310 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
311 | rdev->scratch.free[i] = true; |
||
1963 | serge | 312 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1117 | serge | 313 | } |
314 | } |
||
315 | |||
2997 | Serge | 316 | /** |
317 | * radeon_scratch_get - Allocate a scratch register |
||
318 | * |
||
319 | * @rdev: radeon_device pointer |
||
320 | * @reg: scratch register mmio offset |
||
321 | * |
||
322 | * Allocate a CP scratch register for use by the driver (all asics). |
||
323 | * Returns 0 on success or -EINVAL on failure. |
||
324 | */ |
||
1117 | serge | 325 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
326 | { |
||
327 | int i; |
||
328 | |||
329 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
||
330 | if (rdev->scratch.free[i]) { |
||
331 | rdev->scratch.free[i] = false; |
||
332 | *reg = rdev->scratch.reg[i]; |
||
333 | return 0; |
||
334 | } |
||
335 | } |
||
336 | return -EINVAL; |
||
337 | } |
||
338 | |||
2997 | Serge | 339 | /** |
340 | * radeon_scratch_free - Free a scratch register |
||
341 | * |
||
342 | * @rdev: radeon_device pointer |
||
343 | * @reg: scratch register mmio offset |
||
344 | * |
||
345 | * Free a CP scratch register allocated for use by the driver (all asics) |
||
346 | */ |
||
1117 | serge | 347 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
348 | { |
||
349 | int i; |
||
350 | |||
351 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
||
352 | if (rdev->scratch.reg[i] == reg) { |
||
353 | rdev->scratch.free[i] = true; |
||
354 | return; |
||
355 | } |
||
356 | } |
||
357 | } |
||
358 | |||
2997 | Serge | 359 | /* |
5078 | serge | 360 | * GPU doorbell aperture helpers function. |
361 | */ |
||
362 | /** |
||
363 | * radeon_doorbell_init - Init doorbell driver information. |
||
364 | * |
||
365 | * @rdev: radeon_device pointer |
||
366 | * |
||
367 | * Init doorbell driver information (CIK) |
||
368 | * Returns 0 on success, error on failure. |
||
369 | */ |
||
370 | static int radeon_doorbell_init(struct radeon_device *rdev) |
||
371 | { |
||
372 | /* doorbell bar mapping */ |
||
373 | rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); |
||
374 | rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); |
||
375 | |||
376 | rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); |
||
377 | if (rdev->doorbell.num_doorbells == 0) |
||
378 | return -EINVAL; |
||
379 | |||
380 | rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); |
||
381 | if (rdev->doorbell.ptr == NULL) { |
||
382 | return -ENOMEM; |
||
383 | } |
||
384 | DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); |
||
385 | DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); |
||
386 | |||
387 | memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); |
||
388 | |||
389 | return 0; |
||
390 | } |
||
391 | |||
392 | /** |
||
393 | * radeon_doorbell_fini - Tear down doorbell driver information. |
||
394 | * |
||
395 | * @rdev: radeon_device pointer |
||
396 | * |
||
397 | * Tear down doorbell driver information (CIK) |
||
398 | */ |
||
399 | static void radeon_doorbell_fini(struct radeon_device *rdev) |
||
400 | { |
||
401 | iounmap(rdev->doorbell.ptr); |
||
402 | rdev->doorbell.ptr = NULL; |
||
403 | } |
||
404 | |||
405 | /** |
||
406 | * radeon_doorbell_get - Allocate a doorbell entry |
||
407 | * |
||
408 | * @rdev: radeon_device pointer |
||
409 | * @doorbell: doorbell index |
||
410 | * |
||
411 | * Allocate a doorbell for use by the driver (all asics). |
||
412 | * Returns 0 on success or -EINVAL on failure. |
||
413 | */ |
||
414 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) |
||
415 | { |
||
416 | unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); |
||
417 | if (offset < rdev->doorbell.num_doorbells) { |
||
418 | __set_bit(offset, rdev->doorbell.used); |
||
419 | *doorbell = offset; |
||
420 | return 0; |
||
421 | } else { |
||
422 | return -EINVAL; |
||
423 | } |
||
424 | } |
||
425 | |||
426 | /** |
||
427 | * radeon_doorbell_free - Free a doorbell entry |
||
428 | * |
||
429 | * @rdev: radeon_device pointer |
||
430 | * @doorbell: doorbell index |
||
431 | * |
||
432 | * Free a doorbell allocated for use by the driver (all asics) |
||
433 | */ |
||
434 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) |
||
435 | { |
||
436 | if (doorbell < rdev->doorbell.num_doorbells) |
||
437 | __clear_bit(doorbell, rdev->doorbell.used); |
||
438 | } |
||
439 | |||
440 | /* |
||
2997 | Serge | 441 | * radeon_wb_*() |
442 | * Writeback is the the method by which the the GPU updates special pages |
||
443 | * in memory with the status of certain GPU events (fences, ring pointers, |
||
444 | * etc.). |
||
445 | */ |
||
446 | |||
447 | /** |
||
448 | * radeon_wb_disable - Disable Writeback |
||
449 | * |
||
450 | * @rdev: radeon_device pointer |
||
451 | * |
||
452 | * Disables Writeback (all asics). Used for suspend. |
||
453 | */ |
||
2004 | serge | 454 | void radeon_wb_disable(struct radeon_device *rdev) |
455 | { |
||
456 | rdev->wb.enabled = false; |
||
457 | } |
||
458 | |||
2997 | Serge | 459 | /** |
460 | * radeon_wb_fini - Disable Writeback and free memory |
||
461 | * |
||
462 | * @rdev: radeon_device pointer |
||
463 | * |
||
464 | * Disables Writeback and frees the Writeback memory (all asics). |
||
465 | * Used at driver shutdown. |
||
466 | */ |
||
2004 | serge | 467 | void radeon_wb_fini(struct radeon_device *rdev) |
468 | { |
||
469 | radeon_wb_disable(rdev); |
||
470 | if (rdev->wb.wb_obj) { |
||
5078 | serge | 471 | if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { |
472 | radeon_bo_kunmap(rdev->wb.wb_obj); |
||
473 | radeon_bo_unpin(rdev->wb.wb_obj); |
||
474 | radeon_bo_unreserve(rdev->wb.wb_obj); |
||
475 | } |
||
2004 | serge | 476 | radeon_bo_unref(&rdev->wb.wb_obj); |
477 | rdev->wb.wb = NULL; |
||
478 | rdev->wb.wb_obj = NULL; |
||
479 | } |
||
480 | } |
||
481 | |||
2997 | Serge | 482 | /** |
483 | * radeon_wb_init- Init Writeback driver info and allocate memory |
||
484 | * |
||
485 | * @rdev: radeon_device pointer |
||
486 | * |
||
487 | * Disables Writeback and frees the Writeback memory (all asics). |
||
488 | * Used at driver startup. |
||
489 | * Returns 0 on success or an -error on failure. |
||
490 | */ |
||
2004 | serge | 491 | int radeon_wb_init(struct radeon_device *rdev) |
492 | { |
||
493 | int r; |
||
494 | |||
495 | if (rdev->wb.wb_obj == NULL) { |
||
496 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
||
5078 | serge | 497 | RADEON_GEM_DOMAIN_GTT, 0, NULL, |
498 | &rdev->wb.wb_obj); |
||
2004 | serge | 499 | if (r) { |
500 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
||
501 | return r; |
||
502 | } |
||
503 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
||
504 | if (unlikely(r != 0)) { |
||
505 | radeon_wb_fini(rdev); |
||
506 | return r; |
||
507 | } |
||
508 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
||
509 | &rdev->wb.gpu_addr); |
||
510 | if (r) { |
||
511 | radeon_bo_unreserve(rdev->wb.wb_obj); |
||
512 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
||
513 | radeon_wb_fini(rdev); |
||
514 | return r; |
||
515 | } |
||
516 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
||
517 | radeon_bo_unreserve(rdev->wb.wb_obj); |
||
518 | if (r) { |
||
519 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
||
520 | radeon_wb_fini(rdev); |
||
521 | return r; |
||
522 | } |
||
3764 | Serge | 523 | } |
2004 | serge | 524 | |
525 | /* clear wb memory */ |
||
526 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
||
527 | /* disable event_write fences */ |
||
528 | rdev->wb.use_event = false; |
||
529 | /* disabled via module param */ |
||
2997 | Serge | 530 | if (radeon_no_wb == 1) { |
2004 | serge | 531 | rdev->wb.enabled = false; |
2997 | Serge | 532 | } else { |
533 | if (rdev->flags & RADEON_IS_AGP) { |
||
2004 | serge | 534 | /* often unreliable on AGP */ |
2997 | Serge | 535 | rdev->wb.enabled = false; |
536 | } else if (rdev->family < CHIP_R300) { |
||
537 | /* often unreliable on pre-r300 */ |
||
538 | rdev->wb.enabled = false; |
||
539 | } else { |
||
2004 | serge | 540 | rdev->wb.enabled = true; |
541 | /* event_write fences are only available on r600+ */ |
||
2997 | Serge | 542 | if (rdev->family >= CHIP_R600) { |
2004 | serge | 543 | rdev->wb.use_event = true; |
544 | } |
||
2997 | Serge | 545 | } |
546 | } |
||
547 | /* always use writeback/events on NI, APUs */ |
||
548 | if (rdev->family >= CHIP_PALM) { |
||
2004 | serge | 549 | rdev->wb.enabled = true; |
550 | rdev->wb.use_event = true; |
||
551 | } |
||
552 | |||
553 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
||
554 | |||
555 | return 0; |
||
556 | } |
||
557 | |||
1430 | serge | 558 | /** |
559 | * radeon_vram_location - try to find VRAM location |
||
560 | * @rdev: radeon device structure holding all necessary informations |
||
561 | * @mc: memory controller structure holding memory informations |
||
562 | * @base: base address at which to put VRAM |
||
563 | * |
||
564 | * Function will place try to place VRAM at base address provided |
||
565 | * as parameter (which is so far either PCI aperture address or |
||
566 | * for IGP TOM base address). |
||
567 | * |
||
568 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
||
569 | * address space then we limit the VRAM size to the aperture. |
||
570 | * |
||
571 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
||
572 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
||
573 | * size and print a warning. |
||
574 | * |
||
575 | * This function will never fails, worst case are limiting VRAM. |
||
576 | * |
||
577 | * Note: GTT start, end, size should be initialized before calling this |
||
578 | * function on AGP platform. |
||
579 | * |
||
1963 | serge | 580 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
1430 | serge | 581 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
582 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
||
583 | * not IGP. |
||
584 | * |
||
585 | * Note: we use mc_vram_size as on some board we need to program the mc to |
||
586 | * cover the whole aperture even if VRAM size is inferior to aperture size |
||
587 | * Novell bug 204882 + along with lots of ubuntu ones |
||
588 | * |
||
589 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
||
590 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
||
591 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
||
592 | * ones) |
||
593 | * |
||
594 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
||
595 | * explicitly check for that thought. |
||
596 | * |
||
597 | * FIXME: when reducing VRAM size align new size on power of 2. |
||
1117 | serge | 598 | */ |
1430 | serge | 599 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 600 | { |
2997 | Serge | 601 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
602 | |||
1430 | serge | 603 | mc->vram_start = base; |
3764 | Serge | 604 | if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { |
1430 | serge | 605 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
606 | mc->real_vram_size = mc->aper_size; |
||
607 | mc->mc_vram_size = mc->aper_size; |
||
608 | } |
||
609 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
||
1963 | serge | 610 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
1430 | serge | 611 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
612 | mc->real_vram_size = mc->aper_size; |
||
613 | mc->mc_vram_size = mc->aper_size; |
||
614 | } |
||
615 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
||
2997 | Serge | 616 | if (limit && limit < mc->real_vram_size) |
617 | mc->real_vram_size = limit; |
||
1963 | serge | 618 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
1430 | serge | 619 | mc->mc_vram_size >> 20, mc->vram_start, |
620 | mc->vram_end, mc->real_vram_size >> 20); |
||
621 | } |
||
1117 | serge | 622 | |
1430 | serge | 623 | /** |
624 | * radeon_gtt_location - try to find GTT location |
||
625 | * @rdev: radeon device structure holding all necessary informations |
||
626 | * @mc: memory controller structure holding memory informations |
||
627 | * |
||
628 | * Function will place try to place GTT before or after VRAM. |
||
629 | * |
||
630 | * If GTT size is bigger than space left then we ajust GTT size. |
||
631 | * Thus function will never fails. |
||
632 | * |
||
633 | * FIXME: when reducing GTT size align new size on power of 2. |
||
634 | */ |
||
635 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
||
636 | { |
||
637 | u64 size_af, size_bf; |
||
638 | |||
3764 | Serge | 639 | size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
1963 | serge | 640 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
1430 | serge | 641 | if (size_bf > size_af) { |
642 | if (mc->gtt_size > size_bf) { |
||
643 | dev_warn(rdev->dev, "limiting GTT\n"); |
||
644 | mc->gtt_size = size_bf; |
||
1117 | serge | 645 | } |
1963 | serge | 646 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
1430 | serge | 647 | } else { |
648 | if (mc->gtt_size > size_af) { |
||
649 | dev_warn(rdev->dev, "limiting GTT\n"); |
||
650 | mc->gtt_size = size_af; |
||
1117 | serge | 651 | } |
1963 | serge | 652 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
1117 | serge | 653 | } |
1430 | serge | 654 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
1963 | serge | 655 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
1430 | serge | 656 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
1117 | serge | 657 | } |
658 | |||
659 | /* |
||
660 | * GPU helpers function. |
||
661 | */ |
||
2997 | Serge | 662 | /** |
663 | * radeon_card_posted - check if the hw has already been initialized |
||
664 | * |
||
665 | * @rdev: radeon_device pointer |
||
666 | * |
||
667 | * Check if the asic has been initialized (all asics). |
||
668 | * Used at driver startup. |
||
669 | * Returns true if initialized or false if not. |
||
670 | */ |
||
1179 | serge | 671 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 672 | { |
673 | uint32_t reg; |
||
674 | |||
3764 | Serge | 675 | if (ASIC_IS_NODCE(rdev)) |
676 | goto check_memsize; |
||
677 | |||
1117 | serge | 678 | /* first check CRTCs */ |
3764 | Serge | 679 | if (ASIC_IS_DCE4(rdev)) { |
1430 | serge | 680 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
1963 | serge | 681 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
3764 | Serge | 682 | if (rdev->num_crtc >= 4) { |
683 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
||
684 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
||
685 | } |
||
686 | if (rdev->num_crtc >= 6) { |
||
687 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
||
1430 | serge | 688 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
3764 | Serge | 689 | } |
1430 | serge | 690 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
691 | return true; |
||
692 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
1117 | serge | 693 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
694 | RREG32(AVIVO_D2CRTC_CONTROL); |
||
695 | if (reg & AVIVO_CRTC_EN) { |
||
696 | return true; |
||
697 | } |
||
698 | } else { |
||
699 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
||
700 | RREG32(RADEON_CRTC2_GEN_CNTL); |
||
701 | if (reg & RADEON_CRTC_EN) { |
||
702 | return true; |
||
703 | } |
||
704 | } |
||
705 | |||
3764 | Serge | 706 | check_memsize: |
1117 | serge | 707 | /* then check MEM_SIZE, in case the crtcs are off */ |
708 | if (rdev->family >= CHIP_R600) |
||
709 | reg = RREG32(R600_CONFIG_MEMSIZE); |
||
710 | else |
||
711 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
||
712 | |||
713 | if (reg) |
||
714 | return true; |
||
715 | |||
716 | return false; |
||
717 | |||
718 | } |
||
719 | |||
2997 | Serge | 720 | /** |
721 | * radeon_update_bandwidth_info - update display bandwidth params |
||
722 | * |
||
723 | * @rdev: radeon_device pointer |
||
724 | * |
||
725 | * Used when sclk/mclk are switched or display modes are set. |
||
726 | * params are used to calculate display watermarks (all asics) |
||
727 | */ |
||
1963 | serge | 728 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
729 | { |
||
730 | fixed20_12 a; |
||
731 | u32 sclk = rdev->pm.current_sclk; |
||
732 | u32 mclk = rdev->pm.current_mclk; |
||
733 | |||
734 | /* sclk/mclk in Mhz */ |
||
735 | a.full = dfixed_const(100); |
||
736 | rdev->pm.sclk.full = dfixed_const(sclk); |
||
737 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
||
738 | rdev->pm.mclk.full = dfixed_const(mclk); |
||
739 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
||
740 | |||
741 | if (rdev->flags & RADEON_IS_IGP) { |
||
742 | a.full = dfixed_const(16); |
||
743 | /* core_bandwidth = sclk(Mhz) * 16 */ |
||
744 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
||
745 | } |
||
746 | } |
||
747 | |||
2997 | Serge | 748 | /** |
749 | * radeon_boot_test_post_card - check and possibly initialize the hw |
||
750 | * |
||
751 | * @rdev: radeon_device pointer |
||
752 | * |
||
753 | * Check if the asic is initialized and if not, attempt to initialize |
||
754 | * it (all asics). |
||
755 | * Returns true if initialized or false if not. |
||
756 | */ |
||
1321 | serge | 757 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
758 | { |
||
759 | if (radeon_card_posted(rdev)) |
||
760 | return true; |
||
761 | |||
762 | if (rdev->bios) { |
||
763 | DRM_INFO("GPU not posted. posting now...\n"); |
||
764 | if (rdev->is_atom_bios) |
||
765 | atom_asic_init(rdev->mode_info.atom_context); |
||
766 | else |
||
767 | radeon_combios_asic_init(rdev->ddev); |
||
768 | return true; |
||
769 | } else { |
||
770 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
771 | return false; |
||
772 | } |
||
773 | } |
||
774 | |||
2997 | Serge | 775 | /** |
776 | * radeon_dummy_page_init - init dummy page used by the driver |
||
777 | * |
||
778 | * @rdev: radeon_device pointer |
||
779 | * |
||
780 | * Allocate the dummy page used by the driver (all asics). |
||
781 | * This dummy page is used by the driver as a filler for gart entries |
||
782 | * when pages are taken out of the GART |
||
783 | * Returns 0 on sucess, -ENOMEM on failure. |
||
784 | */ |
||
1233 | serge | 785 | int radeon_dummy_page_init(struct radeon_device *rdev) |
786 | { |
||
1430 | serge | 787 | if (rdev->dummy_page.page) |
788 | return 0; |
||
5078 | serge | 789 | rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); |
1233 | serge | 790 | if (rdev->dummy_page.page == NULL) |
791 | return -ENOMEM; |
||
5078 | serge | 792 | rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, |
793 | 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
||
1233 | serge | 794 | return 0; |
795 | } |
||
1117 | serge | 796 | |
2997 | Serge | 797 | /** |
798 | * radeon_dummy_page_fini - free dummy page used by the driver |
||
799 | * |
||
800 | * @rdev: radeon_device pointer |
||
801 | * |
||
802 | * Frees the dummy page used by the driver (all asics). |
||
803 | */ |
||
1233 | serge | 804 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
805 | { |
||
806 | if (rdev->dummy_page.page == NULL) |
||
807 | return; |
||
5078 | serge | 808 | |
1233 | serge | 809 | rdev->dummy_page.page = NULL; |
810 | } |
||
811 | |||
812 | |||
1117 | serge | 813 | /* ATOM accessor methods */ |
2997 | Serge | 814 | /* |
815 | * ATOM is an interpreted byte code stored in tables in the vbios. The |
||
816 | * driver registers callbacks to access registers and the interpreter |
||
817 | * in the driver parses the tables and executes then to program specific |
||
818 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, |
||
819 | * atombios.h, and atom.c |
||
820 | */ |
||
821 | |||
822 | /** |
||
823 | * cail_pll_read - read PLL register |
||
824 | * |
||
825 | * @info: atom card_info pointer |
||
826 | * @reg: PLL register offset |
||
827 | * |
||
828 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
||
829 | * Returns the value of the PLL register. |
||
830 | */ |
||
1117 | serge | 831 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
832 | { |
||
833 | struct radeon_device *rdev = info->dev->dev_private; |
||
834 | uint32_t r; |
||
835 | |||
836 | r = rdev->pll_rreg(rdev, reg); |
||
837 | return r; |
||
838 | } |
||
839 | |||
2997 | Serge | 840 | /** |
841 | * cail_pll_write - write PLL register |
||
842 | * |
||
843 | * @info: atom card_info pointer |
||
844 | * @reg: PLL register offset |
||
845 | * @val: value to write to the pll register |
||
846 | * |
||
847 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
||
848 | */ |
||
1117 | serge | 849 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
850 | { |
||
851 | struct radeon_device *rdev = info->dev->dev_private; |
||
852 | |||
853 | rdev->pll_wreg(rdev, reg, val); |
||
854 | } |
||
855 | |||
2997 | Serge | 856 | /** |
857 | * cail_mc_read - read MC (Memory Controller) register |
||
858 | * |
||
859 | * @info: atom card_info pointer |
||
860 | * @reg: MC register offset |
||
861 | * |
||
862 | * Provides an MC register accessor for the atom interpreter (r4xx+). |
||
863 | * Returns the value of the MC register. |
||
864 | */ |
||
1117 | serge | 865 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
866 | { |
||
867 | struct radeon_device *rdev = info->dev->dev_private; |
||
868 | uint32_t r; |
||
869 | |||
870 | r = rdev->mc_rreg(rdev, reg); |
||
871 | return r; |
||
872 | } |
||
873 | |||
2997 | Serge | 874 | /** |
875 | * cail_mc_write - write MC (Memory Controller) register |
||
876 | * |
||
877 | * @info: atom card_info pointer |
||
878 | * @reg: MC register offset |
||
879 | * @val: value to write to the pll register |
||
880 | * |
||
881 | * Provides a MC register accessor for the atom interpreter (r4xx+). |
||
882 | */ |
||
1117 | serge | 883 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
884 | { |
||
885 | struct radeon_device *rdev = info->dev->dev_private; |
||
886 | |||
887 | rdev->mc_wreg(rdev, reg, val); |
||
888 | } |
||
889 | |||
2997 | Serge | 890 | /** |
891 | * cail_reg_write - write MMIO register |
||
892 | * |
||
893 | * @info: atom card_info pointer |
||
894 | * @reg: MMIO register offset |
||
895 | * @val: value to write to the pll register |
||
896 | * |
||
897 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). |
||
898 | */ |
||
1117 | serge | 899 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
900 | { |
||
901 | struct radeon_device *rdev = info->dev->dev_private; |
||
902 | |||
903 | WREG32(reg*4, val); |
||
904 | } |
||
905 | |||
2997 | Serge | 906 | /** |
907 | * cail_reg_read - read MMIO register |
||
908 | * |
||
909 | * @info: atom card_info pointer |
||
910 | * @reg: MMIO register offset |
||
911 | * |
||
912 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). |
||
913 | * Returns the value of the MMIO register. |
||
914 | */ |
||
1117 | serge | 915 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
916 | { |
||
917 | struct radeon_device *rdev = info->dev->dev_private; |
||
918 | uint32_t r; |
||
919 | |||
920 | r = RREG32(reg*4); |
||
921 | return r; |
||
922 | } |
||
923 | |||
2997 | Serge | 924 | /** |
925 | * cail_ioreg_write - write IO register |
||
926 | * |
||
927 | * @info: atom card_info pointer |
||
928 | * @reg: IO register offset |
||
929 | * @val: value to write to the pll register |
||
930 | * |
||
931 | * Provides a IO register accessor for the atom interpreter (r4xx+). |
||
932 | */ |
||
1963 | serge | 933 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
934 | { |
||
935 | struct radeon_device *rdev = info->dev->dev_private; |
||
936 | |||
937 | WREG32_IO(reg*4, val); |
||
938 | } |
||
939 | |||
2997 | Serge | 940 | /** |
941 | * cail_ioreg_read - read IO register |
||
942 | * |
||
943 | * @info: atom card_info pointer |
||
944 | * @reg: IO register offset |
||
945 | * |
||
946 | * Provides an IO register accessor for the atom interpreter (r4xx+). |
||
947 | * Returns the value of the IO register. |
||
948 | */ |
||
1963 | serge | 949 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
950 | { |
||
951 | struct radeon_device *rdev = info->dev->dev_private; |
||
952 | uint32_t r; |
||
953 | |||
954 | r = RREG32_IO(reg*4); |
||
955 | return r; |
||
956 | } |
||
957 | |||
2997 | Serge | 958 | /** |
959 | * radeon_atombios_init - init the driver info and callbacks for atombios |
||
960 | * |
||
961 | * @rdev: radeon_device pointer |
||
962 | * |
||
963 | * Initializes the driver info and register access callbacks for the |
||
964 | * ATOM interpreter (r4xx+). |
||
965 | * Returns 0 on sucess, -ENOMEM on failure. |
||
966 | * Called at driver startup. |
||
967 | */ |
||
1117 | serge | 968 | int radeon_atombios_init(struct radeon_device *rdev) |
969 | { |
||
1268 | serge | 970 | struct card_info *atom_card_info = |
971 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 972 | |
1268 | serge | 973 | if (!atom_card_info) |
974 | return -ENOMEM; |
||
975 | |||
976 | rdev->mode_info.atom_card_info = atom_card_info; |
||
977 | atom_card_info->dev = rdev->ddev; |
||
978 | atom_card_info->reg_read = cail_reg_read; |
||
979 | atom_card_info->reg_write = cail_reg_write; |
||
1963 | serge | 980 | /* needed for iio ops */ |
981 | if (rdev->rio_mem) { |
||
982 | atom_card_info->ioreg_read = cail_ioreg_read; |
||
983 | atom_card_info->ioreg_write = cail_ioreg_write; |
||
984 | } else { |
||
985 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
||
986 | atom_card_info->ioreg_read = cail_reg_read; |
||
987 | atom_card_info->ioreg_write = cail_reg_write; |
||
988 | } |
||
1268 | serge | 989 | atom_card_info->mc_read = cail_mc_read; |
990 | atom_card_info->mc_write = cail_mc_write; |
||
991 | atom_card_info->pll_read = cail_pll_read; |
||
992 | atom_card_info->pll_write = cail_pll_write; |
||
993 | |||
994 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
3764 | Serge | 995 | if (!rdev->mode_info.atom_context) { |
996 | radeon_atombios_fini(rdev); |
||
997 | return -ENOMEM; |
||
998 | } |
||
999 | |||
1630 | serge | 1000 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 1001 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 1002 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 1003 | return 0; |
1004 | } |
||
1005 | |||
2997 | Serge | 1006 | /** |
1007 | * radeon_atombios_fini - free the driver info and callbacks for atombios |
||
1008 | * |
||
1009 | * @rdev: radeon_device pointer |
||
1010 | * |
||
1011 | * Frees the driver info and register access callbacks for the ATOM |
||
1012 | * interpreter (r4xx+). |
||
1013 | * Called at driver shutdown. |
||
1014 | */ |
||
1117 | serge | 1015 | void radeon_atombios_fini(struct radeon_device *rdev) |
1016 | { |
||
1321 | serge | 1017 | if (rdev->mode_info.atom_context) { |
1018 | kfree(rdev->mode_info.atom_context->scratch); |
||
3764 | Serge | 1019 | } |
1119 | serge | 1020 | kfree(rdev->mode_info.atom_context); |
3764 | Serge | 1021 | rdev->mode_info.atom_context = NULL; |
1268 | serge | 1022 | kfree(rdev->mode_info.atom_card_info); |
3764 | Serge | 1023 | rdev->mode_info.atom_card_info = NULL; |
1117 | serge | 1024 | } |
1025 | |||
2997 | Serge | 1026 | /* COMBIOS */ |
1027 | /* |
||
1028 | * COMBIOS is the bios format prior to ATOM. It provides |
||
1029 | * command tables similar to ATOM, but doesn't have a unified |
||
1030 | * parser. See radeon_combios.c |
||
1031 | */ |
||
1032 | |||
1033 | /** |
||
1034 | * radeon_combios_init - init the driver info for combios |
||
1035 | * |
||
1036 | * @rdev: radeon_device pointer |
||
1037 | * |
||
1038 | * Initializes the driver info for combios (r1xx-r3xx). |
||
1039 | * Returns 0 on sucess. |
||
1040 | * Called at driver startup. |
||
1041 | */ |
||
1117 | serge | 1042 | int radeon_combios_init(struct radeon_device *rdev) |
1043 | { |
||
1128 | serge | 1044 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 1045 | return 0; |
1046 | } |
||
1047 | |||
2997 | Serge | 1048 | /** |
1049 | * radeon_combios_fini - free the driver info for combios |
||
1050 | * |
||
1051 | * @rdev: radeon_device pointer |
||
1052 | * |
||
1053 | * Frees the driver info for combios (r1xx-r3xx). |
||
1054 | * Called at driver shutdown. |
||
1055 | */ |
||
1117 | serge | 1056 | void radeon_combios_fini(struct radeon_device *rdev) |
1057 | { |
||
1058 | } |
||
1059 | |||
2997 | Serge | 1060 | /* if we get transitioned to only one device, take VGA back */ |
1061 | /** |
||
1062 | * radeon_vga_set_decode - enable/disable vga decode |
||
1063 | * |
||
1064 | * @cookie: radeon_device pointer |
||
1065 | * @state: enable/disable vga decode |
||
1066 | * |
||
1067 | * Enable/disable vga decode (all asics). |
||
1068 | * Returns VGA resource flags. |
||
1069 | */ |
||
1233 | serge | 1070 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
1071 | { |
||
1072 | struct radeon_device *rdev = cookie; |
||
1073 | radeon_vga_set_state(rdev, state); |
||
1074 | if (state) |
||
1075 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
1076 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
1077 | else |
||
1078 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
1079 | } |
||
1117 | serge | 1080 | |
2997 | Serge | 1081 | /** |
1082 | * radeon_check_pot_argument - check that argument is a power of two |
||
1083 | * |
||
1084 | * @arg: value to check |
||
1085 | * |
||
1086 | * Validates that a certain argument is a power of two (all asics). |
||
1087 | * Returns true if argument is valid. |
||
1088 | */ |
||
1089 | static bool radeon_check_pot_argument(int arg) |
||
1404 | serge | 1090 | { |
2997 | Serge | 1091 | return (arg & (arg - 1)) == 0; |
1092 | } |
||
1093 | |||
1094 | /** |
||
1095 | * radeon_check_arguments - validate module params |
||
1096 | * |
||
1097 | * @rdev: radeon_device pointer |
||
1098 | * |
||
1099 | * Validates certain module parameters and updates |
||
1100 | * the associated values used by the driver (all asics). |
||
1101 | */ |
||
1102 | static void radeon_check_arguments(struct radeon_device *rdev) |
||
1103 | { |
||
1404 | serge | 1104 | /* vramlimit must be a power of two */ |
2997 | Serge | 1105 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
1404 | serge | 1106 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
1107 | radeon_vram_limit); |
||
1108 | radeon_vram_limit = 0; |
||
1109 | } |
||
2997 | Serge | 1110 | |
5078 | serge | 1111 | if (radeon_gart_size == -1) { |
1112 | /* default to a larger gart size on newer asics */ |
||
1113 | if (rdev->family >= CHIP_RV770) |
||
1114 | radeon_gart_size = 1024; |
||
1115 | else |
||
1116 | radeon_gart_size = 512; |
||
1117 | } |
||
1404 | serge | 1118 | /* gtt size must be power of two and greater or equal to 32M */ |
2997 | Serge | 1119 | if (radeon_gart_size < 32) { |
5078 | serge | 1120 | dev_warn(rdev->dev, "gart size (%d) too small\n", |
1404 | serge | 1121 | radeon_gart_size); |
5078 | serge | 1122 | if (rdev->family >= CHIP_RV770) |
1123 | radeon_gart_size = 1024; |
||
1124 | else |
||
1404 | serge | 1125 | radeon_gart_size = 512; |
2997 | Serge | 1126 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
1404 | serge | 1127 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
1128 | radeon_gart_size); |
||
5078 | serge | 1129 | if (rdev->family >= CHIP_RV770) |
1130 | radeon_gart_size = 1024; |
||
1131 | else |
||
1404 | serge | 1132 | radeon_gart_size = 512; |
1133 | } |
||
2997 | Serge | 1134 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
1135 | |||
1404 | serge | 1136 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
1137 | switch (radeon_agpmode) { |
||
1138 | case -1: |
||
1139 | case 0: |
||
1140 | case 1: |
||
1141 | case 2: |
||
1142 | case 4: |
||
1143 | case 8: |
||
1144 | break; |
||
1145 | default: |
||
1146 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
1147 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
1148 | radeon_agpmode = 0; |
||
1149 | break; |
||
1150 | } |
||
5078 | serge | 1151 | |
1152 | if (!radeon_check_pot_argument(radeon_vm_size)) { |
||
1153 | dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", |
||
1154 | radeon_vm_size); |
||
1155 | radeon_vm_size = 4; |
||
1156 | } |
||
1157 | |||
1158 | if (radeon_vm_size < 1) { |
||
1159 | dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", |
||
1160 | radeon_vm_size); |
||
1161 | radeon_vm_size = 4; |
||
1162 | } |
||
1163 | |||
1164 | /* |
||
1165 | * Max GPUVM size for Cayman, SI and CI are 40 bits. |
||
1166 | */ |
||
1167 | if (radeon_vm_size > 1024) { |
||
1168 | dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", |
||
1169 | radeon_vm_size); |
||
1170 | radeon_vm_size = 4; |
||
1171 | } |
||
1172 | |||
1173 | /* defines number of bits in page table versus page directory, |
||
1174 | * a page is 4KB so we have 12 bits offset, minimum 9 bits in the |
||
1175 | * page table and the remaining bits are in the page directory */ |
||
1176 | if (radeon_vm_block_size == -1) { |
||
1177 | |||
1178 | /* Total bits covered by PD + PTs */ |
||
5179 | serge | 1179 | unsigned bits = ilog2(radeon_vm_size) + 18; |
5078 | serge | 1180 | |
1181 | /* Make sure the PD is 4K in size up to 8GB address space. |
||
1182 | Above that split equal between PD and PTs */ |
||
1183 | if (radeon_vm_size <= 8) |
||
1184 | radeon_vm_block_size = bits - 9; |
||
1185 | else |
||
1186 | radeon_vm_block_size = (bits + 3) / 2; |
||
1187 | |||
1188 | } else if (radeon_vm_block_size < 9) { |
||
1189 | dev_warn(rdev->dev, "VM page table size (%d) too small\n", |
||
1190 | radeon_vm_block_size); |
||
1191 | radeon_vm_block_size = 9; |
||
1192 | } |
||
1193 | |||
1194 | if (radeon_vm_block_size > 24 || |
||
1195 | (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { |
||
1196 | dev_warn(rdev->dev, "VM page table size (%d) too large\n", |
||
1197 | radeon_vm_block_size); |
||
1198 | radeon_vm_block_size = 9; |
||
1199 | } |
||
1404 | serge | 1200 | } |
1201 | |||
5078 | serge | 1202 | /** |
1203 | * radeon_device_init - initialize the driver |
||
1204 | * |
||
1205 | * @rdev: radeon_device pointer |
||
1206 | * @pdev: drm dev pointer |
||
1207 | * @pdev: pci dev pointer |
||
1208 | * @flags: driver flags |
||
1209 | * |
||
1210 | * Initializes the driver info and hw (all asics). |
||
1211 | * Returns 0 for success or an error on failure. |
||
1212 | * Called at driver startup. |
||
1213 | */ |
||
1117 | serge | 1214 | int radeon_device_init(struct radeon_device *rdev, |
1215 | struct drm_device *ddev, |
||
1216 | struct pci_dev *pdev, |
||
1217 | uint32_t flags) |
||
1218 | { |
||
1963 | serge | 1219 | int r, i; |
1179 | serge | 1220 | int dma_bits; |
5078 | serge | 1221 | bool runtime = false; |
1117 | serge | 1222 | |
1223 | rdev->shutdown = false; |
||
5078 | serge | 1224 | rdev->dev = &pdev->dev; |
1117 | serge | 1225 | rdev->ddev = ddev; |
1226 | rdev->pdev = pdev; |
||
1227 | rdev->flags = flags; |
||
1228 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
1229 | rdev->is_atom_bios = false; |
||
1230 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
5078 | serge | 1231 | rdev->mc.gtt_size = 512 * 1024 * 1024; |
1221 | serge | 1232 | rdev->accel_working = false; |
2997 | Serge | 1233 | /* set up ring ids */ |
1234 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
||
1235 | rdev->ring[i].idx = i; |
||
1236 | } |
||
1963 | serge | 1237 | |
2997 | Serge | 1238 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
1239 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
||
1240 | pdev->subsystem_vendor, pdev->subsystem_device); |
||
1963 | serge | 1241 | |
1117 | serge | 1242 | /* mutex initialization are all done here so we |
1243 | * can recall function without having locking issues */ |
||
2997 | Serge | 1244 | mutex_init(&rdev->ring_lock); |
1630 | serge | 1245 | mutex_init(&rdev->dc_hw_i2c_mutex); |
2997 | Serge | 1246 | atomic_set(&rdev->ih.lock, 0); |
1630 | serge | 1247 | mutex_init(&rdev->gem.mutex); |
1248 | mutex_init(&rdev->pm.mutex); |
||
2997 | Serge | 1249 | mutex_init(&rdev->gpu_clock_mutex); |
5078 | serge | 1250 | mutex_init(&rdev->srbm_mutex); |
3764 | Serge | 1251 | // init_rwsem(&rdev->pm.mclk_lock); |
1252 | // init_rwsem(&rdev->exclusive_lock); |
||
2997 | Serge | 1253 | init_waitqueue_head(&rdev->irq.vblank_queue); |
1254 | r = radeon_gem_init(rdev); |
||
1255 | if (r) |
||
1256 | return r; |
||
5078 | serge | 1257 | |
1258 | radeon_check_arguments(rdev); |
||
2997 | Serge | 1259 | /* Adjust VM size here. |
5078 | serge | 1260 | * Max GPUVM size for cayman+ is 40 bits. |
2997 | Serge | 1261 | */ |
5078 | serge | 1262 | rdev->vm_manager.max_pfn = radeon_vm_size << 18; |
1117 | serge | 1263 | |
1179 | serge | 1264 | /* Set asic functions */ |
1265 | r = radeon_asic_init(rdev); |
||
1404 | serge | 1266 | if (r) |
1179 | serge | 1267 | return r; |
1268 | |||
1963 | serge | 1269 | /* all of the newer IGP chips have an internal gart |
1270 | * However some rs4xx report as AGP, so remove that here. |
||
1271 | */ |
||
1272 | if ((rdev->family >= CHIP_RS400) && |
||
1273 | (rdev->flags & RADEON_IS_IGP)) { |
||
1274 | rdev->flags &= ~RADEON_IS_AGP; |
||
1275 | } |
||
1276 | |||
1321 | serge | 1277 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 1278 | radeon_agp_disable(rdev); |
1117 | serge | 1279 | } |
1280 | |||
3764 | Serge | 1281 | /* Set the internal MC address mask |
1282 | * This is the max address of the GPU's |
||
1283 | * internal address space. |
||
1284 | */ |
||
1285 | if (rdev->family >= CHIP_CAYMAN) |
||
1286 | rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
||
1287 | else if (rdev->family >= CHIP_CEDAR) |
||
1288 | rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ |
||
1289 | else |
||
1290 | rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ |
||
1291 | |||
1179 | serge | 1292 | /* set DMA mask + need_dma32 flags. |
1293 | * PCIE - can handle 40-bits. |
||
2997 | Serge | 1294 | * IGP - can handle 40-bits |
1179 | serge | 1295 | * AGP - generally dma32 is safest |
2997 | Serge | 1296 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
1179 | serge | 1297 | */ |
1298 | rdev->need_dma32 = false; |
||
1299 | if (rdev->flags & RADEON_IS_AGP) |
||
1300 | rdev->need_dma32 = true; |
||
2997 | Serge | 1301 | if ((rdev->flags & RADEON_IS_PCI) && |
1302 | (rdev->family <= CHIP_RS740)) |
||
1179 | serge | 1303 | rdev->need_dma32 = true; |
1117 | serge | 1304 | |
1179 | serge | 1305 | dma_bits = rdev->need_dma32 ? 32 : 40; |
1306 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 1307 | if (r) { |
1986 | serge | 1308 | rdev->need_dma32 = true; |
2997 | Serge | 1309 | dma_bits = 32; |
1119 | serge | 1310 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
1311 | } |
||
1117 | serge | 1312 | |
1313 | /* Registers mapping */ |
||
1314 | /* TODO: block userspace mapping of io register */ |
||
3192 | Serge | 1315 | spin_lock_init(&rdev->mmio_idx_lock); |
5078 | serge | 1316 | spin_lock_init(&rdev->smc_idx_lock); |
1317 | spin_lock_init(&rdev->pll_idx_lock); |
||
1318 | spin_lock_init(&rdev->mc_idx_lock); |
||
1319 | spin_lock_init(&rdev->pcie_idx_lock); |
||
1320 | spin_lock_init(&rdev->pciep_idx_lock); |
||
1321 | spin_lock_init(&rdev->pif_idx_lock); |
||
1322 | spin_lock_init(&rdev->cg_idx_lock); |
||
1323 | spin_lock_init(&rdev->uvd_idx_lock); |
||
1324 | spin_lock_init(&rdev->rcu_idx_lock); |
||
1325 | spin_lock_init(&rdev->didt_idx_lock); |
||
1326 | spin_lock_init(&rdev->end_idx_lock); |
||
1327 | if (rdev->family >= CHIP_BONAIRE) { |
||
1328 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); |
||
1329 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); |
||
1330 | } else { |
||
1117 | serge | 1331 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
1332 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
5078 | serge | 1333 | } |
2997 | Serge | 1334 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
1117 | serge | 1335 | if (rdev->rmmio == NULL) { |
1336 | return -ENOMEM; |
||
1337 | } |
||
1338 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
1339 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
1340 | |||
5078 | serge | 1341 | /* doorbell bar mapping */ |
1342 | if (rdev->family >= CHIP_BONAIRE) |
||
1343 | radeon_doorbell_init(rdev); |
||
1344 | |||
2997 | Serge | 1345 | /* io port mapping */ |
1346 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
||
1347 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
||
1348 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
||
1349 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
||
1350 | break; |
||
1351 | } |
||
1352 | } |
||
1353 | if (rdev->rio_mem == NULL) |
||
1354 | DRM_ERROR("Unable to find PCI I/O BAR\n"); |
||
1355 | |||
5078 | serge | 1356 | if (rdev->flags & RADEON_IS_PX) |
1357 | radeon_device_handle_px_quirks(rdev); |
||
1358 | if (rdev->flags & RADEON_IS_PX) |
||
1359 | runtime = true; |
||
2997 | Serge | 1360 | |
1179 | serge | 1361 | r = radeon_init(rdev); |
1221 | serge | 1362 | if (r) |
1963 | serge | 1363 | return r; |
1117 | serge | 1364 | |
5078 | serge | 1365 | r = radeon_ib_ring_tests(rdev); |
1366 | if (r) |
||
1367 | DRM_ERROR("ib ring test failed (%d).\n", r); |
||
3192 | Serge | 1368 | |
5078 | serge | 1369 | |
1221 | serge | 1370 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
1371 | /* Acceleration not working on AGP card try again |
||
1372 | * with fallback to PCI or PCIE GART |
||
1373 | */ |
||
1963 | serge | 1374 | radeon_asic_reset(rdev); |
1221 | serge | 1375 | radeon_fini(rdev); |
1376 | radeon_agp_disable(rdev); |
||
1377 | r = radeon_init(rdev); |
||
1378 | if (r) |
||
1179 | serge | 1379 | return r; |
1126 | serge | 1380 | } |
5078 | serge | 1381 | |
1382 | if ((radeon_testing & 1)) { |
||
1383 | if (rdev->accel_working) |
||
1384 | radeon_test_moves(rdev); |
||
1385 | else |
||
1386 | DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); |
||
1387 | } |
||
1388 | if ((radeon_testing & 2)) { |
||
1389 | if (rdev->accel_working) |
||
1390 | radeon_test_syncing(rdev); |
||
1391 | else |
||
1392 | DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); |
||
1393 | } |
||
2005 | serge | 1394 | if (radeon_benchmarking) { |
5078 | serge | 1395 | if (rdev->accel_working) |
2997 | Serge | 1396 | radeon_benchmark(rdev, radeon_benchmarking); |
5078 | serge | 1397 | else |
1398 | DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); |
||
2005 | serge | 1399 | } |
1179 | serge | 1400 | return 0; |
1117 | serge | 1401 | } |
1402 | |||
2997 | Serge | 1403 | /** |
1404 | * radeon_gpu_reset - reset the asic |
||
1405 | * |
||
1406 | * @rdev: radeon device pointer |
||
1407 | * |
||
1408 | * Attempt the reset the GPU if it has hung (all asics). |
||
1409 | * Returns 0 for success or an error on failure. |
||
1410 | */ |
||
1411 | int radeon_gpu_reset(struct radeon_device *rdev) |
||
1412 | { |
||
1413 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
||
1414 | uint32_t *ring_data[RADEON_NUM_RINGS]; |
||
1179 | serge | 1415 | |
2997 | Serge | 1416 | bool saved = false; |
1417 | |||
1418 | int i, r; |
||
1419 | int resched; |
||
1420 | |||
1421 | // down_write(&rdev->exclusive_lock); |
||
5078 | serge | 1422 | rdev->needs_reset = false; |
1423 | |||
2997 | Serge | 1424 | radeon_save_bios_scratch_regs(rdev); |
1425 | /* block TTM */ |
||
1426 | // resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
||
1427 | radeon_suspend(rdev); |
||
1428 | |||
1429 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1430 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
||
1431 | &ring_data[i]); |
||
1432 | if (ring_sizes[i]) { |
||
1433 | saved = true; |
||
1434 | dev_info(rdev->dev, "Saved %d dwords of commands " |
||
1435 | "on ring %d.\n", ring_sizes[i], i); |
||
1436 | } |
||
1437 | } |
||
1438 | |||
1439 | retry: |
||
1440 | r = radeon_asic_reset(rdev); |
||
1441 | if (!r) { |
||
1442 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
||
1443 | radeon_resume(rdev); |
||
1444 | } |
||
1445 | |||
1446 | radeon_restore_bios_scratch_regs(rdev); |
||
1447 | |||
1448 | if (!r) { |
||
1449 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1450 | radeon_ring_restore(rdev, &rdev->ring[i], |
||
1451 | ring_sizes[i], ring_data[i]); |
||
1452 | ring_sizes[i] = 0; |
||
1453 | ring_data[i] = NULL; |
||
1454 | } |
||
1455 | |||
3192 | Serge | 1456 | // r = radeon_ib_ring_tests(rdev); |
1457 | // if (r) { |
||
1458 | // dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
||
1459 | // if (saved) { |
||
1460 | // saved = false; |
||
1461 | // radeon_suspend(rdev); |
||
1462 | // goto retry; |
||
1463 | // } |
||
1464 | // } |
||
2997 | Serge | 1465 | } else { |
1466 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1467 | kfree(ring_data[i]); |
||
1468 | } |
||
1469 | } |
||
1470 | |||
1471 | // ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
||
1472 | if (r) { |
||
1473 | /* bad news, how to tell it to userspace ? */ |
||
1474 | dev_info(rdev->dev, "GPU reset failed\n"); |
||
1475 | } |
||
1476 | |||
1477 | // up_write(&rdev->exclusive_lock); |
||
1478 | return r; |
||
1479 | } |
||
1480 | |||
1481 | |||
1117 | serge | 1482 | /* |
1483 | * Driver load/unload |
||
1484 | */ |
||
1485 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
1486 | { |
||
1487 | struct radeon_device *rdev; |
||
1488 | int r; |
||
1489 | |||
1490 | |||
1120 | serge | 1491 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 1492 | if (rdev == NULL) { |
1493 | return -ENOMEM; |
||
1494 | }; |
||
1495 | |||
1496 | dev->dev_private = (void *)rdev; |
||
1497 | |||
1498 | /* update BUS flag */ |
||
5097 | serge | 1499 | if (drm_pci_device_is_agp(dev)) { |
1117 | serge | 1500 | flags |= RADEON_IS_AGP; |
1239 | serge | 1501 | } else if (drm_device_is_pcie(dev)) { |
1502 | flags |= RADEON_IS_PCIE; |
||
1503 | } else { |
||
1504 | flags |= RADEON_IS_PCI; |
||
1505 | } |
||
1117 | serge | 1506 | |
1182 | serge | 1507 | /* radeon_device_init should report only fatal error |
1508 | * like memory allocation failure or iomapping failure, |
||
1509 | * or memory manager initialization failure, it must |
||
1510 | * properly initialize the GPU MC controller and permit |
||
1511 | * VRAM allocation |
||
1512 | */ |
||
1117 | serge | 1513 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
1514 | if (r) { |
||
1182 | serge | 1515 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 1516 | return r; |
1517 | } |
||
1182 | serge | 1518 | /* Again modeset_init should fail only on fatal error |
1519 | * otherwise it should provide enough functionalities |
||
1520 | * for shadowfb to run |
||
1521 | */ |
||
5078 | serge | 1522 | main_device = dev; |
1523 | |||
1246 | serge | 1524 | if( radeon_modeset ) |
1525 | { |
||
1268 | serge | 1526 | r = radeon_modeset_init(rdev); |
1527 | if (r) { |
||
1528 | return r; |
||
1529 | } |
||
5078 | serge | 1530 | init_display_kms(dev, &usermode); |
1531 | } |
||
1986 | serge | 1532 | else |
5078 | serge | 1533 | init_display(rdev, &usermode); |
1126 | serge | 1534 | |
1117 | serge | 1535 | return 0; |
5078 | serge | 1536 | } |
1117 | serge | 1537 | |
1538 | |||
1221 | serge | 1539 | |
1117 | serge | 1540 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
1541 | { |
||
1542 | return pci_resource_start(dev->pdev, resource); |
||
1543 | } |
||
1544 | |||
1545 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
1546 | { |
||
1547 | return pci_resource_len(dev->pdev, resource); |
||
1548 | } |
||
1549 | |||
1123 | serge | 1550 | |
1551 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
1552 | { |
||
1553 | uint64_t rem = *n; |
||
1554 | uint64_t b = base; |
||
1555 | uint64_t res, d = 1; |
||
1556 | uint32_t high = rem >> 32; |
||
1557 | |||
1558 | /* Reduce the thing a bit first */ |
||
1559 | res = 0; |
||
1560 | if (high >= base) { |
||
1561 | high /= base; |
||
1562 | res = (uint64_t) high << 32; |
||
1563 | rem -= (uint64_t) (high*base) << 32; |
||
1564 | } |
||
1565 | |||
1566 | while ((int64_t)b > 0 && b < rem) { |
||
1567 | b = b+b; |
||
1568 | d = d+d; |
||
1569 | } |
||
1570 | |||
1571 | do { |
||
1572 | if (rem >= b) { |
||
1573 | rem -= b; |
||
1574 | res += d; |
||
1575 | } |
||
1576 | b >>= 1; |
||
1577 | d >>= 1; |
||
1578 | } while (d); |
||
1579 | |||
1580 | *n = res; |
||
1581 | return rem; |
||
1582 | } |
||
1583 | |||
1239 | serge | 1584 | static struct pci_device_id pciidlist[] = { |
1585 | radeon_PCI_IDS |
||
1586 | }; |
||
1587 | |||
5078 | serge | 1588 | void radeon_driver_irq_preinstall_kms(struct drm_device *dev); |
1589 | int radeon_driver_irq_postinstall_kms(struct drm_device *dev); |
||
1590 | void radeon_driver_irq_uninstall_kms(struct drm_device *dev); |
||
1591 | irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg); |
||
1239 | serge | 1592 | |
1593 | |||
5078 | serge | 1594 | static struct drm_driver kms_driver = { |
1595 | .driver_features = |
||
1596 | DRIVER_USE_AGP | |
||
1597 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | |
||
1598 | DRIVER_PRIME | DRIVER_RENDER, |
||
1599 | .load = radeon_driver_load_kms, |
||
1600 | // .open = radeon_driver_open_kms, |
||
1601 | // .preclose = radeon_driver_preclose_kms, |
||
1602 | // .postclose = radeon_driver_postclose_kms, |
||
1603 | // .lastclose = radeon_driver_lastclose_kms, |
||
1604 | // .unload = radeon_driver_unload_kms, |
||
1605 | // .get_vblank_counter = radeon_get_vblank_counter_kms, |
||
1606 | // .enable_vblank = radeon_enable_vblank_kms, |
||
1607 | // .disable_vblank = radeon_disable_vblank_kms, |
||
1608 | // .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, |
||
1609 | // .get_scanout_position = radeon_get_crtc_scanoutpos, |
||
1610 | #if defined(CONFIG_DEBUG_FS) |
||
1611 | .debugfs_init = radeon_debugfs_init, |
||
1612 | .debugfs_cleanup = radeon_debugfs_cleanup, |
||
1613 | #endif |
||
1614 | .irq_preinstall = radeon_driver_irq_preinstall_kms, |
||
1615 | .irq_postinstall = radeon_driver_irq_postinstall_kms, |
||
1616 | .irq_uninstall = radeon_driver_irq_uninstall_kms, |
||
1617 | .irq_handler = radeon_driver_irq_handler_kms, |
||
1618 | // .ioctls = radeon_ioctls_kms, |
||
1619 | // .gem_free_object = radeon_gem_object_free, |
||
1620 | // .gem_open_object = radeon_gem_object_open, |
||
1621 | // .gem_close_object = radeon_gem_object_close, |
||
1622 | // .dumb_create = radeon_mode_dumb_create, |
||
1623 | // .dumb_map_offset = radeon_mode_dumb_mmap, |
||
1624 | // .dumb_destroy = drm_gem_dumb_destroy, |
||
1625 | // .fops = &radeon_driver_kms_fops, |
||
3120 | serge | 1626 | |
5078 | serge | 1627 | // .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
1628 | // .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
||
1629 | // .gem_prime_export = drm_gem_prime_export, |
||
1630 | // .gem_prime_import = drm_gem_prime_import, |
||
1631 | // .gem_prime_pin = radeon_gem_prime_pin, |
||
1632 | // .gem_prime_unpin = radeon_gem_prime_unpin, |
||
1633 | // .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table, |
||
1634 | // .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, |
||
1635 | // .gem_prime_vmap = radeon_gem_prime_vmap, |
||
1636 | // .gem_prime_vunmap = radeon_gem_prime_vunmap, |
||
1239 | serge | 1637 | |
5078 | serge | 1638 | }; |
2007 | serge | 1639 | |
5078 | serge | 1640 | int ati_init(void) |
1239 | serge | 1641 | { |
5078 | serge | 1642 | static pci_dev_t device; |
2997 | Serge | 1643 | const struct pci_device_id *ent; |
5078 | serge | 1644 | int err; |
1239 | serge | 1645 | |
1646 | ent = find_pci_device(&device, pciidlist); |
||
1647 | if( unlikely(ent == NULL) ) |
||
1648 | { |
||
1649 | dbgprintf("device not found\n"); |
||
5078 | serge | 1650 | return -ENODEV; |
1239 | serge | 1651 | }; |
1652 | |||
5078 | serge | 1653 | drm_core_init(); |
1654 | |||
1655 | DRM_INFO("device %x:%x\n", device.pci_dev.vendor, |
||
1239 | serge | 1656 | device.pci_dev.device); |
1657 | |||
5078 | serge | 1658 | kms_driver.driver_features |= DRIVER_MODESET; |
3764 | Serge | 1659 | |
5078 | serge | 1660 | err = drm_get_pci_dev(&device.pci_dev, ent, &kms_driver); |
1239 | serge | 1661 | |
1246 | serge | 1662 | return err; |
5078 | serge | 1663 | }>><>><>>>>>=>><>>><>>>=>>><>>>=>><>>>>>>>>>>>><>><> |
1430 | serge | 1664 |