WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
1123	serge	29
1179	serge	30	#include
		31	#include
1221	serge	32	#include
1117	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35	#include "radeon_asic.h"
		36	#include "atom.h"
		37
1221	serge	38	#include
		39
1117	serge	40
		41	int radeon_dynclks = -1;
1123	serge	42	int radeon_r4xx_atom = 0;
1125	serge	43	int radeon_agpmode = -1;
1117	serge	44	int radeon_gart_size = 512; /* default gart size */
1123	serge	45	int radeon_benchmarking = 0;
		46	int radeon_connector_table = 0;
1222	serge	47	int radeon_tv = 0;
1246	serge	48	int radeon_modeset = 1;
1117	serge	49
1233	serge	50	void parse_cmdline(char cmdline, mode_t mode, char *log);
		51	int init_display(struct radeon_device rdev, mode_t mode);
1246	serge	52	int init_display_kms(struct radeon_device rdev, mode_t mode);
		53
1239	serge	54	int get_modes(mode_t mode, int count);
		55	int set_user_mode(mode_t *mode);
1117	serge	56
1239	serge	57
1233	serge	58	/* Legacy VGA regions */
		59	#define VGA_RSRC_NONE 0x00
		60	#define VGA_RSRC_LEGACY_IO 0x01
		61	#define VGA_RSRC_LEGACY_MEM 0x02
		62	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
		63	/* Non-legacy access */
		64	#define VGA_RSRC_NORMAL_IO 0x04
		65	#define VGA_RSRC_NORMAL_MEM 0x08
		66
		67
		68
1117	serge	69	/*
		70	* Clear GPU surface registers.
		71	*/
1179	serge	72	void radeon_surface_init(struct radeon_device *rdev)
1117	serge	73	{
1179	serge	74	ENTER();
1117	serge	75
		76	/* FIXME: check this out */
		77	if (rdev->family < CHIP_R600) {
		78	int i;
		79
		80	for (i = 0; i < 8; i++) {
		81	WREG32(RADEON_SURFACE0_INFO +
		82	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
		83	0);
		84	}
1179	serge	85	/* enable surfaces */
		86	WREG32(RADEON_SURFACE_CNTL, 0);
1117	serge	87	}
		88	}
		89
		90	/*
		91	* GPU scratch registers helpers function.
		92	*/
1179	serge	93	void radeon_scratch_init(struct radeon_device *rdev)
1117	serge	94	{
		95	int i;
		96
		97	/* FIXME: check this out */
		98	if (rdev->family < CHIP_R300) {
		99	rdev->scratch.num_reg = 5;
		100	} else {
		101	rdev->scratch.num_reg = 7;
		102	}
		103	for (i = 0; i < rdev->scratch.num_reg; i++) {
		104	rdev->scratch.free[i] = true;
		105	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
		106	}
		107	}
		108
		109	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		110	{
		111	int i;
		112
		113	for (i = 0; i < rdev->scratch.num_reg; i++) {
		114	if (rdev->scratch.free[i]) {
		115	rdev->scratch.free[i] = false;
		116	*reg = rdev->scratch.reg[i];
		117	return 0;
		118	}
		119	}
		120	return -EINVAL;
		121	}
		122
		123	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		124	{
		125	int i;
		126
		127	for (i = 0; i < rdev->scratch.num_reg; i++) {
		128	if (rdev->scratch.reg[i] == reg) {
		129	rdev->scratch.free[i] = true;
		130	return;
		131	}
		132	}
		133	}
		134
		135	/*
		136	* MC common functions
		137	*/
		138	int radeon_mc_setup(struct radeon_device *rdev)
		139	{
		140	uint32_t tmp;
		141
		142	/* Some chips have an "issue" with the memory controller, the
		143	* location must be aligned to the size. We just align it down,
		144	* too bad if we walk over the top of system memory, we don't
		145	* use DMA without a remapped anyway.
		146	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		147	*/
		148	/* FGLRX seems to setup like this, VRAM a 0, then GART.
		149	*/
1126	serge	150	/*
1117	serge	151	* Note: from R6xx the address space is 40bits but here we only
		152	* use 32bits (still have to see a card which would exhaust 4G
		153	* address space).
		154	*/
		155	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		156	/* vram location was already setup try to put gtt after
		157	* if it fits */
1179	serge	158	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117	serge	159	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		160	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		161	rdev->mc.gtt_location = tmp;
		162	} else {
		163	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
		164	printk(KERN_ERR "[drm] GTT too big to fit "
		165	"before or after vram location.\n");
		166	return -EINVAL;
		167	}
		168	rdev->mc.gtt_location = 0;
		169	}
		170	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		171	/* gtt location was already setup try to put vram before
		172	* if it fits */
1179	serge	173	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117	serge	174	rdev->mc.vram_location = 0;
		175	} else {
		176	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179	serge	177	tmp += (rdev->mc.mc_vram_size - 1);
		178	tmp &= ~(rdev->mc.mc_vram_size - 1);
		179	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117	serge	180	rdev->mc.vram_location = tmp;
		181	} else {
		182	printk(KERN_ERR "[drm] vram too big to fit "
		183	"before or after GTT location.\n");
		184	return -EINVAL;
		185	}
		186	}
		187	} else {
		188	rdev->mc.vram_location = 0;
1179	serge	189	tmp = rdev->mc.mc_vram_size;
		190	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		191	rdev->mc.gtt_location = tmp;
1117	serge	192	}
1179	serge	193	rdev->mc.vram_start = rdev->mc.vram_location;
		194	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		195	rdev->mc.gtt_start = rdev->mc.gtt_location;
		196	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		197	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117	serge	198	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179	serge	199	(unsigned)rdev->mc.vram_location,
		200	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
		201	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117	serge	202	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179	serge	203	(unsigned)rdev->mc.gtt_location,
		204	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117	serge	205	return 0;
		206	}
		207
		208
		209	/*
		210	* GPU helpers function.
		211	*/
1179	serge	212	bool radeon_card_posted(struct radeon_device *rdev)
1117	serge	213	{
		214	uint32_t reg;
		215
1179	serge	216	ENTER();
1117	serge	217
		218	/* first check CRTCs */
		219	if (ASIC_IS_AVIVO(rdev)) {
		220	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		221	RREG32(AVIVO_D2CRTC_CONTROL);
		222	if (reg & AVIVO_CRTC_EN) {
		223	return true;
		224	}
		225	} else {
		226	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		227	RREG32(RADEON_CRTC2_GEN_CNTL);
		228	if (reg & RADEON_CRTC_EN) {
		229	return true;
		230	}
		231	}
		232
		233	/* then check MEM_SIZE, in case the crtcs are off */
		234	if (rdev->family >= CHIP_R600)
		235	reg = RREG32(R600_CONFIG_MEMSIZE);
		236	else
		237	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		238
		239	if (reg)
		240	return true;
		241
		242	return false;
		243
		244	}
		245
1233	serge	246	int radeon_dummy_page_init(struct radeon_device *rdev)
		247	{
		248	rdev->dummy_page.page = AllocPage();
		249	if (rdev->dummy_page.page == NULL)
		250	return -ENOMEM;
		251	rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
		252	if (!rdev->dummy_page.addr) {
		253	// __free_page(rdev->dummy_page.page);
		254	rdev->dummy_page.page = NULL;
		255	return -ENOMEM;
		256	}
		257	return 0;
		258	}
1117	serge	259
1233	serge	260	void radeon_dummy_page_fini(struct radeon_device *rdev)
		261	{
		262	if (rdev->dummy_page.page == NULL)
		263	return;
		264	KernelFree(rdev->dummy_page.addr);
		265	rdev->dummy_page.page = NULL;
		266	}
		267
		268
1117	serge	269	/*
		270	* Registers accessors functions.
		271	*/
		272	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		273	{
		274	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		275	BUG_ON(1);
		276	return 0;
		277	}
		278
		279	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		280	{
		281	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		282	reg, v);
		283	BUG_ON(1);
		284	}
		285
		286	void radeon_register_accessor_init(struct radeon_device *rdev)
		287	{
		288	rdev->mc_rreg = &radeon_invalid_rreg;
		289	rdev->mc_wreg = &radeon_invalid_wreg;
		290	rdev->pll_rreg = &radeon_invalid_rreg;
		291	rdev->pll_wreg = &radeon_invalid_wreg;
		292	rdev->pciep_rreg = &radeon_invalid_rreg;
		293	rdev->pciep_wreg = &radeon_invalid_wreg;
		294
		295	/* Don't change order as we are overridding accessor. */
		296	if (rdev->family < CHIP_RV515) {
1179	serge	297	rdev->pcie_reg_mask = 0xff;
		298	} else {
		299	rdev->pcie_reg_mask = 0x7ff;
1117	serge	300	}
		301	/* FIXME: not sure here */
		302	if (rdev->family <= CHIP_R580) {
1119	serge	303	rdev->pll_rreg = &r100_pll_rreg;
		304	rdev->pll_wreg = &r100_pll_wreg;
1117	serge	305	}
1179	serge	306	if (rdev->family >= CHIP_R420) {
		307	rdev->mc_rreg = &r420_mc_rreg;
		308	rdev->mc_wreg = &r420_mc_wreg;
		309	}
1117	serge	310	if (rdev->family >= CHIP_RV515) {
		311	rdev->mc_rreg = &rv515_mc_rreg;
		312	rdev->mc_wreg = &rv515_mc_wreg;
		313	}
		314	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
1128	serge	315	rdev->mc_rreg = &rs400_mc_rreg;
		316	rdev->mc_wreg = &rs400_mc_wreg;
1117	serge	317	}
1221	serge	318	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		319	rdev->mc_rreg = &rs690_mc_rreg;
		320	rdev->mc_wreg = &rs690_mc_wreg;
		321	}
		322	if (rdev->family == CHIP_RS600) {
		323	rdev->mc_rreg = &rs600_mc_rreg;
		324	rdev->mc_wreg = &rs600_mc_wreg;
		325	}
1233	serge	326	if (rdev->family >= CHIP_R600) {
		327	rdev->pciep_rreg = &r600_pciep_rreg;
		328	rdev->pciep_wreg = &r600_pciep_wreg;
		329	}
1117	serge	330	}
		331
		332
		333	/*
		334	* ASIC
		335	*/
		336	int radeon_asic_init(struct radeon_device *rdev)
		337	{
		338	radeon_register_accessor_init(rdev);
		339	switch (rdev->family) {
		340	case CHIP_R100:
		341	case CHIP_RV100:
		342	case CHIP_RS100:
		343	case CHIP_RV200:
		344	case CHIP_RS200:
		345	case CHIP_R200:
		346	case CHIP_RV250:
		347	case CHIP_RS300:
		348	case CHIP_RV280:
1128	serge	349	rdev->asic = &r100_asic;
1117	serge	350	break;
		351	case CHIP_R300:
		352	case CHIP_R350:
		353	case CHIP_RV350:
		354	case CHIP_RV380:
1128	serge	355	rdev->asic = &r300_asic;
1179	serge	356	if (rdev->flags & RADEON_IS_PCIE) {
		357	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		358	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		359	}
1117	serge	360	break;
		361	case CHIP_R420:
		362	case CHIP_R423:
		363	case CHIP_RV410:
1128	serge	364	rdev->asic = &r420_asic;
1117	serge	365	break;
		366	case CHIP_RS400:
		367	case CHIP_RS480:
1128	serge	368	rdev->asic = &rs400_asic;
1117	serge	369	break;
		370	case CHIP_RS600:
1221	serge	371	rdev->asic = &rs600_asic;
1117	serge	372	break;
		373	case CHIP_RS690:
		374	case CHIP_RS740:
1221	serge	375	rdev->asic = &rs690_asic;
1117	serge	376	break;
		377	case CHIP_RV515:
1128	serge	378	rdev->asic = &rv515_asic;
1117	serge	379	break;
		380	case CHIP_R520:
		381	case CHIP_RV530:
		382	case CHIP_RV560:
		383	case CHIP_RV570:
		384	case CHIP_R580:
		385	rdev->asic = &r520_asic;
		386	break;
		387	case CHIP_R600:
		388	case CHIP_RV610:
		389	case CHIP_RV630:
		390	case CHIP_RV620:
		391	case CHIP_RV635:
		392	case CHIP_RV670:
		393	case CHIP_RS780:
1221	serge	394	case CHIP_RS880:
1233	serge	395	rdev->asic = &r600_asic;
1221	serge	396	break;
1117	serge	397	case CHIP_RV770:
		398	case CHIP_RV730:
		399	case CHIP_RV710:
1221	serge	400	case CHIP_RV740:
1233	serge	401	rdev->asic = &rv770_asic;
1221	serge	402	break;
1117	serge	403	default:
		404	/* FIXME: not supported yet */
		405	return -EINVAL;
		406	}
		407	return 0;
		408	}
		409
		410
		411	/*
		412	* Wrapper around modesetting bits.
		413	*/
		414	int radeon_clocks_init(struct radeon_device *rdev)
		415	{
		416	int r;
		417
1179	serge	418	ENTER();
1117	serge	419
		420	r = radeon_static_clocks_init(rdev->ddev);
		421	if (r) {
		422	return r;
		423	}
		424	DRM_INFO("Clocks initialized !\n");
		425	return 0;
		426	}
		427
		428	void radeon_clocks_fini(struct radeon_device *rdev)
		429	{
		430	}
		431
		432	/* ATOM accessor methods */
		433	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		434	{
		435	struct radeon_device *rdev = info->dev->dev_private;
		436	uint32_t r;
		437
		438	r = rdev->pll_rreg(rdev, reg);
		439	return r;
		440	}
		441
		442	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		443	{
		444	struct radeon_device *rdev = info->dev->dev_private;
		445
		446	rdev->pll_wreg(rdev, reg, val);
		447	}
		448
		449	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		450	{
		451	struct radeon_device *rdev = info->dev->dev_private;
		452	uint32_t r;
		453
		454	r = rdev->mc_rreg(rdev, reg);
		455	return r;
		456	}
		457
		458	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		459	{
		460	struct radeon_device *rdev = info->dev->dev_private;
		461
		462	rdev->mc_wreg(rdev, reg, val);
		463	}
		464
		465	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		466	{
		467	struct radeon_device *rdev = info->dev->dev_private;
		468
		469	WREG32(reg*4, val);
		470	}
		471
		472	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		473	{
		474	struct radeon_device *rdev = info->dev->dev_private;
		475	uint32_t r;
		476
		477	r = RREG32(reg*4);
		478	return r;
		479	}
		480
		481	static struct card_info atom_card_info = {
		482	.dev = NULL,
		483	.reg_read = cail_reg_read,
		484	.reg_write = cail_reg_write,
		485	.mc_read = cail_mc_read,
		486	.mc_write = cail_mc_write,
		487	.pll_read = cail_pll_read,
		488	.pll_write = cail_pll_write,
		489	};
		490
		491	int radeon_atombios_init(struct radeon_device *rdev)
		492	{
1179	serge	493	ENTER();
1117	serge	494
		495	atom_card_info.dev = rdev->ddev;
		496	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
		497	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
		498	return 0;
		499	}
		500
		501	void radeon_atombios_fini(struct radeon_device *rdev)
		502	{
1119	serge	503	kfree(rdev->mode_info.atom_context);
1117	serge	504	}
		505
		506	int radeon_combios_init(struct radeon_device *rdev)
		507	{
1128	serge	508	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117	serge	509	return 0;
		510	}
		511
		512	void radeon_combios_fini(struct radeon_device *rdev)
		513	{
		514	}
		515
1233	serge	516	/* if we get transitioned to only one device, tak VGA back */
		517	static unsigned int radeon_vga_set_decode(void *cookie, bool state)
		518	{
		519	struct radeon_device *rdev = cookie;
		520	radeon_vga_set_state(rdev, state);
		521	if (state)
		522	return VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM \|
		523	VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		524	else
		525	return VGA_RSRC_NORMAL_IO \| VGA_RSRC_NORMAL_MEM;
		526	}
1117	serge	527
1221	serge	528	void radeon_agp_disable(struct radeon_device *rdev)
		529	{
		530	rdev->flags &= ~RADEON_IS_AGP;
		531	if (rdev->family >= CHIP_R600) {
		532	DRM_INFO("Forcing AGP to PCIE mode\n");
		533	rdev->flags \|= RADEON_IS_PCIE;
		534	} else if (rdev->family >= CHIP_RV515 \|\|
		535	rdev->family == CHIP_RV380 \|\|
		536	rdev->family == CHIP_RV410 \|\|
		537	rdev->family == CHIP_R423) {
		538	DRM_INFO("Forcing AGP to PCIE mode\n");
		539	rdev->flags \|= RADEON_IS_PCIE;
		540	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		541	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		542	} else {
		543	DRM_INFO("Forcing AGP to PCI mode\n");
		544	rdev->flags \|= RADEON_IS_PCI;
		545	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		546	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		547	}
		548	}
1179	serge	549
1117	serge	550	/*
		551	* Radeon device.
		552	*/
		553	int radeon_device_init(struct radeon_device *rdev,
		554	struct drm_device *ddev,
		555	struct pci_dev *pdev,
		556	uint32_t flags)
		557	{
1221	serge	558	int r;
1179	serge	559	int dma_bits;
1117	serge	560
1179	serge	561	ENTER();
1117	serge	562
		563	DRM_INFO("radeon: Initializing kernel modesetting.\n");
		564	rdev->shutdown = false;
		565	rdev->ddev = ddev;
		566	rdev->pdev = pdev;
		567	rdev->flags = flags;
		568	rdev->family = flags & RADEON_FAMILY_MASK;
		569	rdev->is_atom_bios = false;
		570	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		571	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		572	rdev->gpu_lockup = false;
1221	serge	573	rdev->accel_working = false;
1117	serge	574	/* mutex initialization are all done here so we
		575	* can recall function without having locking issues */
		576	// mutex_init(&rdev->cs_mutex);
		577	// mutex_init(&rdev->ib_pool.mutex);
		578	// mutex_init(&rdev->cp.mutex);
		579	// rwlock_init(&rdev->fence_drv.lock);
		580
1179	serge	581	/* Set asic functions */
		582	r = radeon_asic_init(rdev);
		583	if (r) {
		584	return r;
		585	}
		586
1117	serge	587	if (radeon_agpmode == -1) {
1221	serge	588	radeon_agp_disable(rdev);
1117	serge	589	}
		590
1179	serge	591	/* set DMA mask + need_dma32 flags.
		592	* PCIE - can handle 40-bits.
		593	* IGP - can handle 40-bits (in theory)
		594	* AGP - generally dma32 is safest
		595	* PCI - only dma32
		596	*/
		597	rdev->need_dma32 = false;
		598	if (rdev->flags & RADEON_IS_AGP)
		599	rdev->need_dma32 = true;
		600	if (rdev->flags & RADEON_IS_PCI)
		601	rdev->need_dma32 = true;
1117	serge	602
1179	serge	603	dma_bits = rdev->need_dma32 ? 32 : 40;
		604	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117	serge	605	if (r) {
1119	serge	606	printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		607	}
1117	serge	608
		609	/* Registers mapping */
		610	/* TODO: block userspace mapping of io register */
		611	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		612
		613	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
		614
		615	rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
		616	PG_SW+PG_NOCACHE);
		617
		618	if (rdev->rmmio == NULL) {
		619	return -ENOMEM;
		620	}
		621	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		622	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		623
1221	serge	624	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
		625	// r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
		626	// if (r) {
		627	// return -EINVAL;
		628	// }
		629
1179	serge	630	r = radeon_init(rdev);
1221	serge	631	if (r)
1117	serge	632	return r;
		633
1221	serge	634	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		635	/* Acceleration not working on AGP card try again
		636	* with fallback to PCI or PCIE GART
		637	*/
		638	radeon_gpu_reset(rdev);
		639	radeon_fini(rdev);
		640	radeon_agp_disable(rdev);
		641	r = radeon_init(rdev);
		642	if (r)
1179	serge	643	return r;
1126	serge	644	}
1179	serge	645	// if (radeon_testing) {
		646	// radeon_test_moves(rdev);
1125	serge	647	// }
1179	serge	648	// if (radeon_benchmarking) {
		649	// radeon_benchmark(rdev);
		650	// }
		651	return 0;
1117	serge	652	}
		653
1179	serge	654
1117	serge	655	/*
		656	* Driver load/unload
		657	*/
		658	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		659	{
		660	struct radeon_device *rdev;
		661	int r;
		662
1182	serge	663	ENTER();
1117	serge	664
1120	serge	665	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117	serge	666	if (rdev == NULL) {
		667	return -ENOMEM;
		668	};
		669
		670	dev->dev_private = (void *)rdev;
		671
		672	/* update BUS flag */
1239	serge	673	if (drm_device_is_agp(dev)) {
1117	serge	674	flags \|= RADEON_IS_AGP;
1239	serge	675	} else if (drm_device_is_pcie(dev)) {
		676	flags \|= RADEON_IS_PCIE;
		677	} else {
		678	flags \|= RADEON_IS_PCI;
		679	}
1117	serge	680
1182	serge	681	/* radeon_device_init should report only fatal error
		682	* like memory allocation failure or iomapping failure,
		683	* or memory manager initialization failure, it must
		684	* properly initialize the GPU MC controller and permit
		685	* VRAM allocation
		686	*/
1117	serge	687	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		688	if (r) {
1182	serge	689	DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117	serge	690	return r;
		691	}
1182	serge	692	/* Again modeset_init should fail only on fatal error
		693	* otherwise it should provide enough functionalities
		694	* for shadowfb to run
		695	*/
1246	serge	696	if( radeon_modeset )
		697	{
1182	serge	698	r = radeon_modeset_init(rdev);
		699	if (r) {
		700	return r;
		701	}
1246	serge	702	};
1117	serge	703	return 0;
		704	}
		705
1239	serge	706	mode_t usermode;
1230	serge	707
1239	serge	708
1117	serge	709	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		710	{
1246	serge	711	static struct drm_device *dev;
1117	serge	712	int ret;
		713
1221	serge	714	ENTER();
1117	serge	715
1246	serge	716	dev = kzalloc(sizeof(*dev), 0);
1117	serge	717	if (!dev)
		718	return -ENOMEM;
		719
		720	// ret = pci_enable_device(pdev);
		721	// if (ret)
		722	// goto err_g1;
		723
		724	// pci_set_master(pdev);
		725
		726	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		727	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		728	// goto err_g2;
		729	// }
		730
		731	dev->pdev = pdev;
		732	dev->pci_device = pdev->device;
		733	dev->pci_vendor = pdev->vendor;
		734
1221	serge	735	ret = radeon_driver_load_kms(dev, ent->driver_data );
		736	if (ret)
1117	serge	737	goto err_g4;
		738
		739	// list_add_tail(&dev->driver_item, &driver->device_list);
		740
		741	// DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
		742	// driver->name, driver->major, driver->minor, driver->patchlevel,
		743	// driver->date, pci_name(pdev), dev->primary->index);
		744
1246	serge	745	if( radeon_modeset )
		746	init_display_kms(dev->dev_private, &usermode);
		747	else
1233	serge	748	init_display(dev->dev_private, &usermode);
1126	serge	749
1221	serge	750	LEAVE();
		751
1117	serge	752	return 0;
		753
		754	err_g4:
		755	// drm_put_minor(&dev->primary);
		756	//err_g3:
		757	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		758	// drm_put_minor(&dev->control);
		759	//err_g2:
		760	// pci_disable_device(pdev);
		761	//err_g1:
		762	free(dev);
		763
1221	serge	764	LEAVE();
		765
1117	serge	766	return ret;
		767	}
		768
		769	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		770	{
		771	return pci_resource_start(dev->pdev, resource);
		772	}
		773
		774	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		775	{
		776	return pci_resource_len(dev->pdev, resource);
		777	}
		778
1123	serge	779
		780	uint32_t __div64_32(uint64_t *n, uint32_t base)
		781	{
		782	uint64_t rem = *n;
		783	uint64_t b = base;
		784	uint64_t res, d = 1;
		785	uint32_t high = rem >> 32;
		786
		787	/* Reduce the thing a bit first */
		788	res = 0;
		789	if (high >= base) {
		790	high /= base;
		791	res = (uint64_t) high << 32;
		792	rem -= (uint64_t) (high*base) << 32;
		793	}
		794
		795	while ((int64_t)b > 0 && b < rem) {
		796	b = b+b;
		797	d = d+d;
		798	}
		799
		800	do {
		801	if (rem >= b) {
		802	rem -= b;
		803	res += d;
		804	}
		805	b >>= 1;
		806	d >>= 1;
		807	} while (d);
		808
		809	*n = res;
		810	return rem;
		811	}
		812
1239	serge	813
		814	static struct pci_device_id pciidlist[] = {
		815	radeon_PCI_IDS
		816	};
		817
		818
		819	#define API_VERSION 0x01000100
		820
		821	#define SRV_GETVERSION 0
		822	#define SRV_ENUM_MODES 1
		823	#define SRV_SET_MODE 2
		824
		825	int _stdcall display_handler(ioctl_t *io)
		826	{
		827	int retval = -1;
		828	u32_t *inp;
		829	u32_t *outp;
		830
		831	inp = io->input;
		832	outp = io->output;
		833
		834	switch(io->io_code)
		835	{
		836	case SRV_GETVERSION:
		837	if(io->out_size==4)
		838	{
		839	*outp = API_VERSION;
		840	retval = 0;
		841	}
		842	break;
		843
		844	case SRV_ENUM_MODES:
		845	dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
		846	inp, io->inp_size, io->out_size );
		847
1246	serge	848	if( radeon_modeset &&
		849	(outp != NULL) && (io->out_size == 4) &&
1239	serge	850	(io->inp_size == outp sizeof(mode_t)) )
		851	{
		852	retval = get_modes((mode_t*)inp, outp);
		853	};
		854	break;
		855
		856	case SRV_SET_MODE:
1246	serge	857	dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
		858	inp, io->inp_size);
		859
		860	if( radeon_modeset &&
		861	(inp != NULL) &&
1239	serge	862	(io->inp_size == sizeof(mode_t)) )
		863	{
		864	retval = set_user_mode((mode_t*)inp);
		865	};
		866	break;
		867	};
		868
		869	return retval;
		870	}
		871
1246	serge	872	static char log[256];
		873	static dev_t device;
		874
1239	serge	875	u32_t drvEntry(int action, char *cmdline)
		876	{
		877	struct pci_device_id *ent;
		878
		879	int err;
		880	u32_t retval = 0;
		881
		882	if(action != 1)
		883	return 0;
		884
		885	if( GetService("DISPLAY") != 0 )
		886	return 0;
		887
		888	if( cmdline && *cmdline )
		889	parse_cmdline(cmdline, &usermode, log);
		890
		891	if(!dbg_open(log))
		892	{
		893	strcpy(log, "/rd/1/drivers/atikms.log");
		894
		895	if(!dbg_open(log))
		896	{
		897	printf("Can't open %s\nExit\n", log);
		898	return 0;
		899	};
		900	}
1246	serge	901	dbgprintf("Radeon RC05 cmdline %s\n", cmdline);
1239	serge	902
		903	enum_pci_devices();
		904
		905	ent = find_pci_device(&device, pciidlist);
		906
		907	if( unlikely(ent == NULL) )
		908	{
		909	dbgprintf("device not found\n");
		910	return 0;
		911	};
		912
		913	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		914	device.pci_dev.device);
		915
		916	err = drm_get_dev(&device.pci_dev, ent);
		917
1246	serge	918	err = RegService("DISPLAY", display_handler);
1239	serge	919
1246	serge	920	if( err != 0)
		921	dbgprintf("Set DISPLAY handler\n");
		922
		923	return err;
1239	serge	924	};

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(root)/drivers/video/drm/radeon/radeon_device.c – Rev 1246