WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_device.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	//#include
1123	serge	29
1179	serge	30	#include
		31	#include
1221	serge	32	#include
1117	serge	33	#include "radeon_reg.h"
		34	#include "radeon.h"
		35	#include "radeon_asic.h"
		36	#include "atom.h"
		37
1221	serge	38	#include
		39
1117	serge	40	#include
		41
		42	int radeon_dynclks = -1;
1123	serge	43	int radeon_r4xx_atom = 0;
1125	serge	44	int radeon_agpmode = -1;
1117	serge	45	int radeon_gart_size = 512; /* default gart size */
1123	serge	46	int radeon_benchmarking = 0;
		47	int radeon_connector_table = 0;
1179	serge	48	int radeon_tv = 1;
1117	serge	49
		50
		51	/*
		52	* Clear GPU surface registers.
		53	*/
1179	serge	54	void radeon_surface_init(struct radeon_device *rdev)
1117	serge	55	{
1179	serge	56	ENTER();
1117	serge	57
		58	/* FIXME: check this out */
		59	if (rdev->family < CHIP_R600) {
		60	int i;
		61
		62	for (i = 0; i < 8; i++) {
		63	WREG32(RADEON_SURFACE0_INFO +
		64	i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
		65	0);
		66	}
1179	serge	67	/* enable surfaces */
		68	WREG32(RADEON_SURFACE_CNTL, 0);
1117	serge	69	}
		70	}
		71
		72	/*
		73	* GPU scratch registers helpers function.
		74	*/
1179	serge	75	void radeon_scratch_init(struct radeon_device *rdev)
1117	serge	76	{
		77	int i;
		78
		79	/* FIXME: check this out */
		80	if (rdev->family < CHIP_R300) {
		81	rdev->scratch.num_reg = 5;
		82	} else {
		83	rdev->scratch.num_reg = 7;
		84	}
		85	for (i = 0; i < rdev->scratch.num_reg; i++) {
		86	rdev->scratch.free[i] = true;
		87	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
		88	}
		89	}
		90
		91	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
		92	{
		93	int i;
		94
		95	for (i = 0; i < rdev->scratch.num_reg; i++) {
		96	if (rdev->scratch.free[i]) {
		97	rdev->scratch.free[i] = false;
		98	*reg = rdev->scratch.reg[i];
		99	return 0;
		100	}
		101	}
		102	return -EINVAL;
		103	}
		104
		105	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
		106	{
		107	int i;
		108
		109	for (i = 0; i < rdev->scratch.num_reg; i++) {
		110	if (rdev->scratch.reg[i] == reg) {
		111	rdev->scratch.free[i] = true;
		112	return;
		113	}
		114	}
		115	}
		116
		117	/*
		118	* MC common functions
		119	*/
		120	int radeon_mc_setup(struct radeon_device *rdev)
		121	{
		122	uint32_t tmp;
		123
		124	/* Some chips have an "issue" with the memory controller, the
		125	* location must be aligned to the size. We just align it down,
		126	* too bad if we walk over the top of system memory, we don't
		127	* use DMA without a remapped anyway.
		128	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
		129	*/
		130	/* FGLRX seems to setup like this, VRAM a 0, then GART.
		131	*/
1126	serge	132	/*
1117	serge	133	* Note: from R6xx the address space is 40bits but here we only
		134	* use 32bits (still have to see a card which would exhaust 4G
		135	* address space).
		136	*/
		137	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		138	/* vram location was already setup try to put gtt after
		139	* if it fits */
1179	serge	140	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
1117	serge	141	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		142	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
		143	rdev->mc.gtt_location = tmp;
		144	} else {
		145	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
		146	printk(KERN_ERR "[drm] GTT too big to fit "
		147	"before or after vram location.\n");
		148	return -EINVAL;
		149	}
		150	rdev->mc.gtt_location = 0;
		151	}
		152	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		153	/* gtt location was already setup try to put vram before
		154	* if it fits */
1179	serge	155	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
1117	serge	156	rdev->mc.vram_location = 0;
		157	} else {
		158	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
1179	serge	159	tmp += (rdev->mc.mc_vram_size - 1);
		160	tmp &= ~(rdev->mc.mc_vram_size - 1);
		161	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
1117	serge	162	rdev->mc.vram_location = tmp;
		163	} else {
		164	printk(KERN_ERR "[drm] vram too big to fit "
		165	"before or after GTT location.\n");
		166	return -EINVAL;
		167	}
		168	}
		169	} else {
		170	rdev->mc.vram_location = 0;
1179	serge	171	tmp = rdev->mc.mc_vram_size;
		172	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		173	rdev->mc.gtt_location = tmp;
1117	serge	174	}
1179	serge	175	rdev->mc.vram_start = rdev->mc.vram_location;
		176	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
		177	rdev->mc.gtt_start = rdev->mc.gtt_location;
		178	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
		179	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
1117	serge	180	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
1179	serge	181	(unsigned)rdev->mc.vram_location,
		182	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
		183	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
1117	serge	184	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
1179	serge	185	(unsigned)rdev->mc.gtt_location,
		186	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
1117	serge	187	return 0;
		188	}
		189
		190
		191	/*
		192	* GPU helpers function.
		193	*/
1179	serge	194	bool radeon_card_posted(struct radeon_device *rdev)
1117	serge	195	{
		196	uint32_t reg;
		197
1179	serge	198	ENTER();
1117	serge	199
		200	/* first check CRTCs */
		201	if (ASIC_IS_AVIVO(rdev)) {
		202	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
		203	RREG32(AVIVO_D2CRTC_CONTROL);
		204	if (reg & AVIVO_CRTC_EN) {
		205	return true;
		206	}
		207	} else {
		208	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
		209	RREG32(RADEON_CRTC2_GEN_CNTL);
		210	if (reg & RADEON_CRTC_EN) {
		211	return true;
		212	}
		213	}
		214
		215	/* then check MEM_SIZE, in case the crtcs are off */
		216	if (rdev->family >= CHIP_R600)
		217	reg = RREG32(R600_CONFIG_MEMSIZE);
		218	else
		219	reg = RREG32(RADEON_CONFIG_MEMSIZE);
		220
		221	if (reg)
		222	return true;
		223
		224	return false;
		225
		226	}
		227
		228
		229	/*
		230	* Registers accessors functions.
		231	*/
		232	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		233	{
		234	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		235	BUG_ON(1);
		236	return 0;
		237	}
		238
		239	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		240	{
		241	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		242	reg, v);
		243	BUG_ON(1);
		244	}
		245
		246	void radeon_register_accessor_init(struct radeon_device *rdev)
		247	{
		248	rdev->mc_rreg = &radeon_invalid_rreg;
		249	rdev->mc_wreg = &radeon_invalid_wreg;
		250	rdev->pll_rreg = &radeon_invalid_rreg;
		251	rdev->pll_wreg = &radeon_invalid_wreg;
		252	rdev->pciep_rreg = &radeon_invalid_rreg;
		253	rdev->pciep_wreg = &radeon_invalid_wreg;
		254
		255	/* Don't change order as we are overridding accessor. */
		256	if (rdev->family < CHIP_RV515) {
1179	serge	257	rdev->pcie_reg_mask = 0xff;
		258	} else {
		259	rdev->pcie_reg_mask = 0x7ff;
1117	serge	260	}
		261	/* FIXME: not sure here */
		262	if (rdev->family <= CHIP_R580) {
1119	serge	263	rdev->pll_rreg = &r100_pll_rreg;
		264	rdev->pll_wreg = &r100_pll_wreg;
1117	serge	265	}
1179	serge	266	if (rdev->family >= CHIP_R420) {
		267	rdev->mc_rreg = &r420_mc_rreg;
		268	rdev->mc_wreg = &r420_mc_wreg;
		269	}
1117	serge	270	if (rdev->family >= CHIP_RV515) {
		271	rdev->mc_rreg = &rv515_mc_rreg;
		272	rdev->mc_wreg = &rv515_mc_wreg;
		273	}
		274	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
1128	serge	275	rdev->mc_rreg = &rs400_mc_rreg;
		276	rdev->mc_wreg = &rs400_mc_wreg;
1117	serge	277	}
1221	serge	278	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		279	rdev->mc_rreg = &rs690_mc_rreg;
		280	rdev->mc_wreg = &rs690_mc_wreg;
		281	}
		282	if (rdev->family == CHIP_RS600) {
		283	rdev->mc_rreg = &rs600_mc_rreg;
		284	rdev->mc_wreg = &rs600_mc_wreg;
		285	}
1179	serge	286	// if (rdev->family >= CHIP_R600) {
		287	// rdev->pciep_rreg = &r600_pciep_rreg;
		288	// rdev->pciep_wreg = &r600_pciep_wreg;
		289	// }
1117	serge	290	}
		291
		292
		293	/*
		294	* ASIC
		295	*/
		296	int radeon_asic_init(struct radeon_device *rdev)
		297	{
		298	radeon_register_accessor_init(rdev);
		299	switch (rdev->family) {
		300	case CHIP_R100:
		301	case CHIP_RV100:
		302	case CHIP_RS100:
		303	case CHIP_RV200:
		304	case CHIP_RS200:
		305	case CHIP_R200:
		306	case CHIP_RV250:
		307	case CHIP_RS300:
		308	case CHIP_RV280:
1128	serge	309	rdev->asic = &r100_asic;
1117	serge	310	break;
		311	case CHIP_R300:
		312	case CHIP_R350:
		313	case CHIP_RV350:
		314	case CHIP_RV380:
1128	serge	315	rdev->asic = &r300_asic;
1179	serge	316	if (rdev->flags & RADEON_IS_PCIE) {
		317	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		318	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		319	}
1117	serge	320	break;
		321	case CHIP_R420:
		322	case CHIP_R423:
		323	case CHIP_RV410:
1128	serge	324	rdev->asic = &r420_asic;
1117	serge	325	break;
		326	case CHIP_RS400:
		327	case CHIP_RS480:
1128	serge	328	rdev->asic = &rs400_asic;
1117	serge	329	break;
		330	case CHIP_RS600:
1221	serge	331	rdev->asic = &rs600_asic;
1117	serge	332	break;
		333	case CHIP_RS690:
		334	case CHIP_RS740:
1221	serge	335	rdev->asic = &rs690_asic;
1117	serge	336	break;
		337	case CHIP_RV515:
1128	serge	338	rdev->asic = &rv515_asic;
1117	serge	339	break;
		340	case CHIP_R520:
		341	case CHIP_RV530:
		342	case CHIP_RV560:
		343	case CHIP_RV570:
		344	case CHIP_R580:
		345	rdev->asic = &r520_asic;
		346	break;
		347	case CHIP_R600:
		348	case CHIP_RV610:
		349	case CHIP_RV630:
		350	case CHIP_RV620:
		351	case CHIP_RV635:
		352	case CHIP_RV670:
		353	case CHIP_RS780:
1221	serge	354	case CHIP_RS880:
		355	// rdev->asic = &r600_asic;
		356	break;
1117	serge	357	case CHIP_RV770:
		358	case CHIP_RV730:
		359	case CHIP_RV710:
1221	serge	360	case CHIP_RV740:
		361	// rdev->asic = &rv770_asic;
		362	break;
1117	serge	363	default:
		364	/* FIXME: not supported yet */
		365	return -EINVAL;
		366	}
		367	return 0;
		368	}
		369
		370
		371	/*
		372	* Wrapper around modesetting bits.
		373	*/
		374	int radeon_clocks_init(struct radeon_device *rdev)
		375	{
		376	int r;
		377
1179	serge	378	ENTER();
1117	serge	379
		380	r = radeon_static_clocks_init(rdev->ddev);
		381	if (r) {
		382	return r;
		383	}
		384	DRM_INFO("Clocks initialized !\n");
		385	return 0;
		386	}
		387
		388	void radeon_clocks_fini(struct radeon_device *rdev)
		389	{
		390	}
		391
		392	/* ATOM accessor methods */
		393	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
		394	{
		395	struct radeon_device *rdev = info->dev->dev_private;
		396	uint32_t r;
		397
		398	r = rdev->pll_rreg(rdev, reg);
		399	return r;
		400	}
		401
		402	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
		403	{
		404	struct radeon_device *rdev = info->dev->dev_private;
		405
		406	rdev->pll_wreg(rdev, reg, val);
		407	}
		408
		409	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
		410	{
		411	struct radeon_device *rdev = info->dev->dev_private;
		412	uint32_t r;
		413
		414	r = rdev->mc_rreg(rdev, reg);
		415	return r;
		416	}
		417
		418	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
		419	{
		420	struct radeon_device *rdev = info->dev->dev_private;
		421
		422	rdev->mc_wreg(rdev, reg, val);
		423	}
		424
		425	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
		426	{
		427	struct radeon_device *rdev = info->dev->dev_private;
		428
		429	WREG32(reg*4, val);
		430	}
		431
		432	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
		433	{
		434	struct radeon_device *rdev = info->dev->dev_private;
		435	uint32_t r;
		436
		437	r = RREG32(reg*4);
		438	return r;
		439	}
		440
		441	static struct card_info atom_card_info = {
		442	.dev = NULL,
		443	.reg_read = cail_reg_read,
		444	.reg_write = cail_reg_write,
		445	.mc_read = cail_mc_read,
		446	.mc_write = cail_mc_write,
		447	.pll_read = cail_pll_read,
		448	.pll_write = cail_pll_write,
		449	};
		450
		451	int radeon_atombios_init(struct radeon_device *rdev)
		452	{
1179	serge	453	ENTER();
1117	serge	454
		455	atom_card_info.dev = rdev->ddev;
		456	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
		457	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
		458	return 0;
		459	}
		460
		461	void radeon_atombios_fini(struct radeon_device *rdev)
		462	{
1119	serge	463	kfree(rdev->mode_info.atom_context);
1117	serge	464	}
		465
		466	int radeon_combios_init(struct radeon_device *rdev)
		467	{
1128	serge	468	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1117	serge	469	return 0;
		470	}
		471
		472	void radeon_combios_fini(struct radeon_device *rdev)
		473	{
		474	}
		475
		476	int radeon_modeset_init(struct radeon_device *rdev);
		477	void radeon_modeset_fini(struct radeon_device *rdev);
		478
1221	serge	479	void radeon_agp_disable(struct radeon_device *rdev)
		480	{
		481	rdev->flags &= ~RADEON_IS_AGP;
		482	if (rdev->family >= CHIP_R600) {
		483	DRM_INFO("Forcing AGP to PCIE mode\n");
		484	rdev->flags \|= RADEON_IS_PCIE;
		485	} else if (rdev->family >= CHIP_RV515 \|\|
		486	rdev->family == CHIP_RV380 \|\|
		487	rdev->family == CHIP_RV410 \|\|
		488	rdev->family == CHIP_R423) {
		489	DRM_INFO("Forcing AGP to PCIE mode\n");
		490	rdev->flags \|= RADEON_IS_PCIE;
		491	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		492	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		493	} else {
		494	DRM_INFO("Forcing AGP to PCI mode\n");
		495	rdev->flags \|= RADEON_IS_PCI;
		496	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		497	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		498	}
		499	}
1179	serge	500
1117	serge	501	/*
		502	* Radeon device.
		503	*/
		504	int radeon_device_init(struct radeon_device *rdev,
		505	struct drm_device *ddev,
		506	struct pci_dev *pdev,
		507	uint32_t flags)
		508	{
1221	serge	509	int r;
1179	serge	510	int dma_bits;
1117	serge	511
1179	serge	512	ENTER();
1117	serge	513
		514	DRM_INFO("radeon: Initializing kernel modesetting.\n");
		515	rdev->shutdown = false;
		516	rdev->ddev = ddev;
		517	rdev->pdev = pdev;
		518	rdev->flags = flags;
		519	rdev->family = flags & RADEON_FAMILY_MASK;
		520	rdev->is_atom_bios = false;
		521	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
		522	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		523	rdev->gpu_lockup = false;
1221	serge	524	rdev->accel_working = false;
1117	serge	525	/* mutex initialization are all done here so we
		526	* can recall function without having locking issues */
		527	// mutex_init(&rdev->cs_mutex);
		528	// mutex_init(&rdev->ib_pool.mutex);
		529	// mutex_init(&rdev->cp.mutex);
		530	// rwlock_init(&rdev->fence_drv.lock);
		531
1179	serge	532	/* Set asic functions */
		533	r = radeon_asic_init(rdev);
		534	if (r) {
		535	return r;
		536	}
		537
1117	serge	538	if (radeon_agpmode == -1) {
1221	serge	539	radeon_agp_disable(rdev);
1117	serge	540	}
		541
1179	serge	542	/* set DMA mask + need_dma32 flags.
		543	* PCIE - can handle 40-bits.
		544	* IGP - can handle 40-bits (in theory)
		545	* AGP - generally dma32 is safest
		546	* PCI - only dma32
		547	*/
		548	rdev->need_dma32 = false;
		549	if (rdev->flags & RADEON_IS_AGP)
		550	rdev->need_dma32 = true;
		551	if (rdev->flags & RADEON_IS_PCI)
		552	rdev->need_dma32 = true;
1117	serge	553
1179	serge	554	dma_bits = rdev->need_dma32 ? 32 : 40;
		555	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1117	serge	556	if (r) {
1119	serge	557	printk(KERN_WARNING "radeon: No suitable DMA available.\n");
		558	}
1117	serge	559
		560	/* Registers mapping */
		561	/* TODO: block userspace mapping of io register */
		562	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
		563
		564	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
		565
		566	rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
		567	PG_SW+PG_NOCACHE);
		568
		569	if (rdev->rmmio == NULL) {
		570	return -ENOMEM;
		571	}
		572	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
		573	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
		574
1221	serge	575	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
		576	// r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
		577	// if (r) {
		578	// return -EINVAL;
		579	// }
		580
1179	serge	581	r = radeon_init(rdev);
1221	serge	582	if (r)
1117	serge	583	return r;
		584
1221	serge	585	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		586	/* Acceleration not working on AGP card try again
		587	* with fallback to PCI or PCIE GART
		588	*/
		589	radeon_gpu_reset(rdev);
		590	radeon_fini(rdev);
		591	radeon_agp_disable(rdev);
		592	r = radeon_init(rdev);
		593	if (r)
1179	serge	594	return r;
1126	serge	595	}
1179	serge	596	// if (radeon_testing) {
		597	// radeon_test_moves(rdev);
1125	serge	598	// }
1179	serge	599	// if (radeon_benchmarking) {
		600	// radeon_benchmark(rdev);
		601	// }
		602	return 0;
1117	serge	603	}
		604
1179	serge	605
1117	serge	606	static struct pci_device_id pciidlist[] = {
		607	radeon_PCI_IDS
		608	};
		609
		610
1179	serge	611	u32_t drvEntry(int action, char *cmdline)
1117	serge	612	{
		613	struct pci_device_id *ent;
		614
		615	dev_t device;
		616	int err;
		617	u32_t retval = 0;
		618
		619	if(action != 1)
		620	return 0;
		621
1120	serge	622	if(!dbg_open("/hd0/2/atikms.log"))
1117	serge	623	{
1120	serge	624	printf("Can't open /hd0/2/atikms.log\nExit\n");
1117	serge	625	return 0;
		626	}
		627
1179	serge	628	if(cmdline)
		629	dbgprintf("cmdline: %s\n", cmdline);
		630
1117	serge	631	enum_pci_devices();
		632
		633	ent = find_pci_device(&device, pciidlist);
		634
		635	if( unlikely(ent == NULL) )
		636	{
		637	dbgprintf("device not found\n");
		638	return 0;
		639	};
		640
		641	dbgprintf("device %x:%x\n", device.pci_dev.vendor,
		642	device.pci_dev.device);
		643
		644	err = drm_get_dev(&device.pci_dev, ent);
		645
		646	return retval;
		647	};
		648
		649
		650
		651	/*
		652	* Driver load/unload
		653	*/
		654	int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
		655	{
		656	struct radeon_device *rdev;
		657	int r;
		658
1182	serge	659	ENTER();
1117	serge	660
1120	serge	661	rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
1117	serge	662	if (rdev == NULL) {
		663	return -ENOMEM;
		664	};
		665
		666	dev->dev_private = (void *)rdev;
		667
		668	/* update BUS flag */
		669	// if (drm_device_is_agp(dev)) {
		670	flags \|= RADEON_IS_AGP;
		671	// } else if (drm_device_is_pcie(dev)) {
		672	// flags \|= RADEON_IS_PCIE;
		673	// } else {
		674	// flags \|= RADEON_IS_PCI;
		675	// }
		676
1182	serge	677	/* radeon_device_init should report only fatal error
		678	* like memory allocation failure or iomapping failure,
		679	* or memory manager initialization failure, it must
		680	* properly initialize the GPU MC controller and permit
		681	* VRAM allocation
		682	*/
1117	serge	683	r = radeon_device_init(rdev, dev, dev->pdev, flags);
		684	if (r) {
1182	serge	685	DRM_ERROR("Fatal error while trying to initialize radeon.\n");
1117	serge	686	return r;
		687	}
1182	serge	688	/* Again modeset_init should fail only on fatal error
		689	* otherwise it should provide enough functionalities
		690	* for shadowfb to run
		691	*/
		692	r = radeon_modeset_init(rdev);
		693	if (r) {
		694	return r;
		695	}
1117	serge	696	return 0;
		697	}
		698
		699	int drm_get_dev(struct pci_dev pdev, const struct pci_device_id ent)
		700	{
		701	struct drm_device *dev;
		702	int ret;
		703
1221	serge	704	ENTER();
1117	serge	705
		706	dev = malloc(sizeof(*dev));
		707	if (!dev)
		708	return -ENOMEM;
		709
		710	// ret = pci_enable_device(pdev);
		711	// if (ret)
		712	// goto err_g1;
		713
		714	// pci_set_master(pdev);
		715
		716	// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
		717	// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
		718	// goto err_g2;
		719	// }
		720
		721	dev->pdev = pdev;
		722	dev->pci_device = pdev->device;
		723	dev->pci_vendor = pdev->vendor;
		724
		725	// if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		726	// pci_set_drvdata(pdev, dev);
		727	// ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
		728	// if (ret)
		729	// goto err_g2;
		730	// }
		731
		732	// if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
		733	// goto err_g3;
		734
		735	// if (dev->driver->load) {
		736	// ret = dev->driver->load(dev, ent->driver_data);
		737	// if (ret)
		738	// goto err_g4;
		739	// }
		740
1221	serge	741	ret = radeon_driver_load_kms(dev, ent->driver_data );
		742	if (ret)
1117	serge	743	goto err_g4;
		744
		745	// list_add_tail(&dev->driver_item, &driver->device_list);
		746
		747	// DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
		748	// driver->name, driver->major, driver->minor, driver->patchlevel,
		749	// driver->date, pci_name(pdev), dev->primary->index);
		750
1221	serge	751	set_mode(dev, 1280, 1024);
1126	serge	752
1221	serge	753	LEAVE();
		754
1117	serge	755	return 0;
		756
		757	err_g4:
		758	// drm_put_minor(&dev->primary);
		759	//err_g3:
		760	// if (drm_core_check_feature(dev, DRIVER_MODESET))
		761	// drm_put_minor(&dev->control);
		762	//err_g2:
		763	// pci_disable_device(pdev);
		764	//err_g1:
		765	free(dev);
		766
1221	serge	767	LEAVE();
		768
1117	serge	769	return ret;
		770	}
		771
		772	resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
		773	{
		774	return pci_resource_start(dev->pdev, resource);
		775	}
		776
		777	resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
		778	{
		779	return pci_resource_len(dev->pdev, resource);
		780	}
		781
1123	serge	782
		783	uint32_t __div64_32(uint64_t *n, uint32_t base)
		784	{
		785	uint64_t rem = *n;
		786	uint64_t b = base;
		787	uint64_t res, d = 1;
		788	uint32_t high = rem >> 32;
		789
		790	/* Reduce the thing a bit first */
		791	res = 0;
		792	if (high >= base) {
		793	high /= base;
		794	res = (uint64_t) high << 32;
		795	rem -= (uint64_t) (high*base) << 32;
		796	}
		797
		798	while ((int64_t)b > 0 && b < rem) {
		799	b = b+b;
		800	d = d+d;
		801	}
		802
		803	do {
		804	if (rem >= b) {
		805	rem -= b;
		806	res += d;
		807	}
		808	b >>= 1;
		809	d >>= 1;
		810	} while (d);
		811
		812	*n = res;
		813	return rem;
		814	}
		815

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c – Rev 1221