WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_combios.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2004 ATI Technologies Inc., Markham, Ontario
		3	* Copyright 2007-8 Advanced Micro Devices, Inc.
		4	* Copyright 2008 Red Hat Inc.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	*/
2997	Serge	27	#include
		28	#include
1123	serge	29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	#ifdef CONFIG_PPC_PMAC
		33	/* not sure which of these are needed */
		34	#include
		35	#include
		36	#include
		37	#include
		38	#endif /* CONFIG_PPC_PMAC */
		39
		40	/* from radeon_encoder.c */
		41	extern uint32_t
1963	serge	42	radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
1123	serge	43	uint8_t dac);
		44	extern void radeon_link_encoder_connector(struct drm_device *dev);
		45
		46	/* from radeon_connector.c */
		47	extern void
		48	radeon_add_legacy_connector(struct drm_device *dev,
		49	uint32_t connector_id,
		50	uint32_t supported_device,
		51	int connector_type,
1268	serge	52	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	53	uint16_t connector_object_id,
		54	struct radeon_hpd *hpd);
1123	serge	55
		56	/* from radeon_legacy_encoder.c */
		57	extern void
1963	serge	58	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1123	serge	59	uint32_t supported_device);
		60
		61	/* old legacy ATI BIOS routines */
		62
		63	/* COMBIOS table offsets */
		64	enum radeon_combios_table_offset {
		65	/* absolute offset tables */
		66	COMBIOS_ASIC_INIT_1_TABLE,
		67	COMBIOS_BIOS_SUPPORT_TABLE,
		68	COMBIOS_DAC_PROGRAMMING_TABLE,
		69	COMBIOS_MAX_COLOR_DEPTH_TABLE,
		70	COMBIOS_CRTC_INFO_TABLE,
		71	COMBIOS_PLL_INFO_TABLE,
		72	COMBIOS_TV_INFO_TABLE,
		73	COMBIOS_DFP_INFO_TABLE,
		74	COMBIOS_HW_CONFIG_INFO_TABLE,
		75	COMBIOS_MULTIMEDIA_INFO_TABLE,
		76	COMBIOS_TV_STD_PATCH_TABLE,
		77	COMBIOS_LCD_INFO_TABLE,
		78	COMBIOS_MOBILE_INFO_TABLE,
		79	COMBIOS_PLL_INIT_TABLE,
		80	COMBIOS_MEM_CONFIG_TABLE,
		81	COMBIOS_SAVE_MASK_TABLE,
		82	COMBIOS_HARDCODED_EDID_TABLE,
		83	COMBIOS_ASIC_INIT_2_TABLE,
		84	COMBIOS_CONNECTOR_INFO_TABLE,
		85	COMBIOS_DYN_CLK_1_TABLE,
		86	COMBIOS_RESERVED_MEM_TABLE,
		87	COMBIOS_EXT_TMDS_INFO_TABLE,
		88	COMBIOS_MEM_CLK_INFO_TABLE,
		89	COMBIOS_EXT_DAC_INFO_TABLE,
		90	COMBIOS_MISC_INFO_TABLE,
		91	COMBIOS_CRT_INFO_TABLE,
		92	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
		93	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
		94	COMBIOS_FAN_SPEED_INFO_TABLE,
		95	COMBIOS_OVERDRIVE_INFO_TABLE,
		96	COMBIOS_OEM_INFO_TABLE,
		97	COMBIOS_DYN_CLK_2_TABLE,
		98	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
		99	COMBIOS_I2C_INFO_TABLE,
		100	/* relative offset tables */
		101	COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
		102	COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
		103	COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
		104	COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
		105	COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
		106	COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
		107	COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
		108	COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
		109	COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
		110	COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
		111	COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
		112	};
		113
		114	enum radeon_combios_ddc {
		115	DDC_NONE_DETECTED,
		116	DDC_MONID,
		117	DDC_DVI,
		118	DDC_VGA,
		119	DDC_CRT2,
		120	DDC_LCD,
		121	DDC_GPIO,
		122	};
		123
		124	enum radeon_combios_connector {
		125	CONNECTOR_NONE_LEGACY,
		126	CONNECTOR_PROPRIETARY_LEGACY,
		127	CONNECTOR_CRT_LEGACY,
		128	CONNECTOR_DVI_I_LEGACY,
		129	CONNECTOR_DVI_D_LEGACY,
		130	CONNECTOR_CTV_LEGACY,
		131	CONNECTOR_STV_LEGACY,
		132	CONNECTOR_UNSUPPORTED_LEGACY
		133	};
		134
		135	const int legacy_connector_convert[] = {
		136	DRM_MODE_CONNECTOR_Unknown,
		137	DRM_MODE_CONNECTOR_DVID,
		138	DRM_MODE_CONNECTOR_VGA,
		139	DRM_MODE_CONNECTOR_DVII,
		140	DRM_MODE_CONNECTOR_DVID,
		141	DRM_MODE_CONNECTOR_Composite,
		142	DRM_MODE_CONNECTOR_SVIDEO,
		143	DRM_MODE_CONNECTOR_Unknown,
		144	};
		145
		146	static uint16_t combios_get_table_offset(struct drm_device *dev,
		147	enum radeon_combios_table_offset table)
		148	{
		149	struct radeon_device *rdev = dev->dev_private;
		150	int rev;
		151	uint16_t offset = 0, check_offset;
		152
1430	serge	153	if (!rdev->bios)
		154	return 0;
		155
1123	serge	156	switch (table) {
		157	/* absolute offset tables */
		158	case COMBIOS_ASIC_INIT_1_TABLE:
		159	check_offset = RBIOS16(rdev->bios_header_start + 0xc);
		160	if (check_offset)
		161	offset = check_offset;
		162	break;
		163	case COMBIOS_BIOS_SUPPORT_TABLE:
		164	check_offset = RBIOS16(rdev->bios_header_start + 0x14);
		165	if (check_offset)
		166	offset = check_offset;
		167	break;
		168	case COMBIOS_DAC_PROGRAMMING_TABLE:
		169	check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
		170	if (check_offset)
		171	offset = check_offset;
		172	break;
		173	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		174	check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
		175	if (check_offset)
		176	offset = check_offset;
		177	break;
		178	case COMBIOS_CRTC_INFO_TABLE:
		179	check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
		180	if (check_offset)
		181	offset = check_offset;
		182	break;
		183	case COMBIOS_PLL_INFO_TABLE:
		184	check_offset = RBIOS16(rdev->bios_header_start + 0x30);
		185	if (check_offset)
		186	offset = check_offset;
		187	break;
		188	case COMBIOS_TV_INFO_TABLE:
		189	check_offset = RBIOS16(rdev->bios_header_start + 0x32);
		190	if (check_offset)
		191	offset = check_offset;
		192	break;
		193	case COMBIOS_DFP_INFO_TABLE:
		194	check_offset = RBIOS16(rdev->bios_header_start + 0x34);
		195	if (check_offset)
		196	offset = check_offset;
		197	break;
		198	case COMBIOS_HW_CONFIG_INFO_TABLE:
		199	check_offset = RBIOS16(rdev->bios_header_start + 0x36);
		200	if (check_offset)
		201	offset = check_offset;
		202	break;
		203	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		204	check_offset = RBIOS16(rdev->bios_header_start + 0x38);
		205	if (check_offset)
		206	offset = check_offset;
		207	break;
		208	case COMBIOS_TV_STD_PATCH_TABLE:
		209	check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
		210	if (check_offset)
		211	offset = check_offset;
		212	break;
		213	case COMBIOS_LCD_INFO_TABLE:
		214	check_offset = RBIOS16(rdev->bios_header_start + 0x40);
		215	if (check_offset)
		216	offset = check_offset;
		217	break;
		218	case COMBIOS_MOBILE_INFO_TABLE:
		219	check_offset = RBIOS16(rdev->bios_header_start + 0x42);
		220	if (check_offset)
		221	offset = check_offset;
		222	break;
		223	case COMBIOS_PLL_INIT_TABLE:
		224	check_offset = RBIOS16(rdev->bios_header_start + 0x46);
		225	if (check_offset)
		226	offset = check_offset;
		227	break;
		228	case COMBIOS_MEM_CONFIG_TABLE:
		229	check_offset = RBIOS16(rdev->bios_header_start + 0x48);
		230	if (check_offset)
		231	offset = check_offset;
		232	break;
		233	case COMBIOS_SAVE_MASK_TABLE:
		234	check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
		235	if (check_offset)
		236	offset = check_offset;
		237	break;
		238	case COMBIOS_HARDCODED_EDID_TABLE:
		239	check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
		240	if (check_offset)
		241	offset = check_offset;
		242	break;
		243	case COMBIOS_ASIC_INIT_2_TABLE:
		244	check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
		245	if (check_offset)
		246	offset = check_offset;
		247	break;
		248	case COMBIOS_CONNECTOR_INFO_TABLE:
		249	check_offset = RBIOS16(rdev->bios_header_start + 0x50);
		250	if (check_offset)
		251	offset = check_offset;
		252	break;
		253	case COMBIOS_DYN_CLK_1_TABLE:
		254	check_offset = RBIOS16(rdev->bios_header_start + 0x52);
		255	if (check_offset)
		256	offset = check_offset;
		257	break;
		258	case COMBIOS_RESERVED_MEM_TABLE:
		259	check_offset = RBIOS16(rdev->bios_header_start + 0x54);
		260	if (check_offset)
		261	offset = check_offset;
		262	break;
		263	case COMBIOS_EXT_TMDS_INFO_TABLE:
		264	check_offset = RBIOS16(rdev->bios_header_start + 0x58);
		265	if (check_offset)
		266	offset = check_offset;
		267	break;
		268	case COMBIOS_MEM_CLK_INFO_TABLE:
		269	check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
		270	if (check_offset)
		271	offset = check_offset;
		272	break;
		273	case COMBIOS_EXT_DAC_INFO_TABLE:
		274	check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
		275	if (check_offset)
		276	offset = check_offset;
		277	break;
		278	case COMBIOS_MISC_INFO_TABLE:
		279	check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
		280	if (check_offset)
		281	offset = check_offset;
		282	break;
		283	case COMBIOS_CRT_INFO_TABLE:
		284	check_offset = RBIOS16(rdev->bios_header_start + 0x60);
		285	if (check_offset)
		286	offset = check_offset;
		287	break;
		288	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		289	check_offset = RBIOS16(rdev->bios_header_start + 0x62);
		290	if (check_offset)
		291	offset = check_offset;
		292	break;
		293	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		294	check_offset = RBIOS16(rdev->bios_header_start + 0x64);
		295	if (check_offset)
		296	offset = check_offset;
		297	break;
		298	case COMBIOS_FAN_SPEED_INFO_TABLE:
		299	check_offset = RBIOS16(rdev->bios_header_start + 0x66);
		300	if (check_offset)
		301	offset = check_offset;
		302	break;
		303	case COMBIOS_OVERDRIVE_INFO_TABLE:
		304	check_offset = RBIOS16(rdev->bios_header_start + 0x68);
		305	if (check_offset)
		306	offset = check_offset;
		307	break;
		308	case COMBIOS_OEM_INFO_TABLE:
		309	check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
		310	if (check_offset)
		311	offset = check_offset;
		312	break;
		313	case COMBIOS_DYN_CLK_2_TABLE:
		314	check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
		315	if (check_offset)
		316	offset = check_offset;
		317	break;
		318	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		319	check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
		320	if (check_offset)
		321	offset = check_offset;
		322	break;
		323	case COMBIOS_I2C_INFO_TABLE:
		324	check_offset = RBIOS16(rdev->bios_header_start + 0x70);
		325	if (check_offset)
		326	offset = check_offset;
		327	break;
		328	/* relative offset tables */
		329	case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
		330	check_offset =
		331	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		332	if (check_offset) {
		333	rev = RBIOS8(check_offset);
		334	if (rev > 0) {
		335	check_offset = RBIOS16(check_offset + 0x3);
		336	if (check_offset)
		337	offset = check_offset;
		338	}
		339	}
		340	break;
		341	case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
		342	check_offset =
		343	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		344	if (check_offset) {
		345	rev = RBIOS8(check_offset);
		346	if (rev > 0) {
		347	check_offset = RBIOS16(check_offset + 0x5);
		348	if (check_offset)
		349	offset = check_offset;
		350	}
		351	}
		352	break;
		353	case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
		354	check_offset =
		355	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		356	if (check_offset) {
		357	rev = RBIOS8(check_offset);
		358	if (rev > 0) {
		359	check_offset = RBIOS16(check_offset + 0x7);
		360	if (check_offset)
		361	offset = check_offset;
		362	}
		363	}
		364	break;
		365	case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
		366	check_offset =
		367	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		368	if (check_offset) {
		369	rev = RBIOS8(check_offset);
		370	if (rev == 2) {
		371	check_offset = RBIOS16(check_offset + 0x9);
		372	if (check_offset)
		373	offset = check_offset;
		374	}
		375	}
		376	break;
		377	case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
		378	check_offset =
		379	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		380	if (check_offset) {
		381	while (RBIOS8(check_offset++));
		382	check_offset += 2;
		383	if (check_offset)
		384	offset = check_offset;
		385	}
		386	break;
		387	case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
		388	check_offset =
		389	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		390	if (check_offset) {
		391	check_offset = RBIOS16(check_offset + 0x11);
		392	if (check_offset)
		393	offset = check_offset;
		394	}
		395	break;
		396	case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
		397	check_offset =
		398	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		399	if (check_offset) {
		400	check_offset = RBIOS16(check_offset + 0x13);
		401	if (check_offset)
		402	offset = check_offset;
		403	}
		404	break;
		405	case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
		406	check_offset =
		407	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		408	if (check_offset) {
		409	check_offset = RBIOS16(check_offset + 0x15);
		410	if (check_offset)
		411	offset = check_offset;
		412	}
		413	break;
		414	case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
		415	check_offset =
		416	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		417	if (check_offset) {
		418	check_offset = RBIOS16(check_offset + 0x17);
		419	if (check_offset)
		420	offset = check_offset;
		421	}
		422	break;
		423	case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
		424	check_offset =
		425	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		426	if (check_offset) {
		427	check_offset = RBIOS16(check_offset + 0x2);
		428	if (check_offset)
		429	offset = check_offset;
		430	}
		431	break;
		432	case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
		433	check_offset =
		434	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		435	if (check_offset) {
		436	check_offset = RBIOS16(check_offset + 0x4);
		437	if (check_offset)
		438	offset = check_offset;
		439	}
		440	break;
		441	default:
		442	break;
		443	}
		444
		445	return offset;
		446
		447	}
		448
1430	serge	449	bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
		450	{
1963	serge	451	int edid_info, size;
1430	serge	452	struct edid *edid;
1963	serge	453	unsigned char *raw;
1430	serge	454	edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
		455	if (!edid_info)
		456	return false;
		457
1963	serge	458	raw = rdev->bios + edid_info;
		459	size = EDID_LENGTH * (raw[0x7e] + 1);
		460	edid = kmalloc(size, GFP_KERNEL);
1430	serge	461	if (edid == NULL)
		462	return false;
		463
1963	serge	464	memcpy((unsigned char *)edid, raw, size);
1430	serge	465
		466	if (!drm_edid_is_valid(edid)) {
		467	kfree(edid);
		468	return false;
		469	}
		470
		471	rdev->mode_info.bios_hardcoded_edid = edid;
1963	serge	472	rdev->mode_info.bios_hardcoded_edid_size = size;
1430	serge	473	return true;
		474	}
		475
1963	serge	476	/* this is used for atom LCDs as well */
1430	serge	477	struct edid *
1963	serge	478	radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
1430	serge	479	{
1963	serge	480	struct edid *edid;
		481
		482	if (rdev->mode_info.bios_hardcoded_edid) {
		483	edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
		484	if (edid) {
		485	memcpy((unsigned char *)edid,
		486	(unsigned char *)rdev->mode_info.bios_hardcoded_edid,
		487	rdev->mode_info.bios_hardcoded_edid_size);
		488	return edid;
		489	}
		490	}
1430	serge	491	return NULL;
		492	}
		493
1321	serge	494	static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
1963	serge	495	enum radeon_combios_ddc ddc,
		496	u32 clk_mask,
		497	u32 data_mask)
1123	serge	498	{
		499	struct radeon_i2c_bus_rec i2c;
1963	serge	500	int ddc_line = 0;
1123	serge	501
1963	serge	502	/* ddc id = mask reg
		503	* DDC_NONE_DETECTED = none
		504	* DDC_DVI = RADEON_GPIO_DVI_DDC
		505	* DDC_VGA = RADEON_GPIO_VGA_DDC
		506	* DDC_LCD = RADEON_GPIOPAD_MASK
		507	* DDC_GPIO = RADEON_MDGPIO_MASK
		508	* r1xx
		509	* DDC_MONID = RADEON_GPIO_MONID
		510	* DDC_CRT2 = RADEON_GPIO_CRT2_DDC
		511	* r200
		512	* DDC_MONID = RADEON_GPIO_MONID
		513	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		514	* r300/r350
		515	* DDC_MONID = RADEON_GPIO_DVI_DDC
		516	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		517	* rv2xx/rv3xx
		518	* DDC_MONID = RADEON_GPIO_MONID
		519	* DDC_CRT2 = RADEON_GPIO_MONID
		520	* rs3xx/rs4xx
		521	* DDC_MONID = RADEON_GPIOPAD_MASK
		522	* DDC_CRT2 = RADEON_GPIO_MONID
		523	*/
		524	switch (ddc) {
		525	case DDC_NONE_DETECTED:
		526	default:
		527	ddc_line = 0;
		528	break;
		529	case DDC_DVI:
		530	ddc_line = RADEON_GPIO_DVI_DDC;
		531	break;
		532	case DDC_VGA:
		533	ddc_line = RADEON_GPIO_VGA_DDC;
		534	break;
		535	case DDC_LCD:
		536	ddc_line = RADEON_GPIOPAD_MASK;
		537	break;
		538	case DDC_GPIO:
		539	ddc_line = RADEON_MDGPIO_MASK;
		540	break;
		541	case DDC_MONID:
		542	if (rdev->family == CHIP_RS300 \|\|
		543	rdev->family == CHIP_RS400 \|\|
		544	rdev->family == CHIP_RS480)
		545	ddc_line = RADEON_GPIOPAD_MASK;
		546	else if (rdev->family == CHIP_R300 \|\|
		547	rdev->family == CHIP_R350) {
		548	ddc_line = RADEON_GPIO_DVI_DDC;
		549	ddc = DDC_DVI;
		550	} else
		551	ddc_line = RADEON_GPIO_MONID;
		552	break;
		553	case DDC_CRT2:
		554	if (rdev->family == CHIP_R200 \|\|
		555	rdev->family == CHIP_R300 \|\|
		556	rdev->family == CHIP_R350) {
		557	ddc_line = RADEON_GPIO_DVI_DDC;
		558	ddc = DDC_DVI;
		559	} else if (rdev->family == CHIP_RS300 \|\|
		560	rdev->family == CHIP_RS400 \|\|
		561	rdev->family == CHIP_RS480)
		562	ddc_line = RADEON_GPIO_MONID;
		563	else if (rdev->family >= CHIP_RV350) {
		564	ddc_line = RADEON_GPIO_MONID;
		565	ddc = DDC_MONID;
		566	} else
		567	ddc_line = RADEON_GPIO_CRT2_DDC;
		568	break;
		569	}
		570
1321	serge	571	if (ddc_line == RADEON_GPIOPAD_MASK) {
		572	i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
		573	i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
		574	i2c.a_clk_reg = RADEON_GPIOPAD_A;
		575	i2c.a_data_reg = RADEON_GPIOPAD_A;
		576	i2c.en_clk_reg = RADEON_GPIOPAD_EN;
		577	i2c.en_data_reg = RADEON_GPIOPAD_EN;
		578	i2c.y_clk_reg = RADEON_GPIOPAD_Y;
		579	i2c.y_data_reg = RADEON_GPIOPAD_Y;
		580	} else if (ddc_line == RADEON_MDGPIO_MASK) {
		581	i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
		582	i2c.mask_data_reg = RADEON_MDGPIO_MASK;
		583	i2c.a_clk_reg = RADEON_MDGPIO_A;
		584	i2c.a_data_reg = RADEON_MDGPIO_A;
		585	i2c.en_clk_reg = RADEON_MDGPIO_EN;
		586	i2c.en_data_reg = RADEON_MDGPIO_EN;
		587	i2c.y_clk_reg = RADEON_MDGPIO_Y;
		588	i2c.y_data_reg = RADEON_MDGPIO_Y;
		589	} else {
1123	serge	590	i2c.mask_clk_reg = ddc_line;
		591	i2c.mask_data_reg = ddc_line;
		592	i2c.a_clk_reg = ddc_line;
		593	i2c.a_data_reg = ddc_line;
1321	serge	594	i2c.en_clk_reg = ddc_line;
		595	i2c.en_data_reg = ddc_line;
		596	i2c.y_clk_reg = ddc_line;
		597	i2c.y_data_reg = ddc_line;
1123	serge	598	}
		599
1963	serge	600	if (clk_mask && data_mask) {
		601	/* system specific masks */
		602	i2c.mask_clk_mask = clk_mask;
		603	i2c.mask_data_mask = data_mask;
		604	i2c.a_clk_mask = clk_mask;
		605	i2c.a_data_mask = data_mask;
		606	i2c.en_clk_mask = clk_mask;
		607	i2c.en_data_mask = data_mask;
		608	i2c.y_clk_mask = clk_mask;
		609	i2c.y_data_mask = data_mask;
		610	} else if ((ddc_line == RADEON_GPIOPAD_MASK) \|\|
		611	(ddc_line == RADEON_MDGPIO_MASK)) {
		612	/* default gpiopad masks */
		613	i2c.mask_clk_mask = (0x20 << 8);
		614	i2c.mask_data_mask = 0x80;
		615	i2c.a_clk_mask = (0x20 << 8);
		616	i2c.a_data_mask = 0x80;
		617	i2c.en_clk_mask = (0x20 << 8);
		618	i2c.en_data_mask = 0x80;
		619	i2c.y_clk_mask = (0x20 << 8);
		620	i2c.y_data_mask = 0x80;
		621	} else {
		622	/* default masks for ddc pads */
2997	Serge	623	i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
		624	i2c.mask_data_mask = RADEON_GPIO_MASK_0;
1963	serge	625	i2c.a_clk_mask = RADEON_GPIO_A_1;
		626	i2c.a_data_mask = RADEON_GPIO_A_0;
		627	i2c.en_clk_mask = RADEON_GPIO_EN_1;
		628	i2c.en_data_mask = RADEON_GPIO_EN_0;
		629	i2c.y_clk_mask = RADEON_GPIO_Y_1;
		630	i2c.y_data_mask = RADEON_GPIO_Y_0;
		631	}
		632
1430	serge	633	switch (rdev->family) {
		634	case CHIP_R100:
		635	case CHIP_RV100:
		636	case CHIP_RS100:
		637	case CHIP_RV200:
		638	case CHIP_RS200:
		639	case CHIP_RS300:
		640	switch (ddc_line) {
		641	case RADEON_GPIO_DVI_DDC:
1963	serge	642	i2c.hw_capable = true;
1430	serge	643	break;
		644	default:
		645	i2c.hw_capable = false;
		646	break;
		647	}
		648	break;
		649	case CHIP_R200:
		650	switch (ddc_line) {
		651	case RADEON_GPIO_DVI_DDC:
		652	case RADEON_GPIO_MONID:
		653	i2c.hw_capable = true;
		654	break;
		655	default:
		656	i2c.hw_capable = false;
		657	break;
		658	}
		659	break;
		660	case CHIP_RV250:
		661	case CHIP_RV280:
		662	switch (ddc_line) {
		663	case RADEON_GPIO_VGA_DDC:
		664	case RADEON_GPIO_DVI_DDC:
		665	case RADEON_GPIO_CRT2_DDC:
		666	i2c.hw_capable = true;
		667	break;
		668	default:
		669	i2c.hw_capable = false;
		670	break;
		671	}
		672	break;
		673	case CHIP_R300:
		674	case CHIP_R350:
		675	switch (ddc_line) {
		676	case RADEON_GPIO_VGA_DDC:
		677	case RADEON_GPIO_DVI_DDC:
		678	i2c.hw_capable = true;
		679	break;
		680	default:
1321	serge	681	i2c.hw_capable = false;
1430	serge	682	break;
		683	}
		684	break;
		685	case CHIP_RV350:
		686	case CHIP_RV380:
		687	case CHIP_RS400:
		688	case CHIP_RS480:
1321	serge	689	switch (ddc_line) {
		690	case RADEON_GPIO_VGA_DDC:
		691	case RADEON_GPIO_DVI_DDC:
		692	i2c.hw_capable = true;
		693	break;
		694	case RADEON_GPIO_MONID:
		695	/* hw i2c on RADEON_GPIO_MONID doesn't seem to work
		696	* reliably on some pre-r4xx hardware; not sure why.
		697	*/
		698	i2c.hw_capable = false;
		699	break;
		700	default:
		701	i2c.hw_capable = false;
		702	break;
		703	}
1430	serge	704	break;
		705	default:
		706	i2c.hw_capable = false;
		707	break;
1321	serge	708	}
		709	i2c.mm_i2c = false;
		710
1963	serge	711	i2c.i2c_id = ddc;
		712	i2c.hpd = RADEON_HPD_NONE;
		713
1123	serge	714	if (ddc_line)
		715	i2c.valid = true;
		716	else
		717	i2c.valid = false;
		718
		719	return i2c;
		720	}
		721
2997	Serge	722	static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
		723	{
		724	struct drm_device *dev = rdev->ddev;
		725	struct radeon_i2c_bus_rec i2c;
		726	u16 offset;
		727	u8 id, blocks, clk, data;
		728	int i;
		729
		730	i2c.valid = false;
		731
		732	offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
		733	if (offset) {
		734	blocks = RBIOS8(offset + 2);
		735	for (i = 0; i < blocks; i++) {
		736	id = RBIOS8(offset + 3 + (i * 5) + 0);
		737	if (id == 136) {
		738	clk = RBIOS8(offset + 3 + (i * 5) + 3);
		739	data = RBIOS8(offset + 3 + (i * 5) + 4);
		740	/* gpiopad */
		741	i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
		742	(1 << clk), (1 << data));
		743	break;
		744	}
		745	}
		746	}
		747	return i2c;
		748	}
		749
1963	serge	750	void radeon_combios_i2c_init(struct radeon_device *rdev)
		751	{
		752	struct drm_device *dev = rdev->ddev;
		753	struct radeon_i2c_bus_rec i2c;
		754
		755	/* actual hw pads
		756	* r1xx/rs2xx/rs3xx
		757	* 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
		758	* r200
		759	* 0x60, 0x64, 0x68, mm
		760	* r300/r350
		761	* 0x60, 0x64, mm
		762	* rv2xx/rv3xx/rs4xx
		763	* 0x60, 0x64, 0x68, gpiopads, mm
		764	*/
		765
		766	/* 0x60 */
		767	i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		768	rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
		769	/* 0x64 */
		770	i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		771	rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
		772
		773	/* mm i2c */
		774	i2c.valid = true;
		775	i2c.hw_capable = true;
		776	i2c.mm_i2c = true;
		777	i2c.i2c_id = 0xa0;
		778	rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
		779
		780	if (rdev->family == CHIP_R300 \|\|
		781	rdev->family == CHIP_R350) {
		782	/* only 2 sw i2c pads */
		783	} else if (rdev->family == CHIP_RS300 \|\|
		784	rdev->family == CHIP_RS400 \|\|
		785	rdev->family == CHIP_RS480) {
		786	/* 0x68 */
		787	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		788	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		789
		790	/* gpiopad */
2997	Serge	791	i2c = radeon_combios_get_i2c_info_from_table(rdev);
		792	if (i2c.valid)
1963	serge	793	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
2160	serge	794	} else if ((rdev->family == CHIP_R200) \|\|
		795	(rdev->family >= CHIP_R300)) {
1963	serge	796	/* 0x68 */
		797	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		798	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		799	} else {
		800	/* 0x68 */
		801	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		802	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		803	/* 0x6c */
		804	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		805	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
		806	}
		807	}
		808
1123	serge	809	bool radeon_combios_get_clock_info(struct drm_device *dev)
		810	{
		811	struct radeon_device *rdev = dev->dev_private;
		812	uint16_t pll_info;
		813	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		814	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		815	struct radeon_pll *spll = &rdev->clock.spll;
		816	struct radeon_pll *mpll = &rdev->clock.mpll;
		817	int8_t rev;
		818	uint16_t sclk, mclk;
		819
		820	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
		821	if (pll_info) {
		822	rev = RBIOS8(pll_info);
		823
		824	/* pixel clocks */
		825	p1pll->reference_freq = RBIOS16(pll_info + 0xe);
		826	p1pll->reference_div = RBIOS16(pll_info + 0x10);
		827	p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
		828	p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
1963	serge	829	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		830	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1123	serge	831
		832	if (rev > 9) {
		833	p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
		834	p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
		835	} else {
		836	p1pll->pll_in_min = 40;
		837	p1pll->pll_in_max = 500;
		838	}
		839	p2pll = p1pll;
		840
		841	/* system clock */
		842	spll->reference_freq = RBIOS16(pll_info + 0x1a);
		843	spll->reference_div = RBIOS16(pll_info + 0x1c);
		844	spll->pll_out_min = RBIOS32(pll_info + 0x1e);
		845	spll->pll_out_max = RBIOS32(pll_info + 0x22);
		846
		847	if (rev > 10) {
		848	spll->pll_in_min = RBIOS32(pll_info + 0x48);
		849	spll->pll_in_max = RBIOS32(pll_info + 0x4c);
		850	} else {
		851	/* ??? */
		852	spll->pll_in_min = 40;
		853	spll->pll_in_max = 500;
		854	}
		855
		856	/* memory clock */
		857	mpll->reference_freq = RBIOS16(pll_info + 0x26);
		858	mpll->reference_div = RBIOS16(pll_info + 0x28);
		859	mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
		860	mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
		861
		862	if (rev > 10) {
		863	mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
		864	mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
		865	} else {
		866	/* ??? */
		867	mpll->pll_in_min = 40;
		868	mpll->pll_in_max = 500;
		869	}
		870
		871	/* default sclk/mclk */
		872	sclk = RBIOS16(pll_info + 0xa);
		873	mclk = RBIOS16(pll_info + 0x8);
		874	if (sclk == 0)
		875	sclk = 200 * 100;
		876	if (mclk == 0)
		877	mclk = 200 * 100;
		878
		879	rdev->clock.default_sclk = sclk;
		880	rdev->clock.default_mclk = mclk;
		881
1963	serge	882	if (RBIOS32(pll_info + 0x16))
		883	rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
		884	else
		885	rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
		886
1123	serge	887	return true;
		888	}
		889	return false;
		890	}
		891
1404	serge	892	bool radeon_combios_sideport_present(struct radeon_device *rdev)
		893	{
		894	struct drm_device *dev = rdev->ddev;
		895	u16 igp_info;
		896
1963	serge	897	/* sideport is AMD only */
		898	if (rdev->family == CHIP_RS400)
		899	return false;
		900
1404	serge	901	igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
		902
		903	if (igp_info) {
		904	if (RBIOS16(igp_info + 0x4))
		905	return true;
		906	}
		907	return false;
		908	}
		909
		910	static const uint32_t default_primarydac_adj[CHIP_LAST] = {
		911	0x00000808, /* r100 */
		912	0x00000808, /* rv100 */
		913	0x00000808, /* rs100 */
		914	0x00000808, /* rv200 */
		915	0x00000808, /* rs200 */
		916	0x00000808, /* r200 */
		917	0x00000808, /* rv250 */
		918	0x00000000, /* rs300 */
		919	0x00000808, /* rv280 */
		920	0x00000808, /* r300 */
		921	0x00000808, /* r350 */
		922	0x00000808, /* rv350 */
		923	0x00000808, /* rv380 */
		924	0x00000808, /* r420 */
		925	0x00000808, /* r423 */
		926	0x00000808, /* rv410 */
		927	0x00000000, /* rs400 */
		928	0x00000000, /* rs480 */
		929	};
		930
		931	static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
		932	struct radeon_encoder_primary_dac *p_dac)
		933	{
		934	p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
		935	return;
		936	}
		937
1123	serge	938	struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
		939	radeon_encoder
		940	*encoder)
		941	{
		942	struct drm_device *dev = encoder->base.dev;
		943	struct radeon_device *rdev = dev->dev_private;
		944	uint16_t dac_info;
		945	uint8_t rev, bg, dac;
		946	struct radeon_encoder_primary_dac *p_dac = NULL;
1404	serge	947	int found = 0;
1123	serge	948
1404	serge	949	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
		950	GFP_KERNEL);
		951
		952	if (!p_dac)
1123	serge	953	return NULL;
		954
		955	/* check CRT table */
		956	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		957	if (dac_info) {
		958	rev = RBIOS8(dac_info) & 0x3;
		959	if (rev < 2) {
		960	bg = RBIOS8(dac_info + 0x2) & 0xf;
		961	dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
		962	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		963	} else {
		964	bg = RBIOS8(dac_info + 0x2) & 0xf;
		965	dac = RBIOS8(dac_info + 0x3) & 0xf;
		966	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		967	}
1963	serge	968	/* if the values are all zeros, use the table */
		969	if (p_dac->ps2_pdac_adj)
1404	serge	970	found = 1;
1123	serge	971	}
		972
3764	Serge	973	/* quirks */
		974	/* Radeon 9100 (R200) */
		975	if ((dev->pdev->device == 0x514D) &&
		976	(dev->pdev->subsystem_vendor == 0x174B) &&
		977	(dev->pdev->subsystem_device == 0x7149)) {
		978	/* vbios value is bad, use the default */
		979	found = 0;
		980	}
		981
1404	serge	982	if (!found) /* fallback to defaults */
		983	radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
		984
1123	serge	985	return p_dac;
		986	}
		987
1404	serge	988	enum radeon_tv_std
		989	radeon_combios_get_tv_info(struct radeon_device *rdev)
1123	serge	990	{
1404	serge	991	struct drm_device *dev = rdev->ddev;
1123	serge	992	uint16_t tv_info;
		993	enum radeon_tv_std tv_std = TV_STD_NTSC;
		994
		995	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		996	if (tv_info) {
		997	if (RBIOS8(tv_info + 6) == 'T') {
		998	switch (RBIOS8(tv_info + 7) & 0xf) {
		999	case 1:
		1000	tv_std = TV_STD_NTSC;
1963	serge	1001	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1123	serge	1002	break;
		1003	case 2:
		1004	tv_std = TV_STD_PAL;
1963	serge	1005	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1123	serge	1006	break;
		1007	case 3:
		1008	tv_std = TV_STD_PAL_M;
1963	serge	1009	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1123	serge	1010	break;
		1011	case 4:
		1012	tv_std = TV_STD_PAL_60;
1963	serge	1013	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1123	serge	1014	break;
		1015	case 5:
		1016	tv_std = TV_STD_NTSC_J;
1963	serge	1017	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1123	serge	1018	break;
		1019	case 6:
		1020	tv_std = TV_STD_SCART_PAL;
1963	serge	1021	DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1123	serge	1022	break;
		1023	default:
		1024	tv_std = TV_STD_NTSC;
1963	serge	1025	DRM_DEBUG_KMS
1123	serge	1026	("Unknown TV standard; defaulting to NTSC\n");
		1027	break;
		1028	}
		1029
		1030	switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
		1031	case 0:
1963	serge	1032	DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1123	serge	1033	break;
		1034	case 1:
1963	serge	1035	DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1123	serge	1036	break;
		1037	case 2:
1963	serge	1038	DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1123	serge	1039	break;
		1040	case 3:
1963	serge	1041	DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1123	serge	1042	break;
		1043	default:
		1044	break;
		1045	}
		1046	}
		1047	}
		1048	return tv_std;
		1049	}
		1050
		1051	static const uint32_t default_tvdac_adj[CHIP_LAST] = {
		1052	0x00000000, /* r100 */
		1053	0x00280000, /* rv100 */
		1054	0x00000000, /* rs100 */
		1055	0x00880000, /* rv200 */
		1056	0x00000000, /* rs200 */
		1057	0x00000000, /* r200 */
		1058	0x00770000, /* rv250 */
		1059	0x00290000, /* rs300 */
		1060	0x00560000, /* rv280 */
		1061	0x00780000, /* r300 */
		1062	0x00770000, /* r350 */
		1063	0x00780000, /* rv350 */
		1064	0x00780000, /* rv380 */
		1065	0x01080000, /* r420 */
		1066	0x01080000, /* r423 */
		1067	0x01080000, /* rv410 */
		1068	0x00780000, /* rs400 */
		1069	0x00780000, /* rs480 */
		1070	};
		1071
1179	serge	1072	static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
		1073	struct radeon_encoder_tv_dac *tv_dac)
1123	serge	1074	{
		1075	tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
		1076	if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
		1077	tv_dac->ps2_tvdac_adj = 0x00880000;
		1078	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1079	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	1080	return;
1123	serge	1081	}
		1082
		1083	struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
		1084	radeon_encoder
		1085	*encoder)
		1086	{
		1087	struct drm_device *dev = encoder->base.dev;
		1088	struct radeon_device *rdev = dev->dev_private;
		1089	uint16_t dac_info;
		1090	uint8_t rev, bg, dac;
		1091	struct radeon_encoder_tv_dac *tv_dac = NULL;
1179	serge	1092	int found = 0;
1123	serge	1093
1179	serge	1094	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1095	if (!tv_dac)
		1096	return NULL;
		1097
1123	serge	1098	/* first check TV table */
		1099	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		1100	if (dac_info) {
		1101	rev = RBIOS8(dac_info + 0x3);
		1102	if (rev > 4) {
		1103	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1104	dac = RBIOS8(dac_info + 0xd) & 0xf;
		1105	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1106
		1107	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1108	dac = RBIOS8(dac_info + 0xf) & 0xf;
		1109	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1110
		1111	bg = RBIOS8(dac_info + 0x10) & 0xf;
		1112	dac = RBIOS8(dac_info + 0x11) & 0xf;
		1113	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1114	/* if the values are all zeros, use the table */
		1115	if (tv_dac->ps2_tvdac_adj)
1179	serge	1116	found = 1;
1123	serge	1117	} else if (rev > 1) {
		1118	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1119	dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
		1120	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1121
		1122	bg = RBIOS8(dac_info + 0xd) & 0xf;
		1123	dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
		1124	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1125
		1126	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1127	dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
		1128	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1129	/* if the values are all zeros, use the table */
		1130	if (tv_dac->ps2_tvdac_adj)
1179	serge	1131	found = 1;
1123	serge	1132	}
1404	serge	1133	tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1179	serge	1134	}
		1135	if (!found) {
1123	serge	1136	/* then check CRT table */
		1137	dac_info =
		1138	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		1139	if (dac_info) {
		1140	rev = RBIOS8(dac_info) & 0x3;
		1141	if (rev < 2) {
		1142	bg = RBIOS8(dac_info + 0x3) & 0xf;
		1143	dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
		1144	tv_dac->ps2_tvdac_adj =
		1145	(bg << 16) \| (dac << 20);
		1146	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1147	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1148	/* if the values are all zeros, use the table */
		1149	if (tv_dac->ps2_tvdac_adj)
1179	serge	1150	found = 1;
1123	serge	1151	} else {
		1152	bg = RBIOS8(dac_info + 0x4) & 0xf;
		1153	dac = RBIOS8(dac_info + 0x5) & 0xf;
		1154	tv_dac->ps2_tvdac_adj =
		1155	(bg << 16) \| (dac << 20);
		1156	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1157	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1158	/* if the values are all zeros, use the table */
		1159	if (tv_dac->ps2_tvdac_adj)
1179	serge	1160	found = 1;
1123	serge	1161	}
		1162	} else {
		1163	DRM_INFO("No TV DAC info found in BIOS\n");
		1164	}
		1165	}
1221	serge	1166
1179	serge	1167	if (!found) /* fallback to defaults */
		1168	radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1123	serge	1169
		1170	return tv_dac;
		1171	}
		1172
		1173	static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
		1174	radeon_device
		1175	*rdev)
		1176	{
		1177	struct radeon_encoder_lvds *lvds = NULL;
		1178	uint32_t fp_vert_stretch, fp_horz_stretch;
		1179	uint32_t ppll_div_sel, ppll_val;
		1180	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		1181
		1182	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1183
		1184	if (!lvds)
		1185	return NULL;
		1186
		1187	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
		1188	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
		1189
		1190	/* These should be fail-safe defaults, fingers crossed */
		1191	lvds->panel_pwr_delay = 200;
		1192	lvds->panel_vcc_delay = 2000;
		1193
		1194	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		1195	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
		1196	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
		1197
		1198	if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1268	serge	1199	lvds->native_mode.vdisplay =
1123	serge	1200	((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
		1201	RADEON_VERT_PANEL_SHIFT) + 1;
		1202	else
1268	serge	1203	lvds->native_mode.vdisplay =
1123	serge	1204	(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
		1205
		1206	if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1268	serge	1207	lvds->native_mode.hdisplay =
1123	serge	1208	(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
		1209	RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
		1210	else
1268	serge	1211	lvds->native_mode.hdisplay =
1123	serge	1212	((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
		1213
1268	serge	1214	if ((lvds->native_mode.hdisplay < 640) \|\|
		1215	(lvds->native_mode.vdisplay < 480)) {
		1216	lvds->native_mode.hdisplay = 640;
		1217	lvds->native_mode.vdisplay = 480;
1123	serge	1218	}
		1219
		1220	ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
		1221	ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
		1222	if ((ppll_val & 0x000707ff) == 0x1bb)
		1223	lvds->use_bios_dividers = false;
		1224	else {
		1225	lvds->panel_ref_divider =
		1226	RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
		1227	lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
		1228	lvds->panel_fb_divider = ppll_val & 0x7ff;
		1229
		1230	if ((lvds->panel_ref_divider != 0) &&
		1231	(lvds->panel_fb_divider > 3))
		1232	lvds->use_bios_dividers = true;
		1233	}
		1234	lvds->panel_vcc_delay = 200;
		1235
		1236	DRM_INFO("Panel info derived from registers\n");
1268	serge	1237	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1238	lvds->native_mode.vdisplay);
1123	serge	1239
		1240	return lvds;
		1241	}
		1242
		1243	struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
		1244	*encoder)
		1245	{
		1246	struct drm_device *dev = encoder->base.dev;
		1247	struct radeon_device *rdev = dev->dev_private;
		1248	uint16_t lcd_info;
		1249	uint32_t panel_setup;
		1250	char stmp[30];
		1251	int tmp, i;
		1252	struct radeon_encoder_lvds *lvds = NULL;
		1253
		1254	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		1255
		1256	if (lcd_info) {
		1257	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1258
		1259	if (!lvds)
		1260	return NULL;
		1261
		1262	for (i = 0; i < 24; i++)
		1263	stmp[i] = RBIOS8(lcd_info + i + 1);
		1264	stmp[24] = 0;
		1265
		1266	DRM_INFO("Panel ID String: %s\n", stmp);
		1267
1268	serge	1268	lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
		1269	lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1123	serge	1270
1268	serge	1271	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1272	lvds->native_mode.vdisplay);
1123	serge	1273
		1274	lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1404	serge	1275	lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1123	serge	1276
		1277	lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
		1278	lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
		1279	lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
		1280
		1281	lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
		1282	lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
		1283	lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
		1284	if ((lvds->panel_ref_divider != 0) &&
		1285	(lvds->panel_fb_divider > 3))
		1286	lvds->use_bios_dividers = true;
		1287
		1288	panel_setup = RBIOS32(lcd_info + 0x39);
		1289	lvds->lvds_gen_cntl = 0xff00;
		1290	if (panel_setup & 0x1)
		1291	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_FORMAT;
		1292
		1293	if ((panel_setup >> 4) & 0x1)
		1294	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_TYPE;
		1295
		1296	switch ((panel_setup >> 8) & 0x7) {
		1297	case 0:
		1298	lvds->lvds_gen_cntl \|= RADEON_LVDS_NO_FM;
		1299	break;
		1300	case 1:
		1301	lvds->lvds_gen_cntl \|= RADEON_LVDS_2_GREY;
		1302	break;
		1303	case 2:
		1304	lvds->lvds_gen_cntl \|= RADEON_LVDS_4_GREY;
		1305	break;
		1306	default:
		1307	break;
		1308	}
		1309
		1310	if ((panel_setup >> 16) & 0x1)
		1311	lvds->lvds_gen_cntl \|= RADEON_LVDS_FP_POL_LOW;
		1312
		1313	if ((panel_setup >> 17) & 0x1)
		1314	lvds->lvds_gen_cntl \|= RADEON_LVDS_LP_POL_LOW;
		1315
		1316	if ((panel_setup >> 18) & 0x1)
		1317	lvds->lvds_gen_cntl \|= RADEON_LVDS_DTM_POL_LOW;
		1318
		1319	if ((panel_setup >> 23) & 0x1)
		1320	lvds->lvds_gen_cntl \|= RADEON_LVDS_BL_CLK_SEL;
		1321
		1322	lvds->lvds_gen_cntl \|= (panel_setup & 0xf0000000);
		1323
		1324	for (i = 0; i < 32; i++) {
		1325	tmp = RBIOS16(lcd_info + 64 + i * 2);
		1326	if (tmp == 0)
		1327	break;
		1328
1268	serge	1329	if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1963	serge	1330	(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
		1331	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
		1332	(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
		1333	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
		1334	(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
		1335	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
		1336	(RBIOS8(tmp + 23) * 8);
1123	serge	1337
1963	serge	1338	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
		1339	(RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
		1340	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1341	((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
		1342	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
		1343	((RBIOS16(tmp + 28) & 0xf800) >> 11);
1268	serge	1344
		1345	lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1123	serge	1346	lvds->native_mode.flags = 0;
1268	serge	1347	/* set crtc values */
		1348	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
		1349
1123	serge	1350	}
		1351	}
		1352	} else {
		1353	DRM_INFO("No panel info found in BIOS\n");
1179	serge	1354	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1123	serge	1355	}
1430	serge	1356
1179	serge	1357	if (lvds)
		1358	encoder->native_mode = lvds->native_mode;
1123	serge	1359	return lvds;
		1360	}
		1361
		1362	static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
		1363	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
		1364	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
		1365	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
		1366	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
		1367	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
		1368	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
		1369	{{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
		1370	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
		1371	{{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
		1372	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
		1373	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
		1374	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
		1375	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
		1376	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
		1377	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
		1378	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1321	serge	1379	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
		1380	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1123	serge	1381	};
		1382
1179	serge	1383	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
		1384	struct radeon_encoder_int_tmds *tmds)
1123	serge	1385	{
1179	serge	1386	struct drm_device *dev = encoder->base.dev;
		1387	struct radeon_device *rdev = dev->dev_private;
1123	serge	1388	int i;
		1389
		1390	for (i = 0; i < 4; i++) {
		1391	tmds->tmds_pll[i].value =
		1392	default_tmds_pll[rdev->family][i].value;
		1393	tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
		1394	}
		1395
1179	serge	1396	return true;
1123	serge	1397	}
		1398
1179	serge	1399	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
		1400	struct radeon_encoder_int_tmds *tmds)
1123	serge	1401	{
		1402	struct drm_device *dev = encoder->base.dev;
		1403	struct radeon_device *rdev = dev->dev_private;
		1404	uint16_t tmds_info;
		1405	int i, n;
		1406	uint8_t ver;
		1407
		1408	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1409
		1410	if (tmds_info) {
		1411	ver = RBIOS8(tmds_info);
1963	serge	1412	DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1123	serge	1413	if (ver == 3) {
		1414	n = RBIOS8(tmds_info + 5) + 1;
		1415	if (n > 4)
		1416	n = 4;
		1417	for (i = 0; i < n; i++) {
		1418	tmds->tmds_pll[i].value =
		1419	RBIOS32(tmds_info + i * 10 + 0x08);
		1420	tmds->tmds_pll[i].freq =
		1421	RBIOS16(tmds_info + i * 10 + 0x10);
1963	serge	1422	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1423	tmds->tmds_pll[i].freq,
		1424	tmds->tmds_pll[i].value);
		1425	}
		1426	} else if (ver == 4) {
		1427	int stride = 0;
		1428	n = RBIOS8(tmds_info + 5) + 1;
		1429	if (n > 4)
		1430	n = 4;
		1431	for (i = 0; i < n; i++) {
		1432	tmds->tmds_pll[i].value =
		1433	RBIOS32(tmds_info + stride + 0x08);
		1434	tmds->tmds_pll[i].freq =
		1435	RBIOS16(tmds_info + stride + 0x10);
		1436	if (i == 0)
		1437	stride += 10;
		1438	else
		1439	stride += 6;
1963	serge	1440	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1441	tmds->tmds_pll[i].freq,
		1442	tmds->tmds_pll[i].value);
		1443	}
		1444	}
1321	serge	1445	} else {
1123	serge	1446	DRM_INFO("No TMDS info found in BIOS\n");
1321	serge	1447	return false;
		1448	}
1179	serge	1449	return true;
		1450	}
		1451
1321	serge	1452	bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
		1453	struct radeon_encoder_ext_tmds *tmds)
1179	serge	1454	{
1321	serge	1455	struct drm_device *dev = encoder->base.dev;
		1456	struct radeon_device *rdev = dev->dev_private;
		1457	struct radeon_i2c_bus_rec i2c_bus;
1179	serge	1458
1321	serge	1459	/* default for macs */
1963	serge	1460	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1461	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1179	serge	1462
1321	serge	1463	/* XXX some macs have duallink chips */
		1464	switch (rdev->mode_info.connector_table) {
		1465	case CT_POWERBOOK_EXTERNAL:
		1466	case CT_MINI_EXTERNAL:
		1467	default:
		1468	tmds->dvo_chip = DVO_SIL164;
		1469	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1470	break;
		1471	}
1179	serge	1472
1321	serge	1473	return true;
1123	serge	1474	}
		1475
1321	serge	1476	bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
		1477	struct radeon_encoder_ext_tmds *tmds)
1123	serge	1478	{
		1479	struct drm_device *dev = encoder->base.dev;
		1480	struct radeon_device *rdev = dev->dev_private;
1321	serge	1481	uint16_t offset;
1963	serge	1482	uint8_t ver;
1321	serge	1483	enum radeon_combios_ddc gpio;
		1484	struct radeon_i2c_bus_rec i2c_bus;
1123	serge	1485
1321	serge	1486	tmds->i2c_bus = NULL;
		1487	if (rdev->flags & RADEON_IS_IGP) {
1963	serge	1488	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1489	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1490	tmds->dvo_chip = DVO_SIL164;
		1491	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1492	} else {
		1493	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1494	if (offset) {
		1495	ver = RBIOS8(offset);
1963	serge	1496	DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1321	serge	1497	tmds->slave_addr = RBIOS8(offset + 4 + 2);
		1498	tmds->slave_addr >>= 1; /* 7 bit addressing */
		1499	gpio = RBIOS8(offset + 4 + 3);
1963	serge	1500	if (gpio == DDC_LCD) {
		1501	/* MM i2c */
1430	serge	1502	i2c_bus.valid = true;
		1503	i2c_bus.hw_capable = true;
		1504	i2c_bus.mm_i2c = true;
1963	serge	1505	i2c_bus.i2c_id = 0xa0;
		1506	} else
		1507	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		1508	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1509	}
		1510	}
		1511
		1512	if (!tmds->i2c_bus) {
		1513	DRM_INFO("No valid Ext TMDS info found in BIOS\n");
		1514	return false;
		1515	}
		1516
		1517	return true;
1123	serge	1518	}
		1519
		1520	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
		1521	{
		1522	struct radeon_device *rdev = dev->dev_private;
		1523	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	1524	struct radeon_hpd hpd;
1123	serge	1525
		1526	rdev->mode_info.connector_table = radeon_connector_table;
		1527	if (rdev->mode_info.connector_table == CT_NONE) {
		1528	#ifdef CONFIG_PPC_PMAC
1430	serge	1529	if (of_machine_is_compatible("PowerBook3,3")) {
1123	serge	1530	/* powerbook with VGA */
		1531	rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1430	serge	1532	} else if (of_machine_is_compatible("PowerBook3,4") \|\|
		1533	of_machine_is_compatible("PowerBook3,5")) {
1123	serge	1534	/* powerbook with internal tmds */
		1535	rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1430	serge	1536	} else if (of_machine_is_compatible("PowerBook5,1") \|\|
		1537	of_machine_is_compatible("PowerBook5,2") \|\|
		1538	of_machine_is_compatible("PowerBook5,3") \|\|
		1539	of_machine_is_compatible("PowerBook5,4") \|\|
		1540	of_machine_is_compatible("PowerBook5,5")) {
1123	serge	1541	/* powerbook with external single link tmds (sil164) */
		1542	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1543	} else if (of_machine_is_compatible("PowerBook5,6")) {
1123	serge	1544	/* powerbook with external dual or single link tmds */
		1545	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1546	} else if (of_machine_is_compatible("PowerBook5,7") \|\|
		1547	of_machine_is_compatible("PowerBook5,8") \|\|
		1548	of_machine_is_compatible("PowerBook5,9")) {
1123	serge	1549	/* PowerBook6,2 ? */
		1550	/* powerbook with external dual link tmds (sil1178?) */
		1551	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1552	} else if (of_machine_is_compatible("PowerBook4,1") \|\|
		1553	of_machine_is_compatible("PowerBook4,2") \|\|
		1554	of_machine_is_compatible("PowerBook4,3") \|\|
		1555	of_machine_is_compatible("PowerBook6,3") \|\|
		1556	of_machine_is_compatible("PowerBook6,5") \|\|
		1557	of_machine_is_compatible("PowerBook6,7")) {
1123	serge	1558	/* ibook */
		1559	rdev->mode_info.connector_table = CT_IBOOK;
3192	Serge	1560	} else if (of_machine_is_compatible("PowerMac3,5")) {
		1561	/* PowerMac G4 Silver radeon 7500 */
		1562	rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1430	serge	1563	} else if (of_machine_is_compatible("PowerMac4,4")) {
1123	serge	1564	/* emac */
		1565	rdev->mode_info.connector_table = CT_EMAC;
1430	serge	1566	} else if (of_machine_is_compatible("PowerMac10,1")) {
1123	serge	1567	/* mini with internal tmds */
		1568	rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1430	serge	1569	} else if (of_machine_is_compatible("PowerMac10,2")) {
1123	serge	1570	/* mini with external tmds */
		1571	rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1430	serge	1572	} else if (of_machine_is_compatible("PowerMac12,1")) {
1123	serge	1573	/* PowerMac8,1 ? */
		1574	/* imac g5 isight */
		1575	rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1963	serge	1576	} else if ((rdev->pdev->device == 0x4a48) &&
		1577	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1578	(rdev->pdev->subsystem_device == 0x4a48)) {
		1579	/* Mac X800 */
		1580	rdev->mode_info.connector_table = CT_MAC_X800;
1986	serge	1581	} else if ((of_machine_is_compatible("PowerMac7,2") \|\|
		1582	of_machine_is_compatible("PowerMac7,3")) &&
		1583	(rdev->pdev->device == 0x4150) &&
		1584	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1585	(rdev->pdev->subsystem_device == 0x4150)) {
		1586	/* Mac G5 tower 9600 */
1963	serge	1587	rdev->mode_info.connector_table = CT_MAC_G5_9600;
2997	Serge	1588	} else if ((rdev->pdev->device == 0x4c66) &&
		1589	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1590	(rdev->pdev->subsystem_device == 0x4c66)) {
		1591	/* SAM440ep RV250 embedded board */
		1592	rdev->mode_info.connector_table = CT_SAM440EP;
1123	serge	1593	} else
		1594	#endif /* CONFIG_PPC_PMAC */
1963	serge	1595	#ifdef CONFIG_PPC64
		1596	if (ASIC_IS_RN50(rdev))
		1597	rdev->mode_info.connector_table = CT_RN50_POWER;
		1598	else
		1599	#endif
1123	serge	1600	rdev->mode_info.connector_table = CT_GENERIC;
		1601	}
		1602
		1603	switch (rdev->mode_info.connector_table) {
		1604	case CT_GENERIC:
		1605	DRM_INFO("Connector Table: %d (generic)\n",
		1606	rdev->mode_info.connector_table);
		1607	/* these are the most common settings */
		1608	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1609	/* VGA - primary dac */
1963	serge	1610	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1611	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1612	radeon_add_legacy_encoder(dev,
1963	serge	1613	radeon_get_encoder_enum(dev,
1123	serge	1614	ATOM_DEVICE_CRT1_SUPPORT,
		1615	1),
		1616	ATOM_DEVICE_CRT1_SUPPORT);
		1617	radeon_add_legacy_connector(dev, 0,
		1618	ATOM_DEVICE_CRT1_SUPPORT,
		1619	DRM_MODE_CONNECTOR_VGA,
1268	serge	1620	&ddc_i2c,
1321	serge	1621	CONNECTOR_OBJECT_ID_VGA,
		1622	&hpd);
1123	serge	1623	} else if (rdev->flags & RADEON_IS_MOBILITY) {
		1624	/* LVDS */
1963	serge	1625	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1321	serge	1626	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1627	radeon_add_legacy_encoder(dev,
1963	serge	1628	radeon_get_encoder_enum(dev,
1123	serge	1629	ATOM_DEVICE_LCD1_SUPPORT,
		1630	0),
		1631	ATOM_DEVICE_LCD1_SUPPORT);
		1632	radeon_add_legacy_connector(dev, 0,
		1633	ATOM_DEVICE_LCD1_SUPPORT,
		1634	DRM_MODE_CONNECTOR_LVDS,
1268	serge	1635	&ddc_i2c,
1321	serge	1636	CONNECTOR_OBJECT_ID_LVDS,
		1637	&hpd);
1123	serge	1638
		1639	/* VGA - primary dac */
1963	serge	1640	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1641	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1642	radeon_add_legacy_encoder(dev,
1963	serge	1643	radeon_get_encoder_enum(dev,
1123	serge	1644	ATOM_DEVICE_CRT1_SUPPORT,
		1645	1),
		1646	ATOM_DEVICE_CRT1_SUPPORT);
		1647	radeon_add_legacy_connector(dev, 1,
		1648	ATOM_DEVICE_CRT1_SUPPORT,
		1649	DRM_MODE_CONNECTOR_VGA,
1268	serge	1650	&ddc_i2c,
1321	serge	1651	CONNECTOR_OBJECT_ID_VGA,
		1652	&hpd);
1123	serge	1653	} else {
		1654	/* DVI-I - tv dac, int tmds */
1963	serge	1655	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1656	hpd.hpd = RADEON_HPD_1;
1123	serge	1657	radeon_add_legacy_encoder(dev,
1963	serge	1658	radeon_get_encoder_enum(dev,
1123	serge	1659	ATOM_DEVICE_DFP1_SUPPORT,
		1660	0),
		1661	ATOM_DEVICE_DFP1_SUPPORT);
		1662	radeon_add_legacy_encoder(dev,
1963	serge	1663	radeon_get_encoder_enum(dev,
1123	serge	1664	ATOM_DEVICE_CRT2_SUPPORT,
		1665	2),
		1666	ATOM_DEVICE_CRT2_SUPPORT);
		1667	radeon_add_legacy_connector(dev, 0,
		1668	ATOM_DEVICE_DFP1_SUPPORT \|
		1669	ATOM_DEVICE_CRT2_SUPPORT,
		1670	DRM_MODE_CONNECTOR_DVII,
1268	serge	1671	&ddc_i2c,
1321	serge	1672	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1673	&hpd);
1123	serge	1674
		1675	/* VGA - primary dac */
1963	serge	1676	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1677	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1678	radeon_add_legacy_encoder(dev,
1963	serge	1679	radeon_get_encoder_enum(dev,
1123	serge	1680	ATOM_DEVICE_CRT1_SUPPORT,
		1681	1),
		1682	ATOM_DEVICE_CRT1_SUPPORT);
		1683	radeon_add_legacy_connector(dev, 1,
		1684	ATOM_DEVICE_CRT1_SUPPORT,
		1685	DRM_MODE_CONNECTOR_VGA,
1268	serge	1686	&ddc_i2c,
1321	serge	1687	CONNECTOR_OBJECT_ID_VGA,
		1688	&hpd);
1123	serge	1689	}
		1690
		1691	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1692	/* TV - tv dac */
1321	serge	1693	ddc_i2c.valid = false;
		1694	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1695	radeon_add_legacy_encoder(dev,
1963	serge	1696	radeon_get_encoder_enum(dev,
1123	serge	1697	ATOM_DEVICE_TV1_SUPPORT,
		1698	2),
		1699	ATOM_DEVICE_TV1_SUPPORT);
		1700	radeon_add_legacy_connector(dev, 2,
		1701	ATOM_DEVICE_TV1_SUPPORT,
		1702	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1703	&ddc_i2c,
1321	serge	1704	CONNECTOR_OBJECT_ID_SVIDEO,
		1705	&hpd);
1123	serge	1706	}
		1707	break;
		1708	case CT_IBOOK:
		1709	DRM_INFO("Connector Table: %d (ibook)\n",
		1710	rdev->mode_info.connector_table);
		1711	/* LVDS */
1963	serge	1712	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1713	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1714	radeon_add_legacy_encoder(dev,
1963	serge	1715	radeon_get_encoder_enum(dev,
1123	serge	1716	ATOM_DEVICE_LCD1_SUPPORT,
		1717	0),
		1718	ATOM_DEVICE_LCD1_SUPPORT);
		1719	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1720	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1721	CONNECTOR_OBJECT_ID_LVDS,
		1722	&hpd);
1123	serge	1723	/* VGA - TV DAC */
1963	serge	1724	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1725	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1726	radeon_add_legacy_encoder(dev,
1963	serge	1727	radeon_get_encoder_enum(dev,
1123	serge	1728	ATOM_DEVICE_CRT2_SUPPORT,
		1729	2),
		1730	ATOM_DEVICE_CRT2_SUPPORT);
		1731	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1732	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1733	CONNECTOR_OBJECT_ID_VGA,
		1734	&hpd);
1123	serge	1735	/* TV - TV DAC */
1321	serge	1736	ddc_i2c.valid = false;
		1737	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1738	radeon_add_legacy_encoder(dev,
1963	serge	1739	radeon_get_encoder_enum(dev,
1123	serge	1740	ATOM_DEVICE_TV1_SUPPORT,
		1741	2),
		1742	ATOM_DEVICE_TV1_SUPPORT);
		1743	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1744	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1745	&ddc_i2c,
1321	serge	1746	CONNECTOR_OBJECT_ID_SVIDEO,
		1747	&hpd);
1123	serge	1748	break;
		1749	case CT_POWERBOOK_EXTERNAL:
		1750	DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
		1751	rdev->mode_info.connector_table);
		1752	/* LVDS */
1963	serge	1753	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1754	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1755	radeon_add_legacy_encoder(dev,
1963	serge	1756	radeon_get_encoder_enum(dev,
1123	serge	1757	ATOM_DEVICE_LCD1_SUPPORT,
		1758	0),
		1759	ATOM_DEVICE_LCD1_SUPPORT);
		1760	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1761	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1762	CONNECTOR_OBJECT_ID_LVDS,
		1763	&hpd);
1123	serge	1764	/* DVI-I - primary dac, ext tmds */
1963	serge	1765	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1766	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1767	radeon_add_legacy_encoder(dev,
1963	serge	1768	radeon_get_encoder_enum(dev,
1123	serge	1769	ATOM_DEVICE_DFP2_SUPPORT,
		1770	0),
		1771	ATOM_DEVICE_DFP2_SUPPORT);
		1772	radeon_add_legacy_encoder(dev,
1963	serge	1773	radeon_get_encoder_enum(dev,
1123	serge	1774	ATOM_DEVICE_CRT1_SUPPORT,
		1775	1),
		1776	ATOM_DEVICE_CRT1_SUPPORT);
1268	serge	1777	/* XXX some are SL */
1123	serge	1778	radeon_add_legacy_connector(dev, 1,
		1779	ATOM_DEVICE_DFP2_SUPPORT \|
		1780	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1781	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1782	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		1783	&hpd);
1123	serge	1784	/* TV - TV DAC */
1321	serge	1785	ddc_i2c.valid = false;
		1786	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1787	radeon_add_legacy_encoder(dev,
1963	serge	1788	radeon_get_encoder_enum(dev,
1123	serge	1789	ATOM_DEVICE_TV1_SUPPORT,
		1790	2),
		1791	ATOM_DEVICE_TV1_SUPPORT);
		1792	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1793	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1794	&ddc_i2c,
1321	serge	1795	CONNECTOR_OBJECT_ID_SVIDEO,
		1796	&hpd);
1123	serge	1797	break;
		1798	case CT_POWERBOOK_INTERNAL:
		1799	DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
		1800	rdev->mode_info.connector_table);
		1801	/* LVDS */
1963	serge	1802	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1803	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1804	radeon_add_legacy_encoder(dev,
1963	serge	1805	radeon_get_encoder_enum(dev,
1123	serge	1806	ATOM_DEVICE_LCD1_SUPPORT,
		1807	0),
		1808	ATOM_DEVICE_LCD1_SUPPORT);
		1809	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1810	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1811	CONNECTOR_OBJECT_ID_LVDS,
		1812	&hpd);
1123	serge	1813	/* DVI-I - primary dac, int tmds */
1963	serge	1814	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1815	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1816	radeon_add_legacy_encoder(dev,
1963	serge	1817	radeon_get_encoder_enum(dev,
1123	serge	1818	ATOM_DEVICE_DFP1_SUPPORT,
		1819	0),
		1820	ATOM_DEVICE_DFP1_SUPPORT);
		1821	radeon_add_legacy_encoder(dev,
1963	serge	1822	radeon_get_encoder_enum(dev,
1123	serge	1823	ATOM_DEVICE_CRT1_SUPPORT,
		1824	1),
		1825	ATOM_DEVICE_CRT1_SUPPORT);
		1826	radeon_add_legacy_connector(dev, 1,
		1827	ATOM_DEVICE_DFP1_SUPPORT \|
		1828	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1829	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1830	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1831	&hpd);
1123	serge	1832	/* TV - TV DAC */
1321	serge	1833	ddc_i2c.valid = false;
		1834	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1835	radeon_add_legacy_encoder(dev,
1963	serge	1836	radeon_get_encoder_enum(dev,
1123	serge	1837	ATOM_DEVICE_TV1_SUPPORT,
		1838	2),
		1839	ATOM_DEVICE_TV1_SUPPORT);
		1840	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1841	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1842	&ddc_i2c,
1321	serge	1843	CONNECTOR_OBJECT_ID_SVIDEO,
		1844	&hpd);
1123	serge	1845	break;
		1846	case CT_POWERBOOK_VGA:
		1847	DRM_INFO("Connector Table: %d (powerbook vga)\n",
		1848	rdev->mode_info.connector_table);
		1849	/* LVDS */
1963	serge	1850	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1851	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1852	radeon_add_legacy_encoder(dev,
1963	serge	1853	radeon_get_encoder_enum(dev,
1123	serge	1854	ATOM_DEVICE_LCD1_SUPPORT,
		1855	0),
		1856	ATOM_DEVICE_LCD1_SUPPORT);
		1857	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1858	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1859	CONNECTOR_OBJECT_ID_LVDS,
		1860	&hpd);
1123	serge	1861	/* VGA - primary dac */
1963	serge	1862	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1863	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1864	radeon_add_legacy_encoder(dev,
1963	serge	1865	radeon_get_encoder_enum(dev,
1123	serge	1866	ATOM_DEVICE_CRT1_SUPPORT,
		1867	1),
		1868	ATOM_DEVICE_CRT1_SUPPORT);
		1869	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1870	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1871	CONNECTOR_OBJECT_ID_VGA,
		1872	&hpd);
1123	serge	1873	/* TV - TV DAC */
1321	serge	1874	ddc_i2c.valid = false;
		1875	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1876	radeon_add_legacy_encoder(dev,
1963	serge	1877	radeon_get_encoder_enum(dev,
1123	serge	1878	ATOM_DEVICE_TV1_SUPPORT,
		1879	2),
		1880	ATOM_DEVICE_TV1_SUPPORT);
		1881	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1882	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1883	&ddc_i2c,
1321	serge	1884	CONNECTOR_OBJECT_ID_SVIDEO,
		1885	&hpd);
1123	serge	1886	break;
		1887	case CT_MINI_EXTERNAL:
		1888	DRM_INFO("Connector Table: %d (mini external tmds)\n",
		1889	rdev->mode_info.connector_table);
		1890	/* DVI-I - tv dac, ext tmds */
1963	serge	1891	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1892	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1893	radeon_add_legacy_encoder(dev,
1963	serge	1894	radeon_get_encoder_enum(dev,
1123	serge	1895	ATOM_DEVICE_DFP2_SUPPORT,
		1896	0),
		1897	ATOM_DEVICE_DFP2_SUPPORT);
		1898	radeon_add_legacy_encoder(dev,
1963	serge	1899	radeon_get_encoder_enum(dev,
1123	serge	1900	ATOM_DEVICE_CRT2_SUPPORT,
		1901	2),
		1902	ATOM_DEVICE_CRT2_SUPPORT);
1268	serge	1903	/* XXX are any DL? */
1123	serge	1904	radeon_add_legacy_connector(dev, 0,
		1905	ATOM_DEVICE_DFP2_SUPPORT \|
		1906	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1907	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1908	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1909	&hpd);
1123	serge	1910	/* TV - TV DAC */
1321	serge	1911	ddc_i2c.valid = false;
		1912	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1913	radeon_add_legacy_encoder(dev,
1963	serge	1914	radeon_get_encoder_enum(dev,
1123	serge	1915	ATOM_DEVICE_TV1_SUPPORT,
		1916	2),
		1917	ATOM_DEVICE_TV1_SUPPORT);
		1918	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1919	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1920	&ddc_i2c,
1321	serge	1921	CONNECTOR_OBJECT_ID_SVIDEO,
		1922	&hpd);
1123	serge	1923	break;
		1924	case CT_MINI_INTERNAL:
		1925	DRM_INFO("Connector Table: %d (mini internal tmds)\n",
		1926	rdev->mode_info.connector_table);
		1927	/* DVI-I - tv dac, int tmds */
1963	serge	1928	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1929	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1930	radeon_add_legacy_encoder(dev,
1963	serge	1931	radeon_get_encoder_enum(dev,
1123	serge	1932	ATOM_DEVICE_DFP1_SUPPORT,
		1933	0),
		1934	ATOM_DEVICE_DFP1_SUPPORT);
		1935	radeon_add_legacy_encoder(dev,
1963	serge	1936	radeon_get_encoder_enum(dev,
1123	serge	1937	ATOM_DEVICE_CRT2_SUPPORT,
		1938	2),
		1939	ATOM_DEVICE_CRT2_SUPPORT);
		1940	radeon_add_legacy_connector(dev, 0,
		1941	ATOM_DEVICE_DFP1_SUPPORT \|
		1942	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1943	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1944	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1945	&hpd);
1123	serge	1946	/* TV - TV DAC */
1321	serge	1947	ddc_i2c.valid = false;
		1948	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1949	radeon_add_legacy_encoder(dev,
1963	serge	1950	radeon_get_encoder_enum(dev,
1123	serge	1951	ATOM_DEVICE_TV1_SUPPORT,
		1952	2),
		1953	ATOM_DEVICE_TV1_SUPPORT);
		1954	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1955	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1956	&ddc_i2c,
1321	serge	1957	CONNECTOR_OBJECT_ID_SVIDEO,
		1958	&hpd);
1123	serge	1959	break;
		1960	case CT_IMAC_G5_ISIGHT:
		1961	DRM_INFO("Connector Table: %d (imac g5 isight)\n",
		1962	rdev->mode_info.connector_table);
		1963	/* DVI-D - int tmds */
1963	serge	1964	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1321	serge	1965	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1966	radeon_add_legacy_encoder(dev,
1963	serge	1967	radeon_get_encoder_enum(dev,
1123	serge	1968	ATOM_DEVICE_DFP1_SUPPORT,
		1969	0),
		1970	ATOM_DEVICE_DFP1_SUPPORT);
		1971	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1268	serge	1972	DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1321	serge	1973	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		1974	&hpd);
1123	serge	1975	/* VGA - tv dac */
1963	serge	1976	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1977	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1978	radeon_add_legacy_encoder(dev,
1963	serge	1979	radeon_get_encoder_enum(dev,
1123	serge	1980	ATOM_DEVICE_CRT2_SUPPORT,
		1981	2),
		1982	ATOM_DEVICE_CRT2_SUPPORT);
		1983	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1984	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1985	CONNECTOR_OBJECT_ID_VGA,
		1986	&hpd);
1123	serge	1987	/* TV - TV DAC */
1321	serge	1988	ddc_i2c.valid = false;
		1989	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1990	radeon_add_legacy_encoder(dev,
1963	serge	1991	radeon_get_encoder_enum(dev,
1123	serge	1992	ATOM_DEVICE_TV1_SUPPORT,
		1993	2),
		1994	ATOM_DEVICE_TV1_SUPPORT);
		1995	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1996	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1997	&ddc_i2c,
1321	serge	1998	CONNECTOR_OBJECT_ID_SVIDEO,
		1999	&hpd);
1123	serge	2000	break;
		2001	case CT_EMAC:
		2002	DRM_INFO("Connector Table: %d (emac)\n",
		2003	rdev->mode_info.connector_table);
		2004	/* VGA - primary dac */
1963	serge	2005	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	2006	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2007	radeon_add_legacy_encoder(dev,
1963	serge	2008	radeon_get_encoder_enum(dev,
1123	serge	2009	ATOM_DEVICE_CRT1_SUPPORT,
		2010	1),
		2011	ATOM_DEVICE_CRT1_SUPPORT);
		2012	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	2013	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	2014	CONNECTOR_OBJECT_ID_VGA,
		2015	&hpd);
1123	serge	2016	/* VGA - tv dac */
1963	serge	2017	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	2018	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2019	radeon_add_legacy_encoder(dev,
1963	serge	2020	radeon_get_encoder_enum(dev,
1123	serge	2021	ATOM_DEVICE_CRT2_SUPPORT,
		2022	2),
		2023	ATOM_DEVICE_CRT2_SUPPORT);
		2024	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	2025	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	2026	CONNECTOR_OBJECT_ID_VGA,
		2027	&hpd);
1123	serge	2028	/* TV - TV DAC */
1321	serge	2029	ddc_i2c.valid = false;
		2030	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2031	radeon_add_legacy_encoder(dev,
1963	serge	2032	radeon_get_encoder_enum(dev,
1123	serge	2033	ATOM_DEVICE_TV1_SUPPORT,
		2034	2),
		2035	ATOM_DEVICE_TV1_SUPPORT);
		2036	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2037	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2038	&ddc_i2c,
1321	serge	2039	CONNECTOR_OBJECT_ID_SVIDEO,
		2040	&hpd);
1123	serge	2041	break;
1963	serge	2042	case CT_RN50_POWER:
		2043	DRM_INFO("Connector Table: %d (rn50-power)\n",
		2044	rdev->mode_info.connector_table);
		2045	/* VGA - primary dac */
		2046	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2047	hpd.hpd = RADEON_HPD_NONE;
		2048	radeon_add_legacy_encoder(dev,
		2049	radeon_get_encoder_enum(dev,
		2050	ATOM_DEVICE_CRT1_SUPPORT,
		2051	1),
		2052	ATOM_DEVICE_CRT1_SUPPORT);
		2053	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
		2054	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2055	CONNECTOR_OBJECT_ID_VGA,
		2056	&hpd);
		2057	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		2058	hpd.hpd = RADEON_HPD_NONE;
		2059	radeon_add_legacy_encoder(dev,
		2060	radeon_get_encoder_enum(dev,
		2061	ATOM_DEVICE_CRT2_SUPPORT,
		2062	2),
		2063	ATOM_DEVICE_CRT2_SUPPORT);
		2064	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		2065	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2066	CONNECTOR_OBJECT_ID_VGA,
		2067	&hpd);
		2068	break;
		2069	case CT_MAC_X800:
		2070	DRM_INFO("Connector Table: %d (mac x800)\n",
		2071	rdev->mode_info.connector_table);
		2072	/* DVI - primary dac, internal tmds */
		2073	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2074	hpd.hpd = RADEON_HPD_1; /* ??? */
		2075	radeon_add_legacy_encoder(dev,
		2076	radeon_get_encoder_enum(dev,
		2077	ATOM_DEVICE_DFP1_SUPPORT,
		2078	0),
		2079	ATOM_DEVICE_DFP1_SUPPORT);
		2080	radeon_add_legacy_encoder(dev,
		2081	radeon_get_encoder_enum(dev,
		2082	ATOM_DEVICE_CRT1_SUPPORT,
		2083	1),
		2084	ATOM_DEVICE_CRT1_SUPPORT);
		2085	radeon_add_legacy_connector(dev, 0,
		2086	ATOM_DEVICE_DFP1_SUPPORT \|
		2087	ATOM_DEVICE_CRT1_SUPPORT,
		2088	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2089	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2090	&hpd);
		2091	/* DVI - tv dac, dvo */
		2092	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		2093	hpd.hpd = RADEON_HPD_2; /* ??? */
		2094	radeon_add_legacy_encoder(dev,
		2095	radeon_get_encoder_enum(dev,
		2096	ATOM_DEVICE_DFP2_SUPPORT,
		2097	0),
		2098	ATOM_DEVICE_DFP2_SUPPORT);
		2099	radeon_add_legacy_encoder(dev,
		2100	radeon_get_encoder_enum(dev,
		2101	ATOM_DEVICE_CRT2_SUPPORT,
		2102	2),
		2103	ATOM_DEVICE_CRT2_SUPPORT);
		2104	radeon_add_legacy_connector(dev, 1,
		2105	ATOM_DEVICE_DFP2_SUPPORT \|
		2106	ATOM_DEVICE_CRT2_SUPPORT,
		2107	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2108	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		2109	&hpd);
		2110	break;
		2111	case CT_MAC_G5_9600:
		2112	DRM_INFO("Connector Table: %d (mac g5 9600)\n",
		2113	rdev->mode_info.connector_table);
		2114	/* DVI - tv dac, dvo */
		2115	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2116	hpd.hpd = RADEON_HPD_1; /* ??? */
		2117	radeon_add_legacy_encoder(dev,
		2118	radeon_get_encoder_enum(dev,
		2119	ATOM_DEVICE_DFP2_SUPPORT,
		2120	0),
		2121	ATOM_DEVICE_DFP2_SUPPORT);
		2122	radeon_add_legacy_encoder(dev,
		2123	radeon_get_encoder_enum(dev,
		2124	ATOM_DEVICE_CRT2_SUPPORT,
		2125	2),
		2126	ATOM_DEVICE_CRT2_SUPPORT);
		2127	radeon_add_legacy_connector(dev, 0,
		2128	ATOM_DEVICE_DFP2_SUPPORT \|
		2129	ATOM_DEVICE_CRT2_SUPPORT,
		2130	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2131	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2132	&hpd);
		2133	/* ADC - primary dac, internal tmds */
		2134	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2135	hpd.hpd = RADEON_HPD_2; /* ??? */
		2136	radeon_add_legacy_encoder(dev,
		2137	radeon_get_encoder_enum(dev,
		2138	ATOM_DEVICE_DFP1_SUPPORT,
		2139	0),
		2140	ATOM_DEVICE_DFP1_SUPPORT);
		2141	radeon_add_legacy_encoder(dev,
		2142	radeon_get_encoder_enum(dev,
		2143	ATOM_DEVICE_CRT1_SUPPORT,
		2144	1),
		2145	ATOM_DEVICE_CRT1_SUPPORT);
		2146	radeon_add_legacy_connector(dev, 1,
		2147	ATOM_DEVICE_DFP1_SUPPORT \|
		2148	ATOM_DEVICE_CRT1_SUPPORT,
		2149	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2150	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2151	&hpd);
		2152	/* TV - TV DAC */
		2153	ddc_i2c.valid = false;
		2154	hpd.hpd = RADEON_HPD_NONE;
		2155	radeon_add_legacy_encoder(dev,
		2156	radeon_get_encoder_enum(dev,
		2157	ATOM_DEVICE_TV1_SUPPORT,
		2158	2),
		2159	ATOM_DEVICE_TV1_SUPPORT);
		2160	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2161	DRM_MODE_CONNECTOR_SVIDEO,
		2162	&ddc_i2c,
		2163	CONNECTOR_OBJECT_ID_SVIDEO,
		2164	&hpd);
		2165	break;
2997	Serge	2166	case CT_SAM440EP:
		2167	DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
		2168	rdev->mode_info.connector_table);
		2169	/* LVDS */
		2170	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
		2171	hpd.hpd = RADEON_HPD_NONE;
		2172	radeon_add_legacy_encoder(dev,
		2173	radeon_get_encoder_enum(dev,
		2174	ATOM_DEVICE_LCD1_SUPPORT,
		2175	0),
		2176	ATOM_DEVICE_LCD1_SUPPORT);
		2177	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		2178	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
		2179	CONNECTOR_OBJECT_ID_LVDS,
		2180	&hpd);
		2181	/* DVI-I - secondary dac, int tmds */
		2182	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2183	hpd.hpd = RADEON_HPD_1; /* ??? */
		2184	radeon_add_legacy_encoder(dev,
		2185	radeon_get_encoder_enum(dev,
		2186	ATOM_DEVICE_DFP1_SUPPORT,
		2187	0),
		2188	ATOM_DEVICE_DFP1_SUPPORT);
		2189	radeon_add_legacy_encoder(dev,
		2190	radeon_get_encoder_enum(dev,
		2191	ATOM_DEVICE_CRT2_SUPPORT,
		2192	2),
		2193	ATOM_DEVICE_CRT2_SUPPORT);
		2194	radeon_add_legacy_connector(dev, 1,
		2195	ATOM_DEVICE_DFP1_SUPPORT \|
		2196	ATOM_DEVICE_CRT2_SUPPORT,
		2197	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2198	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2199	&hpd);
		2200	/* VGA - primary dac */
		2201	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2202	hpd.hpd = RADEON_HPD_NONE;
		2203	radeon_add_legacy_encoder(dev,
		2204	radeon_get_encoder_enum(dev,
		2205	ATOM_DEVICE_CRT1_SUPPORT,
		2206	1),
		2207	ATOM_DEVICE_CRT1_SUPPORT);
		2208	radeon_add_legacy_connector(dev, 2,
		2209	ATOM_DEVICE_CRT1_SUPPORT,
		2210	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2211	CONNECTOR_OBJECT_ID_VGA,
		2212	&hpd);
		2213	/* TV - TV DAC */
		2214	ddc_i2c.valid = false;
		2215	hpd.hpd = RADEON_HPD_NONE;
		2216	radeon_add_legacy_encoder(dev,
		2217	radeon_get_encoder_enum(dev,
		2218	ATOM_DEVICE_TV1_SUPPORT,
		2219	2),
		2220	ATOM_DEVICE_TV1_SUPPORT);
		2221	radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
		2222	DRM_MODE_CONNECTOR_SVIDEO,
		2223	&ddc_i2c,
		2224	CONNECTOR_OBJECT_ID_SVIDEO,
		2225	&hpd);
		2226	break;
3192	Serge	2227	case CT_MAC_G4_SILVER:
		2228	DRM_INFO("Connector Table: %d (mac g4 silver)\n",
		2229	rdev->mode_info.connector_table);
		2230	/* DVI-I - tv dac, int tmds */
		2231	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2232	hpd.hpd = RADEON_HPD_1; /* ??? */
		2233	radeon_add_legacy_encoder(dev,
		2234	radeon_get_encoder_enum(dev,
		2235	ATOM_DEVICE_DFP1_SUPPORT,
		2236	0),
		2237	ATOM_DEVICE_DFP1_SUPPORT);
		2238	radeon_add_legacy_encoder(dev,
		2239	radeon_get_encoder_enum(dev,
		2240	ATOM_DEVICE_CRT2_SUPPORT,
		2241	2),
		2242	ATOM_DEVICE_CRT2_SUPPORT);
		2243	radeon_add_legacy_connector(dev, 0,
		2244	ATOM_DEVICE_DFP1_SUPPORT \|
		2245	ATOM_DEVICE_CRT2_SUPPORT,
		2246	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2247	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2248	&hpd);
		2249	/* VGA - primary dac */
		2250	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2251	hpd.hpd = RADEON_HPD_NONE;
		2252	radeon_add_legacy_encoder(dev,
		2253	radeon_get_encoder_enum(dev,
		2254	ATOM_DEVICE_CRT1_SUPPORT,
		2255	1),
		2256	ATOM_DEVICE_CRT1_SUPPORT);
		2257	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
		2258	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2259	CONNECTOR_OBJECT_ID_VGA,
		2260	&hpd);
		2261	/* TV - TV DAC */
		2262	ddc_i2c.valid = false;
		2263	hpd.hpd = RADEON_HPD_NONE;
		2264	radeon_add_legacy_encoder(dev,
		2265	radeon_get_encoder_enum(dev,
		2266	ATOM_DEVICE_TV1_SUPPORT,
		2267	2),
		2268	ATOM_DEVICE_TV1_SUPPORT);
		2269	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2270	DRM_MODE_CONNECTOR_SVIDEO,
		2271	&ddc_i2c,
		2272	CONNECTOR_OBJECT_ID_SVIDEO,
		2273	&hpd);
		2274	break;
1123	serge	2275	default:
		2276	DRM_INFO("Connector table: %d (invalid)\n",
		2277	rdev->mode_info.connector_table);
		2278	return false;
		2279	}
		2280
		2281	radeon_link_encoder_connector(dev);
		2282
		2283	return true;
		2284	}
		2285
		2286	static bool radeon_apply_legacy_quirks(struct drm_device *dev,
		2287	int bios_index,
		2288	enum radeon_combios_connector
		2289	*legacy_connector,
1321	serge	2290	struct radeon_i2c_bus_rec *ddc_i2c,
		2291	struct radeon_hpd *hpd)
1123	serge	2292	{
		2293
		2294	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
		2295	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
		2296	if (dev->pdev->device == 0x515e &&
		2297	dev->pdev->subsystem_vendor == 0x1014) {
		2298	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
		2299	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		2300	return false;
		2301	}
		2302
		2303	/* X300 card with extra non-existent DVI port */
		2304	if (dev->pdev->device == 0x5B60 &&
		2305	dev->pdev->subsystem_vendor == 0x17af &&
		2306	dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
		2307	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		2308	return false;
		2309	}
		2310
		2311	return true;
		2312	}
		2313
1268	serge	2314	static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
		2315	{
		2316	/* Acer 5102 has non-existent TV port */
		2317	if (dev->pdev->device == 0x5975 &&
		2318	dev->pdev->subsystem_vendor == 0x1025 &&
		2319	dev->pdev->subsystem_device == 0x009f)
		2320	return false;
		2321
		2322	/* HP dc5750 has non-existent TV port */
		2323	if (dev->pdev->device == 0x5974 &&
		2324	dev->pdev->subsystem_vendor == 0x103c &&
		2325	dev->pdev->subsystem_device == 0x280a)
		2326	return false;
		2327
1321	serge	2328	/* MSI S270 has non-existent TV port */
		2329	if (dev->pdev->device == 0x5955 &&
		2330	dev->pdev->subsystem_vendor == 0x1462 &&
		2331	dev->pdev->subsystem_device == 0x0131)
		2332	return false;
		2333
1268	serge	2334	return true;
		2335	}
		2336
		2337	static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
		2338	{
		2339	struct radeon_device *rdev = dev->dev_private;
		2340	uint32_t ext_tmds_info;
		2341
		2342	if (rdev->flags & RADEON_IS_IGP) {
		2343	if (is_dvi_d)
		2344	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2345	else
		2346	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2347	}
		2348	ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		2349	if (ext_tmds_info) {
		2350	uint8_t rev = RBIOS8(ext_tmds_info);
		2351	uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
		2352	if (rev >= 3) {
		2353	if (is_dvi_d)
		2354	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2355	else
		2356	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2357	} else {
		2358	if (flags & 1) {
		2359	if (is_dvi_d)
		2360	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2361	else
		2362	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2363	}
		2364	}
		2365	}
		2366	if (is_dvi_d)
		2367	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2368	else
		2369	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2370	}
		2371
1123	serge	2372	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
		2373	{
		2374	struct radeon_device *rdev = dev->dev_private;
		2375	uint32_t conn_info, entry, devices;
1268	serge	2376	uint16_t tmp, connector_object_id;
1123	serge	2377	enum radeon_combios_ddc ddc_type;
		2378	enum radeon_combios_connector connector;
		2379	int i = 0;
		2380	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	2381	struct radeon_hpd hpd;
1123	serge	2382
		2383	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
		2384	if (conn_info) {
		2385	for (i = 0; i < 4; i++) {
		2386	entry = conn_info + 2 + i * 2;
		2387
		2388	if (!RBIOS16(entry))
		2389	break;
		2390
		2391	tmp = RBIOS16(entry);
		2392
		2393	connector = (tmp >> 12) & 0xf;
		2394
		2395	ddc_type = (tmp >> 8) & 0xf;
2997	Serge	2396	if (ddc_type == 5)
		2397	ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
		2398	else
1963	serge	2399	ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2400
1321	serge	2401	switch (connector) {
		2402	case CONNECTOR_PROPRIETARY_LEGACY:
		2403	case CONNECTOR_DVI_I_LEGACY:
		2404	case CONNECTOR_DVI_D_LEGACY:
		2405	if ((tmp >> 4) & 0x1)
		2406	hpd.hpd = RADEON_HPD_2;
		2407	else
		2408	hpd.hpd = RADEON_HPD_1;
		2409	break;
		2410	default:
		2411	hpd.hpd = RADEON_HPD_NONE;
		2412	break;
		2413	}
		2414
1268	serge	2415	if (!radeon_apply_legacy_quirks(dev, i, &connector,
1321	serge	2416	&ddc_i2c, &hpd))
1268	serge	2417	continue;
1123	serge	2418
		2419	switch (connector) {
		2420	case CONNECTOR_PROPRIETARY_LEGACY:
		2421	if ((tmp >> 4) & 0x1)
		2422	devices = ATOM_DEVICE_DFP2_SUPPORT;
		2423	else
		2424	devices = ATOM_DEVICE_DFP1_SUPPORT;
		2425	radeon_add_legacy_encoder(dev,
1963	serge	2426	radeon_get_encoder_enum
1123	serge	2427	(dev, devices, 0),
		2428	devices);
		2429	radeon_add_legacy_connector(dev, i, devices,
		2430	legacy_connector_convert
		2431	[connector],
1268	serge	2432	&ddc_i2c,
1321	serge	2433	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		2434	&hpd);
1123	serge	2435	break;
		2436	case CONNECTOR_CRT_LEGACY:
		2437	if (tmp & 0x1) {
		2438	devices = ATOM_DEVICE_CRT2_SUPPORT;
		2439	radeon_add_legacy_encoder(dev,
1963	serge	2440	radeon_get_encoder_enum
1123	serge	2441	(dev,
		2442	ATOM_DEVICE_CRT2_SUPPORT,
		2443	2),
		2444	ATOM_DEVICE_CRT2_SUPPORT);
		2445	} else {
		2446	devices = ATOM_DEVICE_CRT1_SUPPORT;
		2447	radeon_add_legacy_encoder(dev,
1963	serge	2448	radeon_get_encoder_enum
1123	serge	2449	(dev,
		2450	ATOM_DEVICE_CRT1_SUPPORT,
		2451	1),
		2452	ATOM_DEVICE_CRT1_SUPPORT);
		2453	}
		2454	radeon_add_legacy_connector(dev,
		2455	i,
		2456	devices,
		2457	legacy_connector_convert
		2458	[connector],
1268	serge	2459	&ddc_i2c,
1321	serge	2460	CONNECTOR_OBJECT_ID_VGA,
		2461	&hpd);
1123	serge	2462	break;
		2463	case CONNECTOR_DVI_I_LEGACY:
		2464	devices = 0;
		2465	if (tmp & 0x1) {
		2466	devices \|= ATOM_DEVICE_CRT2_SUPPORT;
		2467	radeon_add_legacy_encoder(dev,
1963	serge	2468	radeon_get_encoder_enum
1123	serge	2469	(dev,
		2470	ATOM_DEVICE_CRT2_SUPPORT,
		2471	2),
		2472	ATOM_DEVICE_CRT2_SUPPORT);
		2473	} else {
		2474	devices \|= ATOM_DEVICE_CRT1_SUPPORT;
		2475	radeon_add_legacy_encoder(dev,
1963	serge	2476	radeon_get_encoder_enum
1123	serge	2477	(dev,
		2478	ATOM_DEVICE_CRT1_SUPPORT,
		2479	1),
		2480	ATOM_DEVICE_CRT1_SUPPORT);
		2481	}
3764	Serge	2482	/* RV100 board with external TDMS bit mis-set.
		2483	* Actually uses internal TMDS, clear the bit.
		2484	*/
		2485	if (dev->pdev->device == 0x5159 &&
		2486	dev->pdev->subsystem_vendor == 0x1014 &&
		2487	dev->pdev->subsystem_device == 0x029A) {
		2488	tmp &= ~(1 << 4);
		2489	}
1123	serge	2490	if ((tmp >> 4) & 0x1) {
		2491	devices \|= ATOM_DEVICE_DFP2_SUPPORT;
		2492	radeon_add_legacy_encoder(dev,
1963	serge	2493	radeon_get_encoder_enum
1123	serge	2494	(dev,
		2495	ATOM_DEVICE_DFP2_SUPPORT,
		2496	0),
		2497	ATOM_DEVICE_DFP2_SUPPORT);
1268	serge	2498	connector_object_id = combios_check_dl_dvi(dev, 0);
1123	serge	2499	} else {
		2500	devices \|= ATOM_DEVICE_DFP1_SUPPORT;
		2501	radeon_add_legacy_encoder(dev,
1963	serge	2502	radeon_get_encoder_enum
1123	serge	2503	(dev,
		2504	ATOM_DEVICE_DFP1_SUPPORT,
		2505	0),
		2506	ATOM_DEVICE_DFP1_SUPPORT);
1268	serge	2507	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1123	serge	2508	}
		2509	radeon_add_legacy_connector(dev,
		2510	i,
		2511	devices,
		2512	legacy_connector_convert
		2513	[connector],
1268	serge	2514	&ddc_i2c,
1321	serge	2515	connector_object_id,
		2516	&hpd);
1123	serge	2517	break;
		2518	case CONNECTOR_DVI_D_LEGACY:
1268	serge	2519	if ((tmp >> 4) & 0x1) {
1123	serge	2520	devices = ATOM_DEVICE_DFP2_SUPPORT;
1268	serge	2521	connector_object_id = combios_check_dl_dvi(dev, 1);
		2522	} else {
1123	serge	2523	devices = ATOM_DEVICE_DFP1_SUPPORT;
1268	serge	2524	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2525	}
1123	serge	2526	radeon_add_legacy_encoder(dev,
1963	serge	2527	radeon_get_encoder_enum
1123	serge	2528	(dev, devices, 0),
		2529	devices);
		2530	radeon_add_legacy_connector(dev, i, devices,
		2531	legacy_connector_convert
		2532	[connector],
1268	serge	2533	&ddc_i2c,
1321	serge	2534	connector_object_id,
		2535	&hpd);
1123	serge	2536	break;
		2537	case CONNECTOR_CTV_LEGACY:
		2538	case CONNECTOR_STV_LEGACY:
		2539	radeon_add_legacy_encoder(dev,
1963	serge	2540	radeon_get_encoder_enum
1123	serge	2541	(dev,
		2542	ATOM_DEVICE_TV1_SUPPORT,
		2543	2),
		2544	ATOM_DEVICE_TV1_SUPPORT);
		2545	radeon_add_legacy_connector(dev, i,
		2546	ATOM_DEVICE_TV1_SUPPORT,
		2547	legacy_connector_convert
		2548	[connector],
1268	serge	2549	&ddc_i2c,
1321	serge	2550	CONNECTOR_OBJECT_ID_SVIDEO,
		2551	&hpd);
1123	serge	2552	break;
		2553	default:
		2554	DRM_ERROR("Unknown connector type: %d\n",
		2555	connector);
		2556	continue;
		2557	}
		2558
		2559	}
		2560	} else {
		2561	uint16_t tmds_info =
		2562	combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		2563	if (tmds_info) {
1963	serge	2564	DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
1123	serge	2565
		2566	radeon_add_legacy_encoder(dev,
1963	serge	2567	radeon_get_encoder_enum(dev,
1123	serge	2568	ATOM_DEVICE_CRT1_SUPPORT,
		2569	1),
		2570	ATOM_DEVICE_CRT1_SUPPORT);
		2571	radeon_add_legacy_encoder(dev,
1963	serge	2572	radeon_get_encoder_enum(dev,
1123	serge	2573	ATOM_DEVICE_DFP1_SUPPORT,
		2574	0),
		2575	ATOM_DEVICE_DFP1_SUPPORT);
		2576
1963	serge	2577	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2578	hpd.hpd = RADEON_HPD_1;
1123	serge	2579	radeon_add_legacy_connector(dev,
		2580	0,
		2581	ATOM_DEVICE_CRT1_SUPPORT \|
		2582	ATOM_DEVICE_DFP1_SUPPORT,
		2583	DRM_MODE_CONNECTOR_DVII,
1268	serge	2584	&ddc_i2c,
1321	serge	2585	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2586	&hpd);
1123	serge	2587	} else {
1268	serge	2588	uint16_t crt_info =
		2589	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1963	serge	2590	DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
1268	serge	2591	if (crt_info) {
		2592	radeon_add_legacy_encoder(dev,
1963	serge	2593	radeon_get_encoder_enum(dev,
1268	serge	2594	ATOM_DEVICE_CRT1_SUPPORT,
		2595	1),
		2596	ATOM_DEVICE_CRT1_SUPPORT);
1963	serge	2597	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	2598	hpd.hpd = RADEON_HPD_NONE;
1268	serge	2599	radeon_add_legacy_connector(dev,
		2600	0,
		2601	ATOM_DEVICE_CRT1_SUPPORT,
		2602	DRM_MODE_CONNECTOR_VGA,
		2603	&ddc_i2c,
1321	serge	2604	CONNECTOR_OBJECT_ID_VGA,
		2605	&hpd);
1268	serge	2606	} else {
1963	serge	2607	DRM_DEBUG_KMS("No connector info found\n");
1123	serge	2608	return false;
		2609	}
		2610	}
1268	serge	2611	}
1123	serge	2612
		2613	if (rdev->flags & RADEON_IS_MOBILITY \|\| rdev->flags & RADEON_IS_IGP) {
		2614	uint16_t lcd_info =
		2615	combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		2616	if (lcd_info) {
		2617	uint16_t lcd_ddc_info =
		2618	combios_get_table_offset(dev,
		2619	COMBIOS_LCD_DDC_INFO_TABLE);
		2620
		2621	radeon_add_legacy_encoder(dev,
1963	serge	2622	radeon_get_encoder_enum(dev,
1123	serge	2623	ATOM_DEVICE_LCD1_SUPPORT,
		2624	0),
		2625	ATOM_DEVICE_LCD1_SUPPORT);
		2626
		2627	if (lcd_ddc_info) {
		2628	ddc_type = RBIOS8(lcd_ddc_info + 2);
		2629	switch (ddc_type) {
		2630	case DDC_LCD:
		2631	ddc_i2c =
1963	serge	2632	combios_setup_i2c_bus(rdev,
		2633	DDC_LCD,
		2634	RBIOS32(lcd_ddc_info + 3),
		2635	RBIOS32(lcd_ddc_info + 7));
		2636	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2637	break;
		2638	case DDC_GPIO:
		2639	ddc_i2c =
1963	serge	2640	combios_setup_i2c_bus(rdev,
		2641	DDC_GPIO,
		2642	RBIOS32(lcd_ddc_info + 3),
		2643	RBIOS32(lcd_ddc_info + 7));
		2644	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2645	break;
		2646	default:
1963	serge	2647	ddc_i2c =
		2648	combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2649	break;
		2650	}
1963	serge	2651	DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
1123	serge	2652	} else
		2653	ddc_i2c.valid = false;
		2654
1321	serge	2655	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2656	radeon_add_legacy_connector(dev,
		2657	5,
		2658	ATOM_DEVICE_LCD1_SUPPORT,
		2659	DRM_MODE_CONNECTOR_LVDS,
1268	serge	2660	&ddc_i2c,
1321	serge	2661	CONNECTOR_OBJECT_ID_LVDS,
		2662	&hpd);
1123	serge	2663	}
		2664	}
		2665
		2666	/* check TV table */
		2667	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		2668	uint32_t tv_info =
		2669	combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		2670	if (tv_info) {
		2671	if (RBIOS8(tv_info + 6) == 'T') {
1268	serge	2672	if (radeon_apply_legacy_tv_quirks(dev)) {
1321	serge	2673	hpd.hpd = RADEON_HPD_NONE;
1963	serge	2674	ddc_i2c.valid = false;
1123	serge	2675	radeon_add_legacy_encoder(dev,
1963	serge	2676	radeon_get_encoder_enum
1123	serge	2677	(dev,
		2678	ATOM_DEVICE_TV1_SUPPORT,
		2679	2),
		2680	ATOM_DEVICE_TV1_SUPPORT);
		2681	radeon_add_legacy_connector(dev, 6,
		2682	ATOM_DEVICE_TV1_SUPPORT,
		2683	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2684	&ddc_i2c,
1321	serge	2685	CONNECTOR_OBJECT_ID_SVIDEO,
		2686	&hpd);
1268	serge	2687	}
1123	serge	2688	}
		2689	}
		2690	}
		2691
		2692	radeon_link_encoder_connector(dev);
		2693
		2694	return true;
		2695	}
		2696
1963	serge	2697	static const char *thermal_controller_names[] = {
		2698	"NONE",
		2699	"lm63",
		2700	"adm1032",
		2701	};
		2702
1430	serge	2703	void radeon_combios_get_power_modes(struct radeon_device *rdev)
		2704	{
		2705	struct drm_device *dev = rdev->ddev;
		2706	u16 offset, misc, misc2 = 0;
		2707	u8 rev, blocks, tmp;
		2708	int state_index = 0;
2160	serge	2709	struct radeon_i2c_bus_rec i2c_bus;
1430	serge	2710
1963	serge	2711	rdev->pm.default_power_state_index = -1;
1430	serge	2712
1963	serge	2713	/* allocate 2 power states */
		2714	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2997	Serge	2715	if (rdev->pm.power_state) {
		2716	/* allocate 1 clock mode per state */
		2717	rdev->pm.power_state[0].clock_info =
		2718	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2719	rdev->pm.power_state[1].clock_info =
		2720	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2721	if (!rdev->pm.power_state[0].clock_info \|\|
		2722	!rdev->pm.power_state[1].clock_info)
		2723	goto pm_failed;
		2724	} else
		2725	goto pm_failed;
1963	serge	2726
		2727	/* check for a thermal chip */
		2728	offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
		2729	if (offset) {
		2730	u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
		2731
		2732	rev = RBIOS8(offset);
		2733
		2734	if (rev == 0) {
		2735	thermal_controller = RBIOS8(offset + 3);
		2736	gpio = RBIOS8(offset + 4) & 0x3f;
		2737	i2c_addr = RBIOS8(offset + 5);
		2738	} else if (rev == 1) {
		2739	thermal_controller = RBIOS8(offset + 4);
		2740	gpio = RBIOS8(offset + 5) & 0x3f;
		2741	i2c_addr = RBIOS8(offset + 6);
		2742	} else if (rev == 2) {
		2743	thermal_controller = RBIOS8(offset + 4);
		2744	gpio = RBIOS8(offset + 5) & 0x3f;
		2745	i2c_addr = RBIOS8(offset + 6);
		2746	clk_bit = RBIOS8(offset + 0xa);
		2747	data_bit = RBIOS8(offset + 0xb);
		2748	}
		2749	if ((thermal_controller > 0) && (thermal_controller < 3)) {
		2750	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2751	thermal_controller_names[thermal_controller],
		2752	i2c_addr >> 1);
		2753	if (gpio == DDC_LCD) {
		2754	/* MM i2c */
		2755	i2c_bus.valid = true;
		2756	i2c_bus.hw_capable = true;
		2757	i2c_bus.mm_i2c = true;
		2758	i2c_bus.i2c_id = 0xa0;
		2759	} else if (gpio == DDC_GPIO)
		2760	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
		2761	else
		2762	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		2763	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2764	if (rdev->pm.i2c_bus) {
		2765	struct i2c_board_info info = { };
		2766	const char *name = thermal_controller_names[thermal_controller];
		2767	info.addr = i2c_addr >> 1;
		2768	strlcpy(info.type, name, sizeof(info.type));
		2769	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2770	}
		2771	}
2997	Serge	2772	} else {
		2773	/* boards with a thermal chip, but no overdrive table */
		2774
		2775	/* Asus 9600xt has an f75375 on the monid bus */
		2776	if ((dev->pdev->device == 0x4152) &&
		2777	(dev->pdev->subsystem_vendor == 0x1043) &&
		2778	(dev->pdev->subsystem_device == 0xc002)) {
		2779	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		2780	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2781	if (rdev->pm.i2c_bus) {
		2782	struct i2c_board_info info = { };
		2783	const char *name = "f75375";
		2784	info.addr = 0x28;
		2785	strlcpy(info.type, name, sizeof(info.type));
		2786	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2787	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2788	name, info.addr);
		2789	}
		2790	}
1963	serge	2791	}
		2792
1430	serge	2793	if (rdev->flags & RADEON_IS_MOBILITY) {
		2794	offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
		2795	if (offset) {
		2796	rev = RBIOS8(offset);
		2797	blocks = RBIOS8(offset + 0x2);
		2798	/* power mode 0 tends to be the only valid one */
		2799	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2800	rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
		2801	rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
		2802	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2803	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2804	goto default_mode;
		2805	rdev->pm.power_state[state_index].type =
		2806	POWER_STATE_TYPE_BATTERY;
		2807	misc = RBIOS16(offset + 0x5 + 0x0);
		2808	if (rev > 4)
		2809	misc2 = RBIOS16(offset + 0x5 + 0xe);
1963	serge	2810	rdev->pm.power_state[state_index].misc = misc;
		2811	rdev->pm.power_state[state_index].misc2 = misc2;
1430	serge	2812	if (misc & 0x4) {
		2813	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
		2814	if (misc & 0x8)
		2815	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2816	true;
		2817	else
		2818	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2819	false;
		2820	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
		2821	if (rev < 6) {
		2822	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2823	RBIOS16(offset + 0x5 + 0xb) * 4;
		2824	tmp = RBIOS8(offset + 0x5 + 0xd);
		2825	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2826	} else {
		2827	u8 entries = RBIOS8(offset + 0x5 + 0xb);
		2828	u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
		2829	if (entries && voltage_table_offset) {
		2830	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2831	RBIOS16(voltage_table_offset) * 4;
		2832	tmp = RBIOS8(voltage_table_offset + 0x2);
		2833	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2834	} else
		2835	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
		2836	}
		2837	switch ((misc2 & 0x700) >> 8) {
		2838	case 0:
		2839	default:
		2840	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
		2841	break;
		2842	case 1:
		2843	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
		2844	break;
		2845	case 2:
		2846	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
		2847	break;
		2848	case 3:
		2849	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
		2850	break;
		2851	case 4:
		2852	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
		2853	break;
		2854	}
		2855	} else
		2856	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2857	if (rev > 6)
1963	serge	2858	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2859	RBIOS8(offset + 0x5 + 0x10);
1963	serge	2860	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2861	state_index++;
		2862	} else {
		2863	/* XXX figure out some good default low power mode for mobility cards w/out power tables */
		2864	}
		2865	} else {
		2866	/* XXX figure out some good default low power mode for desktop cards */
		2867	}
		2868
		2869	default_mode:
		2870	/* add the default mode */
		2871	rdev->pm.power_state[state_index].type =
		2872	POWER_STATE_TYPE_DEFAULT;
		2873	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2874	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2875	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2876	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
1963	serge	2877	if ((state_index > 0) &&
		2878	(rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
		2879	rdev->pm.power_state[state_index].clock_info[0].voltage =
		2880	rdev->pm.power_state[0].clock_info[0].voltage;
		2881	else
1430	serge	2882	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2883	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2884	rdev->pm.power_state[state_index].flags = 0;
		2885	rdev->pm.default_power_state_index = state_index;
1430	serge	2886	rdev->pm.num_power_states = state_index + 1;
		2887
1963	serge	2888	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2889	rdev->pm.current_clock_mode_index = 0;
2997	Serge	2890	return;
		2891
		2892	pm_failed:
		2893	rdev->pm.default_power_state_index = state_index;
		2894	rdev->pm.num_power_states = 0;
		2895
		2896	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2897	rdev->pm.current_clock_mode_index = 0;
1430	serge	2898	}
		2899
1321	serge	2900	void radeon_external_tmds_setup(struct drm_encoder *encoder)
		2901	{
		2902	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2903	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2904
		2905	if (!tmds)
		2906	return;
		2907
		2908	switch (tmds->dvo_chip) {
		2909	case DVO_SIL164:
		2910	/* sil 164 */
1430	serge	2911	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2912	tmds->slave_addr,
		2913	0x08, 0x30);
1430	serge	2914	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2915	tmds->slave_addr,
		2916	0x09, 0x00);
1430	serge	2917	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2918	tmds->slave_addr,
		2919	0x0a, 0x90);
1430	serge	2920	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2921	tmds->slave_addr,
		2922	0x0c, 0x89);
1430	serge	2923	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2924	tmds->slave_addr,
		2925	0x08, 0x3b);
		2926	break;
		2927	case DVO_SIL1178:
		2928	/* sil 1178 - untested */
		2929	/*
		2930	* 0x0f, 0x44
		2931	* 0x0f, 0x4c
		2932	* 0x0e, 0x01
		2933	* 0x0a, 0x80
		2934	* 0x09, 0x30
		2935	* 0x0c, 0xc9
		2936	* 0x0d, 0x70
		2937	* 0x08, 0x32
		2938	* 0x08, 0x33
		2939	*/
		2940	break;
		2941	default:
		2942	break;
		2943	}
		2944
		2945	}
		2946
		2947	bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
		2948	{
		2949	struct drm_device *dev = encoder->dev;
		2950	struct radeon_device *rdev = dev->dev_private;
		2951	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2952	uint16_t offset;
		2953	uint8_t blocks, slave_addr, rev;
		2954	uint32_t index, id;
		2955	uint32_t reg, val, and_mask, or_mask;
		2956	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2957
		2958	if (!tmds)
		2959	return false;
		2960
		2961	if (rdev->flags & RADEON_IS_IGP) {
		2962	offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
		2963	rev = RBIOS8(offset);
		2964	if (offset) {
		2965	rev = RBIOS8(offset);
		2966	if (rev > 1) {
		2967	blocks = RBIOS8(offset + 3);
		2968	index = offset + 4;
		2969	while (blocks > 0) {
		2970	id = RBIOS16(index);
		2971	index += 2;
		2972	switch (id >> 13) {
		2973	case 0:
		2974	reg = (id & 0x1fff) * 4;
		2975	val = RBIOS32(index);
		2976	index += 4;
		2977	WREG32(reg, val);
		2978	break;
		2979	case 2:
		2980	reg = (id & 0x1fff) * 4;
		2981	and_mask = RBIOS32(index);
		2982	index += 4;
		2983	or_mask = RBIOS32(index);
		2984	index += 4;
		2985	val = RREG32(reg);
		2986	val = (val & and_mask) \| or_mask;
		2987	WREG32(reg, val);
		2988	break;
		2989	case 3:
		2990	val = RBIOS16(index);
		2991	index += 2;
		2992	udelay(val);
		2993	break;
		2994	case 4:
		2995	val = RBIOS16(index);
		2996	index += 2;
2997	Serge	2997	mdelay(val);
1321	serge	2998	break;
		2999	case 6:
		3000	slave_addr = id & 0xff;
		3001	slave_addr >>= 1; /* 7 bit addressing */
		3002	index++;
		3003	reg = RBIOS8(index);
		3004	index++;
		3005	val = RBIOS8(index);
		3006	index++;
1430	serge	3007	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	3008	slave_addr,
		3009	reg, val);
		3010	break;
		3011	default:
		3012	DRM_ERROR("Unknown id %d\n", id >> 13);
		3013	break;
		3014	}
		3015	blocks--;
		3016	}
		3017	return true;
		3018	}
		3019	}
		3020	} else {
		3021	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		3022	if (offset) {
		3023	index = offset + 10;
		3024	id = RBIOS16(index);
		3025	while (id != 0xffff) {
		3026	index += 2;
		3027	switch (id >> 13) {
		3028	case 0:
		3029	reg = (id & 0x1fff) * 4;
		3030	val = RBIOS32(index);
		3031	WREG32(reg, val);
		3032	break;
		3033	case 2:
		3034	reg = (id & 0x1fff) * 4;
		3035	and_mask = RBIOS32(index);
		3036	index += 4;
		3037	or_mask = RBIOS32(index);
		3038	index += 4;
		3039	val = RREG32(reg);
		3040	val = (val & and_mask) \| or_mask;
		3041	WREG32(reg, val);
		3042	break;
		3043	case 4:
		3044	val = RBIOS16(index);
		3045	index += 2;
		3046	udelay(val);
		3047	break;
		3048	case 5:
		3049	reg = id & 0x1fff;
		3050	and_mask = RBIOS32(index);
		3051	index += 4;
		3052	or_mask = RBIOS32(index);
		3053	index += 4;
		3054	val = RREG32_PLL(reg);
		3055	val = (val & and_mask) \| or_mask;
		3056	WREG32_PLL(reg, val);
		3057	break;
		3058	case 6:
		3059	reg = id & 0x1fff;
		3060	val = RBIOS8(index);
		3061	index += 1;
1430	serge	3062	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	3063	tmds->slave_addr,
		3064	reg, val);
		3065	break;
		3066	default:
		3067	DRM_ERROR("Unknown id %d\n", id >> 13);
		3068	break;
		3069	}
		3070	id = RBIOS16(index);
		3071	}
		3072	return true;
		3073	}
		3074	}
		3075	return false;
		3076	}
		3077
1123	serge	3078	static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
		3079	{
		3080	struct radeon_device *rdev = dev->dev_private;
		3081
		3082	if (offset) {
		3083	while (RBIOS16(offset)) {
		3084	uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
		3085	uint32_t addr = (RBIOS16(offset) & 0x1fff);
		3086	uint32_t val, and_mask, or_mask;
		3087	uint32_t tmp;
		3088
		3089	offset += 2;
		3090	switch (cmd) {
		3091	case 0:
		3092	val = RBIOS32(offset);
		3093	offset += 4;
		3094	WREG32(addr, val);
		3095	break;
		3096	case 1:
		3097	val = RBIOS32(offset);
		3098	offset += 4;
		3099	WREG32(addr, val);
		3100	break;
		3101	case 2:
		3102	and_mask = RBIOS32(offset);
		3103	offset += 4;
		3104	or_mask = RBIOS32(offset);
		3105	offset += 4;
		3106	tmp = RREG32(addr);
		3107	tmp &= and_mask;
		3108	tmp \|= or_mask;
		3109	WREG32(addr, tmp);
		3110	break;
		3111	case 3:
		3112	and_mask = RBIOS32(offset);
		3113	offset += 4;
		3114	or_mask = RBIOS32(offset);
		3115	offset += 4;
		3116	tmp = RREG32(addr);
		3117	tmp &= and_mask;
		3118	tmp \|= or_mask;
		3119	WREG32(addr, tmp);
		3120	break;
		3121	case 4:
		3122	val = RBIOS16(offset);
		3123	offset += 2;
		3124	udelay(val);
		3125	break;
		3126	case 5:
		3127	val = RBIOS16(offset);
		3128	offset += 2;
		3129	switch (addr) {
		3130	case 8:
		3131	while (val--) {
		3132	if (!
		3133	(RREG32_PLL
		3134	(RADEON_CLK_PWRMGT_CNTL) &
		3135	RADEON_MC_BUSY))
		3136	break;
		3137	}
		3138	break;
		3139	case 9:
		3140	while (val--) {
		3141	if ((RREG32(RADEON_MC_STATUS) &
		3142	RADEON_MC_IDLE))
		3143	break;
		3144	}
		3145	break;
		3146	default:
		3147	break;
		3148	}
		3149	break;
		3150	default:
		3151	break;
		3152	}
		3153	}
		3154	}
		3155	}
		3156
		3157	static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
		3158	{
		3159	struct radeon_device *rdev = dev->dev_private;
		3160
		3161	if (offset) {
		3162	while (RBIOS8(offset)) {
		3163	uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
		3164	uint8_t addr = (RBIOS8(offset) & 0x3f);
		3165	uint32_t val, shift, tmp;
		3166	uint32_t and_mask, or_mask;
		3167
		3168	offset++;
		3169	switch (cmd) {
		3170	case 0:
		3171	val = RBIOS32(offset);
		3172	offset += 4;
		3173	WREG32_PLL(addr, val);
		3174	break;
		3175	case 1:
		3176	shift = RBIOS8(offset) * 8;
		3177	offset++;
		3178	and_mask = RBIOS8(offset) << shift;
		3179	and_mask \|= ~(0xff << shift);
		3180	offset++;
		3181	or_mask = RBIOS8(offset) << shift;
		3182	offset++;
		3183	tmp = RREG32_PLL(addr);
		3184	tmp &= and_mask;
		3185	tmp \|= or_mask;
		3186	WREG32_PLL(addr, tmp);
		3187	break;
		3188	case 2:
		3189	case 3:
		3190	tmp = 1000;
		3191	switch (addr) {
		3192	case 1:
		3193	udelay(150);
		3194	break;
		3195	case 2:
2997	Serge	3196	mdelay(1);
1123	serge	3197	break;
		3198	case 3:
		3199	while (tmp--) {
		3200	if (!
		3201	(RREG32_PLL
		3202	(RADEON_CLK_PWRMGT_CNTL) &
		3203	RADEON_MC_BUSY))
		3204	break;
		3205	}
		3206	break;
		3207	case 4:
		3208	while (tmp--) {
		3209	if (RREG32_PLL
		3210	(RADEON_CLK_PWRMGT_CNTL) &
		3211	RADEON_DLL_READY)
		3212	break;
		3213	}
		3214	break;
		3215	case 5:
		3216	tmp =
		3217	RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
		3218	if (tmp & RADEON_CG_NO1_DEBUG_0) {
		3219	#if 0
		3220	uint32_t mclk_cntl =
		3221	RREG32_PLL
		3222	(RADEON_MCLK_CNTL);
		3223	mclk_cntl &= 0xffff0000;
		3224	/mclk_cntl \|= 0x00001111;//* ??? */
		3225	WREG32_PLL(RADEON_MCLK_CNTL,
		3226	mclk_cntl);
2997	Serge	3227	mdelay(10);
1123	serge	3228	#endif
		3229	WREG32_PLL
		3230	(RADEON_CLK_PWRMGT_CNTL,
		3231	tmp &
		3232	~RADEON_CG_NO1_DEBUG_0);
2997	Serge	3233	mdelay(10);
1123	serge	3234	}
		3235	break;
		3236	default:
		3237	break;
		3238	}
		3239	break;
		3240	default:
		3241	break;
		3242	}
		3243	}
		3244	}
		3245	}
		3246
		3247	static void combios_parse_ram_reset_table(struct drm_device *dev,
		3248	uint16_t offset)
		3249	{
		3250	struct radeon_device *rdev = dev->dev_private;
		3251	uint32_t tmp;
		3252
		3253	if (offset) {
		3254	uint8_t val = RBIOS8(offset);
		3255	while (val != 0xff) {
		3256	offset++;
		3257
		3258	if (val == 0x0f) {
		3259	uint32_t channel_complete_mask;
		3260
		3261	if (ASIC_IS_R300(rdev))
		3262	channel_complete_mask =
		3263	R300_MEM_PWRUP_COMPLETE;
		3264	else
		3265	channel_complete_mask =
		3266	RADEON_MEM_PWRUP_COMPLETE;
		3267	tmp = 20000;
		3268	while (tmp--) {
		3269	if ((RREG32(RADEON_MEM_STR_CNTL) &
		3270	channel_complete_mask) ==
		3271	channel_complete_mask)
		3272	break;
		3273	}
		3274	} else {
		3275	uint32_t or_mask = RBIOS16(offset);
		3276	offset += 2;
		3277
		3278	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3279	tmp &= RADEON_SDRAM_MODE_MASK;
		3280	tmp \|= or_mask;
		3281	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3282
		3283	or_mask = val << 24;
		3284	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3285	tmp &= RADEON_B3MEM_RESET_MASK;
		3286	tmp \|= or_mask;
		3287	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3288	}
		3289	val = RBIOS8(offset);
		3290	}
		3291	}
		3292	}
		3293
		3294	static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
		3295	int mem_addr_mapping)
		3296	{
		3297	struct radeon_device *rdev = dev->dev_private;
		3298	uint32_t mem_cntl;
		3299	uint32_t mem_size;
		3300	uint32_t addr = 0;
		3301
		3302	mem_cntl = RREG32(RADEON_MEM_CNTL);
		3303	if (mem_cntl & RV100_HALF_MODE)
		3304	ram /= 2;
		3305	mem_size = ram;
		3306	mem_cntl &= ~(0xff << 8);
		3307	mem_cntl \|= (mem_addr_mapping & 0xff) << 8;
		3308	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3309	RREG32(RADEON_MEM_CNTL);
		3310
		3311	/* sdram reset ? */
		3312
		3313	/* something like this???? */
		3314	while (ram--) {
		3315	addr = ram * 1024 * 1024;
		3316	/* write to each page */
3192	Serge	3317	WREG32_IDX((addr) \| RADEON_MM_APER, 0xdeadbeef);
1123	serge	3318	/* read back and verify */
3192	Serge	3319	if (RREG32_IDX((addr) \| RADEON_MM_APER) != 0xdeadbeef)
1123	serge	3320	return 0;
		3321	}
		3322
		3323	return mem_size;
		3324	}
		3325
		3326	static void combios_write_ram_size(struct drm_device *dev)
		3327	{
		3328	struct radeon_device *rdev = dev->dev_private;
		3329	uint8_t rev;
		3330	uint16_t offset;
		3331	uint32_t mem_size = 0;
		3332	uint32_t mem_cntl = 0;
		3333
		3334	/* should do something smarter here I guess... */
		3335	if (rdev->flags & RADEON_IS_IGP)
		3336	return;
		3337
		3338	/* first check detected mem table */
		3339	offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
		3340	if (offset) {
		3341	rev = RBIOS8(offset);
		3342	if (rev < 3) {
		3343	mem_cntl = RBIOS32(offset + 1);
		3344	mem_size = RBIOS16(offset + 5);
1963	serge	3345	if ((rdev->family < CHIP_R200) &&
		3346	!ASIC_IS_RN50(rdev))
1123	serge	3347	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3348	}
		3349	}
		3350
		3351	if (!mem_size) {
		3352	offset =
		3353	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		3354	if (offset) {
		3355	rev = RBIOS8(offset - 1);
		3356	if (rev < 1) {
1963	serge	3357	if ((rdev->family < CHIP_R200)
		3358	&& !ASIC_IS_RN50(rdev)) {
1123	serge	3359	int ram = 0;
		3360	int mem_addr_mapping = 0;
		3361
		3362	while (RBIOS8(offset)) {
		3363	ram = RBIOS8(offset);
		3364	mem_addr_mapping =
		3365	RBIOS8(offset + 1);
		3366	if (mem_addr_mapping != 0x25)
		3367	ram *= 2;
		3368	mem_size =
		3369	combios_detect_ram(dev, ram,
		3370	mem_addr_mapping);
		3371	if (mem_size)
		3372	break;
		3373	offset += 2;
		3374	}
		3375	} else
		3376	mem_size = RBIOS8(offset);
		3377	} else {
		3378	mem_size = RBIOS8(offset);
		3379	mem_size = 2; / convert to MB */
		3380	}
		3381	}
		3382	}
		3383
		3384	mem_size = (1024 1024); /* convert to bytes */
		3385	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
		3386	}
		3387
		3388	void radeon_combios_asic_init(struct drm_device *dev)
		3389	{
		3390	struct radeon_device *rdev = dev->dev_private;
		3391	uint16_t table;
		3392
		3393	/* port hardcoded mac stuff from radeonfb */
		3394	if (rdev->bios == NULL)
		3395	return;
		3396
		3397	/* ASIC INIT 1 */
		3398	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
		3399	if (table)
		3400	combios_parse_mmio_table(dev, table);
		3401
		3402	/* PLL INIT */
		3403	table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
		3404	if (table)
		3405	combios_parse_pll_table(dev, table);
		3406
		3407	/* ASIC INIT 2 */
		3408	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
		3409	if (table)
		3410	combios_parse_mmio_table(dev, table);
		3411
		3412	if (!(rdev->flags & RADEON_IS_IGP)) {
		3413	/* ASIC INIT 4 */
		3414	table =
		3415	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
		3416	if (table)
		3417	combios_parse_mmio_table(dev, table);
		3418
		3419	/* RAM RESET */
		3420	table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
		3421	if (table)
		3422	combios_parse_ram_reset_table(dev, table);
		3423
		3424	/* ASIC INIT 3 */
		3425	table =
		3426	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
		3427	if (table)
		3428	combios_parse_mmio_table(dev, table);
		3429
		3430	/* write CONFIG_MEMSIZE */
		3431	combios_write_ram_size(dev);
		3432	}
		3433
1963	serge	3434	/* quirk for rs4xx HP nx6125 laptop to make it resume
		3435	* - it hangs on resume inside the dynclk 1 table.
		3436	*/
		3437	if (rdev->family == CHIP_RS480 &&
		3438	rdev->pdev->subsystem_vendor == 0x103c &&
		3439	rdev->pdev->subsystem_device == 0x308b)
		3440	return;
		3441
		3442	/* quirk for rs4xx HP dv5000 laptop to make it resume
		3443	* - it hangs on resume inside the dynclk 1 table.
		3444	*/
		3445	if (rdev->family == CHIP_RS480 &&
		3446	rdev->pdev->subsystem_vendor == 0x103c &&
		3447	rdev->pdev->subsystem_device == 0x30a4)
		3448	return;
		3449
2997	Serge	3450	/* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
		3451	* - it hangs on resume inside the dynclk 1 table.
		3452	*/
		3453	if (rdev->family == CHIP_RS480 &&
		3454	rdev->pdev->subsystem_vendor == 0x103c &&
		3455	rdev->pdev->subsystem_device == 0x30ae)
		3456	return;
		3457
1123	serge	3458	/* DYN CLK 1 */
		3459	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		3460	if (table)
		3461	combios_parse_pll_table(dev, table);
		3462
		3463	}
		3464
		3465	void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
		3466	{
		3467	struct radeon_device *rdev = dev->dev_private;
		3468	uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
		3469
		3470	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		3471	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3472	bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
		3473
		3474	/* let the bios control the backlight */
		3475	bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
		3476
		3477	/* tell the bios not to handle mode switching */
		3478	bios_6_scratch \|= (RADEON_DISPLAY_SWITCHING_DIS \|
		3479	RADEON_ACC_MODE_CHANGE);
		3480
		3481	/* tell the bios a driver is loaded */
		3482	bios_7_scratch \|= RADEON_DRV_LOADED;
		3483
		3484	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		3485	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3486	WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
		3487	}
		3488
		3489	void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
		3490	{
		3491	struct drm_device *dev = encoder->dev;
		3492	struct radeon_device *rdev = dev->dev_private;
		3493	uint32_t bios_6_scratch;
		3494
		3495	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3496
		3497	if (lock)
		3498	bios_6_scratch \|= RADEON_DRIVER_CRITICAL;
		3499	else
		3500	bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
		3501
		3502	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3503	}
		3504
		3505	void
		3506	radeon_combios_connected_scratch_regs(struct drm_connector *connector,
		3507	struct drm_encoder *encoder,
		3508	bool connected)
		3509	{
		3510	struct drm_device *dev = connector->dev;
		3511	struct radeon_device *rdev = dev->dev_private;
		3512	struct radeon_connector *radeon_connector =
		3513	to_radeon_connector(connector);
		3514	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3515	uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
		3516	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3517
		3518	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		3519	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		3520	if (connected) {
1963	serge	3521	DRM_DEBUG_KMS("TV1 connected\n");
1123	serge	3522	/* fix me */
		3523	bios_4_scratch \|= RADEON_TV1_ATTACHED_SVIDEO;
		3524	/save->bios_4_scratch \|= RADEON_TV1_ATTACHED_COMP; /
		3525	bios_5_scratch \|= RADEON_TV1_ON;
		3526	bios_5_scratch \|= RADEON_ACC_REQ_TV1;
		3527	} else {
1963	serge	3528	DRM_DEBUG_KMS("TV1 disconnected\n");
1123	serge	3529	bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
		3530	bios_5_scratch &= ~RADEON_TV1_ON;
		3531	bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
		3532	}
		3533	}
		3534	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		3535	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		3536	if (connected) {
1963	serge	3537	DRM_DEBUG_KMS("LCD1 connected\n");
1123	serge	3538	bios_4_scratch \|= RADEON_LCD1_ATTACHED;
		3539	bios_5_scratch \|= RADEON_LCD1_ON;
		3540	bios_5_scratch \|= RADEON_ACC_REQ_LCD1;
		3541	} else {
1963	serge	3542	DRM_DEBUG_KMS("LCD1 disconnected\n");
1123	serge	3543	bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
		3544	bios_5_scratch &= ~RADEON_LCD1_ON;
		3545	bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
		3546	}
		3547	}
		3548	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		3549	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		3550	if (connected) {
1963	serge	3551	DRM_DEBUG_KMS("CRT1 connected\n");
1123	serge	3552	bios_4_scratch \|= RADEON_CRT1_ATTACHED_COLOR;
		3553	bios_5_scratch \|= RADEON_CRT1_ON;
		3554	bios_5_scratch \|= RADEON_ACC_REQ_CRT1;
		3555	} else {
1963	serge	3556	DRM_DEBUG_KMS("CRT1 disconnected\n");
1123	serge	3557	bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
		3558	bios_5_scratch &= ~RADEON_CRT1_ON;
		3559	bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
		3560	}
		3561	}
		3562	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		3563	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		3564	if (connected) {
1963	serge	3565	DRM_DEBUG_KMS("CRT2 connected\n");
1123	serge	3566	bios_4_scratch \|= RADEON_CRT2_ATTACHED_COLOR;
		3567	bios_5_scratch \|= RADEON_CRT2_ON;
		3568	bios_5_scratch \|= RADEON_ACC_REQ_CRT2;
		3569	} else {
1963	serge	3570	DRM_DEBUG_KMS("CRT2 disconnected\n");
1123	serge	3571	bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
		3572	bios_5_scratch &= ~RADEON_CRT2_ON;
		3573	bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
		3574	}
		3575	}
		3576	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		3577	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		3578	if (connected) {
1963	serge	3579	DRM_DEBUG_KMS("DFP1 connected\n");
1123	serge	3580	bios_4_scratch \|= RADEON_DFP1_ATTACHED;
		3581	bios_5_scratch \|= RADEON_DFP1_ON;
		3582	bios_5_scratch \|= RADEON_ACC_REQ_DFP1;
		3583	} else {
1963	serge	3584	DRM_DEBUG_KMS("DFP1 disconnected\n");
1123	serge	3585	bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
		3586	bios_5_scratch &= ~RADEON_DFP1_ON;
		3587	bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
		3588	}
		3589	}
		3590	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		3591	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		3592	if (connected) {
1963	serge	3593	DRM_DEBUG_KMS("DFP2 connected\n");
1123	serge	3594	bios_4_scratch \|= RADEON_DFP2_ATTACHED;
		3595	bios_5_scratch \|= RADEON_DFP2_ON;
		3596	bios_5_scratch \|= RADEON_ACC_REQ_DFP2;
		3597	} else {
1963	serge	3598	DRM_DEBUG_KMS("DFP2 disconnected\n");
1123	serge	3599	bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
		3600	bios_5_scratch &= ~RADEON_DFP2_ON;
		3601	bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
		3602	}
		3603	}
		3604	WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
		3605	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3606	}
		3607
		3608	void
		3609	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		3610	{
		3611	struct drm_device *dev = encoder->dev;
		3612	struct radeon_device *rdev = dev->dev_private;
		3613	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3614	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3615
		3616	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		3617	bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
		3618	bios_5_scratch \|= (crtc << RADEON_TV1_CRTC_SHIFT);
		3619	}
		3620	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3621	bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
		3622	bios_5_scratch \|= (crtc << RADEON_CRT1_CRTC_SHIFT);
		3623	}
		3624	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3625	bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
		3626	bios_5_scratch \|= (crtc << RADEON_CRT2_CRTC_SHIFT);
		3627	}
		3628	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3629	bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
		3630	bios_5_scratch \|= (crtc << RADEON_LCD1_CRTC_SHIFT);
		3631	}
		3632	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3633	bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
		3634	bios_5_scratch \|= (crtc << RADEON_DFP1_CRTC_SHIFT);
		3635	}
		3636	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3637	bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
		3638	bios_5_scratch \|= (crtc << RADEON_DFP2_CRTC_SHIFT);
		3639	}
		3640	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3641	}
		3642
		3643	void
		3644	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		3645	{
		3646	struct drm_device *dev = encoder->dev;
		3647	struct radeon_device *rdev = dev->dev_private;
		3648	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3649	uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3650
		3651	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		3652	if (on)
		3653	bios_6_scratch \|= RADEON_TV_DPMS_ON;
		3654	else
		3655	bios_6_scratch &= ~RADEON_TV_DPMS_ON;
		3656	}
		3657	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		3658	if (on)
		3659	bios_6_scratch \|= RADEON_CRT_DPMS_ON;
		3660	else
		3661	bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
		3662	}
		3663	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		3664	if (on)
		3665	bios_6_scratch \|= RADEON_LCD_DPMS_ON;
		3666	else
		3667	bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
		3668	}
		3669	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		3670	if (on)
		3671	bios_6_scratch \|= RADEON_DFP_DPMS_ON;
		3672	else
		3673	bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
		3674	}
		3675	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3676	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_combios.c – Rev 3764