WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_combios.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2004 ATI Technologies Inc., Markham, Ontario
		3	* Copyright 2007-8 Advanced Micro Devices, Inc.
		4	* Copyright 2008 Red Hat Inc.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	*/
		27	#include "drmP.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	#ifdef CONFIG_PPC_PMAC
		33	/* not sure which of these are needed */
		34	#include
		35	#include
		36	#include
		37	#include
		38	#endif /* CONFIG_PPC_PMAC */
		39
		40	/* from radeon_encoder.c */
		41	extern uint32_t
1963	serge	42	radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
1123	serge	43	uint8_t dac);
		44	extern void radeon_link_encoder_connector(struct drm_device *dev);
		45
		46	/* from radeon_connector.c */
		47	extern void
		48	radeon_add_legacy_connector(struct drm_device *dev,
		49	uint32_t connector_id,
		50	uint32_t supported_device,
		51	int connector_type,
1268	serge	52	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	53	uint16_t connector_object_id,
		54	struct radeon_hpd *hpd);
1123	serge	55
		56	/* from radeon_legacy_encoder.c */
		57	extern void
1963	serge	58	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1123	serge	59	uint32_t supported_device);
		60
		61	/* old legacy ATI BIOS routines */
		62
		63	/* COMBIOS table offsets */
		64	enum radeon_combios_table_offset {
		65	/* absolute offset tables */
		66	COMBIOS_ASIC_INIT_1_TABLE,
		67	COMBIOS_BIOS_SUPPORT_TABLE,
		68	COMBIOS_DAC_PROGRAMMING_TABLE,
		69	COMBIOS_MAX_COLOR_DEPTH_TABLE,
		70	COMBIOS_CRTC_INFO_TABLE,
		71	COMBIOS_PLL_INFO_TABLE,
		72	COMBIOS_TV_INFO_TABLE,
		73	COMBIOS_DFP_INFO_TABLE,
		74	COMBIOS_HW_CONFIG_INFO_TABLE,
		75	COMBIOS_MULTIMEDIA_INFO_TABLE,
		76	COMBIOS_TV_STD_PATCH_TABLE,
		77	COMBIOS_LCD_INFO_TABLE,
		78	COMBIOS_MOBILE_INFO_TABLE,
		79	COMBIOS_PLL_INIT_TABLE,
		80	COMBIOS_MEM_CONFIG_TABLE,
		81	COMBIOS_SAVE_MASK_TABLE,
		82	COMBIOS_HARDCODED_EDID_TABLE,
		83	COMBIOS_ASIC_INIT_2_TABLE,
		84	COMBIOS_CONNECTOR_INFO_TABLE,
		85	COMBIOS_DYN_CLK_1_TABLE,
		86	COMBIOS_RESERVED_MEM_TABLE,
		87	COMBIOS_EXT_TMDS_INFO_TABLE,
		88	COMBIOS_MEM_CLK_INFO_TABLE,
		89	COMBIOS_EXT_DAC_INFO_TABLE,
		90	COMBIOS_MISC_INFO_TABLE,
		91	COMBIOS_CRT_INFO_TABLE,
		92	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
		93	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
		94	COMBIOS_FAN_SPEED_INFO_TABLE,
		95	COMBIOS_OVERDRIVE_INFO_TABLE,
		96	COMBIOS_OEM_INFO_TABLE,
		97	COMBIOS_DYN_CLK_2_TABLE,
		98	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
		99	COMBIOS_I2C_INFO_TABLE,
		100	/* relative offset tables */
		101	COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
		102	COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
		103	COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
		104	COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
		105	COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
		106	COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
		107	COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
		108	COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
		109	COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
		110	COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
		111	COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
		112	};
		113
		114	enum radeon_combios_ddc {
		115	DDC_NONE_DETECTED,
		116	DDC_MONID,
		117	DDC_DVI,
		118	DDC_VGA,
		119	DDC_CRT2,
		120	DDC_LCD,
		121	DDC_GPIO,
		122	};
		123
		124	enum radeon_combios_connector {
		125	CONNECTOR_NONE_LEGACY,
		126	CONNECTOR_PROPRIETARY_LEGACY,
		127	CONNECTOR_CRT_LEGACY,
		128	CONNECTOR_DVI_I_LEGACY,
		129	CONNECTOR_DVI_D_LEGACY,
		130	CONNECTOR_CTV_LEGACY,
		131	CONNECTOR_STV_LEGACY,
		132	CONNECTOR_UNSUPPORTED_LEGACY
		133	};
		134
		135	const int legacy_connector_convert[] = {
		136	DRM_MODE_CONNECTOR_Unknown,
		137	DRM_MODE_CONNECTOR_DVID,
		138	DRM_MODE_CONNECTOR_VGA,
		139	DRM_MODE_CONNECTOR_DVII,
		140	DRM_MODE_CONNECTOR_DVID,
		141	DRM_MODE_CONNECTOR_Composite,
		142	DRM_MODE_CONNECTOR_SVIDEO,
		143	DRM_MODE_CONNECTOR_Unknown,
		144	};
		145
		146	static uint16_t combios_get_table_offset(struct drm_device *dev,
		147	enum radeon_combios_table_offset table)
		148	{
		149	struct radeon_device *rdev = dev->dev_private;
		150	int rev;
		151	uint16_t offset = 0, check_offset;
		152
1430	serge	153	if (!rdev->bios)
		154	return 0;
		155
1123	serge	156	switch (table) {
		157	/* absolute offset tables */
		158	case COMBIOS_ASIC_INIT_1_TABLE:
		159	check_offset = RBIOS16(rdev->bios_header_start + 0xc);
		160	if (check_offset)
		161	offset = check_offset;
		162	break;
		163	case COMBIOS_BIOS_SUPPORT_TABLE:
		164	check_offset = RBIOS16(rdev->bios_header_start + 0x14);
		165	if (check_offset)
		166	offset = check_offset;
		167	break;
		168	case COMBIOS_DAC_PROGRAMMING_TABLE:
		169	check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
		170	if (check_offset)
		171	offset = check_offset;
		172	break;
		173	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		174	check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
		175	if (check_offset)
		176	offset = check_offset;
		177	break;
		178	case COMBIOS_CRTC_INFO_TABLE:
		179	check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
		180	if (check_offset)
		181	offset = check_offset;
		182	break;
		183	case COMBIOS_PLL_INFO_TABLE:
		184	check_offset = RBIOS16(rdev->bios_header_start + 0x30);
		185	if (check_offset)
		186	offset = check_offset;
		187	break;
		188	case COMBIOS_TV_INFO_TABLE:
		189	check_offset = RBIOS16(rdev->bios_header_start + 0x32);
		190	if (check_offset)
		191	offset = check_offset;
		192	break;
		193	case COMBIOS_DFP_INFO_TABLE:
		194	check_offset = RBIOS16(rdev->bios_header_start + 0x34);
		195	if (check_offset)
		196	offset = check_offset;
		197	break;
		198	case COMBIOS_HW_CONFIG_INFO_TABLE:
		199	check_offset = RBIOS16(rdev->bios_header_start + 0x36);
		200	if (check_offset)
		201	offset = check_offset;
		202	break;
		203	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		204	check_offset = RBIOS16(rdev->bios_header_start + 0x38);
		205	if (check_offset)
		206	offset = check_offset;
		207	break;
		208	case COMBIOS_TV_STD_PATCH_TABLE:
		209	check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
		210	if (check_offset)
		211	offset = check_offset;
		212	break;
		213	case COMBIOS_LCD_INFO_TABLE:
		214	check_offset = RBIOS16(rdev->bios_header_start + 0x40);
		215	if (check_offset)
		216	offset = check_offset;
		217	break;
		218	case COMBIOS_MOBILE_INFO_TABLE:
		219	check_offset = RBIOS16(rdev->bios_header_start + 0x42);
		220	if (check_offset)
		221	offset = check_offset;
		222	break;
		223	case COMBIOS_PLL_INIT_TABLE:
		224	check_offset = RBIOS16(rdev->bios_header_start + 0x46);
		225	if (check_offset)
		226	offset = check_offset;
		227	break;
		228	case COMBIOS_MEM_CONFIG_TABLE:
		229	check_offset = RBIOS16(rdev->bios_header_start + 0x48);
		230	if (check_offset)
		231	offset = check_offset;
		232	break;
		233	case COMBIOS_SAVE_MASK_TABLE:
		234	check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
		235	if (check_offset)
		236	offset = check_offset;
		237	break;
		238	case COMBIOS_HARDCODED_EDID_TABLE:
		239	check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
		240	if (check_offset)
		241	offset = check_offset;
		242	break;
		243	case COMBIOS_ASIC_INIT_2_TABLE:
		244	check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
		245	if (check_offset)
		246	offset = check_offset;
		247	break;
		248	case COMBIOS_CONNECTOR_INFO_TABLE:
		249	check_offset = RBIOS16(rdev->bios_header_start + 0x50);
		250	if (check_offset)
		251	offset = check_offset;
		252	break;
		253	case COMBIOS_DYN_CLK_1_TABLE:
		254	check_offset = RBIOS16(rdev->bios_header_start + 0x52);
		255	if (check_offset)
		256	offset = check_offset;
		257	break;
		258	case COMBIOS_RESERVED_MEM_TABLE:
		259	check_offset = RBIOS16(rdev->bios_header_start + 0x54);
		260	if (check_offset)
		261	offset = check_offset;
		262	break;
		263	case COMBIOS_EXT_TMDS_INFO_TABLE:
		264	check_offset = RBIOS16(rdev->bios_header_start + 0x58);
		265	if (check_offset)
		266	offset = check_offset;
		267	break;
		268	case COMBIOS_MEM_CLK_INFO_TABLE:
		269	check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
		270	if (check_offset)
		271	offset = check_offset;
		272	break;
		273	case COMBIOS_EXT_DAC_INFO_TABLE:
		274	check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
		275	if (check_offset)
		276	offset = check_offset;
		277	break;
		278	case COMBIOS_MISC_INFO_TABLE:
		279	check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
		280	if (check_offset)
		281	offset = check_offset;
		282	break;
		283	case COMBIOS_CRT_INFO_TABLE:
		284	check_offset = RBIOS16(rdev->bios_header_start + 0x60);
		285	if (check_offset)
		286	offset = check_offset;
		287	break;
		288	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		289	check_offset = RBIOS16(rdev->bios_header_start + 0x62);
		290	if (check_offset)
		291	offset = check_offset;
		292	break;
		293	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		294	check_offset = RBIOS16(rdev->bios_header_start + 0x64);
		295	if (check_offset)
		296	offset = check_offset;
		297	break;
		298	case COMBIOS_FAN_SPEED_INFO_TABLE:
		299	check_offset = RBIOS16(rdev->bios_header_start + 0x66);
		300	if (check_offset)
		301	offset = check_offset;
		302	break;
		303	case COMBIOS_OVERDRIVE_INFO_TABLE:
		304	check_offset = RBIOS16(rdev->bios_header_start + 0x68);
		305	if (check_offset)
		306	offset = check_offset;
		307	break;
		308	case COMBIOS_OEM_INFO_TABLE:
		309	check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
		310	if (check_offset)
		311	offset = check_offset;
		312	break;
		313	case COMBIOS_DYN_CLK_2_TABLE:
		314	check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
		315	if (check_offset)
		316	offset = check_offset;
		317	break;
		318	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		319	check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
		320	if (check_offset)
		321	offset = check_offset;
		322	break;
		323	case COMBIOS_I2C_INFO_TABLE:
		324	check_offset = RBIOS16(rdev->bios_header_start + 0x70);
		325	if (check_offset)
		326	offset = check_offset;
		327	break;
		328	/* relative offset tables */
		329	case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
		330	check_offset =
		331	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		332	if (check_offset) {
		333	rev = RBIOS8(check_offset);
		334	if (rev > 0) {
		335	check_offset = RBIOS16(check_offset + 0x3);
		336	if (check_offset)
		337	offset = check_offset;
		338	}
		339	}
		340	break;
		341	case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
		342	check_offset =
		343	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		344	if (check_offset) {
		345	rev = RBIOS8(check_offset);
		346	if (rev > 0) {
		347	check_offset = RBIOS16(check_offset + 0x5);
		348	if (check_offset)
		349	offset = check_offset;
		350	}
		351	}
		352	break;
		353	case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
		354	check_offset =
		355	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		356	if (check_offset) {
		357	rev = RBIOS8(check_offset);
		358	if (rev > 0) {
		359	check_offset = RBIOS16(check_offset + 0x7);
		360	if (check_offset)
		361	offset = check_offset;
		362	}
		363	}
		364	break;
		365	case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
		366	check_offset =
		367	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		368	if (check_offset) {
		369	rev = RBIOS8(check_offset);
		370	if (rev == 2) {
		371	check_offset = RBIOS16(check_offset + 0x9);
		372	if (check_offset)
		373	offset = check_offset;
		374	}
		375	}
		376	break;
		377	case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
		378	check_offset =
		379	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		380	if (check_offset) {
		381	while (RBIOS8(check_offset++));
		382	check_offset += 2;
		383	if (check_offset)
		384	offset = check_offset;
		385	}
		386	break;
		387	case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
		388	check_offset =
		389	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		390	if (check_offset) {
		391	check_offset = RBIOS16(check_offset + 0x11);
		392	if (check_offset)
		393	offset = check_offset;
		394	}
		395	break;
		396	case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
		397	check_offset =
		398	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		399	if (check_offset) {
		400	check_offset = RBIOS16(check_offset + 0x13);
		401	if (check_offset)
		402	offset = check_offset;
		403	}
		404	break;
		405	case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
		406	check_offset =
		407	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		408	if (check_offset) {
		409	check_offset = RBIOS16(check_offset + 0x15);
		410	if (check_offset)
		411	offset = check_offset;
		412	}
		413	break;
		414	case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
		415	check_offset =
		416	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		417	if (check_offset) {
		418	check_offset = RBIOS16(check_offset + 0x17);
		419	if (check_offset)
		420	offset = check_offset;
		421	}
		422	break;
		423	case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
		424	check_offset =
		425	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		426	if (check_offset) {
		427	check_offset = RBIOS16(check_offset + 0x2);
		428	if (check_offset)
		429	offset = check_offset;
		430	}
		431	break;
		432	case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
		433	check_offset =
		434	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		435	if (check_offset) {
		436	check_offset = RBIOS16(check_offset + 0x4);
		437	if (check_offset)
		438	offset = check_offset;
		439	}
		440	break;
		441	default:
		442	break;
		443	}
		444
		445	return offset;
		446
		447	}
		448
1430	serge	449	bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
		450	{
1963	serge	451	int edid_info, size;
1430	serge	452	struct edid *edid;
1963	serge	453	unsigned char *raw;
1430	serge	454	edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
		455	if (!edid_info)
		456	return false;
		457
1963	serge	458	raw = rdev->bios + edid_info;
		459	size = EDID_LENGTH * (raw[0x7e] + 1);
		460	edid = kmalloc(size, GFP_KERNEL);
1430	serge	461	if (edid == NULL)
		462	return false;
		463
1963	serge	464	memcpy((unsigned char *)edid, raw, size);
1430	serge	465
		466	if (!drm_edid_is_valid(edid)) {
		467	kfree(edid);
		468	return false;
		469	}
		470
		471	rdev->mode_info.bios_hardcoded_edid = edid;
1963	serge	472	rdev->mode_info.bios_hardcoded_edid_size = size;
1430	serge	473	return true;
		474	}
		475
1963	serge	476	/* this is used for atom LCDs as well */
1430	serge	477	struct edid *
1963	serge	478	radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
1430	serge	479	{
1963	serge	480	struct edid *edid;
		481
		482	if (rdev->mode_info.bios_hardcoded_edid) {
		483	edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
		484	if (edid) {
		485	memcpy((unsigned char *)edid,
		486	(unsigned char *)rdev->mode_info.bios_hardcoded_edid,
		487	rdev->mode_info.bios_hardcoded_edid_size);
		488	return edid;
		489	}
		490	}
1430	serge	491	return NULL;
		492	}
		493
1321	serge	494	static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
1963	serge	495	enum radeon_combios_ddc ddc,
		496	u32 clk_mask,
		497	u32 data_mask)
1123	serge	498	{
		499	struct radeon_i2c_bus_rec i2c;
1963	serge	500	int ddc_line = 0;
1123	serge	501
1963	serge	502	/* ddc id = mask reg
		503	* DDC_NONE_DETECTED = none
		504	* DDC_DVI = RADEON_GPIO_DVI_DDC
		505	* DDC_VGA = RADEON_GPIO_VGA_DDC
		506	* DDC_LCD = RADEON_GPIOPAD_MASK
		507	* DDC_GPIO = RADEON_MDGPIO_MASK
		508	* r1xx
		509	* DDC_MONID = RADEON_GPIO_MONID
		510	* DDC_CRT2 = RADEON_GPIO_CRT2_DDC
		511	* r200
		512	* DDC_MONID = RADEON_GPIO_MONID
		513	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		514	* r300/r350
		515	* DDC_MONID = RADEON_GPIO_DVI_DDC
		516	* DDC_CRT2 = RADEON_GPIO_DVI_DDC
		517	* rv2xx/rv3xx
		518	* DDC_MONID = RADEON_GPIO_MONID
		519	* DDC_CRT2 = RADEON_GPIO_MONID
		520	* rs3xx/rs4xx
		521	* DDC_MONID = RADEON_GPIOPAD_MASK
		522	* DDC_CRT2 = RADEON_GPIO_MONID
		523	*/
		524	switch (ddc) {
		525	case DDC_NONE_DETECTED:
		526	default:
		527	ddc_line = 0;
		528	break;
		529	case DDC_DVI:
		530	ddc_line = RADEON_GPIO_DVI_DDC;
		531	break;
		532	case DDC_VGA:
		533	ddc_line = RADEON_GPIO_VGA_DDC;
		534	break;
		535	case DDC_LCD:
		536	ddc_line = RADEON_GPIOPAD_MASK;
		537	break;
		538	case DDC_GPIO:
		539	ddc_line = RADEON_MDGPIO_MASK;
		540	break;
		541	case DDC_MONID:
		542	if (rdev->family == CHIP_RS300 \|\|
		543	rdev->family == CHIP_RS400 \|\|
		544	rdev->family == CHIP_RS480)
		545	ddc_line = RADEON_GPIOPAD_MASK;
		546	else if (rdev->family == CHIP_R300 \|\|
		547	rdev->family == CHIP_R350) {
		548	ddc_line = RADEON_GPIO_DVI_DDC;
		549	ddc = DDC_DVI;
		550	} else
		551	ddc_line = RADEON_GPIO_MONID;
		552	break;
		553	case DDC_CRT2:
		554	if (rdev->family == CHIP_R200 \|\|
		555	rdev->family == CHIP_R300 \|\|
		556	rdev->family == CHIP_R350) {
		557	ddc_line = RADEON_GPIO_DVI_DDC;
		558	ddc = DDC_DVI;
		559	} else if (rdev->family == CHIP_RS300 \|\|
		560	rdev->family == CHIP_RS400 \|\|
		561	rdev->family == CHIP_RS480)
		562	ddc_line = RADEON_GPIO_MONID;
		563	else if (rdev->family >= CHIP_RV350) {
		564	ddc_line = RADEON_GPIO_MONID;
		565	ddc = DDC_MONID;
		566	} else
		567	ddc_line = RADEON_GPIO_CRT2_DDC;
		568	break;
		569	}
		570
1321	serge	571	if (ddc_line == RADEON_GPIOPAD_MASK) {
		572	i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
		573	i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
		574	i2c.a_clk_reg = RADEON_GPIOPAD_A;
		575	i2c.a_data_reg = RADEON_GPIOPAD_A;
		576	i2c.en_clk_reg = RADEON_GPIOPAD_EN;
		577	i2c.en_data_reg = RADEON_GPIOPAD_EN;
		578	i2c.y_clk_reg = RADEON_GPIOPAD_Y;
		579	i2c.y_data_reg = RADEON_GPIOPAD_Y;
		580	} else if (ddc_line == RADEON_MDGPIO_MASK) {
		581	i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
		582	i2c.mask_data_reg = RADEON_MDGPIO_MASK;
		583	i2c.a_clk_reg = RADEON_MDGPIO_A;
		584	i2c.a_data_reg = RADEON_MDGPIO_A;
		585	i2c.en_clk_reg = RADEON_MDGPIO_EN;
		586	i2c.en_data_reg = RADEON_MDGPIO_EN;
		587	i2c.y_clk_reg = RADEON_MDGPIO_Y;
		588	i2c.y_data_reg = RADEON_MDGPIO_Y;
		589	} else {
1123	serge	590	i2c.mask_clk_reg = ddc_line;
		591	i2c.mask_data_reg = ddc_line;
		592	i2c.a_clk_reg = ddc_line;
		593	i2c.a_data_reg = ddc_line;
1321	serge	594	i2c.en_clk_reg = ddc_line;
		595	i2c.en_data_reg = ddc_line;
		596	i2c.y_clk_reg = ddc_line;
		597	i2c.y_data_reg = ddc_line;
1123	serge	598	}
		599
1963	serge	600	if (clk_mask && data_mask) {
		601	/* system specific masks */
		602	i2c.mask_clk_mask = clk_mask;
		603	i2c.mask_data_mask = data_mask;
		604	i2c.a_clk_mask = clk_mask;
		605	i2c.a_data_mask = data_mask;
		606	i2c.en_clk_mask = clk_mask;
		607	i2c.en_data_mask = data_mask;
		608	i2c.y_clk_mask = clk_mask;
		609	i2c.y_data_mask = data_mask;
		610	} else if ((ddc_line == RADEON_GPIOPAD_MASK) \|\|
		611	(ddc_line == RADEON_MDGPIO_MASK)) {
		612	/* default gpiopad masks */
		613	i2c.mask_clk_mask = (0x20 << 8);
		614	i2c.mask_data_mask = 0x80;
		615	i2c.a_clk_mask = (0x20 << 8);
		616	i2c.a_data_mask = 0x80;
		617	i2c.en_clk_mask = (0x20 << 8);
		618	i2c.en_data_mask = 0x80;
		619	i2c.y_clk_mask = (0x20 << 8);
		620	i2c.y_data_mask = 0x80;
		621	} else {
		622	/* default masks for ddc pads */
		623	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
		624	i2c.mask_data_mask = RADEON_GPIO_EN_0;
		625	i2c.a_clk_mask = RADEON_GPIO_A_1;
		626	i2c.a_data_mask = RADEON_GPIO_A_0;
		627	i2c.en_clk_mask = RADEON_GPIO_EN_1;
		628	i2c.en_data_mask = RADEON_GPIO_EN_0;
		629	i2c.y_clk_mask = RADEON_GPIO_Y_1;
		630	i2c.y_data_mask = RADEON_GPIO_Y_0;
		631	}
		632
1430	serge	633	switch (rdev->family) {
		634	case CHIP_R100:
		635	case CHIP_RV100:
		636	case CHIP_RS100:
		637	case CHIP_RV200:
		638	case CHIP_RS200:
		639	case CHIP_RS300:
		640	switch (ddc_line) {
		641	case RADEON_GPIO_DVI_DDC:
1963	serge	642	i2c.hw_capable = true;
1430	serge	643	break;
		644	default:
		645	i2c.hw_capable = false;
		646	break;
		647	}
		648	break;
		649	case CHIP_R200:
		650	switch (ddc_line) {
		651	case RADEON_GPIO_DVI_DDC:
		652	case RADEON_GPIO_MONID:
		653	i2c.hw_capable = true;
		654	break;
		655	default:
		656	i2c.hw_capable = false;
		657	break;
		658	}
		659	break;
		660	case CHIP_RV250:
		661	case CHIP_RV280:
		662	switch (ddc_line) {
		663	case RADEON_GPIO_VGA_DDC:
		664	case RADEON_GPIO_DVI_DDC:
		665	case RADEON_GPIO_CRT2_DDC:
		666	i2c.hw_capable = true;
		667	break;
		668	default:
		669	i2c.hw_capable = false;
		670	break;
		671	}
		672	break;
		673	case CHIP_R300:
		674	case CHIP_R350:
		675	switch (ddc_line) {
		676	case RADEON_GPIO_VGA_DDC:
		677	case RADEON_GPIO_DVI_DDC:
		678	i2c.hw_capable = true;
		679	break;
		680	default:
1321	serge	681	i2c.hw_capable = false;
1430	serge	682	break;
		683	}
		684	break;
		685	case CHIP_RV350:
		686	case CHIP_RV380:
		687	case CHIP_RS400:
		688	case CHIP_RS480:
1321	serge	689	switch (ddc_line) {
		690	case RADEON_GPIO_VGA_DDC:
		691	case RADEON_GPIO_DVI_DDC:
		692	i2c.hw_capable = true;
		693	break;
		694	case RADEON_GPIO_MONID:
		695	/* hw i2c on RADEON_GPIO_MONID doesn't seem to work
		696	* reliably on some pre-r4xx hardware; not sure why.
		697	*/
		698	i2c.hw_capable = false;
		699	break;
		700	default:
		701	i2c.hw_capable = false;
		702	break;
		703	}
1430	serge	704	break;
		705	default:
		706	i2c.hw_capable = false;
		707	break;
1321	serge	708	}
		709	i2c.mm_i2c = false;
		710
1963	serge	711	i2c.i2c_id = ddc;
		712	i2c.hpd = RADEON_HPD_NONE;
		713
1123	serge	714	if (ddc_line)
		715	i2c.valid = true;
		716	else
		717	i2c.valid = false;
		718
		719	return i2c;
		720	}
		721
1963	serge	722	void radeon_combios_i2c_init(struct radeon_device *rdev)
		723	{
		724	struct drm_device *dev = rdev->ddev;
		725	struct radeon_i2c_bus_rec i2c;
		726
		727	/* actual hw pads
		728	* r1xx/rs2xx/rs3xx
		729	* 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
		730	* r200
		731	* 0x60, 0x64, 0x68, mm
		732	* r300/r350
		733	* 0x60, 0x64, mm
		734	* rv2xx/rv3xx/rs4xx
		735	* 0x60, 0x64, 0x68, gpiopads, mm
		736	*/
		737
		738	/* 0x60 */
		739	i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		740	rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
		741	/* 0x64 */
		742	i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		743	rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
		744
		745	/* mm i2c */
		746	i2c.valid = true;
		747	i2c.hw_capable = true;
		748	i2c.mm_i2c = true;
		749	i2c.i2c_id = 0xa0;
		750	rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
		751
		752	if (rdev->family == CHIP_R300 \|\|
		753	rdev->family == CHIP_R350) {
		754	/* only 2 sw i2c pads */
		755	} else if (rdev->family == CHIP_RS300 \|\|
		756	rdev->family == CHIP_RS400 \|\|
		757	rdev->family == CHIP_RS480) {
		758	u16 offset;
		759	u8 id, blocks, clk, data;
		760	int i;
		761
		762	/* 0x68 */
		763	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		764	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		765
		766	offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
		767	if (offset) {
		768	blocks = RBIOS8(offset + 2);
		769	for (i = 0; i < blocks; i++) {
		770	id = RBIOS8(offset + 3 + (i * 5) + 0);
		771	if (id == 136) {
		772	clk = RBIOS8(offset + 3 + (i * 5) + 3);
		773	data = RBIOS8(offset + 3 + (i * 5) + 4);
		774	/* gpiopad */
		775	i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
		776	(1 << clk), (1 << data));
		777	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
		778	break;
		779	}
		780	}
		781	}
2160	serge	782	} else if ((rdev->family == CHIP_R200) \|\|
		783	(rdev->family >= CHIP_R300)) {
1963	serge	784	/* 0x68 */
		785	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		786	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		787	} else {
		788	/* 0x68 */
		789	i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		790	rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
		791	/* 0x6c */
		792	i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		793	rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
		794	}
		795	}
		796
1123	serge	797	bool radeon_combios_get_clock_info(struct drm_device *dev)
		798	{
		799	struct radeon_device *rdev = dev->dev_private;
		800	uint16_t pll_info;
		801	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		802	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		803	struct radeon_pll *spll = &rdev->clock.spll;
		804	struct radeon_pll *mpll = &rdev->clock.mpll;
		805	int8_t rev;
		806	uint16_t sclk, mclk;
		807
		808	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
		809	if (pll_info) {
		810	rev = RBIOS8(pll_info);
		811
		812	/* pixel clocks */
		813	p1pll->reference_freq = RBIOS16(pll_info + 0xe);
		814	p1pll->reference_div = RBIOS16(pll_info + 0x10);
		815	p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
		816	p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
1963	serge	817	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		818	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1123	serge	819
		820	if (rev > 9) {
		821	p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
		822	p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
		823	} else {
		824	p1pll->pll_in_min = 40;
		825	p1pll->pll_in_max = 500;
		826	}
		827	p2pll = p1pll;
		828
		829	/* system clock */
		830	spll->reference_freq = RBIOS16(pll_info + 0x1a);
		831	spll->reference_div = RBIOS16(pll_info + 0x1c);
		832	spll->pll_out_min = RBIOS32(pll_info + 0x1e);
		833	spll->pll_out_max = RBIOS32(pll_info + 0x22);
		834
		835	if (rev > 10) {
		836	spll->pll_in_min = RBIOS32(pll_info + 0x48);
		837	spll->pll_in_max = RBIOS32(pll_info + 0x4c);
		838	} else {
		839	/* ??? */
		840	spll->pll_in_min = 40;
		841	spll->pll_in_max = 500;
		842	}
		843
		844	/* memory clock */
		845	mpll->reference_freq = RBIOS16(pll_info + 0x26);
		846	mpll->reference_div = RBIOS16(pll_info + 0x28);
		847	mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
		848	mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
		849
		850	if (rev > 10) {
		851	mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
		852	mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
		853	} else {
		854	/* ??? */
		855	mpll->pll_in_min = 40;
		856	mpll->pll_in_max = 500;
		857	}
		858
		859	/* default sclk/mclk */
		860	sclk = RBIOS16(pll_info + 0xa);
		861	mclk = RBIOS16(pll_info + 0x8);
		862	if (sclk == 0)
		863	sclk = 200 * 100;
		864	if (mclk == 0)
		865	mclk = 200 * 100;
		866
		867	rdev->clock.default_sclk = sclk;
		868	rdev->clock.default_mclk = mclk;
		869
1963	serge	870	if (RBIOS32(pll_info + 0x16))
		871	rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
		872	else
		873	rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
		874
1123	serge	875	return true;
		876	}
		877	return false;
		878	}
		879
1404	serge	880	bool radeon_combios_sideport_present(struct radeon_device *rdev)
		881	{
		882	struct drm_device *dev = rdev->ddev;
		883	u16 igp_info;
		884
1963	serge	885	/* sideport is AMD only */
		886	if (rdev->family == CHIP_RS400)
		887	return false;
		888
1404	serge	889	igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
		890
		891	if (igp_info) {
		892	if (RBIOS16(igp_info + 0x4))
		893	return true;
		894	}
		895	return false;
		896	}
		897
		898	static const uint32_t default_primarydac_adj[CHIP_LAST] = {
		899	0x00000808, /* r100 */
		900	0x00000808, /* rv100 */
		901	0x00000808, /* rs100 */
		902	0x00000808, /* rv200 */
		903	0x00000808, /* rs200 */
		904	0x00000808, /* r200 */
		905	0x00000808, /* rv250 */
		906	0x00000000, /* rs300 */
		907	0x00000808, /* rv280 */
		908	0x00000808, /* r300 */
		909	0x00000808, /* r350 */
		910	0x00000808, /* rv350 */
		911	0x00000808, /* rv380 */
		912	0x00000808, /* r420 */
		913	0x00000808, /* r423 */
		914	0x00000808, /* rv410 */
		915	0x00000000, /* rs400 */
		916	0x00000000, /* rs480 */
		917	};
		918
		919	static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
		920	struct radeon_encoder_primary_dac *p_dac)
		921	{
		922	p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
		923	return;
		924	}
		925
1123	serge	926	struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
		927	radeon_encoder
		928	*encoder)
		929	{
		930	struct drm_device *dev = encoder->base.dev;
		931	struct radeon_device *rdev = dev->dev_private;
		932	uint16_t dac_info;
		933	uint8_t rev, bg, dac;
		934	struct radeon_encoder_primary_dac *p_dac = NULL;
1404	serge	935	int found = 0;
1123	serge	936
1404	serge	937	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
		938	GFP_KERNEL);
		939
		940	if (!p_dac)
1123	serge	941	return NULL;
		942
		943	/* check CRT table */
		944	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		945	if (dac_info) {
		946	rev = RBIOS8(dac_info) & 0x3;
		947	if (rev < 2) {
		948	bg = RBIOS8(dac_info + 0x2) & 0xf;
		949	dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
		950	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		951	} else {
		952	bg = RBIOS8(dac_info + 0x2) & 0xf;
		953	dac = RBIOS8(dac_info + 0x3) & 0xf;
		954	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		955	}
1963	serge	956	/* if the values are all zeros, use the table */
		957	if (p_dac->ps2_pdac_adj)
1404	serge	958	found = 1;
1123	serge	959	}
		960
1404	serge	961	if (!found) /* fallback to defaults */
		962	radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
		963
1123	serge	964	return p_dac;
		965	}
		966
1404	serge	967	enum radeon_tv_std
		968	radeon_combios_get_tv_info(struct radeon_device *rdev)
1123	serge	969	{
1404	serge	970	struct drm_device *dev = rdev->ddev;
1123	serge	971	uint16_t tv_info;
		972	enum radeon_tv_std tv_std = TV_STD_NTSC;
		973
		974	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		975	if (tv_info) {
		976	if (RBIOS8(tv_info + 6) == 'T') {
		977	switch (RBIOS8(tv_info + 7) & 0xf) {
		978	case 1:
		979	tv_std = TV_STD_NTSC;
1963	serge	980	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1123	serge	981	break;
		982	case 2:
		983	tv_std = TV_STD_PAL;
1963	serge	984	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1123	serge	985	break;
		986	case 3:
		987	tv_std = TV_STD_PAL_M;
1963	serge	988	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1123	serge	989	break;
		990	case 4:
		991	tv_std = TV_STD_PAL_60;
1963	serge	992	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1123	serge	993	break;
		994	case 5:
		995	tv_std = TV_STD_NTSC_J;
1963	serge	996	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1123	serge	997	break;
		998	case 6:
		999	tv_std = TV_STD_SCART_PAL;
1963	serge	1000	DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1123	serge	1001	break;
		1002	default:
		1003	tv_std = TV_STD_NTSC;
1963	serge	1004	DRM_DEBUG_KMS
1123	serge	1005	("Unknown TV standard; defaulting to NTSC\n");
		1006	break;
		1007	}
		1008
		1009	switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
		1010	case 0:
1963	serge	1011	DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1123	serge	1012	break;
		1013	case 1:
1963	serge	1014	DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1123	serge	1015	break;
		1016	case 2:
1963	serge	1017	DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1123	serge	1018	break;
		1019	case 3:
1963	serge	1020	DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1123	serge	1021	break;
		1022	default:
		1023	break;
		1024	}
		1025	}
		1026	}
		1027	return tv_std;
		1028	}
		1029
		1030	static const uint32_t default_tvdac_adj[CHIP_LAST] = {
		1031	0x00000000, /* r100 */
		1032	0x00280000, /* rv100 */
		1033	0x00000000, /* rs100 */
		1034	0x00880000, /* rv200 */
		1035	0x00000000, /* rs200 */
		1036	0x00000000, /* r200 */
		1037	0x00770000, /* rv250 */
		1038	0x00290000, /* rs300 */
		1039	0x00560000, /* rv280 */
		1040	0x00780000, /* r300 */
		1041	0x00770000, /* r350 */
		1042	0x00780000, /* rv350 */
		1043	0x00780000, /* rv380 */
		1044	0x01080000, /* r420 */
		1045	0x01080000, /* r423 */
		1046	0x01080000, /* rv410 */
		1047	0x00780000, /* rs400 */
		1048	0x00780000, /* rs480 */
		1049	};
		1050
1179	serge	1051	static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
		1052	struct radeon_encoder_tv_dac *tv_dac)
1123	serge	1053	{
		1054	tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
		1055	if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
		1056	tv_dac->ps2_tvdac_adj = 0x00880000;
		1057	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1058	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	1059	return;
1123	serge	1060	}
		1061
		1062	struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
		1063	radeon_encoder
		1064	*encoder)
		1065	{
		1066	struct drm_device *dev = encoder->base.dev;
		1067	struct radeon_device *rdev = dev->dev_private;
		1068	uint16_t dac_info;
		1069	uint8_t rev, bg, dac;
		1070	struct radeon_encoder_tv_dac *tv_dac = NULL;
1179	serge	1071	int found = 0;
1123	serge	1072
1179	serge	1073	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1074	if (!tv_dac)
		1075	return NULL;
		1076
1123	serge	1077	/* first check TV table */
		1078	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		1079	if (dac_info) {
		1080	rev = RBIOS8(dac_info + 0x3);
		1081	if (rev > 4) {
		1082	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1083	dac = RBIOS8(dac_info + 0xd) & 0xf;
		1084	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1085
		1086	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1087	dac = RBIOS8(dac_info + 0xf) & 0xf;
		1088	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1089
		1090	bg = RBIOS8(dac_info + 0x10) & 0xf;
		1091	dac = RBIOS8(dac_info + 0x11) & 0xf;
		1092	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1093	/* if the values are all zeros, use the table */
		1094	if (tv_dac->ps2_tvdac_adj)
1179	serge	1095	found = 1;
1123	serge	1096	} else if (rev > 1) {
		1097	bg = RBIOS8(dac_info + 0xc) & 0xf;
		1098	dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
		1099	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1100
		1101	bg = RBIOS8(dac_info + 0xd) & 0xf;
		1102	dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
		1103	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1104
		1105	bg = RBIOS8(dac_info + 0xe) & 0xf;
		1106	dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
		1107	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1963	serge	1108	/* if the values are all zeros, use the table */
		1109	if (tv_dac->ps2_tvdac_adj)
1179	serge	1110	found = 1;
1123	serge	1111	}
1404	serge	1112	tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1179	serge	1113	}
		1114	if (!found) {
1123	serge	1115	/* then check CRT table */
		1116	dac_info =
		1117	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		1118	if (dac_info) {
		1119	rev = RBIOS8(dac_info) & 0x3;
		1120	if (rev < 2) {
		1121	bg = RBIOS8(dac_info + 0x3) & 0xf;
		1122	dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
		1123	tv_dac->ps2_tvdac_adj =
		1124	(bg << 16) \| (dac << 20);
		1125	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1126	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1127	/* if the values are all zeros, use the table */
		1128	if (tv_dac->ps2_tvdac_adj)
1179	serge	1129	found = 1;
1123	serge	1130	} else {
		1131	bg = RBIOS8(dac_info + 0x4) & 0xf;
		1132	dac = RBIOS8(dac_info + 0x5) & 0xf;
		1133	tv_dac->ps2_tvdac_adj =
		1134	(bg << 16) \| (dac << 20);
		1135	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		1136	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1963	serge	1137	/* if the values are all zeros, use the table */
		1138	if (tv_dac->ps2_tvdac_adj)
1179	serge	1139	found = 1;
1123	serge	1140	}
		1141	} else {
		1142	DRM_INFO("No TV DAC info found in BIOS\n");
		1143	}
		1144	}
1221	serge	1145
1179	serge	1146	if (!found) /* fallback to defaults */
		1147	radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1123	serge	1148
		1149	return tv_dac;
		1150	}
		1151
		1152	static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
		1153	radeon_device
		1154	*rdev)
		1155	{
		1156	struct radeon_encoder_lvds *lvds = NULL;
		1157	uint32_t fp_vert_stretch, fp_horz_stretch;
		1158	uint32_t ppll_div_sel, ppll_val;
		1159	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		1160
		1161	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1162
		1163	if (!lvds)
		1164	return NULL;
		1165
		1166	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
		1167	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
		1168
		1169	/* These should be fail-safe defaults, fingers crossed */
		1170	lvds->panel_pwr_delay = 200;
		1171	lvds->panel_vcc_delay = 2000;
		1172
		1173	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		1174	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
		1175	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
		1176
		1177	if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1268	serge	1178	lvds->native_mode.vdisplay =
1123	serge	1179	((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
		1180	RADEON_VERT_PANEL_SHIFT) + 1;
		1181	else
1268	serge	1182	lvds->native_mode.vdisplay =
1123	serge	1183	(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
		1184
		1185	if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1268	serge	1186	lvds->native_mode.hdisplay =
1123	serge	1187	(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
		1188	RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
		1189	else
1268	serge	1190	lvds->native_mode.hdisplay =
1123	serge	1191	((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
		1192
1268	serge	1193	if ((lvds->native_mode.hdisplay < 640) \|\|
		1194	(lvds->native_mode.vdisplay < 480)) {
		1195	lvds->native_mode.hdisplay = 640;
		1196	lvds->native_mode.vdisplay = 480;
1123	serge	1197	}
		1198
		1199	ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
		1200	ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
		1201	if ((ppll_val & 0x000707ff) == 0x1bb)
		1202	lvds->use_bios_dividers = false;
		1203	else {
		1204	lvds->panel_ref_divider =
		1205	RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
		1206	lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
		1207	lvds->panel_fb_divider = ppll_val & 0x7ff;
		1208
		1209	if ((lvds->panel_ref_divider != 0) &&
		1210	(lvds->panel_fb_divider > 3))
		1211	lvds->use_bios_dividers = true;
		1212	}
		1213	lvds->panel_vcc_delay = 200;
		1214
		1215	DRM_INFO("Panel info derived from registers\n");
1268	serge	1216	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1217	lvds->native_mode.vdisplay);
1123	serge	1218
		1219	return lvds;
		1220	}
		1221
		1222	struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
		1223	*encoder)
		1224	{
		1225	struct drm_device *dev = encoder->base.dev;
		1226	struct radeon_device *rdev = dev->dev_private;
		1227	uint16_t lcd_info;
		1228	uint32_t panel_setup;
		1229	char stmp[30];
		1230	int tmp, i;
		1231	struct radeon_encoder_lvds *lvds = NULL;
		1232
		1233	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		1234
		1235	if (lcd_info) {
		1236	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		1237
		1238	if (!lvds)
		1239	return NULL;
		1240
		1241	for (i = 0; i < 24; i++)
		1242	stmp[i] = RBIOS8(lcd_info + i + 1);
		1243	stmp[24] = 0;
		1244
		1245	DRM_INFO("Panel ID String: %s\n", stmp);
		1246
1268	serge	1247	lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
		1248	lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1123	serge	1249
1268	serge	1250	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
		1251	lvds->native_mode.vdisplay);
1123	serge	1252
		1253	lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1404	serge	1254	lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1123	serge	1255
		1256	lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
		1257	lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
		1258	lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
		1259
		1260	lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
		1261	lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
		1262	lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
		1263	if ((lvds->panel_ref_divider != 0) &&
		1264	(lvds->panel_fb_divider > 3))
		1265	lvds->use_bios_dividers = true;
		1266
		1267	panel_setup = RBIOS32(lcd_info + 0x39);
		1268	lvds->lvds_gen_cntl = 0xff00;
		1269	if (panel_setup & 0x1)
		1270	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_FORMAT;
		1271
		1272	if ((panel_setup >> 4) & 0x1)
		1273	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_TYPE;
		1274
		1275	switch ((panel_setup >> 8) & 0x7) {
		1276	case 0:
		1277	lvds->lvds_gen_cntl \|= RADEON_LVDS_NO_FM;
		1278	break;
		1279	case 1:
		1280	lvds->lvds_gen_cntl \|= RADEON_LVDS_2_GREY;
		1281	break;
		1282	case 2:
		1283	lvds->lvds_gen_cntl \|= RADEON_LVDS_4_GREY;
		1284	break;
		1285	default:
		1286	break;
		1287	}
		1288
		1289	if ((panel_setup >> 16) & 0x1)
		1290	lvds->lvds_gen_cntl \|= RADEON_LVDS_FP_POL_LOW;
		1291
		1292	if ((panel_setup >> 17) & 0x1)
		1293	lvds->lvds_gen_cntl \|= RADEON_LVDS_LP_POL_LOW;
		1294
		1295	if ((panel_setup >> 18) & 0x1)
		1296	lvds->lvds_gen_cntl \|= RADEON_LVDS_DTM_POL_LOW;
		1297
		1298	if ((panel_setup >> 23) & 0x1)
		1299	lvds->lvds_gen_cntl \|= RADEON_LVDS_BL_CLK_SEL;
		1300
		1301	lvds->lvds_gen_cntl \|= (panel_setup & 0xf0000000);
		1302
		1303	for (i = 0; i < 32; i++) {
		1304	tmp = RBIOS16(lcd_info + 64 + i * 2);
		1305	if (tmp == 0)
		1306	break;
		1307
1268	serge	1308	if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1963	serge	1309	(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
		1310	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
		1311	(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
		1312	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
		1313	(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
		1314	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
		1315	(RBIOS8(tmp + 23) * 8);
1123	serge	1316
1963	serge	1317	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
		1318	(RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
		1319	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1320	((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
		1321	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
		1322	((RBIOS16(tmp + 28) & 0xf800) >> 11);
1268	serge	1323
		1324	lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1123	serge	1325	lvds->native_mode.flags = 0;
1268	serge	1326	/* set crtc values */
		1327	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
		1328
1123	serge	1329	}
		1330	}
		1331	} else {
		1332	DRM_INFO("No panel info found in BIOS\n");
1179	serge	1333	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1123	serge	1334	}
1430	serge	1335
1179	serge	1336	if (lvds)
		1337	encoder->native_mode = lvds->native_mode;
1123	serge	1338	return lvds;
		1339	}
		1340
		1341	static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
		1342	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
		1343	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
		1344	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
		1345	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
		1346	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
		1347	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
		1348	{{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
		1349	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
		1350	{{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
		1351	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
		1352	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
		1353	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
		1354	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
		1355	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
		1356	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
		1357	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1321	serge	1358	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
		1359	{ {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1123	serge	1360	};
		1361
1179	serge	1362	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
		1363	struct radeon_encoder_int_tmds *tmds)
1123	serge	1364	{
1179	serge	1365	struct drm_device *dev = encoder->base.dev;
		1366	struct radeon_device *rdev = dev->dev_private;
1123	serge	1367	int i;
		1368
		1369	for (i = 0; i < 4; i++) {
		1370	tmds->tmds_pll[i].value =
		1371	default_tmds_pll[rdev->family][i].value;
		1372	tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
		1373	}
		1374
1179	serge	1375	return true;
1123	serge	1376	}
		1377
1179	serge	1378	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
		1379	struct radeon_encoder_int_tmds *tmds)
1123	serge	1380	{
		1381	struct drm_device *dev = encoder->base.dev;
		1382	struct radeon_device *rdev = dev->dev_private;
		1383	uint16_t tmds_info;
		1384	int i, n;
		1385	uint8_t ver;
		1386
		1387	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1388
		1389	if (tmds_info) {
		1390	ver = RBIOS8(tmds_info);
1963	serge	1391	DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1123	serge	1392	if (ver == 3) {
		1393	n = RBIOS8(tmds_info + 5) + 1;
		1394	if (n > 4)
		1395	n = 4;
		1396	for (i = 0; i < n; i++) {
		1397	tmds->tmds_pll[i].value =
		1398	RBIOS32(tmds_info + i * 10 + 0x08);
		1399	tmds->tmds_pll[i].freq =
		1400	RBIOS16(tmds_info + i * 10 + 0x10);
1963	serge	1401	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1402	tmds->tmds_pll[i].freq,
		1403	tmds->tmds_pll[i].value);
		1404	}
		1405	} else if (ver == 4) {
		1406	int stride = 0;
		1407	n = RBIOS8(tmds_info + 5) + 1;
		1408	if (n > 4)
		1409	n = 4;
		1410	for (i = 0; i < n; i++) {
		1411	tmds->tmds_pll[i].value =
		1412	RBIOS32(tmds_info + stride + 0x08);
		1413	tmds->tmds_pll[i].freq =
		1414	RBIOS16(tmds_info + stride + 0x10);
		1415	if (i == 0)
		1416	stride += 10;
		1417	else
		1418	stride += 6;
1963	serge	1419	DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1123	serge	1420	tmds->tmds_pll[i].freq,
		1421	tmds->tmds_pll[i].value);
		1422	}
		1423	}
1321	serge	1424	} else {
1123	serge	1425	DRM_INFO("No TMDS info found in BIOS\n");
1321	serge	1426	return false;
		1427	}
1179	serge	1428	return true;
		1429	}
		1430
1321	serge	1431	bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
		1432	struct radeon_encoder_ext_tmds *tmds)
1179	serge	1433	{
1321	serge	1434	struct drm_device *dev = encoder->base.dev;
		1435	struct radeon_device *rdev = dev->dev_private;
		1436	struct radeon_i2c_bus_rec i2c_bus;
1179	serge	1437
1321	serge	1438	/* default for macs */
1963	serge	1439	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1440	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1179	serge	1441
1321	serge	1442	/* XXX some macs have duallink chips */
		1443	switch (rdev->mode_info.connector_table) {
		1444	case CT_POWERBOOK_EXTERNAL:
		1445	case CT_MINI_EXTERNAL:
		1446	default:
		1447	tmds->dvo_chip = DVO_SIL164;
		1448	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1449	break;
		1450	}
1179	serge	1451
1321	serge	1452	return true;
1123	serge	1453	}
		1454
1321	serge	1455	bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
		1456	struct radeon_encoder_ext_tmds *tmds)
1123	serge	1457	{
		1458	struct drm_device *dev = encoder->base.dev;
		1459	struct radeon_device *rdev = dev->dev_private;
1321	serge	1460	uint16_t offset;
1963	serge	1461	uint8_t ver;
1321	serge	1462	enum radeon_combios_ddc gpio;
		1463	struct radeon_i2c_bus_rec i2c_bus;
1123	serge	1464
1321	serge	1465	tmds->i2c_bus = NULL;
		1466	if (rdev->flags & RADEON_IS_IGP) {
1963	serge	1467	i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		1468	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1469	tmds->dvo_chip = DVO_SIL164;
		1470	tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
		1471	} else {
		1472	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1473	if (offset) {
		1474	ver = RBIOS8(offset);
1963	serge	1475	DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1321	serge	1476	tmds->slave_addr = RBIOS8(offset + 4 + 2);
		1477	tmds->slave_addr >>= 1; /* 7 bit addressing */
		1478	gpio = RBIOS8(offset + 4 + 3);
1963	serge	1479	if (gpio == DDC_LCD) {
		1480	/* MM i2c */
1430	serge	1481	i2c_bus.valid = true;
		1482	i2c_bus.hw_capable = true;
		1483	i2c_bus.mm_i2c = true;
1963	serge	1484	i2c_bus.i2c_id = 0xa0;
		1485	} else
		1486	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		1487	tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1321	serge	1488	}
		1489	}
		1490
		1491	if (!tmds->i2c_bus) {
		1492	DRM_INFO("No valid Ext TMDS info found in BIOS\n");
		1493	return false;
		1494	}
		1495
		1496	return true;
1123	serge	1497	}
		1498
		1499	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
		1500	{
		1501	struct radeon_device *rdev = dev->dev_private;
		1502	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	1503	struct radeon_hpd hpd;
1123	serge	1504
		1505	rdev->mode_info.connector_table = radeon_connector_table;
		1506	if (rdev->mode_info.connector_table == CT_NONE) {
		1507	#ifdef CONFIG_PPC_PMAC
1430	serge	1508	if (of_machine_is_compatible("PowerBook3,3")) {
1123	serge	1509	/* powerbook with VGA */
		1510	rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1430	serge	1511	} else if (of_machine_is_compatible("PowerBook3,4") \|\|
		1512	of_machine_is_compatible("PowerBook3,5")) {
1123	serge	1513	/* powerbook with internal tmds */
		1514	rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1430	serge	1515	} else if (of_machine_is_compatible("PowerBook5,1") \|\|
		1516	of_machine_is_compatible("PowerBook5,2") \|\|
		1517	of_machine_is_compatible("PowerBook5,3") \|\|
		1518	of_machine_is_compatible("PowerBook5,4") \|\|
		1519	of_machine_is_compatible("PowerBook5,5")) {
1123	serge	1520	/* powerbook with external single link tmds (sil164) */
		1521	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1522	} else if (of_machine_is_compatible("PowerBook5,6")) {
1123	serge	1523	/* powerbook with external dual or single link tmds */
		1524	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1525	} else if (of_machine_is_compatible("PowerBook5,7") \|\|
		1526	of_machine_is_compatible("PowerBook5,8") \|\|
		1527	of_machine_is_compatible("PowerBook5,9")) {
1123	serge	1528	/* PowerBook6,2 ? */
		1529	/* powerbook with external dual link tmds (sil1178?) */
		1530	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1430	serge	1531	} else if (of_machine_is_compatible("PowerBook4,1") \|\|
		1532	of_machine_is_compatible("PowerBook4,2") \|\|
		1533	of_machine_is_compatible("PowerBook4,3") \|\|
		1534	of_machine_is_compatible("PowerBook6,3") \|\|
		1535	of_machine_is_compatible("PowerBook6,5") \|\|
		1536	of_machine_is_compatible("PowerBook6,7")) {
1123	serge	1537	/* ibook */
		1538	rdev->mode_info.connector_table = CT_IBOOK;
1430	serge	1539	} else if (of_machine_is_compatible("PowerMac4,4")) {
1123	serge	1540	/* emac */
		1541	rdev->mode_info.connector_table = CT_EMAC;
1430	serge	1542	} else if (of_machine_is_compatible("PowerMac10,1")) {
1123	serge	1543	/* mini with internal tmds */
		1544	rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1430	serge	1545	} else if (of_machine_is_compatible("PowerMac10,2")) {
1123	serge	1546	/* mini with external tmds */
		1547	rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1430	serge	1548	} else if (of_machine_is_compatible("PowerMac12,1")) {
1123	serge	1549	/* PowerMac8,1 ? */
		1550	/* imac g5 isight */
		1551	rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1963	serge	1552	} else if ((rdev->pdev->device == 0x4a48) &&
		1553	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1554	(rdev->pdev->subsystem_device == 0x4a48)) {
		1555	/* Mac X800 */
		1556	rdev->mode_info.connector_table = CT_MAC_X800;
1986	serge	1557	} else if ((of_machine_is_compatible("PowerMac7,2") \|\|
		1558	of_machine_is_compatible("PowerMac7,3")) &&
		1559	(rdev->pdev->device == 0x4150) &&
		1560	(rdev->pdev->subsystem_vendor == 0x1002) &&
		1561	(rdev->pdev->subsystem_device == 0x4150)) {
		1562	/* Mac G5 tower 9600 */
1963	serge	1563	rdev->mode_info.connector_table = CT_MAC_G5_9600;
1123	serge	1564	} else
		1565	#endif /* CONFIG_PPC_PMAC */
1963	serge	1566	#ifdef CONFIG_PPC64
		1567	if (ASIC_IS_RN50(rdev))
		1568	rdev->mode_info.connector_table = CT_RN50_POWER;
		1569	else
		1570	#endif
1123	serge	1571	rdev->mode_info.connector_table = CT_GENERIC;
		1572	}
		1573
		1574	switch (rdev->mode_info.connector_table) {
		1575	case CT_GENERIC:
		1576	DRM_INFO("Connector Table: %d (generic)\n",
		1577	rdev->mode_info.connector_table);
		1578	/* these are the most common settings */
		1579	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1580	/* VGA - primary dac */
1963	serge	1581	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1582	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1583	radeon_add_legacy_encoder(dev,
1963	serge	1584	radeon_get_encoder_enum(dev,
1123	serge	1585	ATOM_DEVICE_CRT1_SUPPORT,
		1586	1),
		1587	ATOM_DEVICE_CRT1_SUPPORT);
		1588	radeon_add_legacy_connector(dev, 0,
		1589	ATOM_DEVICE_CRT1_SUPPORT,
		1590	DRM_MODE_CONNECTOR_VGA,
1268	serge	1591	&ddc_i2c,
1321	serge	1592	CONNECTOR_OBJECT_ID_VGA,
		1593	&hpd);
1123	serge	1594	} else if (rdev->flags & RADEON_IS_MOBILITY) {
		1595	/* LVDS */
1963	serge	1596	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1321	serge	1597	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1598	radeon_add_legacy_encoder(dev,
1963	serge	1599	radeon_get_encoder_enum(dev,
1123	serge	1600	ATOM_DEVICE_LCD1_SUPPORT,
		1601	0),
		1602	ATOM_DEVICE_LCD1_SUPPORT);
		1603	radeon_add_legacy_connector(dev, 0,
		1604	ATOM_DEVICE_LCD1_SUPPORT,
		1605	DRM_MODE_CONNECTOR_LVDS,
1268	serge	1606	&ddc_i2c,
1321	serge	1607	CONNECTOR_OBJECT_ID_LVDS,
		1608	&hpd);
1123	serge	1609
		1610	/* VGA - primary dac */
1963	serge	1611	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1612	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1613	radeon_add_legacy_encoder(dev,
1963	serge	1614	radeon_get_encoder_enum(dev,
1123	serge	1615	ATOM_DEVICE_CRT1_SUPPORT,
		1616	1),
		1617	ATOM_DEVICE_CRT1_SUPPORT);
		1618	radeon_add_legacy_connector(dev, 1,
		1619	ATOM_DEVICE_CRT1_SUPPORT,
		1620	DRM_MODE_CONNECTOR_VGA,
1268	serge	1621	&ddc_i2c,
1321	serge	1622	CONNECTOR_OBJECT_ID_VGA,
		1623	&hpd);
1123	serge	1624	} else {
		1625	/* DVI-I - tv dac, int tmds */
1963	serge	1626	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1627	hpd.hpd = RADEON_HPD_1;
1123	serge	1628	radeon_add_legacy_encoder(dev,
1963	serge	1629	radeon_get_encoder_enum(dev,
1123	serge	1630	ATOM_DEVICE_DFP1_SUPPORT,
		1631	0),
		1632	ATOM_DEVICE_DFP1_SUPPORT);
		1633	radeon_add_legacy_encoder(dev,
1963	serge	1634	radeon_get_encoder_enum(dev,
1123	serge	1635	ATOM_DEVICE_CRT2_SUPPORT,
		1636	2),
		1637	ATOM_DEVICE_CRT2_SUPPORT);
		1638	radeon_add_legacy_connector(dev, 0,
		1639	ATOM_DEVICE_DFP1_SUPPORT \|
		1640	ATOM_DEVICE_CRT2_SUPPORT,
		1641	DRM_MODE_CONNECTOR_DVII,
1268	serge	1642	&ddc_i2c,
1321	serge	1643	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1644	&hpd);
1123	serge	1645
		1646	/* VGA - primary dac */
1963	serge	1647	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1648	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1649	radeon_add_legacy_encoder(dev,
1963	serge	1650	radeon_get_encoder_enum(dev,
1123	serge	1651	ATOM_DEVICE_CRT1_SUPPORT,
		1652	1),
		1653	ATOM_DEVICE_CRT1_SUPPORT);
		1654	radeon_add_legacy_connector(dev, 1,
		1655	ATOM_DEVICE_CRT1_SUPPORT,
		1656	DRM_MODE_CONNECTOR_VGA,
1268	serge	1657	&ddc_i2c,
1321	serge	1658	CONNECTOR_OBJECT_ID_VGA,
		1659	&hpd);
1123	serge	1660	}
		1661
		1662	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1663	/* TV - tv dac */
1321	serge	1664	ddc_i2c.valid = false;
		1665	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1666	radeon_add_legacy_encoder(dev,
1963	serge	1667	radeon_get_encoder_enum(dev,
1123	serge	1668	ATOM_DEVICE_TV1_SUPPORT,
		1669	2),
		1670	ATOM_DEVICE_TV1_SUPPORT);
		1671	radeon_add_legacy_connector(dev, 2,
		1672	ATOM_DEVICE_TV1_SUPPORT,
		1673	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1674	&ddc_i2c,
1321	serge	1675	CONNECTOR_OBJECT_ID_SVIDEO,
		1676	&hpd);
1123	serge	1677	}
		1678	break;
		1679	case CT_IBOOK:
		1680	DRM_INFO("Connector Table: %d (ibook)\n",
		1681	rdev->mode_info.connector_table);
		1682	/* LVDS */
1963	serge	1683	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1684	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1685	radeon_add_legacy_encoder(dev,
1963	serge	1686	radeon_get_encoder_enum(dev,
1123	serge	1687	ATOM_DEVICE_LCD1_SUPPORT,
		1688	0),
		1689	ATOM_DEVICE_LCD1_SUPPORT);
		1690	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1691	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1692	CONNECTOR_OBJECT_ID_LVDS,
		1693	&hpd);
1123	serge	1694	/* VGA - TV DAC */
1963	serge	1695	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1696	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1697	radeon_add_legacy_encoder(dev,
1963	serge	1698	radeon_get_encoder_enum(dev,
1123	serge	1699	ATOM_DEVICE_CRT2_SUPPORT,
		1700	2),
		1701	ATOM_DEVICE_CRT2_SUPPORT);
		1702	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1703	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1704	CONNECTOR_OBJECT_ID_VGA,
		1705	&hpd);
1123	serge	1706	/* TV - TV DAC */
1321	serge	1707	ddc_i2c.valid = false;
		1708	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1709	radeon_add_legacy_encoder(dev,
1963	serge	1710	radeon_get_encoder_enum(dev,
1123	serge	1711	ATOM_DEVICE_TV1_SUPPORT,
		1712	2),
		1713	ATOM_DEVICE_TV1_SUPPORT);
		1714	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1715	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1716	&ddc_i2c,
1321	serge	1717	CONNECTOR_OBJECT_ID_SVIDEO,
		1718	&hpd);
1123	serge	1719	break;
		1720	case CT_POWERBOOK_EXTERNAL:
		1721	DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
		1722	rdev->mode_info.connector_table);
		1723	/* LVDS */
1963	serge	1724	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1725	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1726	radeon_add_legacy_encoder(dev,
1963	serge	1727	radeon_get_encoder_enum(dev,
1123	serge	1728	ATOM_DEVICE_LCD1_SUPPORT,
		1729	0),
		1730	ATOM_DEVICE_LCD1_SUPPORT);
		1731	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1732	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1733	CONNECTOR_OBJECT_ID_LVDS,
		1734	&hpd);
1123	serge	1735	/* DVI-I - primary dac, ext tmds */
1963	serge	1736	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1737	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1738	radeon_add_legacy_encoder(dev,
1963	serge	1739	radeon_get_encoder_enum(dev,
1123	serge	1740	ATOM_DEVICE_DFP2_SUPPORT,
		1741	0),
		1742	ATOM_DEVICE_DFP2_SUPPORT);
		1743	radeon_add_legacy_encoder(dev,
1963	serge	1744	radeon_get_encoder_enum(dev,
1123	serge	1745	ATOM_DEVICE_CRT1_SUPPORT,
		1746	1),
		1747	ATOM_DEVICE_CRT1_SUPPORT);
1268	serge	1748	/* XXX some are SL */
1123	serge	1749	radeon_add_legacy_connector(dev, 1,
		1750	ATOM_DEVICE_DFP2_SUPPORT \|
		1751	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1752	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1753	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		1754	&hpd);
1123	serge	1755	/* TV - TV DAC */
1321	serge	1756	ddc_i2c.valid = false;
		1757	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1758	radeon_add_legacy_encoder(dev,
1963	serge	1759	radeon_get_encoder_enum(dev,
1123	serge	1760	ATOM_DEVICE_TV1_SUPPORT,
		1761	2),
		1762	ATOM_DEVICE_TV1_SUPPORT);
		1763	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1764	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1765	&ddc_i2c,
1321	serge	1766	CONNECTOR_OBJECT_ID_SVIDEO,
		1767	&hpd);
1123	serge	1768	break;
		1769	case CT_POWERBOOK_INTERNAL:
		1770	DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
		1771	rdev->mode_info.connector_table);
		1772	/* LVDS */
1963	serge	1773	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1774	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1775	radeon_add_legacy_encoder(dev,
1963	serge	1776	radeon_get_encoder_enum(dev,
1123	serge	1777	ATOM_DEVICE_LCD1_SUPPORT,
		1778	0),
		1779	ATOM_DEVICE_LCD1_SUPPORT);
		1780	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1781	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1782	CONNECTOR_OBJECT_ID_LVDS,
		1783	&hpd);
1123	serge	1784	/* DVI-I - primary dac, int tmds */
1963	serge	1785	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1786	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1787	radeon_add_legacy_encoder(dev,
1963	serge	1788	radeon_get_encoder_enum(dev,
1123	serge	1789	ATOM_DEVICE_DFP1_SUPPORT,
		1790	0),
		1791	ATOM_DEVICE_DFP1_SUPPORT);
		1792	radeon_add_legacy_encoder(dev,
1963	serge	1793	radeon_get_encoder_enum(dev,
1123	serge	1794	ATOM_DEVICE_CRT1_SUPPORT,
		1795	1),
		1796	ATOM_DEVICE_CRT1_SUPPORT);
		1797	radeon_add_legacy_connector(dev, 1,
		1798	ATOM_DEVICE_DFP1_SUPPORT \|
		1799	ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1800	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1801	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1802	&hpd);
1123	serge	1803	/* TV - TV DAC */
1321	serge	1804	ddc_i2c.valid = false;
		1805	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1806	radeon_add_legacy_encoder(dev,
1963	serge	1807	radeon_get_encoder_enum(dev,
1123	serge	1808	ATOM_DEVICE_TV1_SUPPORT,
		1809	2),
		1810	ATOM_DEVICE_TV1_SUPPORT);
		1811	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1812	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1813	&ddc_i2c,
1321	serge	1814	CONNECTOR_OBJECT_ID_SVIDEO,
		1815	&hpd);
1123	serge	1816	break;
		1817	case CT_POWERBOOK_VGA:
		1818	DRM_INFO("Connector Table: %d (powerbook vga)\n",
		1819	rdev->mode_info.connector_table);
		1820	/* LVDS */
1963	serge	1821	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1822	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1823	radeon_add_legacy_encoder(dev,
1963	serge	1824	radeon_get_encoder_enum(dev,
1123	serge	1825	ATOM_DEVICE_LCD1_SUPPORT,
		1826	0),
		1827	ATOM_DEVICE_LCD1_SUPPORT);
		1828	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1268	serge	1829	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1321	serge	1830	CONNECTOR_OBJECT_ID_LVDS,
		1831	&hpd);
1123	serge	1832	/* VGA - primary dac */
1963	serge	1833	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1834	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1835	radeon_add_legacy_encoder(dev,
1963	serge	1836	radeon_get_encoder_enum(dev,
1123	serge	1837	ATOM_DEVICE_CRT1_SUPPORT,
		1838	1),
		1839	ATOM_DEVICE_CRT1_SUPPORT);
		1840	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1841	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1842	CONNECTOR_OBJECT_ID_VGA,
		1843	&hpd);
1123	serge	1844	/* TV - TV DAC */
1321	serge	1845	ddc_i2c.valid = false;
		1846	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1847	radeon_add_legacy_encoder(dev,
1963	serge	1848	radeon_get_encoder_enum(dev,
1123	serge	1849	ATOM_DEVICE_TV1_SUPPORT,
		1850	2),
		1851	ATOM_DEVICE_TV1_SUPPORT);
		1852	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1853	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1854	&ddc_i2c,
1321	serge	1855	CONNECTOR_OBJECT_ID_SVIDEO,
		1856	&hpd);
1123	serge	1857	break;
		1858	case CT_MINI_EXTERNAL:
		1859	DRM_INFO("Connector Table: %d (mini external tmds)\n",
		1860	rdev->mode_info.connector_table);
		1861	/* DVI-I - tv dac, ext tmds */
1963	serge	1862	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1863	hpd.hpd = RADEON_HPD_2; /* ??? */
1123	serge	1864	radeon_add_legacy_encoder(dev,
1963	serge	1865	radeon_get_encoder_enum(dev,
1123	serge	1866	ATOM_DEVICE_DFP2_SUPPORT,
		1867	0),
		1868	ATOM_DEVICE_DFP2_SUPPORT);
		1869	radeon_add_legacy_encoder(dev,
1963	serge	1870	radeon_get_encoder_enum(dev,
1123	serge	1871	ATOM_DEVICE_CRT2_SUPPORT,
		1872	2),
		1873	ATOM_DEVICE_CRT2_SUPPORT);
1268	serge	1874	/* XXX are any DL? */
1123	serge	1875	radeon_add_legacy_connector(dev, 0,
		1876	ATOM_DEVICE_DFP2_SUPPORT \|
		1877	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1878	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1879	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1880	&hpd);
1123	serge	1881	/* TV - TV DAC */
1321	serge	1882	ddc_i2c.valid = false;
		1883	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1884	radeon_add_legacy_encoder(dev,
1963	serge	1885	radeon_get_encoder_enum(dev,
1123	serge	1886	ATOM_DEVICE_TV1_SUPPORT,
		1887	2),
		1888	ATOM_DEVICE_TV1_SUPPORT);
		1889	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1890	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1891	&ddc_i2c,
1321	serge	1892	CONNECTOR_OBJECT_ID_SVIDEO,
		1893	&hpd);
1123	serge	1894	break;
		1895	case CT_MINI_INTERNAL:
		1896	DRM_INFO("Connector Table: %d (mini internal tmds)\n",
		1897	rdev->mode_info.connector_table);
		1898	/* DVI-I - tv dac, int tmds */
1963	serge	1899	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1900	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1901	radeon_add_legacy_encoder(dev,
1963	serge	1902	radeon_get_encoder_enum(dev,
1123	serge	1903	ATOM_DEVICE_DFP1_SUPPORT,
		1904	0),
		1905	ATOM_DEVICE_DFP1_SUPPORT);
		1906	radeon_add_legacy_encoder(dev,
1963	serge	1907	radeon_get_encoder_enum(dev,
1123	serge	1908	ATOM_DEVICE_CRT2_SUPPORT,
		1909	2),
		1910	ATOM_DEVICE_CRT2_SUPPORT);
		1911	radeon_add_legacy_connector(dev, 0,
		1912	ATOM_DEVICE_DFP1_SUPPORT \|
		1913	ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1914	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1321	serge	1915	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		1916	&hpd);
1123	serge	1917	/* TV - TV DAC */
1321	serge	1918	ddc_i2c.valid = false;
		1919	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1920	radeon_add_legacy_encoder(dev,
1963	serge	1921	radeon_get_encoder_enum(dev,
1123	serge	1922	ATOM_DEVICE_TV1_SUPPORT,
		1923	2),
		1924	ATOM_DEVICE_TV1_SUPPORT);
		1925	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1926	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1927	&ddc_i2c,
1321	serge	1928	CONNECTOR_OBJECT_ID_SVIDEO,
		1929	&hpd);
1123	serge	1930	break;
		1931	case CT_IMAC_G5_ISIGHT:
		1932	DRM_INFO("Connector Table: %d (imac g5 isight)\n",
		1933	rdev->mode_info.connector_table);
		1934	/* DVI-D - int tmds */
1963	serge	1935	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1321	serge	1936	hpd.hpd = RADEON_HPD_1; /* ??? */
1123	serge	1937	radeon_add_legacy_encoder(dev,
1963	serge	1938	radeon_get_encoder_enum(dev,
1123	serge	1939	ATOM_DEVICE_DFP1_SUPPORT,
		1940	0),
		1941	ATOM_DEVICE_DFP1_SUPPORT);
		1942	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1268	serge	1943	DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1321	serge	1944	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		1945	&hpd);
1123	serge	1946	/* VGA - tv dac */
1963	serge	1947	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1321	serge	1948	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1949	radeon_add_legacy_encoder(dev,
1963	serge	1950	radeon_get_encoder_enum(dev,
1123	serge	1951	ATOM_DEVICE_CRT2_SUPPORT,
		1952	2),
		1953	ATOM_DEVICE_CRT2_SUPPORT);
		1954	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1955	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1956	CONNECTOR_OBJECT_ID_VGA,
		1957	&hpd);
1123	serge	1958	/* TV - TV DAC */
1321	serge	1959	ddc_i2c.valid = false;
		1960	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1961	radeon_add_legacy_encoder(dev,
1963	serge	1962	radeon_get_encoder_enum(dev,
1123	serge	1963	ATOM_DEVICE_TV1_SUPPORT,
		1964	2),
		1965	ATOM_DEVICE_TV1_SUPPORT);
		1966	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1967	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	1968	&ddc_i2c,
1321	serge	1969	CONNECTOR_OBJECT_ID_SVIDEO,
		1970	&hpd);
1123	serge	1971	break;
		1972	case CT_EMAC:
		1973	DRM_INFO("Connector Table: %d (emac)\n",
		1974	rdev->mode_info.connector_table);
		1975	/* VGA - primary dac */
1963	serge	1976	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	1977	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1978	radeon_add_legacy_encoder(dev,
1963	serge	1979	radeon_get_encoder_enum(dev,
1123	serge	1980	ATOM_DEVICE_CRT1_SUPPORT,
		1981	1),
		1982	ATOM_DEVICE_CRT1_SUPPORT);
		1983	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1268	serge	1984	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1985	CONNECTOR_OBJECT_ID_VGA,
		1986	&hpd);
1123	serge	1987	/* VGA - tv dac */
1963	serge	1988	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1321	serge	1989	hpd.hpd = RADEON_HPD_NONE;
1123	serge	1990	radeon_add_legacy_encoder(dev,
1963	serge	1991	radeon_get_encoder_enum(dev,
1123	serge	1992	ATOM_DEVICE_CRT2_SUPPORT,
		1993	2),
		1994	ATOM_DEVICE_CRT2_SUPPORT);
		1995	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1268	serge	1996	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1321	serge	1997	CONNECTOR_OBJECT_ID_VGA,
		1998	&hpd);
1123	serge	1999	/* TV - TV DAC */
1321	serge	2000	ddc_i2c.valid = false;
		2001	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2002	radeon_add_legacy_encoder(dev,
1963	serge	2003	radeon_get_encoder_enum(dev,
1123	serge	2004	ATOM_DEVICE_TV1_SUPPORT,
		2005	2),
		2006	ATOM_DEVICE_TV1_SUPPORT);
		2007	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2008	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2009	&ddc_i2c,
1321	serge	2010	CONNECTOR_OBJECT_ID_SVIDEO,
		2011	&hpd);
1123	serge	2012	break;
1963	serge	2013	case CT_RN50_POWER:
		2014	DRM_INFO("Connector Table: %d (rn50-power)\n",
		2015	rdev->mode_info.connector_table);
		2016	/* VGA - primary dac */
		2017	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2018	hpd.hpd = RADEON_HPD_NONE;
		2019	radeon_add_legacy_encoder(dev,
		2020	radeon_get_encoder_enum(dev,
		2021	ATOM_DEVICE_CRT1_SUPPORT,
		2022	1),
		2023	ATOM_DEVICE_CRT1_SUPPORT);
		2024	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
		2025	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2026	CONNECTOR_OBJECT_ID_VGA,
		2027	&hpd);
		2028	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
		2029	hpd.hpd = RADEON_HPD_NONE;
		2030	radeon_add_legacy_encoder(dev,
		2031	radeon_get_encoder_enum(dev,
		2032	ATOM_DEVICE_CRT2_SUPPORT,
		2033	2),
		2034	ATOM_DEVICE_CRT2_SUPPORT);
		2035	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		2036	DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
		2037	CONNECTOR_OBJECT_ID_VGA,
		2038	&hpd);
		2039	break;
		2040	case CT_MAC_X800:
		2041	DRM_INFO("Connector Table: %d (mac x800)\n",
		2042	rdev->mode_info.connector_table);
		2043	/* DVI - primary dac, internal tmds */
		2044	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2045	hpd.hpd = RADEON_HPD_1; /* ??? */
		2046	radeon_add_legacy_encoder(dev,
		2047	radeon_get_encoder_enum(dev,
		2048	ATOM_DEVICE_DFP1_SUPPORT,
		2049	0),
		2050	ATOM_DEVICE_DFP1_SUPPORT);
		2051	radeon_add_legacy_encoder(dev,
		2052	radeon_get_encoder_enum(dev,
		2053	ATOM_DEVICE_CRT1_SUPPORT,
		2054	1),
		2055	ATOM_DEVICE_CRT1_SUPPORT);
		2056	radeon_add_legacy_connector(dev, 0,
		2057	ATOM_DEVICE_DFP1_SUPPORT \|
		2058	ATOM_DEVICE_CRT1_SUPPORT,
		2059	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2060	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2061	&hpd);
		2062	/* DVI - tv dac, dvo */
		2063	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
		2064	hpd.hpd = RADEON_HPD_2; /* ??? */
		2065	radeon_add_legacy_encoder(dev,
		2066	radeon_get_encoder_enum(dev,
		2067	ATOM_DEVICE_DFP2_SUPPORT,
		2068	0),
		2069	ATOM_DEVICE_DFP2_SUPPORT);
		2070	radeon_add_legacy_encoder(dev,
		2071	radeon_get_encoder_enum(dev,
		2072	ATOM_DEVICE_CRT2_SUPPORT,
		2073	2),
		2074	ATOM_DEVICE_CRT2_SUPPORT);
		2075	radeon_add_legacy_connector(dev, 1,
		2076	ATOM_DEVICE_DFP2_SUPPORT \|
		2077	ATOM_DEVICE_CRT2_SUPPORT,
		2078	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2079	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
		2080	&hpd);
		2081	break;
		2082	case CT_MAC_G5_9600:
		2083	DRM_INFO("Connector Table: %d (mac g5 9600)\n",
		2084	rdev->mode_info.connector_table);
		2085	/* DVI - tv dac, dvo */
		2086	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2087	hpd.hpd = RADEON_HPD_1; /* ??? */
		2088	radeon_add_legacy_encoder(dev,
		2089	radeon_get_encoder_enum(dev,
		2090	ATOM_DEVICE_DFP2_SUPPORT,
		2091	0),
		2092	ATOM_DEVICE_DFP2_SUPPORT);
		2093	radeon_add_legacy_encoder(dev,
		2094	radeon_get_encoder_enum(dev,
		2095	ATOM_DEVICE_CRT2_SUPPORT,
		2096	2),
		2097	ATOM_DEVICE_CRT2_SUPPORT);
		2098	radeon_add_legacy_connector(dev, 0,
		2099	ATOM_DEVICE_DFP2_SUPPORT \|
		2100	ATOM_DEVICE_CRT2_SUPPORT,
		2101	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2102	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2103	&hpd);
		2104	/* ADC - primary dac, internal tmds */
		2105	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
		2106	hpd.hpd = RADEON_HPD_2; /* ??? */
		2107	radeon_add_legacy_encoder(dev,
		2108	radeon_get_encoder_enum(dev,
		2109	ATOM_DEVICE_DFP1_SUPPORT,
		2110	0),
		2111	ATOM_DEVICE_DFP1_SUPPORT);
		2112	radeon_add_legacy_encoder(dev,
		2113	radeon_get_encoder_enum(dev,
		2114	ATOM_DEVICE_CRT1_SUPPORT,
		2115	1),
		2116	ATOM_DEVICE_CRT1_SUPPORT);
		2117	radeon_add_legacy_connector(dev, 1,
		2118	ATOM_DEVICE_DFP1_SUPPORT \|
		2119	ATOM_DEVICE_CRT1_SUPPORT,
		2120	DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
		2121	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2122	&hpd);
		2123	/* TV - TV DAC */
		2124	ddc_i2c.valid = false;
		2125	hpd.hpd = RADEON_HPD_NONE;
		2126	radeon_add_legacy_encoder(dev,
		2127	radeon_get_encoder_enum(dev,
		2128	ATOM_DEVICE_TV1_SUPPORT,
		2129	2),
		2130	ATOM_DEVICE_TV1_SUPPORT);
		2131	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		2132	DRM_MODE_CONNECTOR_SVIDEO,
		2133	&ddc_i2c,
		2134	CONNECTOR_OBJECT_ID_SVIDEO,
		2135	&hpd);
		2136	break;
1123	serge	2137	default:
		2138	DRM_INFO("Connector table: %d (invalid)\n",
		2139	rdev->mode_info.connector_table);
		2140	return false;
		2141	}
		2142
		2143	radeon_link_encoder_connector(dev);
		2144
		2145	return true;
		2146	}
		2147
		2148	static bool radeon_apply_legacy_quirks(struct drm_device *dev,
		2149	int bios_index,
		2150	enum radeon_combios_connector
		2151	*legacy_connector,
1321	serge	2152	struct radeon_i2c_bus_rec *ddc_i2c,
		2153	struct radeon_hpd *hpd)
1123	serge	2154	{
		2155
		2156	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
		2157	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
		2158	if (dev->pdev->device == 0x515e &&
		2159	dev->pdev->subsystem_vendor == 0x1014) {
		2160	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
		2161	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		2162	return false;
		2163	}
		2164
		2165	/* X300 card with extra non-existent DVI port */
		2166	if (dev->pdev->device == 0x5B60 &&
		2167	dev->pdev->subsystem_vendor == 0x17af &&
		2168	dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
		2169	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		2170	return false;
		2171	}
		2172
		2173	return true;
		2174	}
		2175
1268	serge	2176	static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
		2177	{
		2178	/* Acer 5102 has non-existent TV port */
		2179	if (dev->pdev->device == 0x5975 &&
		2180	dev->pdev->subsystem_vendor == 0x1025 &&
		2181	dev->pdev->subsystem_device == 0x009f)
		2182	return false;
		2183
		2184	/* HP dc5750 has non-existent TV port */
		2185	if (dev->pdev->device == 0x5974 &&
		2186	dev->pdev->subsystem_vendor == 0x103c &&
		2187	dev->pdev->subsystem_device == 0x280a)
		2188	return false;
		2189
1321	serge	2190	/* MSI S270 has non-existent TV port */
		2191	if (dev->pdev->device == 0x5955 &&
		2192	dev->pdev->subsystem_vendor == 0x1462 &&
		2193	dev->pdev->subsystem_device == 0x0131)
		2194	return false;
		2195
1268	serge	2196	return true;
		2197	}
		2198
		2199	static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
		2200	{
		2201	struct radeon_device *rdev = dev->dev_private;
		2202	uint32_t ext_tmds_info;
		2203
		2204	if (rdev->flags & RADEON_IS_IGP) {
		2205	if (is_dvi_d)
		2206	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2207	else
		2208	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2209	}
		2210	ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		2211	if (ext_tmds_info) {
		2212	uint8_t rev = RBIOS8(ext_tmds_info);
		2213	uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
		2214	if (rev >= 3) {
		2215	if (is_dvi_d)
		2216	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2217	else
		2218	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2219	} else {
		2220	if (flags & 1) {
		2221	if (is_dvi_d)
		2222	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		2223	else
		2224	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		2225	}
		2226	}
		2227	}
		2228	if (is_dvi_d)
		2229	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		2230	else
		2231	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2232	}
		2233
1123	serge	2234	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
		2235	{
		2236	struct radeon_device *rdev = dev->dev_private;
		2237	uint32_t conn_info, entry, devices;
1268	serge	2238	uint16_t tmp, connector_object_id;
1123	serge	2239	enum radeon_combios_ddc ddc_type;
		2240	enum radeon_combios_connector connector;
		2241	int i = 0;
		2242	struct radeon_i2c_bus_rec ddc_i2c;
1321	serge	2243	struct radeon_hpd hpd;
1123	serge	2244
		2245	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
		2246	if (conn_info) {
		2247	for (i = 0; i < 4; i++) {
		2248	entry = conn_info + 2 + i * 2;
		2249
		2250	if (!RBIOS16(entry))
		2251	break;
		2252
		2253	tmp = RBIOS16(entry);
		2254
		2255	connector = (tmp >> 12) & 0xf;
		2256
		2257	ddc_type = (tmp >> 8) & 0xf;
1963	serge	2258	ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2259
1321	serge	2260	switch (connector) {
		2261	case CONNECTOR_PROPRIETARY_LEGACY:
		2262	case CONNECTOR_DVI_I_LEGACY:
		2263	case CONNECTOR_DVI_D_LEGACY:
		2264	if ((tmp >> 4) & 0x1)
		2265	hpd.hpd = RADEON_HPD_2;
		2266	else
		2267	hpd.hpd = RADEON_HPD_1;
		2268	break;
		2269	default:
		2270	hpd.hpd = RADEON_HPD_NONE;
		2271	break;
		2272	}
		2273
1268	serge	2274	if (!radeon_apply_legacy_quirks(dev, i, &connector,
1321	serge	2275	&ddc_i2c, &hpd))
1268	serge	2276	continue;
1123	serge	2277
		2278	switch (connector) {
		2279	case CONNECTOR_PROPRIETARY_LEGACY:
		2280	if ((tmp >> 4) & 0x1)
		2281	devices = ATOM_DEVICE_DFP2_SUPPORT;
		2282	else
		2283	devices = ATOM_DEVICE_DFP1_SUPPORT;
		2284	radeon_add_legacy_encoder(dev,
1963	serge	2285	radeon_get_encoder_enum
1123	serge	2286	(dev, devices, 0),
		2287	devices);
		2288	radeon_add_legacy_connector(dev, i, devices,
		2289	legacy_connector_convert
		2290	[connector],
1268	serge	2291	&ddc_i2c,
1321	serge	2292	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
		2293	&hpd);
1123	serge	2294	break;
		2295	case CONNECTOR_CRT_LEGACY:
		2296	if (tmp & 0x1) {
		2297	devices = ATOM_DEVICE_CRT2_SUPPORT;
		2298	radeon_add_legacy_encoder(dev,
1963	serge	2299	radeon_get_encoder_enum
1123	serge	2300	(dev,
		2301	ATOM_DEVICE_CRT2_SUPPORT,
		2302	2),
		2303	ATOM_DEVICE_CRT2_SUPPORT);
		2304	} else {
		2305	devices = ATOM_DEVICE_CRT1_SUPPORT;
		2306	radeon_add_legacy_encoder(dev,
1963	serge	2307	radeon_get_encoder_enum
1123	serge	2308	(dev,
		2309	ATOM_DEVICE_CRT1_SUPPORT,
		2310	1),
		2311	ATOM_DEVICE_CRT1_SUPPORT);
		2312	}
		2313	radeon_add_legacy_connector(dev,
		2314	i,
		2315	devices,
		2316	legacy_connector_convert
		2317	[connector],
1268	serge	2318	&ddc_i2c,
1321	serge	2319	CONNECTOR_OBJECT_ID_VGA,
		2320	&hpd);
1123	serge	2321	break;
		2322	case CONNECTOR_DVI_I_LEGACY:
		2323	devices = 0;
		2324	if (tmp & 0x1) {
		2325	devices \|= ATOM_DEVICE_CRT2_SUPPORT;
		2326	radeon_add_legacy_encoder(dev,
1963	serge	2327	radeon_get_encoder_enum
1123	serge	2328	(dev,
		2329	ATOM_DEVICE_CRT2_SUPPORT,
		2330	2),
		2331	ATOM_DEVICE_CRT2_SUPPORT);
		2332	} else {
		2333	devices \|= ATOM_DEVICE_CRT1_SUPPORT;
		2334	radeon_add_legacy_encoder(dev,
1963	serge	2335	radeon_get_encoder_enum
1123	serge	2336	(dev,
		2337	ATOM_DEVICE_CRT1_SUPPORT,
		2338	1),
		2339	ATOM_DEVICE_CRT1_SUPPORT);
		2340	}
		2341	if ((tmp >> 4) & 0x1) {
		2342	devices \|= ATOM_DEVICE_DFP2_SUPPORT;
		2343	radeon_add_legacy_encoder(dev,
1963	serge	2344	radeon_get_encoder_enum
1123	serge	2345	(dev,
		2346	ATOM_DEVICE_DFP2_SUPPORT,
		2347	0),
		2348	ATOM_DEVICE_DFP2_SUPPORT);
1268	serge	2349	connector_object_id = combios_check_dl_dvi(dev, 0);
1123	serge	2350	} else {
		2351	devices \|= ATOM_DEVICE_DFP1_SUPPORT;
		2352	radeon_add_legacy_encoder(dev,
1963	serge	2353	radeon_get_encoder_enum
1123	serge	2354	(dev,
		2355	ATOM_DEVICE_DFP1_SUPPORT,
		2356	0),
		2357	ATOM_DEVICE_DFP1_SUPPORT);
1268	serge	2358	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1123	serge	2359	}
		2360	radeon_add_legacy_connector(dev,
		2361	i,
		2362	devices,
		2363	legacy_connector_convert
		2364	[connector],
1268	serge	2365	&ddc_i2c,
1321	serge	2366	connector_object_id,
		2367	&hpd);
1123	serge	2368	break;
		2369	case CONNECTOR_DVI_D_LEGACY:
1268	serge	2370	if ((tmp >> 4) & 0x1) {
1123	serge	2371	devices = ATOM_DEVICE_DFP2_SUPPORT;
1268	serge	2372	connector_object_id = combios_check_dl_dvi(dev, 1);
		2373	} else {
1123	serge	2374	devices = ATOM_DEVICE_DFP1_SUPPORT;
1268	serge	2375	connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		2376	}
1123	serge	2377	radeon_add_legacy_encoder(dev,
1963	serge	2378	radeon_get_encoder_enum
1123	serge	2379	(dev, devices, 0),
		2380	devices);
		2381	radeon_add_legacy_connector(dev, i, devices,
		2382	legacy_connector_convert
		2383	[connector],
1268	serge	2384	&ddc_i2c,
1321	serge	2385	connector_object_id,
		2386	&hpd);
1123	serge	2387	break;
		2388	case CONNECTOR_CTV_LEGACY:
		2389	case CONNECTOR_STV_LEGACY:
		2390	radeon_add_legacy_encoder(dev,
1963	serge	2391	radeon_get_encoder_enum
1123	serge	2392	(dev,
		2393	ATOM_DEVICE_TV1_SUPPORT,
		2394	2),
		2395	ATOM_DEVICE_TV1_SUPPORT);
		2396	radeon_add_legacy_connector(dev, i,
		2397	ATOM_DEVICE_TV1_SUPPORT,
		2398	legacy_connector_convert
		2399	[connector],
1268	serge	2400	&ddc_i2c,
1321	serge	2401	CONNECTOR_OBJECT_ID_SVIDEO,
		2402	&hpd);
1123	serge	2403	break;
		2404	default:
		2405	DRM_ERROR("Unknown connector type: %d\n",
		2406	connector);
		2407	continue;
		2408	}
		2409
		2410	}
		2411	} else {
		2412	uint16_t tmds_info =
		2413	combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		2414	if (tmds_info) {
1963	serge	2415	DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
1123	serge	2416
		2417	radeon_add_legacy_encoder(dev,
1963	serge	2418	radeon_get_encoder_enum(dev,
1123	serge	2419	ATOM_DEVICE_CRT1_SUPPORT,
		2420	1),
		2421	ATOM_DEVICE_CRT1_SUPPORT);
		2422	radeon_add_legacy_encoder(dev,
1963	serge	2423	radeon_get_encoder_enum(dev,
1123	serge	2424	ATOM_DEVICE_DFP1_SUPPORT,
		2425	0),
		2426	ATOM_DEVICE_DFP1_SUPPORT);
		2427
1963	serge	2428	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
		2429	hpd.hpd = RADEON_HPD_1;
1123	serge	2430	radeon_add_legacy_connector(dev,
		2431	0,
		2432	ATOM_DEVICE_CRT1_SUPPORT \|
		2433	ATOM_DEVICE_DFP1_SUPPORT,
		2434	DRM_MODE_CONNECTOR_DVII,
1268	serge	2435	&ddc_i2c,
1321	serge	2436	CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
		2437	&hpd);
1123	serge	2438	} else {
1268	serge	2439	uint16_t crt_info =
		2440	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1963	serge	2441	DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
1268	serge	2442	if (crt_info) {
		2443	radeon_add_legacy_encoder(dev,
1963	serge	2444	radeon_get_encoder_enum(dev,
1268	serge	2445	ATOM_DEVICE_CRT1_SUPPORT,
		2446	1),
		2447	ATOM_DEVICE_CRT1_SUPPORT);
1963	serge	2448	ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1321	serge	2449	hpd.hpd = RADEON_HPD_NONE;
1268	serge	2450	radeon_add_legacy_connector(dev,
		2451	0,
		2452	ATOM_DEVICE_CRT1_SUPPORT,
		2453	DRM_MODE_CONNECTOR_VGA,
		2454	&ddc_i2c,
1321	serge	2455	CONNECTOR_OBJECT_ID_VGA,
		2456	&hpd);
1268	serge	2457	} else {
1963	serge	2458	DRM_DEBUG_KMS("No connector info found\n");
1123	serge	2459	return false;
		2460	}
		2461	}
1268	serge	2462	}
1123	serge	2463
		2464	if (rdev->flags & RADEON_IS_MOBILITY \|\| rdev->flags & RADEON_IS_IGP) {
		2465	uint16_t lcd_info =
		2466	combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		2467	if (lcd_info) {
		2468	uint16_t lcd_ddc_info =
		2469	combios_get_table_offset(dev,
		2470	COMBIOS_LCD_DDC_INFO_TABLE);
		2471
		2472	radeon_add_legacy_encoder(dev,
1963	serge	2473	radeon_get_encoder_enum(dev,
1123	serge	2474	ATOM_DEVICE_LCD1_SUPPORT,
		2475	0),
		2476	ATOM_DEVICE_LCD1_SUPPORT);
		2477
		2478	if (lcd_ddc_info) {
		2479	ddc_type = RBIOS8(lcd_ddc_info + 2);
		2480	switch (ddc_type) {
		2481	case DDC_LCD:
		2482	ddc_i2c =
1963	serge	2483	combios_setup_i2c_bus(rdev,
		2484	DDC_LCD,
		2485	RBIOS32(lcd_ddc_info + 3),
		2486	RBIOS32(lcd_ddc_info + 7));
		2487	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2488	break;
		2489	case DDC_GPIO:
		2490	ddc_i2c =
1963	serge	2491	combios_setup_i2c_bus(rdev,
		2492	DDC_GPIO,
		2493	RBIOS32(lcd_ddc_info + 3),
		2494	RBIOS32(lcd_ddc_info + 7));
		2495	radeon_i2c_add(rdev, &ddc_i2c, "LCD");
1123	serge	2496	break;
		2497	default:
1963	serge	2498	ddc_i2c =
		2499	combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
1123	serge	2500	break;
		2501	}
1963	serge	2502	DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
1123	serge	2503	} else
		2504	ddc_i2c.valid = false;
		2505
1321	serge	2506	hpd.hpd = RADEON_HPD_NONE;
1123	serge	2507	radeon_add_legacy_connector(dev,
		2508	5,
		2509	ATOM_DEVICE_LCD1_SUPPORT,
		2510	DRM_MODE_CONNECTOR_LVDS,
1268	serge	2511	&ddc_i2c,
1321	serge	2512	CONNECTOR_OBJECT_ID_LVDS,
		2513	&hpd);
1123	serge	2514	}
		2515	}
		2516
		2517	/* check TV table */
		2518	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		2519	uint32_t tv_info =
		2520	combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		2521	if (tv_info) {
		2522	if (RBIOS8(tv_info + 6) == 'T') {
1268	serge	2523	if (radeon_apply_legacy_tv_quirks(dev)) {
1321	serge	2524	hpd.hpd = RADEON_HPD_NONE;
1963	serge	2525	ddc_i2c.valid = false;
1123	serge	2526	radeon_add_legacy_encoder(dev,
1963	serge	2527	radeon_get_encoder_enum
1123	serge	2528	(dev,
		2529	ATOM_DEVICE_TV1_SUPPORT,
		2530	2),
		2531	ATOM_DEVICE_TV1_SUPPORT);
		2532	radeon_add_legacy_connector(dev, 6,
		2533	ATOM_DEVICE_TV1_SUPPORT,
		2534	DRM_MODE_CONNECTOR_SVIDEO,
1268	serge	2535	&ddc_i2c,
1321	serge	2536	CONNECTOR_OBJECT_ID_SVIDEO,
		2537	&hpd);
1268	serge	2538	}
1123	serge	2539	}
		2540	}
		2541	}
		2542
		2543	radeon_link_encoder_connector(dev);
		2544
		2545	return true;
		2546	}
		2547
1963	serge	2548	static const char *thermal_controller_names[] = {
		2549	"NONE",
		2550	"lm63",
		2551	"adm1032",
		2552	};
		2553
1430	serge	2554	void radeon_combios_get_power_modes(struct radeon_device *rdev)
		2555	{
		2556	struct drm_device *dev = rdev->ddev;
		2557	u16 offset, misc, misc2 = 0;
		2558	u8 rev, blocks, tmp;
		2559	int state_index = 0;
2160	serge	2560	struct radeon_i2c_bus_rec i2c_bus;
1430	serge	2561
1963	serge	2562	rdev->pm.default_power_state_index = -1;
1430	serge	2563
1963	serge	2564	/* allocate 2 power states */
		2565	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
		2566	if (!rdev->pm.power_state) {
		2567	rdev->pm.default_power_state_index = state_index;
		2568	rdev->pm.num_power_states = 0;
		2569
		2570	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2571	rdev->pm.current_clock_mode_index = 0;
		2572	return;
		2573	}
		2574
		2575	/* check for a thermal chip */
		2576	offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
		2577	if (offset) {
		2578	u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
		2579
		2580	rev = RBIOS8(offset);
		2581
		2582	if (rev == 0) {
		2583	thermal_controller = RBIOS8(offset + 3);
		2584	gpio = RBIOS8(offset + 4) & 0x3f;
		2585	i2c_addr = RBIOS8(offset + 5);
		2586	} else if (rev == 1) {
		2587	thermal_controller = RBIOS8(offset + 4);
		2588	gpio = RBIOS8(offset + 5) & 0x3f;
		2589	i2c_addr = RBIOS8(offset + 6);
		2590	} else if (rev == 2) {
		2591	thermal_controller = RBIOS8(offset + 4);
		2592	gpio = RBIOS8(offset + 5) & 0x3f;
		2593	i2c_addr = RBIOS8(offset + 6);
		2594	clk_bit = RBIOS8(offset + 0xa);
		2595	data_bit = RBIOS8(offset + 0xb);
		2596	}
		2597	if ((thermal_controller > 0) && (thermal_controller < 3)) {
		2598	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2599	thermal_controller_names[thermal_controller],
		2600	i2c_addr >> 1);
		2601	if (gpio == DDC_LCD) {
		2602	/* MM i2c */
		2603	i2c_bus.valid = true;
		2604	i2c_bus.hw_capable = true;
		2605	i2c_bus.mm_i2c = true;
		2606	i2c_bus.i2c_id = 0xa0;
		2607	} else if (gpio == DDC_GPIO)
		2608	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
		2609	else
		2610	i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
		2611	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2612	if (rdev->pm.i2c_bus) {
		2613	struct i2c_board_info info = { };
		2614	const char *name = thermal_controller_names[thermal_controller];
		2615	info.addr = i2c_addr >> 1;
		2616	strlcpy(info.type, name, sizeof(info.type));
		2617	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2618	}
		2619	}
		2620	}
		2621
1430	serge	2622	if (rdev->flags & RADEON_IS_MOBILITY) {
		2623	offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
		2624	if (offset) {
		2625	rev = RBIOS8(offset);
		2626	blocks = RBIOS8(offset + 0x2);
		2627	/* power mode 0 tends to be the only valid one */
		2628	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2629	rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
		2630	rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
		2631	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2632	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2633	goto default_mode;
		2634	rdev->pm.power_state[state_index].type =
		2635	POWER_STATE_TYPE_BATTERY;
		2636	misc = RBIOS16(offset + 0x5 + 0x0);
		2637	if (rev > 4)
		2638	misc2 = RBIOS16(offset + 0x5 + 0xe);
1963	serge	2639	rdev->pm.power_state[state_index].misc = misc;
		2640	rdev->pm.power_state[state_index].misc2 = misc2;
1430	serge	2641	if (misc & 0x4) {
		2642	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
		2643	if (misc & 0x8)
		2644	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2645	true;
		2646	else
		2647	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2648	false;
		2649	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
		2650	if (rev < 6) {
		2651	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2652	RBIOS16(offset + 0x5 + 0xb) * 4;
		2653	tmp = RBIOS8(offset + 0x5 + 0xd);
		2654	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2655	} else {
		2656	u8 entries = RBIOS8(offset + 0x5 + 0xb);
		2657	u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
		2658	if (entries && voltage_table_offset) {
		2659	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
		2660	RBIOS16(voltage_table_offset) * 4;
		2661	tmp = RBIOS8(voltage_table_offset + 0x2);
		2662	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
		2663	} else
		2664	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
		2665	}
		2666	switch ((misc2 & 0x700) >> 8) {
		2667	case 0:
		2668	default:
		2669	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
		2670	break;
		2671	case 1:
		2672	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
		2673	break;
		2674	case 2:
		2675	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
		2676	break;
		2677	case 3:
		2678	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
		2679	break;
		2680	case 4:
		2681	rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
		2682	break;
		2683	}
		2684	} else
		2685	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2686	if (rev > 6)
1963	serge	2687	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2688	RBIOS8(offset + 0x5 + 0x10);
1963	serge	2689	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2690	state_index++;
		2691	} else {
		2692	/* XXX figure out some good default low power mode for mobility cards w/out power tables */
		2693	}
		2694	} else {
		2695	/* XXX figure out some good default low power mode for desktop cards */
		2696	}
		2697
		2698	default_mode:
		2699	/* add the default mode */
		2700	rdev->pm.power_state[state_index].type =
		2701	POWER_STATE_TYPE_DEFAULT;
		2702	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2703	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2704	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2705	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
1963	serge	2706	if ((state_index > 0) &&
		2707	(rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
		2708	rdev->pm.power_state[state_index].clock_info[0].voltage =
		2709	rdev->pm.power_state[0].clock_info[0].voltage;
		2710	else
1430	serge	2711	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2712	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2713	rdev->pm.power_state[state_index].flags = 0;
		2714	rdev->pm.default_power_state_index = state_index;
1430	serge	2715	rdev->pm.num_power_states = state_index + 1;
		2716
1963	serge	2717	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2718	rdev->pm.current_clock_mode_index = 0;
1430	serge	2719	}
		2720
1321	serge	2721	void radeon_external_tmds_setup(struct drm_encoder *encoder)
		2722	{
		2723	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2724	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2725
		2726	if (!tmds)
		2727	return;
		2728
		2729	switch (tmds->dvo_chip) {
		2730	case DVO_SIL164:
		2731	/* sil 164 */
1430	serge	2732	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2733	tmds->slave_addr,
		2734	0x08, 0x30);
1430	serge	2735	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2736	tmds->slave_addr,
		2737	0x09, 0x00);
1430	serge	2738	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2739	tmds->slave_addr,
		2740	0x0a, 0x90);
1430	serge	2741	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2742	tmds->slave_addr,
		2743	0x0c, 0x89);
1430	serge	2744	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2745	tmds->slave_addr,
		2746	0x08, 0x3b);
		2747	break;
		2748	case DVO_SIL1178:
		2749	/* sil 1178 - untested */
		2750	/*
		2751	* 0x0f, 0x44
		2752	* 0x0f, 0x4c
		2753	* 0x0e, 0x01
		2754	* 0x0a, 0x80
		2755	* 0x09, 0x30
		2756	* 0x0c, 0xc9
		2757	* 0x0d, 0x70
		2758	* 0x08, 0x32
		2759	* 0x08, 0x33
		2760	*/
		2761	break;
		2762	default:
		2763	break;
		2764	}
		2765
		2766	}
		2767
		2768	bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
		2769	{
		2770	struct drm_device *dev = encoder->dev;
		2771	struct radeon_device *rdev = dev->dev_private;
		2772	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2773	uint16_t offset;
		2774	uint8_t blocks, slave_addr, rev;
		2775	uint32_t index, id;
		2776	uint32_t reg, val, and_mask, or_mask;
		2777	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
		2778
		2779	if (!tmds)
		2780	return false;
		2781
		2782	if (rdev->flags & RADEON_IS_IGP) {
		2783	offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
		2784	rev = RBIOS8(offset);
		2785	if (offset) {
		2786	rev = RBIOS8(offset);
		2787	if (rev > 1) {
		2788	blocks = RBIOS8(offset + 3);
		2789	index = offset + 4;
		2790	while (blocks > 0) {
		2791	id = RBIOS16(index);
		2792	index += 2;
		2793	switch (id >> 13) {
		2794	case 0:
		2795	reg = (id & 0x1fff) * 4;
		2796	val = RBIOS32(index);
		2797	index += 4;
		2798	WREG32(reg, val);
		2799	break;
		2800	case 2:
		2801	reg = (id & 0x1fff) * 4;
		2802	and_mask = RBIOS32(index);
		2803	index += 4;
		2804	or_mask = RBIOS32(index);
		2805	index += 4;
		2806	val = RREG32(reg);
		2807	val = (val & and_mask) \| or_mask;
		2808	WREG32(reg, val);
		2809	break;
		2810	case 3:
		2811	val = RBIOS16(index);
		2812	index += 2;
		2813	udelay(val);
		2814	break;
		2815	case 4:
		2816	val = RBIOS16(index);
		2817	index += 2;
		2818	udelay(val * 1000);
		2819	break;
		2820	case 6:
		2821	slave_addr = id & 0xff;
		2822	slave_addr >>= 1; /* 7 bit addressing */
		2823	index++;
		2824	reg = RBIOS8(index);
		2825	index++;
		2826	val = RBIOS8(index);
		2827	index++;
1430	serge	2828	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2829	slave_addr,
		2830	reg, val);
		2831	break;
		2832	default:
		2833	DRM_ERROR("Unknown id %d\n", id >> 13);
		2834	break;
		2835	}
		2836	blocks--;
		2837	}
		2838	return true;
		2839	}
		2840	}
		2841	} else {
		2842	offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		2843	if (offset) {
		2844	index = offset + 10;
		2845	id = RBIOS16(index);
		2846	while (id != 0xffff) {
		2847	index += 2;
		2848	switch (id >> 13) {
		2849	case 0:
		2850	reg = (id & 0x1fff) * 4;
		2851	val = RBIOS32(index);
		2852	WREG32(reg, val);
		2853	break;
		2854	case 2:
		2855	reg = (id & 0x1fff) * 4;
		2856	and_mask = RBIOS32(index);
		2857	index += 4;
		2858	or_mask = RBIOS32(index);
		2859	index += 4;
		2860	val = RREG32(reg);
		2861	val = (val & and_mask) \| or_mask;
		2862	WREG32(reg, val);
		2863	break;
		2864	case 4:
		2865	val = RBIOS16(index);
		2866	index += 2;
		2867	udelay(val);
		2868	break;
		2869	case 5:
		2870	reg = id & 0x1fff;
		2871	and_mask = RBIOS32(index);
		2872	index += 4;
		2873	or_mask = RBIOS32(index);
		2874	index += 4;
		2875	val = RREG32_PLL(reg);
		2876	val = (val & and_mask) \| or_mask;
		2877	WREG32_PLL(reg, val);
		2878	break;
		2879	case 6:
		2880	reg = id & 0x1fff;
		2881	val = RBIOS8(index);
		2882	index += 1;
1430	serge	2883	radeon_i2c_put_byte(tmds->i2c_bus,
1321	serge	2884	tmds->slave_addr,
		2885	reg, val);
		2886	break;
		2887	default:
		2888	DRM_ERROR("Unknown id %d\n", id >> 13);
		2889	break;
		2890	}
		2891	id = RBIOS16(index);
		2892	}
		2893	return true;
		2894	}
		2895	}
		2896	return false;
		2897	}
		2898
1123	serge	2899	static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
		2900	{
		2901	struct radeon_device *rdev = dev->dev_private;
		2902
		2903	if (offset) {
		2904	while (RBIOS16(offset)) {
		2905	uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
		2906	uint32_t addr = (RBIOS16(offset) & 0x1fff);
		2907	uint32_t val, and_mask, or_mask;
		2908	uint32_t tmp;
		2909
		2910	offset += 2;
		2911	switch (cmd) {
		2912	case 0:
		2913	val = RBIOS32(offset);
		2914	offset += 4;
		2915	WREG32(addr, val);
		2916	break;
		2917	case 1:
		2918	val = RBIOS32(offset);
		2919	offset += 4;
		2920	WREG32(addr, val);
		2921	break;
		2922	case 2:
		2923	and_mask = RBIOS32(offset);
		2924	offset += 4;
		2925	or_mask = RBIOS32(offset);
		2926	offset += 4;
		2927	tmp = RREG32(addr);
		2928	tmp &= and_mask;
		2929	tmp \|= or_mask;
		2930	WREG32(addr, tmp);
		2931	break;
		2932	case 3:
		2933	and_mask = RBIOS32(offset);
		2934	offset += 4;
		2935	or_mask = RBIOS32(offset);
		2936	offset += 4;
		2937	tmp = RREG32(addr);
		2938	tmp &= and_mask;
		2939	tmp \|= or_mask;
		2940	WREG32(addr, tmp);
		2941	break;
		2942	case 4:
		2943	val = RBIOS16(offset);
		2944	offset += 2;
		2945	udelay(val);
		2946	break;
		2947	case 5:
		2948	val = RBIOS16(offset);
		2949	offset += 2;
		2950	switch (addr) {
		2951	case 8:
		2952	while (val--) {
		2953	if (!
		2954	(RREG32_PLL
		2955	(RADEON_CLK_PWRMGT_CNTL) &
		2956	RADEON_MC_BUSY))
		2957	break;
		2958	}
		2959	break;
		2960	case 9:
		2961	while (val--) {
		2962	if ((RREG32(RADEON_MC_STATUS) &
		2963	RADEON_MC_IDLE))
		2964	break;
		2965	}
		2966	break;
		2967	default:
		2968	break;
		2969	}
		2970	break;
		2971	default:
		2972	break;
		2973	}
		2974	}
		2975	}
		2976	}
		2977
		2978	static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
		2979	{
		2980	struct radeon_device *rdev = dev->dev_private;
		2981
		2982	if (offset) {
		2983	while (RBIOS8(offset)) {
		2984	uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
		2985	uint8_t addr = (RBIOS8(offset) & 0x3f);
		2986	uint32_t val, shift, tmp;
		2987	uint32_t and_mask, or_mask;
		2988
		2989	offset++;
		2990	switch (cmd) {
		2991	case 0:
		2992	val = RBIOS32(offset);
		2993	offset += 4;
		2994	WREG32_PLL(addr, val);
		2995	break;
		2996	case 1:
		2997	shift = RBIOS8(offset) * 8;
		2998	offset++;
		2999	and_mask = RBIOS8(offset) << shift;
		3000	and_mask \|= ~(0xff << shift);
		3001	offset++;
		3002	or_mask = RBIOS8(offset) << shift;
		3003	offset++;
		3004	tmp = RREG32_PLL(addr);
		3005	tmp &= and_mask;
		3006	tmp \|= or_mask;
		3007	WREG32_PLL(addr, tmp);
		3008	break;
		3009	case 2:
		3010	case 3:
		3011	tmp = 1000;
		3012	switch (addr) {
		3013	case 1:
		3014	udelay(150);
		3015	break;
		3016	case 2:
		3017	udelay(1000);
		3018	break;
		3019	case 3:
		3020	while (tmp--) {
		3021	if (!
		3022	(RREG32_PLL
		3023	(RADEON_CLK_PWRMGT_CNTL) &
		3024	RADEON_MC_BUSY))
		3025	break;
		3026	}
		3027	break;
		3028	case 4:
		3029	while (tmp--) {
		3030	if (RREG32_PLL
		3031	(RADEON_CLK_PWRMGT_CNTL) &
		3032	RADEON_DLL_READY)
		3033	break;
		3034	}
		3035	break;
		3036	case 5:
		3037	tmp =
		3038	RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
		3039	if (tmp & RADEON_CG_NO1_DEBUG_0) {
		3040	#if 0
		3041	uint32_t mclk_cntl =
		3042	RREG32_PLL
		3043	(RADEON_MCLK_CNTL);
		3044	mclk_cntl &= 0xffff0000;
		3045	/mclk_cntl \|= 0x00001111;//* ??? */
		3046	WREG32_PLL(RADEON_MCLK_CNTL,
		3047	mclk_cntl);
		3048	udelay(10000);
		3049	#endif
		3050	WREG32_PLL
		3051	(RADEON_CLK_PWRMGT_CNTL,
		3052	tmp &
		3053	~RADEON_CG_NO1_DEBUG_0);
		3054	udelay(10000);
		3055	}
		3056	break;
		3057	default:
		3058	break;
		3059	}
		3060	break;
		3061	default:
		3062	break;
		3063	}
		3064	}
		3065	}
		3066	}
		3067
		3068	static void combios_parse_ram_reset_table(struct drm_device *dev,
		3069	uint16_t offset)
		3070	{
		3071	struct radeon_device *rdev = dev->dev_private;
		3072	uint32_t tmp;
		3073
		3074	if (offset) {
		3075	uint8_t val = RBIOS8(offset);
		3076	while (val != 0xff) {
		3077	offset++;
		3078
		3079	if (val == 0x0f) {
		3080	uint32_t channel_complete_mask;
		3081
		3082	if (ASIC_IS_R300(rdev))
		3083	channel_complete_mask =
		3084	R300_MEM_PWRUP_COMPLETE;
		3085	else
		3086	channel_complete_mask =
		3087	RADEON_MEM_PWRUP_COMPLETE;
		3088	tmp = 20000;
		3089	while (tmp--) {
		3090	if ((RREG32(RADEON_MEM_STR_CNTL) &
		3091	channel_complete_mask) ==
		3092	channel_complete_mask)
		3093	break;
		3094	}
		3095	} else {
		3096	uint32_t or_mask = RBIOS16(offset);
		3097	offset += 2;
		3098
		3099	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3100	tmp &= RADEON_SDRAM_MODE_MASK;
		3101	tmp \|= or_mask;
		3102	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3103
		3104	or_mask = val << 24;
		3105	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		3106	tmp &= RADEON_B3MEM_RESET_MASK;
		3107	tmp \|= or_mask;
		3108	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		3109	}
		3110	val = RBIOS8(offset);
		3111	}
		3112	}
		3113	}
		3114
		3115	static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
		3116	int mem_addr_mapping)
		3117	{
		3118	struct radeon_device *rdev = dev->dev_private;
		3119	uint32_t mem_cntl;
		3120	uint32_t mem_size;
		3121	uint32_t addr = 0;
		3122
		3123	mem_cntl = RREG32(RADEON_MEM_CNTL);
		3124	if (mem_cntl & RV100_HALF_MODE)
		3125	ram /= 2;
		3126	mem_size = ram;
		3127	mem_cntl &= ~(0xff << 8);
		3128	mem_cntl \|= (mem_addr_mapping & 0xff) << 8;
		3129	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3130	RREG32(RADEON_MEM_CNTL);
		3131
		3132	/* sdram reset ? */
		3133
		3134	/* something like this???? */
		3135	while (ram--) {
		3136	addr = ram * 1024 * 1024;
		3137	/* write to each page */
		3138	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		3139	WREG32(RADEON_MM_DATA, 0xdeadbeef);
		3140	/* read back and verify */
		3141	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		3142	if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
		3143	return 0;
		3144	}
		3145
		3146	return mem_size;
		3147	}
		3148
		3149	static void combios_write_ram_size(struct drm_device *dev)
		3150	{
		3151	struct radeon_device *rdev = dev->dev_private;
		3152	uint8_t rev;
		3153	uint16_t offset;
		3154	uint32_t mem_size = 0;
		3155	uint32_t mem_cntl = 0;
		3156
		3157	/* should do something smarter here I guess... */
		3158	if (rdev->flags & RADEON_IS_IGP)
		3159	return;
		3160
		3161	/* first check detected mem table */
		3162	offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
		3163	if (offset) {
		3164	rev = RBIOS8(offset);
		3165	if (rev < 3) {
		3166	mem_cntl = RBIOS32(offset + 1);
		3167	mem_size = RBIOS16(offset + 5);
1963	serge	3168	if ((rdev->family < CHIP_R200) &&
		3169	!ASIC_IS_RN50(rdev))
1123	serge	3170	WREG32(RADEON_MEM_CNTL, mem_cntl);
		3171	}
		3172	}
		3173
		3174	if (!mem_size) {
		3175	offset =
		3176	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		3177	if (offset) {
		3178	rev = RBIOS8(offset - 1);
		3179	if (rev < 1) {
1963	serge	3180	if ((rdev->family < CHIP_R200)
		3181	&& !ASIC_IS_RN50(rdev)) {
1123	serge	3182	int ram = 0;
		3183	int mem_addr_mapping = 0;
		3184
		3185	while (RBIOS8(offset)) {
		3186	ram = RBIOS8(offset);
		3187	mem_addr_mapping =
		3188	RBIOS8(offset + 1);
		3189	if (mem_addr_mapping != 0x25)
		3190	ram *= 2;
		3191	mem_size =
		3192	combios_detect_ram(dev, ram,
		3193	mem_addr_mapping);
		3194	if (mem_size)
		3195	break;
		3196	offset += 2;
		3197	}
		3198	} else
		3199	mem_size = RBIOS8(offset);
		3200	} else {
		3201	mem_size = RBIOS8(offset);
		3202	mem_size = 2; / convert to MB */
		3203	}
		3204	}
		3205	}
		3206
		3207	mem_size = (1024 1024); /* convert to bytes */
		3208	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
		3209	}
		3210
		3211	void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
		3212	{
		3213	uint16_t dyn_clk_info =
		3214	combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		3215
		3216	if (dyn_clk_info)
		3217	combios_parse_pll_table(dev, dyn_clk_info);
		3218	}
		3219
		3220	void radeon_combios_asic_init(struct drm_device *dev)
		3221	{
		3222	struct radeon_device *rdev = dev->dev_private;
		3223	uint16_t table;
		3224
		3225	/* port hardcoded mac stuff from radeonfb */
		3226	if (rdev->bios == NULL)
		3227	return;
		3228
		3229	/* ASIC INIT 1 */
		3230	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
		3231	if (table)
		3232	combios_parse_mmio_table(dev, table);
		3233
		3234	/* PLL INIT */
		3235	table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
		3236	if (table)
		3237	combios_parse_pll_table(dev, table);
		3238
		3239	/* ASIC INIT 2 */
		3240	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
		3241	if (table)
		3242	combios_parse_mmio_table(dev, table);
		3243
		3244	if (!(rdev->flags & RADEON_IS_IGP)) {
		3245	/* ASIC INIT 4 */
		3246	table =
		3247	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
		3248	if (table)
		3249	combios_parse_mmio_table(dev, table);
		3250
		3251	/* RAM RESET */
		3252	table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
		3253	if (table)
		3254	combios_parse_ram_reset_table(dev, table);
		3255
		3256	/* ASIC INIT 3 */
		3257	table =
		3258	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
		3259	if (table)
		3260	combios_parse_mmio_table(dev, table);
		3261
		3262	/* write CONFIG_MEMSIZE */
		3263	combios_write_ram_size(dev);
		3264	}
		3265
1963	serge	3266	/* quirk for rs4xx HP nx6125 laptop to make it resume
		3267	* - it hangs on resume inside the dynclk 1 table.
		3268	*/
		3269	if (rdev->family == CHIP_RS480 &&
		3270	rdev->pdev->subsystem_vendor == 0x103c &&
		3271	rdev->pdev->subsystem_device == 0x308b)
		3272	return;
		3273
		3274	/* quirk for rs4xx HP dv5000 laptop to make it resume
		3275	* - it hangs on resume inside the dynclk 1 table.
		3276	*/
		3277	if (rdev->family == CHIP_RS480 &&
		3278	rdev->pdev->subsystem_vendor == 0x103c &&
		3279	rdev->pdev->subsystem_device == 0x30a4)
		3280	return;
		3281
1123	serge	3282	/* DYN CLK 1 */
		3283	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		3284	if (table)
		3285	combios_parse_pll_table(dev, table);
		3286
		3287	}
		3288
		3289	void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
		3290	{
		3291	struct radeon_device *rdev = dev->dev_private;
		3292	uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
		3293
		3294	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		3295	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3296	bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
		3297
		3298	/* let the bios control the backlight */
		3299	bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
		3300
		3301	/* tell the bios not to handle mode switching */
		3302	bios_6_scratch \|= (RADEON_DISPLAY_SWITCHING_DIS \|
		3303	RADEON_ACC_MODE_CHANGE);
		3304
		3305	/* tell the bios a driver is loaded */
		3306	bios_7_scratch \|= RADEON_DRV_LOADED;
		3307
		3308	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		3309	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3310	WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
		3311	}
		3312
		3313	void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
		3314	{
		3315	struct drm_device *dev = encoder->dev;
		3316	struct radeon_device *rdev = dev->dev_private;
		3317	uint32_t bios_6_scratch;
		3318
		3319	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3320
		3321	if (lock)
		3322	bios_6_scratch \|= RADEON_DRIVER_CRITICAL;
		3323	else
		3324	bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
		3325
		3326	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3327	}
		3328
		3329	void
		3330	radeon_combios_connected_scratch_regs(struct drm_connector *connector,
		3331	struct drm_encoder *encoder,
		3332	bool connected)
		3333	{
		3334	struct drm_device *dev = connector->dev;
		3335	struct radeon_device *rdev = dev->dev_private;
		3336	struct radeon_connector *radeon_connector =
		3337	to_radeon_connector(connector);
		3338	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3339	uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
		3340	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3341
		3342	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		3343	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		3344	if (connected) {
1963	serge	3345	DRM_DEBUG_KMS("TV1 connected\n");
1123	serge	3346	/* fix me */
		3347	bios_4_scratch \|= RADEON_TV1_ATTACHED_SVIDEO;
		3348	/save->bios_4_scratch \|= RADEON_TV1_ATTACHED_COMP; /
		3349	bios_5_scratch \|= RADEON_TV1_ON;
		3350	bios_5_scratch \|= RADEON_ACC_REQ_TV1;
		3351	} else {
1963	serge	3352	DRM_DEBUG_KMS("TV1 disconnected\n");
1123	serge	3353	bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
		3354	bios_5_scratch &= ~RADEON_TV1_ON;
		3355	bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
		3356	}
		3357	}
		3358	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		3359	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		3360	if (connected) {
1963	serge	3361	DRM_DEBUG_KMS("LCD1 connected\n");
1123	serge	3362	bios_4_scratch \|= RADEON_LCD1_ATTACHED;
		3363	bios_5_scratch \|= RADEON_LCD1_ON;
		3364	bios_5_scratch \|= RADEON_ACC_REQ_LCD1;
		3365	} else {
1963	serge	3366	DRM_DEBUG_KMS("LCD1 disconnected\n");
1123	serge	3367	bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
		3368	bios_5_scratch &= ~RADEON_LCD1_ON;
		3369	bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
		3370	}
		3371	}
		3372	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		3373	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		3374	if (connected) {
1963	serge	3375	DRM_DEBUG_KMS("CRT1 connected\n");
1123	serge	3376	bios_4_scratch \|= RADEON_CRT1_ATTACHED_COLOR;
		3377	bios_5_scratch \|= RADEON_CRT1_ON;
		3378	bios_5_scratch \|= RADEON_ACC_REQ_CRT1;
		3379	} else {
1963	serge	3380	DRM_DEBUG_KMS("CRT1 disconnected\n");
1123	serge	3381	bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
		3382	bios_5_scratch &= ~RADEON_CRT1_ON;
		3383	bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
		3384	}
		3385	}
		3386	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		3387	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		3388	if (connected) {
1963	serge	3389	DRM_DEBUG_KMS("CRT2 connected\n");
1123	serge	3390	bios_4_scratch \|= RADEON_CRT2_ATTACHED_COLOR;
		3391	bios_5_scratch \|= RADEON_CRT2_ON;
		3392	bios_5_scratch \|= RADEON_ACC_REQ_CRT2;
		3393	} else {
1963	serge	3394	DRM_DEBUG_KMS("CRT2 disconnected\n");
1123	serge	3395	bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
		3396	bios_5_scratch &= ~RADEON_CRT2_ON;
		3397	bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
		3398	}
		3399	}
		3400	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		3401	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		3402	if (connected) {
1963	serge	3403	DRM_DEBUG_KMS("DFP1 connected\n");
1123	serge	3404	bios_4_scratch \|= RADEON_DFP1_ATTACHED;
		3405	bios_5_scratch \|= RADEON_DFP1_ON;
		3406	bios_5_scratch \|= RADEON_ACC_REQ_DFP1;
		3407	} else {
1963	serge	3408	DRM_DEBUG_KMS("DFP1 disconnected\n");
1123	serge	3409	bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
		3410	bios_5_scratch &= ~RADEON_DFP1_ON;
		3411	bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
		3412	}
		3413	}
		3414	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		3415	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		3416	if (connected) {
1963	serge	3417	DRM_DEBUG_KMS("DFP2 connected\n");
1123	serge	3418	bios_4_scratch \|= RADEON_DFP2_ATTACHED;
		3419	bios_5_scratch \|= RADEON_DFP2_ON;
		3420	bios_5_scratch \|= RADEON_ACC_REQ_DFP2;
		3421	} else {
1963	serge	3422	DRM_DEBUG_KMS("DFP2 disconnected\n");
1123	serge	3423	bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
		3424	bios_5_scratch &= ~RADEON_DFP2_ON;
		3425	bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
		3426	}
		3427	}
		3428	WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
		3429	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3430	}
		3431
		3432	void
		3433	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		3434	{
		3435	struct drm_device *dev = encoder->dev;
		3436	struct radeon_device *rdev = dev->dev_private;
		3437	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3438	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		3439
		3440	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		3441	bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
		3442	bios_5_scratch \|= (crtc << RADEON_TV1_CRTC_SHIFT);
		3443	}
		3444	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		3445	bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
		3446	bios_5_scratch \|= (crtc << RADEON_CRT1_CRTC_SHIFT);
		3447	}
		3448	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		3449	bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
		3450	bios_5_scratch \|= (crtc << RADEON_CRT2_CRTC_SHIFT);
		3451	}
		3452	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		3453	bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
		3454	bios_5_scratch \|= (crtc << RADEON_LCD1_CRTC_SHIFT);
		3455	}
		3456	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		3457	bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
		3458	bios_5_scratch \|= (crtc << RADEON_DFP1_CRTC_SHIFT);
		3459	}
		3460	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		3461	bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
		3462	bios_5_scratch \|= (crtc << RADEON_DFP2_CRTC_SHIFT);
		3463	}
		3464	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		3465	}
		3466
		3467	void
		3468	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		3469	{
		3470	struct drm_device *dev = encoder->dev;
		3471	struct radeon_device *rdev = dev->dev_private;
		3472	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		3473	uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		3474
		3475	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		3476	if (on)
		3477	bios_6_scratch \|= RADEON_TV_DPMS_ON;
		3478	else
		3479	bios_6_scratch &= ~RADEON_TV_DPMS_ON;
		3480	}
		3481	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		3482	if (on)
		3483	bios_6_scratch \|= RADEON_CRT_DPMS_ON;
		3484	else
		3485	bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
		3486	}
		3487	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		3488	if (on)
		3489	bios_6_scratch \|= RADEON_LCD_DPMS_ON;
		3490	else
		3491	bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
		3492	}
		3493	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		3494	if (on)
		3495	bios_6_scratch \|= RADEON_DFP_DPMS_ON;
		3496	else
		3497	bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
		3498	}
		3499	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		3500	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_combios.c – Rev 2160