WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_combios.c

Rev	Author	Line No.	Line
1123	serge	1	/*
		2	* Copyright 2004 ATI Technologies Inc., Markham, Ontario
		3	* Copyright 2007-8 Advanced Micro Devices, Inc.
		4	* Copyright 2008 Red Hat Inc.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	*/
		27	#include "drmP.h"
		28	#include "radeon_drm.h"
		29	#include "radeon.h"
		30	#include "atom.h"
		31
		32	#ifdef CONFIG_PPC_PMAC
		33	/* not sure which of these are needed */
		34	#include
		35	#include
		36	#include
		37	#include
		38	#endif /* CONFIG_PPC_PMAC */
		39
		40	/* from radeon_encoder.c */
		41	extern uint32_t
		42	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		43	uint8_t dac);
		44	extern void radeon_link_encoder_connector(struct drm_device *dev);
		45
		46	/* from radeon_connector.c */
		47	extern void
		48	radeon_add_legacy_connector(struct drm_device *dev,
		49	uint32_t connector_id,
		50	uint32_t supported_device,
		51	int connector_type,
		52	struct radeon_i2c_bus_rec *i2c_bus);
		53
		54	/* from radeon_legacy_encoder.c */
		55	extern void
		56	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		57	uint32_t supported_device);
		58
		59	/* old legacy ATI BIOS routines */
		60
		61	/* COMBIOS table offsets */
		62	enum radeon_combios_table_offset {
		63	/* absolute offset tables */
		64	COMBIOS_ASIC_INIT_1_TABLE,
		65	COMBIOS_BIOS_SUPPORT_TABLE,
		66	COMBIOS_DAC_PROGRAMMING_TABLE,
		67	COMBIOS_MAX_COLOR_DEPTH_TABLE,
		68	COMBIOS_CRTC_INFO_TABLE,
		69	COMBIOS_PLL_INFO_TABLE,
		70	COMBIOS_TV_INFO_TABLE,
		71	COMBIOS_DFP_INFO_TABLE,
		72	COMBIOS_HW_CONFIG_INFO_TABLE,
		73	COMBIOS_MULTIMEDIA_INFO_TABLE,
		74	COMBIOS_TV_STD_PATCH_TABLE,
		75	COMBIOS_LCD_INFO_TABLE,
		76	COMBIOS_MOBILE_INFO_TABLE,
		77	COMBIOS_PLL_INIT_TABLE,
		78	COMBIOS_MEM_CONFIG_TABLE,
		79	COMBIOS_SAVE_MASK_TABLE,
		80	COMBIOS_HARDCODED_EDID_TABLE,
		81	COMBIOS_ASIC_INIT_2_TABLE,
		82	COMBIOS_CONNECTOR_INFO_TABLE,
		83	COMBIOS_DYN_CLK_1_TABLE,
		84	COMBIOS_RESERVED_MEM_TABLE,
		85	COMBIOS_EXT_TMDS_INFO_TABLE,
		86	COMBIOS_MEM_CLK_INFO_TABLE,
		87	COMBIOS_EXT_DAC_INFO_TABLE,
		88	COMBIOS_MISC_INFO_TABLE,
		89	COMBIOS_CRT_INFO_TABLE,
		90	COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
		91	COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
		92	COMBIOS_FAN_SPEED_INFO_TABLE,
		93	COMBIOS_OVERDRIVE_INFO_TABLE,
		94	COMBIOS_OEM_INFO_TABLE,
		95	COMBIOS_DYN_CLK_2_TABLE,
		96	COMBIOS_POWER_CONNECTOR_INFO_TABLE,
		97	COMBIOS_I2C_INFO_TABLE,
		98	/* relative offset tables */
		99	COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
		100	COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
		101	COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
		102	COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
		103	COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
		104	COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
		105	COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
		106	COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
		107	COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
		108	COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
		109	COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
		110	};
		111
		112	enum radeon_combios_ddc {
		113	DDC_NONE_DETECTED,
		114	DDC_MONID,
		115	DDC_DVI,
		116	DDC_VGA,
		117	DDC_CRT2,
		118	DDC_LCD,
		119	DDC_GPIO,
		120	};
		121
		122	enum radeon_combios_connector {
		123	CONNECTOR_NONE_LEGACY,
		124	CONNECTOR_PROPRIETARY_LEGACY,
		125	CONNECTOR_CRT_LEGACY,
		126	CONNECTOR_DVI_I_LEGACY,
		127	CONNECTOR_DVI_D_LEGACY,
		128	CONNECTOR_CTV_LEGACY,
		129	CONNECTOR_STV_LEGACY,
		130	CONNECTOR_UNSUPPORTED_LEGACY
		131	};
		132
		133	const int legacy_connector_convert[] = {
		134	DRM_MODE_CONNECTOR_Unknown,
		135	DRM_MODE_CONNECTOR_DVID,
		136	DRM_MODE_CONNECTOR_VGA,
		137	DRM_MODE_CONNECTOR_DVII,
		138	DRM_MODE_CONNECTOR_DVID,
		139	DRM_MODE_CONNECTOR_Composite,
		140	DRM_MODE_CONNECTOR_SVIDEO,
		141	DRM_MODE_CONNECTOR_Unknown,
		142	};
		143
		144	static uint16_t combios_get_table_offset(struct drm_device *dev,
		145	enum radeon_combios_table_offset table)
		146	{
		147	struct radeon_device *rdev = dev->dev_private;
		148	int rev;
		149	uint16_t offset = 0, check_offset;
		150
		151	switch (table) {
		152	/* absolute offset tables */
		153	case COMBIOS_ASIC_INIT_1_TABLE:
		154	check_offset = RBIOS16(rdev->bios_header_start + 0xc);
		155	if (check_offset)
		156	offset = check_offset;
		157	break;
		158	case COMBIOS_BIOS_SUPPORT_TABLE:
		159	check_offset = RBIOS16(rdev->bios_header_start + 0x14);
		160	if (check_offset)
		161	offset = check_offset;
		162	break;
		163	case COMBIOS_DAC_PROGRAMMING_TABLE:
		164	check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
		165	if (check_offset)
		166	offset = check_offset;
		167	break;
		168	case COMBIOS_MAX_COLOR_DEPTH_TABLE:
		169	check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
		170	if (check_offset)
		171	offset = check_offset;
		172	break;
		173	case COMBIOS_CRTC_INFO_TABLE:
		174	check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
		175	if (check_offset)
		176	offset = check_offset;
		177	break;
		178	case COMBIOS_PLL_INFO_TABLE:
		179	check_offset = RBIOS16(rdev->bios_header_start + 0x30);
		180	if (check_offset)
		181	offset = check_offset;
		182	break;
		183	case COMBIOS_TV_INFO_TABLE:
		184	check_offset = RBIOS16(rdev->bios_header_start + 0x32);
		185	if (check_offset)
		186	offset = check_offset;
		187	break;
		188	case COMBIOS_DFP_INFO_TABLE:
		189	check_offset = RBIOS16(rdev->bios_header_start + 0x34);
		190	if (check_offset)
		191	offset = check_offset;
		192	break;
		193	case COMBIOS_HW_CONFIG_INFO_TABLE:
		194	check_offset = RBIOS16(rdev->bios_header_start + 0x36);
		195	if (check_offset)
		196	offset = check_offset;
		197	break;
		198	case COMBIOS_MULTIMEDIA_INFO_TABLE:
		199	check_offset = RBIOS16(rdev->bios_header_start + 0x38);
		200	if (check_offset)
		201	offset = check_offset;
		202	break;
		203	case COMBIOS_TV_STD_PATCH_TABLE:
		204	check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
		205	if (check_offset)
		206	offset = check_offset;
		207	break;
		208	case COMBIOS_LCD_INFO_TABLE:
		209	check_offset = RBIOS16(rdev->bios_header_start + 0x40);
		210	if (check_offset)
		211	offset = check_offset;
		212	break;
		213	case COMBIOS_MOBILE_INFO_TABLE:
		214	check_offset = RBIOS16(rdev->bios_header_start + 0x42);
		215	if (check_offset)
		216	offset = check_offset;
		217	break;
		218	case COMBIOS_PLL_INIT_TABLE:
		219	check_offset = RBIOS16(rdev->bios_header_start + 0x46);
		220	if (check_offset)
		221	offset = check_offset;
		222	break;
		223	case COMBIOS_MEM_CONFIG_TABLE:
		224	check_offset = RBIOS16(rdev->bios_header_start + 0x48);
		225	if (check_offset)
		226	offset = check_offset;
		227	break;
		228	case COMBIOS_SAVE_MASK_TABLE:
		229	check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
		230	if (check_offset)
		231	offset = check_offset;
		232	break;
		233	case COMBIOS_HARDCODED_EDID_TABLE:
		234	check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
		235	if (check_offset)
		236	offset = check_offset;
		237	break;
		238	case COMBIOS_ASIC_INIT_2_TABLE:
		239	check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
		240	if (check_offset)
		241	offset = check_offset;
		242	break;
		243	case COMBIOS_CONNECTOR_INFO_TABLE:
		244	check_offset = RBIOS16(rdev->bios_header_start + 0x50);
		245	if (check_offset)
		246	offset = check_offset;
		247	break;
		248	case COMBIOS_DYN_CLK_1_TABLE:
		249	check_offset = RBIOS16(rdev->bios_header_start + 0x52);
		250	if (check_offset)
		251	offset = check_offset;
		252	break;
		253	case COMBIOS_RESERVED_MEM_TABLE:
		254	check_offset = RBIOS16(rdev->bios_header_start + 0x54);
		255	if (check_offset)
		256	offset = check_offset;
		257	break;
		258	case COMBIOS_EXT_TMDS_INFO_TABLE:
		259	check_offset = RBIOS16(rdev->bios_header_start + 0x58);
		260	if (check_offset)
		261	offset = check_offset;
		262	break;
		263	case COMBIOS_MEM_CLK_INFO_TABLE:
		264	check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
		265	if (check_offset)
		266	offset = check_offset;
		267	break;
		268	case COMBIOS_EXT_DAC_INFO_TABLE:
		269	check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
		270	if (check_offset)
		271	offset = check_offset;
		272	break;
		273	case COMBIOS_MISC_INFO_TABLE:
		274	check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
		275	if (check_offset)
		276	offset = check_offset;
		277	break;
		278	case COMBIOS_CRT_INFO_TABLE:
		279	check_offset = RBIOS16(rdev->bios_header_start + 0x60);
		280	if (check_offset)
		281	offset = check_offset;
		282	break;
		283	case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
		284	check_offset = RBIOS16(rdev->bios_header_start + 0x62);
		285	if (check_offset)
		286	offset = check_offset;
		287	break;
		288	case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
		289	check_offset = RBIOS16(rdev->bios_header_start + 0x64);
		290	if (check_offset)
		291	offset = check_offset;
		292	break;
		293	case COMBIOS_FAN_SPEED_INFO_TABLE:
		294	check_offset = RBIOS16(rdev->bios_header_start + 0x66);
		295	if (check_offset)
		296	offset = check_offset;
		297	break;
		298	case COMBIOS_OVERDRIVE_INFO_TABLE:
		299	check_offset = RBIOS16(rdev->bios_header_start + 0x68);
		300	if (check_offset)
		301	offset = check_offset;
		302	break;
		303	case COMBIOS_OEM_INFO_TABLE:
		304	check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
		305	if (check_offset)
		306	offset = check_offset;
		307	break;
		308	case COMBIOS_DYN_CLK_2_TABLE:
		309	check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
		310	if (check_offset)
		311	offset = check_offset;
		312	break;
		313	case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
		314	check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
		315	if (check_offset)
		316	offset = check_offset;
		317	break;
		318	case COMBIOS_I2C_INFO_TABLE:
		319	check_offset = RBIOS16(rdev->bios_header_start + 0x70);
		320	if (check_offset)
		321	offset = check_offset;
		322	break;
		323	/* relative offset tables */
		324	case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
		325	check_offset =
		326	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		327	if (check_offset) {
		328	rev = RBIOS8(check_offset);
		329	if (rev > 0) {
		330	check_offset = RBIOS16(check_offset + 0x3);
		331	if (check_offset)
		332	offset = check_offset;
		333	}
		334	}
		335	break;
		336	case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
		337	check_offset =
		338	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		339	if (check_offset) {
		340	rev = RBIOS8(check_offset);
		341	if (rev > 0) {
		342	check_offset = RBIOS16(check_offset + 0x5);
		343	if (check_offset)
		344	offset = check_offset;
		345	}
		346	}
		347	break;
		348	case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
		349	check_offset =
		350	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		351	if (check_offset) {
		352	rev = RBIOS8(check_offset);
		353	if (rev > 0) {
		354	check_offset = RBIOS16(check_offset + 0x7);
		355	if (check_offset)
		356	offset = check_offset;
		357	}
		358	}
		359	break;
		360	case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
		361	check_offset =
		362	combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
		363	if (check_offset) {
		364	rev = RBIOS8(check_offset);
		365	if (rev == 2) {
		366	check_offset = RBIOS16(check_offset + 0x9);
		367	if (check_offset)
		368	offset = check_offset;
		369	}
		370	}
		371	break;
		372	case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
		373	check_offset =
		374	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		375	if (check_offset) {
		376	while (RBIOS8(check_offset++));
		377	check_offset += 2;
		378	if (check_offset)
		379	offset = check_offset;
		380	}
		381	break;
		382	case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
		383	check_offset =
		384	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		385	if (check_offset) {
		386	check_offset = RBIOS16(check_offset + 0x11);
		387	if (check_offset)
		388	offset = check_offset;
		389	}
		390	break;
		391	case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
		392	check_offset =
		393	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		394	if (check_offset) {
		395	check_offset = RBIOS16(check_offset + 0x13);
		396	if (check_offset)
		397	offset = check_offset;
		398	}
		399	break;
		400	case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
		401	check_offset =
		402	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		403	if (check_offset) {
		404	check_offset = RBIOS16(check_offset + 0x15);
		405	if (check_offset)
		406	offset = check_offset;
		407	}
		408	break;
		409	case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
		410	check_offset =
		411	combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
		412	if (check_offset) {
		413	check_offset = RBIOS16(check_offset + 0x17);
		414	if (check_offset)
		415	offset = check_offset;
		416	}
		417	break;
		418	case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
		419	check_offset =
		420	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		421	if (check_offset) {
		422	check_offset = RBIOS16(check_offset + 0x2);
		423	if (check_offset)
		424	offset = check_offset;
		425	}
		426	break;
		427	case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
		428	check_offset =
		429	combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
		430	if (check_offset) {
		431	check_offset = RBIOS16(check_offset + 0x4);
		432	if (check_offset)
		433	offset = check_offset;
		434	}
		435	break;
		436	default:
		437	break;
		438	}
		439
		440	return offset;
		441
		442	}
		443
		444	struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
		445	{
		446	struct radeon_i2c_bus_rec i2c;
		447
		448	i2c.mask_clk_mask = RADEON_GPIO_EN_1;
		449	i2c.mask_data_mask = RADEON_GPIO_EN_0;
		450	i2c.a_clk_mask = RADEON_GPIO_A_1;
		451	i2c.a_data_mask = RADEON_GPIO_A_0;
		452	i2c.put_clk_mask = RADEON_GPIO_EN_1;
		453	i2c.put_data_mask = RADEON_GPIO_EN_0;
		454	i2c.get_clk_mask = RADEON_GPIO_Y_1;
		455	i2c.get_data_mask = RADEON_GPIO_Y_0;
		456	if ((ddc_line == RADEON_LCD_GPIO_MASK) \|\|
		457	(ddc_line == RADEON_MDGPIO_EN_REG)) {
		458	i2c.mask_clk_reg = ddc_line;
		459	i2c.mask_data_reg = ddc_line;
		460	i2c.a_clk_reg = ddc_line;
		461	i2c.a_data_reg = ddc_line;
		462	i2c.put_clk_reg = ddc_line;
		463	i2c.put_data_reg = ddc_line;
		464	i2c.get_clk_reg = ddc_line + 4;
		465	i2c.get_data_reg = ddc_line + 4;
		466	} else {
		467	i2c.mask_clk_reg = ddc_line;
		468	i2c.mask_data_reg = ddc_line;
		469	i2c.a_clk_reg = ddc_line;
		470	i2c.a_data_reg = ddc_line;
		471	i2c.put_clk_reg = ddc_line;
		472	i2c.put_data_reg = ddc_line;
		473	i2c.get_clk_reg = ddc_line;
		474	i2c.get_data_reg = ddc_line;
		475	}
		476
		477	if (ddc_line)
		478	i2c.valid = true;
		479	else
		480	i2c.valid = false;
		481
		482	return i2c;
		483	}
		484
		485	bool radeon_combios_get_clock_info(struct drm_device *dev)
		486	{
		487	struct radeon_device *rdev = dev->dev_private;
		488	uint16_t pll_info;
		489	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		490	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		491	struct radeon_pll *spll = &rdev->clock.spll;
		492	struct radeon_pll *mpll = &rdev->clock.mpll;
		493	int8_t rev;
		494	uint16_t sclk, mclk;
		495
		496	if (rdev->bios == NULL)
		497	return NULL;
		498
		499	pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
		500	if (pll_info) {
		501	rev = RBIOS8(pll_info);
		502
		503	/* pixel clocks */
		504	p1pll->reference_freq = RBIOS16(pll_info + 0xe);
		505	p1pll->reference_div = RBIOS16(pll_info + 0x10);
		506	p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
		507	p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
		508
		509	if (rev > 9) {
		510	p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
		511	p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
		512	} else {
		513	p1pll->pll_in_min = 40;
		514	p1pll->pll_in_max = 500;
		515	}
		516	p2pll = p1pll;
		517
		518	/* system clock */
		519	spll->reference_freq = RBIOS16(pll_info + 0x1a);
		520	spll->reference_div = RBIOS16(pll_info + 0x1c);
		521	spll->pll_out_min = RBIOS32(pll_info + 0x1e);
		522	spll->pll_out_max = RBIOS32(pll_info + 0x22);
		523
		524	if (rev > 10) {
		525	spll->pll_in_min = RBIOS32(pll_info + 0x48);
		526	spll->pll_in_max = RBIOS32(pll_info + 0x4c);
		527	} else {
		528	/* ??? */
		529	spll->pll_in_min = 40;
		530	spll->pll_in_max = 500;
		531	}
		532
		533	/* memory clock */
		534	mpll->reference_freq = RBIOS16(pll_info + 0x26);
		535	mpll->reference_div = RBIOS16(pll_info + 0x28);
		536	mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
		537	mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
		538
		539	if (rev > 10) {
		540	mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
		541	mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
		542	} else {
		543	/* ??? */
		544	mpll->pll_in_min = 40;
		545	mpll->pll_in_max = 500;
		546	}
		547
		548	/* default sclk/mclk */
		549	sclk = RBIOS16(pll_info + 0xa);
		550	mclk = RBIOS16(pll_info + 0x8);
		551	if (sclk == 0)
		552	sclk = 200 * 100;
		553	if (mclk == 0)
		554	mclk = 200 * 100;
		555
		556	rdev->clock.default_sclk = sclk;
		557	rdev->clock.default_mclk = mclk;
		558
		559	return true;
		560	}
		561	return false;
		562	}
		563
		564	struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
		565	radeon_encoder
		566	*encoder)
		567	{
		568	struct drm_device *dev = encoder->base.dev;
		569	struct radeon_device *rdev = dev->dev_private;
		570	uint16_t dac_info;
		571	uint8_t rev, bg, dac;
		572	struct radeon_encoder_primary_dac *p_dac = NULL;
		573
		574	if (rdev->bios == NULL)
		575	return NULL;
		576
		577	/* check CRT table */
		578	dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		579	if (dac_info) {
		580	p_dac =
		581	kzalloc(sizeof(struct radeon_encoder_primary_dac),
		582	GFP_KERNEL);
		583
		584	if (!p_dac)
		585	return NULL;
		586
		587	rev = RBIOS8(dac_info) & 0x3;
		588	if (rev < 2) {
		589	bg = RBIOS8(dac_info + 0x2) & 0xf;
		590	dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
		591	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		592	} else {
		593	bg = RBIOS8(dac_info + 0x2) & 0xf;
		594	dac = RBIOS8(dac_info + 0x3) & 0xf;
		595	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		596	}
		597
		598	}
		599
		600	return p_dac;
		601	}
		602
		603	static enum radeon_tv_std
		604	radeon_combios_get_tv_info(struct radeon_encoder *encoder)
		605	{
		606	struct drm_device *dev = encoder->base.dev;
		607	struct radeon_device *rdev = dev->dev_private;
		608	uint16_t tv_info;
		609	enum radeon_tv_std tv_std = TV_STD_NTSC;
		610
		611	tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		612	if (tv_info) {
		613	if (RBIOS8(tv_info + 6) == 'T') {
		614	switch (RBIOS8(tv_info + 7) & 0xf) {
		615	case 1:
		616	tv_std = TV_STD_NTSC;
		617	DRM_INFO("Default TV standard: NTSC\n");
		618	break;
		619	case 2:
		620	tv_std = TV_STD_PAL;
		621	DRM_INFO("Default TV standard: PAL\n");
		622	break;
		623	case 3:
		624	tv_std = TV_STD_PAL_M;
		625	DRM_INFO("Default TV standard: PAL-M\n");
		626	break;
		627	case 4:
		628	tv_std = TV_STD_PAL_60;
		629	DRM_INFO("Default TV standard: PAL-60\n");
		630	break;
		631	case 5:
		632	tv_std = TV_STD_NTSC_J;
		633	DRM_INFO("Default TV standard: NTSC-J\n");
		634	break;
		635	case 6:
		636	tv_std = TV_STD_SCART_PAL;
		637	DRM_INFO("Default TV standard: SCART-PAL\n");
		638	break;
		639	default:
		640	tv_std = TV_STD_NTSC;
		641	DRM_INFO
		642	("Unknown TV standard; defaulting to NTSC\n");
		643	break;
		644	}
		645
		646	switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
		647	case 0:
		648	DRM_INFO("29.498928713 MHz TV ref clk\n");
		649	break;
		650	case 1:
		651	DRM_INFO("28.636360000 MHz TV ref clk\n");
		652	break;
		653	case 2:
		654	DRM_INFO("14.318180000 MHz TV ref clk\n");
		655	break;
		656	case 3:
		657	DRM_INFO("27.000000000 MHz TV ref clk\n");
		658	break;
		659	default:
		660	break;
		661	}
		662	}
		663	}
		664	return tv_std;
		665	}
		666
		667	static const uint32_t default_tvdac_adj[CHIP_LAST] = {
		668	0x00000000, /* r100 */
		669	0x00280000, /* rv100 */
		670	0x00000000, /* rs100 */
		671	0x00880000, /* rv200 */
		672	0x00000000, /* rs200 */
		673	0x00000000, /* r200 */
		674	0x00770000, /* rv250 */
		675	0x00290000, /* rs300 */
		676	0x00560000, /* rv280 */
		677	0x00780000, /* r300 */
		678	0x00770000, /* r350 */
		679	0x00780000, /* rv350 */
		680	0x00780000, /* rv380 */
		681	0x01080000, /* r420 */
		682	0x01080000, /* r423 */
		683	0x01080000, /* rv410 */
		684	0x00780000, /* rs400 */
		685	0x00780000, /* rs480 */
		686	};
		687
1179	serge	688	static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
		689	struct radeon_encoder_tv_dac *tv_dac)
1123	serge	690	{
		691	tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
		692	if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
		693	tv_dac->ps2_tvdac_adj = 0x00880000;
		694	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		695	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	696	return;
1123	serge	697	}
		698
		699	struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
		700	radeon_encoder
		701	*encoder)
		702	{
		703	struct drm_device *dev = encoder->base.dev;
		704	struct radeon_device *rdev = dev->dev_private;
		705	uint16_t dac_info;
		706	uint8_t rev, bg, dac;
		707	struct radeon_encoder_tv_dac *tv_dac = NULL;
1179	serge	708	int found = 0;
1123	serge	709
1179	serge	710	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		711	if (!tv_dac)
		712	return NULL;
		713
1123	serge	714	if (rdev->bios == NULL)
1179	serge	715	goto out;
1123	serge	716
		717	/* first check TV table */
		718	dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		719	if (dac_info) {
		720	rev = RBIOS8(dac_info + 0x3);
		721	if (rev > 4) {
		722	bg = RBIOS8(dac_info + 0xc) & 0xf;
		723	dac = RBIOS8(dac_info + 0xd) & 0xf;
		724	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		725
		726	bg = RBIOS8(dac_info + 0xe) & 0xf;
		727	dac = RBIOS8(dac_info + 0xf) & 0xf;
		728	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		729
		730	bg = RBIOS8(dac_info + 0x10) & 0xf;
		731	dac = RBIOS8(dac_info + 0x11) & 0xf;
		732	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1179	serge	733	found = 1;
1123	serge	734	} else if (rev > 1) {
		735	bg = RBIOS8(dac_info + 0xc) & 0xf;
		736	dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
		737	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		738
		739	bg = RBIOS8(dac_info + 0xd) & 0xf;
		740	dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
		741	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		742
		743	bg = RBIOS8(dac_info + 0xe) & 0xf;
		744	dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
		745	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
1179	serge	746	found = 1;
1123	serge	747	}
		748
		749	tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
1179	serge	750	}
		751	if (!found) {
1123	serge	752	/* then check CRT table */
		753	dac_info =
		754	combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
		755	if (dac_info) {
		756	rev = RBIOS8(dac_info) & 0x3;
		757	if (rev < 2) {
		758	bg = RBIOS8(dac_info + 0x3) & 0xf;
		759	dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
		760	tv_dac->ps2_tvdac_adj =
		761	(bg << 16) \| (dac << 20);
		762	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		763	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	764	found = 1;
1123	serge	765	} else {
		766	bg = RBIOS8(dac_info + 0x4) & 0xf;
		767	dac = RBIOS8(dac_info + 0x5) & 0xf;
		768	tv_dac->ps2_tvdac_adj =
		769	(bg << 16) \| (dac << 20);
		770	tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
		771	tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1179	serge	772	found = 1;
1123	serge	773	}
		774	} else {
		775	DRM_INFO("No TV DAC info found in BIOS\n");
		776	}
		777	}
1179	serge	778	out:
		779	if (!found) /* fallback to defaults */
		780	radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1123	serge	781
		782	return tv_dac;
		783	}
		784
		785	static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
		786	radeon_device
		787	*rdev)
		788	{
		789	struct radeon_encoder_lvds *lvds = NULL;
		790	uint32_t fp_vert_stretch, fp_horz_stretch;
		791	uint32_t ppll_div_sel, ppll_val;
		792	uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
		793
		794	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		795
		796	if (!lvds)
		797	return NULL;
		798
		799	fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
		800	fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
		801
		802	/* These should be fail-safe defaults, fingers crossed */
		803	lvds->panel_pwr_delay = 200;
		804	lvds->panel_vcc_delay = 2000;
		805
		806	lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
		807	lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
		808	lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
		809
		810	if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
		811	lvds->native_mode.panel_yres =
		812	((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
		813	RADEON_VERT_PANEL_SHIFT) + 1;
		814	else
		815	lvds->native_mode.panel_yres =
		816	(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
		817
		818	if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
		819	lvds->native_mode.panel_xres =
		820	(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
		821	RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
		822	else
		823	lvds->native_mode.panel_xres =
		824	((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
		825
		826	if ((lvds->native_mode.panel_xres < 640) \|\|
		827	(lvds->native_mode.panel_yres < 480)) {
		828	lvds->native_mode.panel_xres = 640;
		829	lvds->native_mode.panel_yres = 480;
		830	}
		831
		832	ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
		833	ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
		834	if ((ppll_val & 0x000707ff) == 0x1bb)
		835	lvds->use_bios_dividers = false;
		836	else {
		837	lvds->panel_ref_divider =
		838	RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
		839	lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
		840	lvds->panel_fb_divider = ppll_val & 0x7ff;
		841
		842	if ((lvds->panel_ref_divider != 0) &&
		843	(lvds->panel_fb_divider > 3))
		844	lvds->use_bios_dividers = true;
		845	}
		846	lvds->panel_vcc_delay = 200;
		847
		848	DRM_INFO("Panel info derived from registers\n");
		849	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
		850	lvds->native_mode.panel_yres);
		851
		852	return lvds;
		853	}
		854
		855	struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
		856	*encoder)
		857	{
		858	struct drm_device *dev = encoder->base.dev;
		859	struct radeon_device *rdev = dev->dev_private;
		860	uint16_t lcd_info;
		861	uint32_t panel_setup;
		862	char stmp[30];
		863	int tmp, i;
		864	struct radeon_encoder_lvds *lvds = NULL;
		865
1179	serge	866	if (rdev->bios == NULL) {
		867	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
		868	goto out;
		869	}
1123	serge	870
		871	lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		872
		873	if (lcd_info) {
		874	lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
		875
		876	if (!lvds)
		877	return NULL;
		878
		879	for (i = 0; i < 24; i++)
		880	stmp[i] = RBIOS8(lcd_info + i + 1);
		881	stmp[24] = 0;
		882
		883	DRM_INFO("Panel ID String: %s\n", stmp);
		884
		885	lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
		886	lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
		887
		888	DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
		889	lvds->native_mode.panel_yres);
		890
		891	lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
		892	if (lvds->panel_vcc_delay > 2000 \|\| lvds->panel_vcc_delay < 0)
		893	lvds->panel_vcc_delay = 2000;
		894
		895	lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
		896	lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
		897	lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
		898
		899	lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
		900	lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
		901	lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
		902	if ((lvds->panel_ref_divider != 0) &&
		903	(lvds->panel_fb_divider > 3))
		904	lvds->use_bios_dividers = true;
		905
		906	panel_setup = RBIOS32(lcd_info + 0x39);
		907	lvds->lvds_gen_cntl = 0xff00;
		908	if (panel_setup & 0x1)
		909	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_FORMAT;
		910
		911	if ((panel_setup >> 4) & 0x1)
		912	lvds->lvds_gen_cntl \|= RADEON_LVDS_PANEL_TYPE;
		913
		914	switch ((panel_setup >> 8) & 0x7) {
		915	case 0:
		916	lvds->lvds_gen_cntl \|= RADEON_LVDS_NO_FM;
		917	break;
		918	case 1:
		919	lvds->lvds_gen_cntl \|= RADEON_LVDS_2_GREY;
		920	break;
		921	case 2:
		922	lvds->lvds_gen_cntl \|= RADEON_LVDS_4_GREY;
		923	break;
		924	default:
		925	break;
		926	}
		927
		928	if ((panel_setup >> 16) & 0x1)
		929	lvds->lvds_gen_cntl \|= RADEON_LVDS_FP_POL_LOW;
		930
		931	if ((panel_setup >> 17) & 0x1)
		932	lvds->lvds_gen_cntl \|= RADEON_LVDS_LP_POL_LOW;
		933
		934	if ((panel_setup >> 18) & 0x1)
		935	lvds->lvds_gen_cntl \|= RADEON_LVDS_DTM_POL_LOW;
		936
		937	if ((panel_setup >> 23) & 0x1)
		938	lvds->lvds_gen_cntl \|= RADEON_LVDS_BL_CLK_SEL;
		939
		940	lvds->lvds_gen_cntl \|= (panel_setup & 0xf0000000);
		941
		942	for (i = 0; i < 32; i++) {
		943	tmp = RBIOS16(lcd_info + 64 + i * 2);
		944	if (tmp == 0)
		945	break;
		946
		947	if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
		948	(RBIOS16(tmp + 2) ==
		949	lvds->native_mode.panel_yres)) {
		950	lvds->native_mode.hblank =
		951	(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
		952	lvds->native_mode.hoverplus =
		953	(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
		954	1) * 8;
		955	lvds->native_mode.hsync_width =
		956	RBIOS8(tmp + 23) * 8;
		957
		958	lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
		959	RBIOS16(tmp + 26));
		960	lvds->native_mode.voverplus =
		961	((RBIOS16(tmp + 28) & 0x7ff) -
		962	RBIOS16(tmp + 26));
		963	lvds->native_mode.vsync_width =
		964	((RBIOS16(tmp + 28) & 0xf800) >> 11);
		965	lvds->native_mode.dotclock =
		966	RBIOS16(tmp + 9) * 10;
		967	lvds->native_mode.flags = 0;
		968	}
		969	}
		970	} else {
		971	DRM_INFO("No panel info found in BIOS\n");
1179	serge	972	lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1123	serge	973	}
1179	serge	974	out:
		975	if (lvds)
		976	encoder->native_mode = lvds->native_mode;
1123	serge	977	return lvds;
		978	}
		979
		980	static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
		981	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
		982	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
		983	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
		984	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
		985	{{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
		986	{{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
		987	{{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
		988	{{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
		989	{{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
		990	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
		991	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
		992	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
		993	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
		994	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
		995	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
		996	{{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
		997	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS400 */
		998	{{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */
		999	};
		1000
1179	serge	1001	bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
		1002	struct radeon_encoder_int_tmds *tmds)
1123	serge	1003	{
1179	serge	1004	struct drm_device *dev = encoder->base.dev;
		1005	struct radeon_device *rdev = dev->dev_private;
1123	serge	1006	int i;
		1007
		1008	for (i = 0; i < 4; i++) {
		1009	tmds->tmds_pll[i].value =
		1010	default_tmds_pll[rdev->family][i].value;
		1011	tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
		1012	}
		1013
1179	serge	1014	return true;
1123	serge	1015	}
		1016
1179	serge	1017	bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
		1018	struct radeon_encoder_int_tmds *tmds)
1123	serge	1019	{
		1020	struct drm_device *dev = encoder->base.dev;
		1021	struct radeon_device *rdev = dev->dev_private;
		1022	uint16_t tmds_info;
		1023	int i, n;
		1024	uint8_t ver;
		1025
		1026	if (rdev->bios == NULL)
1179	serge	1027	return false;
1123	serge	1028
		1029	tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1030
		1031	if (tmds_info) {
		1032
		1033	ver = RBIOS8(tmds_info);
		1034	DRM_INFO("DFP table revision: %d\n", ver);
		1035	if (ver == 3) {
		1036	n = RBIOS8(tmds_info + 5) + 1;
		1037	if (n > 4)
		1038	n = 4;
		1039	for (i = 0; i < n; i++) {
		1040	tmds->tmds_pll[i].value =
		1041	RBIOS32(tmds_info + i * 10 + 0x08);
		1042	tmds->tmds_pll[i].freq =
		1043	RBIOS16(tmds_info + i * 10 + 0x10);
		1044	DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
		1045	tmds->tmds_pll[i].freq,
		1046	tmds->tmds_pll[i].value);
		1047	}
		1048	} else if (ver == 4) {
		1049	int stride = 0;
		1050	n = RBIOS8(tmds_info + 5) + 1;
		1051	if (n > 4)
		1052	n = 4;
		1053	for (i = 0; i < n; i++) {
		1054	tmds->tmds_pll[i].value =
		1055	RBIOS32(tmds_info + stride + 0x08);
		1056	tmds->tmds_pll[i].freq =
		1057	RBIOS16(tmds_info + stride + 0x10);
		1058	if (i == 0)
		1059	stride += 10;
		1060	else
		1061	stride += 6;
		1062	DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
		1063	tmds->tmds_pll[i].freq,
		1064	tmds->tmds_pll[i].value);
		1065	}
		1066	}
		1067	} else
		1068	DRM_INFO("No TMDS info found in BIOS\n");
1179	serge	1069	return true;
		1070	}
		1071
		1072	struct radeon_encoder_int_tmds radeon_combios_get_tmds_info(struct radeon_encoder encoder)
		1073	{
		1074	struct radeon_encoder_int_tmds *tmds = NULL;
		1075	bool ret;
		1076
		1077	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
		1078
		1079	if (!tmds)
		1080	return NULL;
		1081
		1082	ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
		1083	if (ret == false)
		1084	radeon_legacy_get_tmds_info_from_table(encoder, tmds);
		1085
1123	serge	1086	return tmds;
		1087	}
		1088
		1089	void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
		1090	{
		1091	struct drm_device *dev = encoder->base.dev;
		1092	struct radeon_device *rdev = dev->dev_private;
		1093	uint16_t ext_tmds_info;
		1094	uint8_t ver;
		1095
		1096	if (rdev->bios == NULL)
		1097	return;
		1098
		1099	ext_tmds_info =
		1100	combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
		1101	if (ext_tmds_info) {
		1102	ver = RBIOS8(ext_tmds_info);
		1103	DRM_INFO("External TMDS Table revision: %d\n", ver);
		1104	// TODO
		1105	}
		1106	}
		1107
		1108	bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
		1109	{
		1110	struct radeon_device *rdev = dev->dev_private;
		1111	struct radeon_i2c_bus_rec ddc_i2c;
		1112
		1113	rdev->mode_info.connector_table = radeon_connector_table;
		1114	if (rdev->mode_info.connector_table == CT_NONE) {
		1115	#ifdef CONFIG_PPC_PMAC
		1116	if (machine_is_compatible("PowerBook3,3")) {
		1117	/* powerbook with VGA */
		1118	rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
		1119	} else if (machine_is_compatible("PowerBook3,4") \|\|
		1120	machine_is_compatible("PowerBook3,5")) {
		1121	/* powerbook with internal tmds */
		1122	rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
		1123	} else if (machine_is_compatible("PowerBook5,1") \|\|
		1124	machine_is_compatible("PowerBook5,2") \|\|
		1125	machine_is_compatible("PowerBook5,3") \|\|
		1126	machine_is_compatible("PowerBook5,4") \|\|
		1127	machine_is_compatible("PowerBook5,5")) {
		1128	/* powerbook with external single link tmds (sil164) */
		1129	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1130	} else if (machine_is_compatible("PowerBook5,6")) {
		1131	/* powerbook with external dual or single link tmds */
		1132	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1133	} else if (machine_is_compatible("PowerBook5,7") \|\|
		1134	machine_is_compatible("PowerBook5,8") \|\|
		1135	machine_is_compatible("PowerBook5,9")) {
		1136	/* PowerBook6,2 ? */
		1137	/* powerbook with external dual link tmds (sil1178?) */
		1138	rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
		1139	} else if (machine_is_compatible("PowerBook4,1") \|\|
		1140	machine_is_compatible("PowerBook4,2") \|\|
		1141	machine_is_compatible("PowerBook4,3") \|\|
		1142	machine_is_compatible("PowerBook6,3") \|\|
		1143	machine_is_compatible("PowerBook6,5") \|\|
		1144	machine_is_compatible("PowerBook6,7")) {
		1145	/* ibook */
		1146	rdev->mode_info.connector_table = CT_IBOOK;
		1147	} else if (machine_is_compatible("PowerMac4,4")) {
		1148	/* emac */
		1149	rdev->mode_info.connector_table = CT_EMAC;
		1150	} else if (machine_is_compatible("PowerMac10,1")) {
		1151	/* mini with internal tmds */
		1152	rdev->mode_info.connector_table = CT_MINI_INTERNAL;
		1153	} else if (machine_is_compatible("PowerMac10,2")) {
		1154	/* mini with external tmds */
		1155	rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
		1156	} else if (machine_is_compatible("PowerMac12,1")) {
		1157	/* PowerMac8,1 ? */
		1158	/* imac g5 isight */
		1159	rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
		1160	} else
		1161	#endif /* CONFIG_PPC_PMAC */
		1162	rdev->mode_info.connector_table = CT_GENERIC;
		1163	}
		1164
		1165	switch (rdev->mode_info.connector_table) {
		1166	case CT_GENERIC:
		1167	DRM_INFO("Connector Table: %d (generic)\n",
		1168	rdev->mode_info.connector_table);
		1169	/* these are the most common settings */
		1170	if (rdev->flags & RADEON_SINGLE_CRTC) {
		1171	/* VGA - primary dac */
		1172	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1173	radeon_add_legacy_encoder(dev,
		1174	radeon_get_encoder_id(dev,
		1175	ATOM_DEVICE_CRT1_SUPPORT,
		1176	1),
		1177	ATOM_DEVICE_CRT1_SUPPORT);
		1178	radeon_add_legacy_connector(dev, 0,
		1179	ATOM_DEVICE_CRT1_SUPPORT,
		1180	DRM_MODE_CONNECTOR_VGA,
		1181	&ddc_i2c);
		1182	} else if (rdev->flags & RADEON_IS_MOBILITY) {
		1183	/* LVDS */
		1184	ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
		1185	radeon_add_legacy_encoder(dev,
		1186	radeon_get_encoder_id(dev,
		1187	ATOM_DEVICE_LCD1_SUPPORT,
		1188	0),
		1189	ATOM_DEVICE_LCD1_SUPPORT);
		1190	radeon_add_legacy_connector(dev, 0,
		1191	ATOM_DEVICE_LCD1_SUPPORT,
		1192	DRM_MODE_CONNECTOR_LVDS,
		1193	&ddc_i2c);
		1194
		1195	/* VGA - primary dac */
		1196	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1197	radeon_add_legacy_encoder(dev,
		1198	radeon_get_encoder_id(dev,
		1199	ATOM_DEVICE_CRT1_SUPPORT,
		1200	1),
		1201	ATOM_DEVICE_CRT1_SUPPORT);
		1202	radeon_add_legacy_connector(dev, 1,
		1203	ATOM_DEVICE_CRT1_SUPPORT,
		1204	DRM_MODE_CONNECTOR_VGA,
		1205	&ddc_i2c);
		1206	} else {
		1207	/* DVI-I - tv dac, int tmds */
		1208	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1209	radeon_add_legacy_encoder(dev,
		1210	radeon_get_encoder_id(dev,
		1211	ATOM_DEVICE_DFP1_SUPPORT,
		1212	0),
		1213	ATOM_DEVICE_DFP1_SUPPORT);
		1214	radeon_add_legacy_encoder(dev,
		1215	radeon_get_encoder_id(dev,
		1216	ATOM_DEVICE_CRT2_SUPPORT,
		1217	2),
		1218	ATOM_DEVICE_CRT2_SUPPORT);
		1219	radeon_add_legacy_connector(dev, 0,
		1220	ATOM_DEVICE_DFP1_SUPPORT \|
		1221	ATOM_DEVICE_CRT2_SUPPORT,
		1222	DRM_MODE_CONNECTOR_DVII,
		1223	&ddc_i2c);
		1224
		1225	/* VGA - primary dac */
		1226	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1227	radeon_add_legacy_encoder(dev,
		1228	radeon_get_encoder_id(dev,
		1229	ATOM_DEVICE_CRT1_SUPPORT,
		1230	1),
		1231	ATOM_DEVICE_CRT1_SUPPORT);
		1232	radeon_add_legacy_connector(dev, 1,
		1233	ATOM_DEVICE_CRT1_SUPPORT,
		1234	DRM_MODE_CONNECTOR_VGA,
		1235	&ddc_i2c);
		1236	}
		1237
		1238	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1239	/* TV - tv dac */
		1240	radeon_add_legacy_encoder(dev,
		1241	radeon_get_encoder_id(dev,
		1242	ATOM_DEVICE_TV1_SUPPORT,
		1243	2),
		1244	ATOM_DEVICE_TV1_SUPPORT);
		1245	radeon_add_legacy_connector(dev, 2,
		1246	ATOM_DEVICE_TV1_SUPPORT,
		1247	DRM_MODE_CONNECTOR_SVIDEO,
		1248	&ddc_i2c);
		1249	}
		1250	break;
		1251	case CT_IBOOK:
		1252	DRM_INFO("Connector Table: %d (ibook)\n",
		1253	rdev->mode_info.connector_table);
		1254	/* LVDS */
		1255	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1256	radeon_add_legacy_encoder(dev,
		1257	radeon_get_encoder_id(dev,
		1258	ATOM_DEVICE_LCD1_SUPPORT,
		1259	0),
		1260	ATOM_DEVICE_LCD1_SUPPORT);
		1261	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		1262	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
		1263	/* VGA - TV DAC */
		1264	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1265	radeon_add_legacy_encoder(dev,
		1266	radeon_get_encoder_id(dev,
		1267	ATOM_DEVICE_CRT2_SUPPORT,
		1268	2),
		1269	ATOM_DEVICE_CRT2_SUPPORT);
		1270	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		1271	DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
		1272	/* TV - TV DAC */
		1273	radeon_add_legacy_encoder(dev,
		1274	radeon_get_encoder_id(dev,
		1275	ATOM_DEVICE_TV1_SUPPORT,
		1276	2),
		1277	ATOM_DEVICE_TV1_SUPPORT);
		1278	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1279	DRM_MODE_CONNECTOR_SVIDEO,
		1280	&ddc_i2c);
		1281	break;
		1282	case CT_POWERBOOK_EXTERNAL:
		1283	DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
		1284	rdev->mode_info.connector_table);
		1285	/* LVDS */
		1286	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1287	radeon_add_legacy_encoder(dev,
		1288	radeon_get_encoder_id(dev,
		1289	ATOM_DEVICE_LCD1_SUPPORT,
		1290	0),
		1291	ATOM_DEVICE_LCD1_SUPPORT);
		1292	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		1293	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
		1294	/* DVI-I - primary dac, ext tmds */
		1295	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1296	radeon_add_legacy_encoder(dev,
		1297	radeon_get_encoder_id(dev,
		1298	ATOM_DEVICE_DFP2_SUPPORT,
		1299	0),
		1300	ATOM_DEVICE_DFP2_SUPPORT);
		1301	radeon_add_legacy_encoder(dev,
		1302	radeon_get_encoder_id(dev,
		1303	ATOM_DEVICE_CRT1_SUPPORT,
		1304	1),
		1305	ATOM_DEVICE_CRT1_SUPPORT);
		1306	radeon_add_legacy_connector(dev, 1,
		1307	ATOM_DEVICE_DFP2_SUPPORT \|
		1308	ATOM_DEVICE_CRT1_SUPPORT,
		1309	DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
		1310	/* TV - TV DAC */
		1311	radeon_add_legacy_encoder(dev,
		1312	radeon_get_encoder_id(dev,
		1313	ATOM_DEVICE_TV1_SUPPORT,
		1314	2),
		1315	ATOM_DEVICE_TV1_SUPPORT);
		1316	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1317	DRM_MODE_CONNECTOR_SVIDEO,
		1318	&ddc_i2c);
		1319	break;
		1320	case CT_POWERBOOK_INTERNAL:
		1321	DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
		1322	rdev->mode_info.connector_table);
		1323	/* LVDS */
		1324	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1325	radeon_add_legacy_encoder(dev,
		1326	radeon_get_encoder_id(dev,
		1327	ATOM_DEVICE_LCD1_SUPPORT,
		1328	0),
		1329	ATOM_DEVICE_LCD1_SUPPORT);
		1330	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		1331	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
		1332	/* DVI-I - primary dac, int tmds */
		1333	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1334	radeon_add_legacy_encoder(dev,
		1335	radeon_get_encoder_id(dev,
		1336	ATOM_DEVICE_DFP1_SUPPORT,
		1337	0),
		1338	ATOM_DEVICE_DFP1_SUPPORT);
		1339	radeon_add_legacy_encoder(dev,
		1340	radeon_get_encoder_id(dev,
		1341	ATOM_DEVICE_CRT1_SUPPORT,
		1342	1),
		1343	ATOM_DEVICE_CRT1_SUPPORT);
		1344	radeon_add_legacy_connector(dev, 1,
		1345	ATOM_DEVICE_DFP1_SUPPORT \|
		1346	ATOM_DEVICE_CRT1_SUPPORT,
		1347	DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
		1348	/* TV - TV DAC */
		1349	radeon_add_legacy_encoder(dev,
		1350	radeon_get_encoder_id(dev,
		1351	ATOM_DEVICE_TV1_SUPPORT,
		1352	2),
		1353	ATOM_DEVICE_TV1_SUPPORT);
		1354	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1355	DRM_MODE_CONNECTOR_SVIDEO,
		1356	&ddc_i2c);
		1357	break;
		1358	case CT_POWERBOOK_VGA:
		1359	DRM_INFO("Connector Table: %d (powerbook vga)\n",
		1360	rdev->mode_info.connector_table);
		1361	/* LVDS */
		1362	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1363	radeon_add_legacy_encoder(dev,
		1364	radeon_get_encoder_id(dev,
		1365	ATOM_DEVICE_LCD1_SUPPORT,
		1366	0),
		1367	ATOM_DEVICE_LCD1_SUPPORT);
		1368	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
		1369	DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
		1370	/* VGA - primary dac */
		1371	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1372	radeon_add_legacy_encoder(dev,
		1373	radeon_get_encoder_id(dev,
		1374	ATOM_DEVICE_CRT1_SUPPORT,
		1375	1),
		1376	ATOM_DEVICE_CRT1_SUPPORT);
		1377	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
		1378	DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
		1379	/* TV - TV DAC */
		1380	radeon_add_legacy_encoder(dev,
		1381	radeon_get_encoder_id(dev,
		1382	ATOM_DEVICE_TV1_SUPPORT,
		1383	2),
		1384	ATOM_DEVICE_TV1_SUPPORT);
		1385	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1386	DRM_MODE_CONNECTOR_SVIDEO,
		1387	&ddc_i2c);
		1388	break;
		1389	case CT_MINI_EXTERNAL:
		1390	DRM_INFO("Connector Table: %d (mini external tmds)\n",
		1391	rdev->mode_info.connector_table);
		1392	/* DVI-I - tv dac, ext tmds */
		1393	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
		1394	radeon_add_legacy_encoder(dev,
		1395	radeon_get_encoder_id(dev,
		1396	ATOM_DEVICE_DFP2_SUPPORT,
		1397	0),
		1398	ATOM_DEVICE_DFP2_SUPPORT);
		1399	radeon_add_legacy_encoder(dev,
		1400	radeon_get_encoder_id(dev,
		1401	ATOM_DEVICE_CRT2_SUPPORT,
		1402	2),
		1403	ATOM_DEVICE_CRT2_SUPPORT);
		1404	radeon_add_legacy_connector(dev, 0,
		1405	ATOM_DEVICE_DFP2_SUPPORT \|
		1406	ATOM_DEVICE_CRT2_SUPPORT,
		1407	DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
		1408	/* TV - TV DAC */
		1409	radeon_add_legacy_encoder(dev,
		1410	radeon_get_encoder_id(dev,
		1411	ATOM_DEVICE_TV1_SUPPORT,
		1412	2),
		1413	ATOM_DEVICE_TV1_SUPPORT);
		1414	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1415	DRM_MODE_CONNECTOR_SVIDEO,
		1416	&ddc_i2c);
		1417	break;
		1418	case CT_MINI_INTERNAL:
		1419	DRM_INFO("Connector Table: %d (mini internal tmds)\n",
		1420	rdev->mode_info.connector_table);
		1421	/* DVI-I - tv dac, int tmds */
		1422	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
		1423	radeon_add_legacy_encoder(dev,
		1424	radeon_get_encoder_id(dev,
		1425	ATOM_DEVICE_DFP1_SUPPORT,
		1426	0),
		1427	ATOM_DEVICE_DFP1_SUPPORT);
		1428	radeon_add_legacy_encoder(dev,
		1429	radeon_get_encoder_id(dev,
		1430	ATOM_DEVICE_CRT2_SUPPORT,
		1431	2),
		1432	ATOM_DEVICE_CRT2_SUPPORT);
		1433	radeon_add_legacy_connector(dev, 0,
		1434	ATOM_DEVICE_DFP1_SUPPORT \|
		1435	ATOM_DEVICE_CRT2_SUPPORT,
		1436	DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
		1437	/* TV - TV DAC */
		1438	radeon_add_legacy_encoder(dev,
		1439	radeon_get_encoder_id(dev,
		1440	ATOM_DEVICE_TV1_SUPPORT,
		1441	2),
		1442	ATOM_DEVICE_TV1_SUPPORT);
		1443	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
		1444	DRM_MODE_CONNECTOR_SVIDEO,
		1445	&ddc_i2c);
		1446	break;
		1447	case CT_IMAC_G5_ISIGHT:
		1448	DRM_INFO("Connector Table: %d (imac g5 isight)\n",
		1449	rdev->mode_info.connector_table);
		1450	/* DVI-D - int tmds */
		1451	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
		1452	radeon_add_legacy_encoder(dev,
		1453	radeon_get_encoder_id(dev,
		1454	ATOM_DEVICE_DFP1_SUPPORT,
		1455	0),
		1456	ATOM_DEVICE_DFP1_SUPPORT);
		1457	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
		1458	DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
		1459	/* VGA - tv dac */
		1460	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1461	radeon_add_legacy_encoder(dev,
		1462	radeon_get_encoder_id(dev,
		1463	ATOM_DEVICE_CRT2_SUPPORT,
		1464	2),
		1465	ATOM_DEVICE_CRT2_SUPPORT);
		1466	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		1467	DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
		1468	/* TV - TV DAC */
		1469	radeon_add_legacy_encoder(dev,
		1470	radeon_get_encoder_id(dev,
		1471	ATOM_DEVICE_TV1_SUPPORT,
		1472	2),
		1473	ATOM_DEVICE_TV1_SUPPORT);
		1474	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1475	DRM_MODE_CONNECTOR_SVIDEO,
		1476	&ddc_i2c);
		1477	break;
		1478	case CT_EMAC:
		1479	DRM_INFO("Connector Table: %d (emac)\n",
		1480	rdev->mode_info.connector_table);
		1481	/* VGA - primary dac */
		1482	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1483	radeon_add_legacy_encoder(dev,
		1484	radeon_get_encoder_id(dev,
		1485	ATOM_DEVICE_CRT1_SUPPORT,
		1486	1),
		1487	ATOM_DEVICE_CRT1_SUPPORT);
		1488	radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
		1489	DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
		1490	/* VGA - tv dac */
		1491	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
		1492	radeon_add_legacy_encoder(dev,
		1493	radeon_get_encoder_id(dev,
		1494	ATOM_DEVICE_CRT2_SUPPORT,
		1495	2),
		1496	ATOM_DEVICE_CRT2_SUPPORT);
		1497	radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
		1498	DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
		1499	/* TV - TV DAC */
		1500	radeon_add_legacy_encoder(dev,
		1501	radeon_get_encoder_id(dev,
		1502	ATOM_DEVICE_TV1_SUPPORT,
		1503	2),
		1504	ATOM_DEVICE_TV1_SUPPORT);
		1505	radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
		1506	DRM_MODE_CONNECTOR_SVIDEO,
		1507	&ddc_i2c);
		1508	break;
		1509	default:
		1510	DRM_INFO("Connector table: %d (invalid)\n",
		1511	rdev->mode_info.connector_table);
		1512	return false;
		1513	}
		1514
		1515	radeon_link_encoder_connector(dev);
		1516
		1517	return true;
		1518	}
		1519
		1520	static bool radeon_apply_legacy_quirks(struct drm_device *dev,
		1521	int bios_index,
		1522	enum radeon_combios_connector
		1523	*legacy_connector,
		1524	struct radeon_i2c_bus_rec *ddc_i2c)
		1525	{
		1526	struct radeon_device *rdev = dev->dev_private;
		1527
		1528	/* XPRESS DDC quirks */
		1529	if ((rdev->family == CHIP_RS400 \|\|
		1530	rdev->family == CHIP_RS480) &&
		1531	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		1532	*ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
		1533	else if ((rdev->family == CHIP_RS400 \|\|
		1534	rdev->family == CHIP_RS480) &&
		1535	ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
		1536	ddc_i2c->valid = true;
		1537	ddc_i2c->mask_clk_mask = (0x20 << 8);
		1538	ddc_i2c->mask_data_mask = 0x80;
		1539	ddc_i2c->a_clk_mask = (0x20 << 8);
		1540	ddc_i2c->a_data_mask = 0x80;
		1541	ddc_i2c->put_clk_mask = (0x20 << 8);
		1542	ddc_i2c->put_data_mask = 0x80;
		1543	ddc_i2c->get_clk_mask = (0x20 << 8);
		1544	ddc_i2c->get_data_mask = 0x80;
		1545	ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
		1546	ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
		1547	ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
		1548	ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
		1549	ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
		1550	ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
		1551	ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
		1552	ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
		1553	}
		1554
		1555	/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
		1556	one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
		1557	if (dev->pdev->device == 0x515e &&
		1558	dev->pdev->subsystem_vendor == 0x1014) {
		1559	if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
		1560	ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
		1561	return false;
		1562	}
		1563
		1564	/* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
		1565	if (dev->pdev->device == 0x5159 &&
		1566	dev->pdev->subsystem_vendor == 0x1002 &&
		1567	dev->pdev->subsystem_device == 0x013a) {
		1568	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		1569	*legacy_connector = CONNECTOR_CRT_LEGACY;
		1570
		1571	}
		1572
		1573	/* X300 card with extra non-existent DVI port */
		1574	if (dev->pdev->device == 0x5B60 &&
		1575	dev->pdev->subsystem_vendor == 0x17af &&
		1576	dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
		1577	if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
		1578	return false;
		1579	}
		1580
		1581	return true;
		1582	}
		1583
		1584	bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
		1585	{
		1586	struct radeon_device *rdev = dev->dev_private;
		1587	uint32_t conn_info, entry, devices;
		1588	uint16_t tmp;
		1589	enum radeon_combios_ddc ddc_type;
		1590	enum radeon_combios_connector connector;
		1591	int i = 0;
		1592	struct radeon_i2c_bus_rec ddc_i2c;
		1593
		1594	if (rdev->bios == NULL)
		1595	return false;
		1596
		1597	conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
		1598	if (conn_info) {
		1599	for (i = 0; i < 4; i++) {
		1600	entry = conn_info + 2 + i * 2;
		1601
		1602	if (!RBIOS16(entry))
		1603	break;
		1604
		1605	tmp = RBIOS16(entry);
		1606
		1607	connector = (tmp >> 12) & 0xf;
		1608
		1609	ddc_type = (tmp >> 8) & 0xf;
		1610	switch (ddc_type) {
		1611	case DDC_MONID:
		1612	ddc_i2c =
		1613	combios_setup_i2c_bus(RADEON_GPIO_MONID);
		1614	break;
		1615	case DDC_DVI:
		1616	ddc_i2c =
		1617	combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1618	break;
		1619	case DDC_VGA:
		1620	ddc_i2c =
		1621	combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
		1622	break;
		1623	case DDC_CRT2:
		1624	ddc_i2c =
		1625	combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
		1626	break;
		1627	default:
		1628	break;
		1629	}
		1630
		1631	radeon_apply_legacy_quirks(dev, i, &connector,
		1632	&ddc_i2c);
		1633
		1634	switch (connector) {
		1635	case CONNECTOR_PROPRIETARY_LEGACY:
		1636	if ((tmp >> 4) & 0x1)
		1637	devices = ATOM_DEVICE_DFP2_SUPPORT;
		1638	else
		1639	devices = ATOM_DEVICE_DFP1_SUPPORT;
		1640	radeon_add_legacy_encoder(dev,
		1641	radeon_get_encoder_id
		1642	(dev, devices, 0),
		1643	devices);
		1644	radeon_add_legacy_connector(dev, i, devices,
		1645	legacy_connector_convert
		1646	[connector],
		1647	&ddc_i2c);
		1648	break;
		1649	case CONNECTOR_CRT_LEGACY:
		1650	if (tmp & 0x1) {
		1651	devices = ATOM_DEVICE_CRT2_SUPPORT;
		1652	radeon_add_legacy_encoder(dev,
		1653	radeon_get_encoder_id
		1654	(dev,
		1655	ATOM_DEVICE_CRT2_SUPPORT,
		1656	2),
		1657	ATOM_DEVICE_CRT2_SUPPORT);
		1658	} else {
		1659	devices = ATOM_DEVICE_CRT1_SUPPORT;
		1660	radeon_add_legacy_encoder(dev,
		1661	radeon_get_encoder_id
		1662	(dev,
		1663	ATOM_DEVICE_CRT1_SUPPORT,
		1664	1),
		1665	ATOM_DEVICE_CRT1_SUPPORT);
		1666	}
		1667	radeon_add_legacy_connector(dev,
		1668	i,
		1669	devices,
		1670	legacy_connector_convert
		1671	[connector],
		1672	&ddc_i2c);
		1673	break;
		1674	case CONNECTOR_DVI_I_LEGACY:
		1675	devices = 0;
		1676	if (tmp & 0x1) {
		1677	devices \|= ATOM_DEVICE_CRT2_SUPPORT;
		1678	radeon_add_legacy_encoder(dev,
		1679	radeon_get_encoder_id
		1680	(dev,
		1681	ATOM_DEVICE_CRT2_SUPPORT,
		1682	2),
		1683	ATOM_DEVICE_CRT2_SUPPORT);
		1684	} else {
		1685	devices \|= ATOM_DEVICE_CRT1_SUPPORT;
		1686	radeon_add_legacy_encoder(dev,
		1687	radeon_get_encoder_id
		1688	(dev,
		1689	ATOM_DEVICE_CRT1_SUPPORT,
		1690	1),
		1691	ATOM_DEVICE_CRT1_SUPPORT);
		1692	}
		1693	if ((tmp >> 4) & 0x1) {
		1694	devices \|= ATOM_DEVICE_DFP2_SUPPORT;
		1695	radeon_add_legacy_encoder(dev,
		1696	radeon_get_encoder_id
		1697	(dev,
		1698	ATOM_DEVICE_DFP2_SUPPORT,
		1699	0),
		1700	ATOM_DEVICE_DFP2_SUPPORT);
		1701	} else {
		1702	devices \|= ATOM_DEVICE_DFP1_SUPPORT;
		1703	radeon_add_legacy_encoder(dev,
		1704	radeon_get_encoder_id
		1705	(dev,
		1706	ATOM_DEVICE_DFP1_SUPPORT,
		1707	0),
		1708	ATOM_DEVICE_DFP1_SUPPORT);
		1709	}
		1710	radeon_add_legacy_connector(dev,
		1711	i,
		1712	devices,
		1713	legacy_connector_convert
		1714	[connector],
		1715	&ddc_i2c);
		1716	break;
		1717	case CONNECTOR_DVI_D_LEGACY:
		1718	if ((tmp >> 4) & 0x1)
		1719	devices = ATOM_DEVICE_DFP2_SUPPORT;
		1720	else
		1721	devices = ATOM_DEVICE_DFP1_SUPPORT;
		1722	radeon_add_legacy_encoder(dev,
		1723	radeon_get_encoder_id
		1724	(dev, devices, 0),
		1725	devices);
		1726	radeon_add_legacy_connector(dev, i, devices,
		1727	legacy_connector_convert
		1728	[connector],
		1729	&ddc_i2c);
		1730	break;
		1731	case CONNECTOR_CTV_LEGACY:
		1732	case CONNECTOR_STV_LEGACY:
		1733	radeon_add_legacy_encoder(dev,
		1734	radeon_get_encoder_id
		1735	(dev,
		1736	ATOM_DEVICE_TV1_SUPPORT,
		1737	2),
		1738	ATOM_DEVICE_TV1_SUPPORT);
		1739	radeon_add_legacy_connector(dev, i,
		1740	ATOM_DEVICE_TV1_SUPPORT,
		1741	legacy_connector_convert
		1742	[connector],
		1743	&ddc_i2c);
		1744	break;
		1745	default:
		1746	DRM_ERROR("Unknown connector type: %d\n",
		1747	connector);
		1748	continue;
		1749	}
		1750
		1751	}
		1752	} else {
		1753	uint16_t tmds_info =
		1754	combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
		1755	if (tmds_info) {
		1756	DRM_DEBUG("Found DFP table, assuming DVI connector\n");
		1757
		1758	radeon_add_legacy_encoder(dev,
		1759	radeon_get_encoder_id(dev,
		1760	ATOM_DEVICE_CRT1_SUPPORT,
		1761	1),
		1762	ATOM_DEVICE_CRT1_SUPPORT);
		1763	radeon_add_legacy_encoder(dev,
		1764	radeon_get_encoder_id(dev,
		1765	ATOM_DEVICE_DFP1_SUPPORT,
		1766	0),
		1767	ATOM_DEVICE_DFP1_SUPPORT);
		1768
		1769	ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
		1770	radeon_add_legacy_connector(dev,
		1771	0,
		1772	ATOM_DEVICE_CRT1_SUPPORT \|
		1773	ATOM_DEVICE_DFP1_SUPPORT,
		1774	DRM_MODE_CONNECTOR_DVII,
		1775	&ddc_i2c);
		1776	} else {
		1777	DRM_DEBUG("No connector info found\n");
		1778	return false;
		1779	}
		1780	}
		1781
		1782	if (rdev->flags & RADEON_IS_MOBILITY \|\| rdev->flags & RADEON_IS_IGP) {
		1783	uint16_t lcd_info =
		1784	combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
		1785	if (lcd_info) {
		1786	uint16_t lcd_ddc_info =
		1787	combios_get_table_offset(dev,
		1788	COMBIOS_LCD_DDC_INFO_TABLE);
		1789
		1790	radeon_add_legacy_encoder(dev,
		1791	radeon_get_encoder_id(dev,
		1792	ATOM_DEVICE_LCD1_SUPPORT,
		1793	0),
		1794	ATOM_DEVICE_LCD1_SUPPORT);
		1795
		1796	if (lcd_ddc_info) {
		1797	ddc_type = RBIOS8(lcd_ddc_info + 2);
		1798	switch (ddc_type) {
		1799	case DDC_MONID:
		1800	ddc_i2c =
		1801	combios_setup_i2c_bus
		1802	(RADEON_GPIO_MONID);
		1803	break;
		1804	case DDC_DVI:
		1805	ddc_i2c =
		1806	combios_setup_i2c_bus
		1807	(RADEON_GPIO_DVI_DDC);
		1808	break;
		1809	case DDC_VGA:
		1810	ddc_i2c =
		1811	combios_setup_i2c_bus
		1812	(RADEON_GPIO_VGA_DDC);
		1813	break;
		1814	case DDC_CRT2:
		1815	ddc_i2c =
		1816	combios_setup_i2c_bus
		1817	(RADEON_GPIO_CRT2_DDC);
		1818	break;
		1819	case DDC_LCD:
		1820	ddc_i2c =
		1821	combios_setup_i2c_bus
		1822	(RADEON_LCD_GPIO_MASK);
		1823	ddc_i2c.mask_clk_mask =
		1824	RBIOS32(lcd_ddc_info + 3);
		1825	ddc_i2c.mask_data_mask =
		1826	RBIOS32(lcd_ddc_info + 7);
		1827	ddc_i2c.a_clk_mask =
		1828	RBIOS32(lcd_ddc_info + 3);
		1829	ddc_i2c.a_data_mask =
		1830	RBIOS32(lcd_ddc_info + 7);
		1831	ddc_i2c.put_clk_mask =
		1832	RBIOS32(lcd_ddc_info + 3);
		1833	ddc_i2c.put_data_mask =
		1834	RBIOS32(lcd_ddc_info + 7);
		1835	ddc_i2c.get_clk_mask =
		1836	RBIOS32(lcd_ddc_info + 3);
		1837	ddc_i2c.get_data_mask =
		1838	RBIOS32(lcd_ddc_info + 7);
		1839	break;
		1840	case DDC_GPIO:
		1841	ddc_i2c =
		1842	combios_setup_i2c_bus
		1843	(RADEON_MDGPIO_EN_REG);
		1844	ddc_i2c.mask_clk_mask =
		1845	RBIOS32(lcd_ddc_info + 3);
		1846	ddc_i2c.mask_data_mask =
		1847	RBIOS32(lcd_ddc_info + 7);
		1848	ddc_i2c.a_clk_mask =
		1849	RBIOS32(lcd_ddc_info + 3);
		1850	ddc_i2c.a_data_mask =
		1851	RBIOS32(lcd_ddc_info + 7);
		1852	ddc_i2c.put_clk_mask =
		1853	RBIOS32(lcd_ddc_info + 3);
		1854	ddc_i2c.put_data_mask =
		1855	RBIOS32(lcd_ddc_info + 7);
		1856	ddc_i2c.get_clk_mask =
		1857	RBIOS32(lcd_ddc_info + 3);
		1858	ddc_i2c.get_data_mask =
		1859	RBIOS32(lcd_ddc_info + 7);
		1860	break;
		1861	default:
		1862	ddc_i2c.valid = false;
		1863	break;
		1864	}
		1865	DRM_DEBUG("LCD DDC Info Table found!\n");
		1866	} else
		1867	ddc_i2c.valid = false;
		1868
		1869	radeon_add_legacy_connector(dev,
		1870	5,
		1871	ATOM_DEVICE_LCD1_SUPPORT,
		1872	DRM_MODE_CONNECTOR_LVDS,
		1873	&ddc_i2c);
		1874	}
		1875	}
		1876
		1877	/* check TV table */
		1878	if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
		1879	uint32_t tv_info =
		1880	combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
		1881	if (tv_info) {
		1882	if (RBIOS8(tv_info + 6) == 'T') {
		1883	radeon_add_legacy_encoder(dev,
		1884	radeon_get_encoder_id
		1885	(dev,
		1886	ATOM_DEVICE_TV1_SUPPORT,
		1887	2),
		1888	ATOM_DEVICE_TV1_SUPPORT);
		1889	radeon_add_legacy_connector(dev, 6,
		1890	ATOM_DEVICE_TV1_SUPPORT,
		1891	DRM_MODE_CONNECTOR_SVIDEO,
		1892	&ddc_i2c);
		1893	}
		1894	}
		1895	}
		1896
		1897	radeon_link_encoder_connector(dev);
		1898
		1899	return true;
		1900	}
		1901
		1902	static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
		1903	{
		1904	struct radeon_device *rdev = dev->dev_private;
		1905
		1906	if (offset) {
		1907	while (RBIOS16(offset)) {
		1908	uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
		1909	uint32_t addr = (RBIOS16(offset) & 0x1fff);
		1910	uint32_t val, and_mask, or_mask;
		1911	uint32_t tmp;
		1912
		1913	offset += 2;
		1914	switch (cmd) {
		1915	case 0:
		1916	val = RBIOS32(offset);
		1917	offset += 4;
		1918	WREG32(addr, val);
		1919	break;
		1920	case 1:
		1921	val = RBIOS32(offset);
		1922	offset += 4;
		1923	WREG32(addr, val);
		1924	break;
		1925	case 2:
		1926	and_mask = RBIOS32(offset);
		1927	offset += 4;
		1928	or_mask = RBIOS32(offset);
		1929	offset += 4;
		1930	tmp = RREG32(addr);
		1931	tmp &= and_mask;
		1932	tmp \|= or_mask;
		1933	WREG32(addr, tmp);
		1934	break;
		1935	case 3:
		1936	and_mask = RBIOS32(offset);
		1937	offset += 4;
		1938	or_mask = RBIOS32(offset);
		1939	offset += 4;
		1940	tmp = RREG32(addr);
		1941	tmp &= and_mask;
		1942	tmp \|= or_mask;
		1943	WREG32(addr, tmp);
		1944	break;
		1945	case 4:
		1946	val = RBIOS16(offset);
		1947	offset += 2;
		1948	udelay(val);
		1949	break;
		1950	case 5:
		1951	val = RBIOS16(offset);
		1952	offset += 2;
		1953	switch (addr) {
		1954	case 8:
		1955	while (val--) {
		1956	if (!
		1957	(RREG32_PLL
		1958	(RADEON_CLK_PWRMGT_CNTL) &
		1959	RADEON_MC_BUSY))
		1960	break;
		1961	}
		1962	break;
		1963	case 9:
		1964	while (val--) {
		1965	if ((RREG32(RADEON_MC_STATUS) &
		1966	RADEON_MC_IDLE))
		1967	break;
		1968	}
		1969	break;
		1970	default:
		1971	break;
		1972	}
		1973	break;
		1974	default:
		1975	break;
		1976	}
		1977	}
		1978	}
		1979	}
		1980
		1981	static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
		1982	{
		1983	struct radeon_device *rdev = dev->dev_private;
		1984
		1985	if (offset) {
		1986	while (RBIOS8(offset)) {
		1987	uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
		1988	uint8_t addr = (RBIOS8(offset) & 0x3f);
		1989	uint32_t val, shift, tmp;
		1990	uint32_t and_mask, or_mask;
		1991
		1992	offset++;
		1993	switch (cmd) {
		1994	case 0:
		1995	val = RBIOS32(offset);
		1996	offset += 4;
		1997	WREG32_PLL(addr, val);
		1998	break;
		1999	case 1:
		2000	shift = RBIOS8(offset) * 8;
		2001	offset++;
		2002	and_mask = RBIOS8(offset) << shift;
		2003	and_mask \|= ~(0xff << shift);
		2004	offset++;
		2005	or_mask = RBIOS8(offset) << shift;
		2006	offset++;
		2007	tmp = RREG32_PLL(addr);
		2008	tmp &= and_mask;
		2009	tmp \|= or_mask;
		2010	WREG32_PLL(addr, tmp);
		2011	break;
		2012	case 2:
		2013	case 3:
		2014	tmp = 1000;
		2015	switch (addr) {
		2016	case 1:
		2017	udelay(150);
		2018	break;
		2019	case 2:
		2020	udelay(1000);
		2021	break;
		2022	case 3:
		2023	while (tmp--) {
		2024	if (!
		2025	(RREG32_PLL
		2026	(RADEON_CLK_PWRMGT_CNTL) &
		2027	RADEON_MC_BUSY))
		2028	break;
		2029	}
		2030	break;
		2031	case 4:
		2032	while (tmp--) {
		2033	if (RREG32_PLL
		2034	(RADEON_CLK_PWRMGT_CNTL) &
		2035	RADEON_DLL_READY)
		2036	break;
		2037	}
		2038	break;
		2039	case 5:
		2040	tmp =
		2041	RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
		2042	if (tmp & RADEON_CG_NO1_DEBUG_0) {
		2043	#if 0
		2044	uint32_t mclk_cntl =
		2045	RREG32_PLL
		2046	(RADEON_MCLK_CNTL);
		2047	mclk_cntl &= 0xffff0000;
		2048	/mclk_cntl \|= 0x00001111;//* ??? */
		2049	WREG32_PLL(RADEON_MCLK_CNTL,
		2050	mclk_cntl);
		2051	udelay(10000);
		2052	#endif
		2053	WREG32_PLL
		2054	(RADEON_CLK_PWRMGT_CNTL,
		2055	tmp &
		2056	~RADEON_CG_NO1_DEBUG_0);
		2057	udelay(10000);
		2058	}
		2059	break;
		2060	default:
		2061	break;
		2062	}
		2063	break;
		2064	default:
		2065	break;
		2066	}
		2067	}
		2068	}
		2069	}
		2070
		2071	static void combios_parse_ram_reset_table(struct drm_device *dev,
		2072	uint16_t offset)
		2073	{
		2074	struct radeon_device *rdev = dev->dev_private;
		2075	uint32_t tmp;
		2076
		2077	if (offset) {
		2078	uint8_t val = RBIOS8(offset);
		2079	while (val != 0xff) {
		2080	offset++;
		2081
		2082	if (val == 0x0f) {
		2083	uint32_t channel_complete_mask;
		2084
		2085	if (ASIC_IS_R300(rdev))
		2086	channel_complete_mask =
		2087	R300_MEM_PWRUP_COMPLETE;
		2088	else
		2089	channel_complete_mask =
		2090	RADEON_MEM_PWRUP_COMPLETE;
		2091	tmp = 20000;
		2092	while (tmp--) {
		2093	if ((RREG32(RADEON_MEM_STR_CNTL) &
		2094	channel_complete_mask) ==
		2095	channel_complete_mask)
		2096	break;
		2097	}
		2098	} else {
		2099	uint32_t or_mask = RBIOS16(offset);
		2100	offset += 2;
		2101
		2102	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2103	tmp &= RADEON_SDRAM_MODE_MASK;
		2104	tmp \|= or_mask;
		2105	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		2106
		2107	or_mask = val << 24;
		2108	tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
		2109	tmp &= RADEON_B3MEM_RESET_MASK;
		2110	tmp \|= or_mask;
		2111	WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
		2112	}
		2113	val = RBIOS8(offset);
		2114	}
		2115	}
		2116	}
		2117
		2118	static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
		2119	int mem_addr_mapping)
		2120	{
		2121	struct radeon_device *rdev = dev->dev_private;
		2122	uint32_t mem_cntl;
		2123	uint32_t mem_size;
		2124	uint32_t addr = 0;
		2125
		2126	mem_cntl = RREG32(RADEON_MEM_CNTL);
		2127	if (mem_cntl & RV100_HALF_MODE)
		2128	ram /= 2;
		2129	mem_size = ram;
		2130	mem_cntl &= ~(0xff << 8);
		2131	mem_cntl \|= (mem_addr_mapping & 0xff) << 8;
		2132	WREG32(RADEON_MEM_CNTL, mem_cntl);
		2133	RREG32(RADEON_MEM_CNTL);
		2134
		2135	/* sdram reset ? */
		2136
		2137	/* something like this???? */
		2138	while (ram--) {
		2139	addr = ram * 1024 * 1024;
		2140	/* write to each page */
		2141	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		2142	WREG32(RADEON_MM_DATA, 0xdeadbeef);
		2143	/* read back and verify */
		2144	WREG32(RADEON_MM_INDEX, (addr) \| RADEON_MM_APER);
		2145	if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
		2146	return 0;
		2147	}
		2148
		2149	return mem_size;
		2150	}
		2151
		2152	static void combios_write_ram_size(struct drm_device *dev)
		2153	{
		2154	struct radeon_device *rdev = dev->dev_private;
		2155	uint8_t rev;
		2156	uint16_t offset;
		2157	uint32_t mem_size = 0;
		2158	uint32_t mem_cntl = 0;
		2159
		2160	/* should do something smarter here I guess... */
		2161	if (rdev->flags & RADEON_IS_IGP)
		2162	return;
		2163
		2164	/* first check detected mem table */
		2165	offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
		2166	if (offset) {
		2167	rev = RBIOS8(offset);
		2168	if (rev < 3) {
		2169	mem_cntl = RBIOS32(offset + 1);
		2170	mem_size = RBIOS16(offset + 5);
		2171	if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
		2172	((dev->pdev->device != 0x515e)
		2173	&& (dev->pdev->device != 0x5969)))
		2174	WREG32(RADEON_MEM_CNTL, mem_cntl);
		2175	}
		2176	}
		2177
		2178	if (!mem_size) {
		2179	offset =
		2180	combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
		2181	if (offset) {
		2182	rev = RBIOS8(offset - 1);
		2183	if (rev < 1) {
		2184	if (((rdev->flags & RADEON_FAMILY_MASK) <
		2185	CHIP_R200)
		2186	&& ((dev->pdev->device != 0x515e)
		2187	&& (dev->pdev->device != 0x5969))) {
		2188	int ram = 0;
		2189	int mem_addr_mapping = 0;
		2190
		2191	while (RBIOS8(offset)) {
		2192	ram = RBIOS8(offset);
		2193	mem_addr_mapping =
		2194	RBIOS8(offset + 1);
		2195	if (mem_addr_mapping != 0x25)
		2196	ram *= 2;
		2197	mem_size =
		2198	combios_detect_ram(dev, ram,
		2199	mem_addr_mapping);
		2200	if (mem_size)
		2201	break;
		2202	offset += 2;
		2203	}
		2204	} else
		2205	mem_size = RBIOS8(offset);
		2206	} else {
		2207	mem_size = RBIOS8(offset);
		2208	mem_size = 2; / convert to MB */
		2209	}
		2210	}
		2211	}
		2212
		2213	mem_size = (1024 1024); /* convert to bytes */
		2214	WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
		2215	}
		2216
		2217	void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
		2218	{
		2219	uint16_t dyn_clk_info =
		2220	combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		2221
		2222	if (dyn_clk_info)
		2223	combios_parse_pll_table(dev, dyn_clk_info);
		2224	}
		2225
		2226	void radeon_combios_asic_init(struct drm_device *dev)
		2227	{
		2228	struct radeon_device *rdev = dev->dev_private;
		2229	uint16_t table;
		2230
		2231	/* port hardcoded mac stuff from radeonfb */
		2232	if (rdev->bios == NULL)
		2233	return;
		2234
		2235	/* ASIC INIT 1 */
		2236	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
		2237	if (table)
		2238	combios_parse_mmio_table(dev, table);
		2239
		2240	/* PLL INIT */
		2241	table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
		2242	if (table)
		2243	combios_parse_pll_table(dev, table);
		2244
		2245	/* ASIC INIT 2 */
		2246	table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
		2247	if (table)
		2248	combios_parse_mmio_table(dev, table);
		2249
		2250	if (!(rdev->flags & RADEON_IS_IGP)) {
		2251	/* ASIC INIT 4 */
		2252	table =
		2253	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
		2254	if (table)
		2255	combios_parse_mmio_table(dev, table);
		2256
		2257	/* RAM RESET */
		2258	table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
		2259	if (table)
		2260	combios_parse_ram_reset_table(dev, table);
		2261
		2262	/* ASIC INIT 3 */
		2263	table =
		2264	combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
		2265	if (table)
		2266	combios_parse_mmio_table(dev, table);
		2267
		2268	/* write CONFIG_MEMSIZE */
		2269	combios_write_ram_size(dev);
		2270	}
		2271
		2272	/* DYN CLK 1 */
		2273	table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
		2274	if (table)
		2275	combios_parse_pll_table(dev, table);
		2276
		2277	}
		2278
		2279	void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
		2280	{
		2281	struct radeon_device *rdev = dev->dev_private;
		2282	uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
		2283
		2284	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		2285	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2286	bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
		2287
		2288	/* let the bios control the backlight */
		2289	bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
		2290
		2291	/* tell the bios not to handle mode switching */
		2292	bios_6_scratch \|= (RADEON_DISPLAY_SWITCHING_DIS \|
		2293	RADEON_ACC_MODE_CHANGE);
		2294
		2295	/* tell the bios a driver is loaded */
		2296	bios_7_scratch \|= RADEON_DRV_LOADED;
		2297
		2298	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		2299	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2300	WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
		2301	}
		2302
		2303	void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
		2304	{
		2305	struct drm_device *dev = encoder->dev;
		2306	struct radeon_device *rdev = dev->dev_private;
		2307	uint32_t bios_6_scratch;
		2308
		2309	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2310
		2311	if (lock)
		2312	bios_6_scratch \|= RADEON_DRIVER_CRITICAL;
		2313	else
		2314	bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
		2315
		2316	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2317	}
		2318
		2319	void
		2320	radeon_combios_connected_scratch_regs(struct drm_connector *connector,
		2321	struct drm_encoder *encoder,
		2322	bool connected)
		2323	{
		2324	struct drm_device *dev = connector->dev;
		2325	struct radeon_device *rdev = dev->dev_private;
		2326	struct radeon_connector *radeon_connector =
		2327	to_radeon_connector(connector);
		2328	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2329	uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
		2330	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		2331
		2332	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		2333	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		2334	if (connected) {
		2335	DRM_DEBUG("TV1 connected\n");
		2336	/* fix me */
		2337	bios_4_scratch \|= RADEON_TV1_ATTACHED_SVIDEO;
		2338	/save->bios_4_scratch \|= RADEON_TV1_ATTACHED_COMP; /
		2339	bios_5_scratch \|= RADEON_TV1_ON;
		2340	bios_5_scratch \|= RADEON_ACC_REQ_TV1;
		2341	} else {
		2342	DRM_DEBUG("TV1 disconnected\n");
		2343	bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
		2344	bios_5_scratch &= ~RADEON_TV1_ON;
		2345	bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
		2346	}
		2347	}
		2348	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		2349	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		2350	if (connected) {
		2351	DRM_DEBUG("LCD1 connected\n");
		2352	bios_4_scratch \|= RADEON_LCD1_ATTACHED;
		2353	bios_5_scratch \|= RADEON_LCD1_ON;
		2354	bios_5_scratch \|= RADEON_ACC_REQ_LCD1;
		2355	} else {
		2356	DRM_DEBUG("LCD1 disconnected\n");
		2357	bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
		2358	bios_5_scratch &= ~RADEON_LCD1_ON;
		2359	bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
		2360	}
		2361	}
		2362	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		2363	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		2364	if (connected) {
		2365	DRM_DEBUG("CRT1 connected\n");
		2366	bios_4_scratch \|= RADEON_CRT1_ATTACHED_COLOR;
		2367	bios_5_scratch \|= RADEON_CRT1_ON;
		2368	bios_5_scratch \|= RADEON_ACC_REQ_CRT1;
		2369	} else {
		2370	DRM_DEBUG("CRT1 disconnected\n");
		2371	bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
		2372	bios_5_scratch &= ~RADEON_CRT1_ON;
		2373	bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
		2374	}
		2375	}
		2376	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		2377	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		2378	if (connected) {
		2379	DRM_DEBUG("CRT2 connected\n");
		2380	bios_4_scratch \|= RADEON_CRT2_ATTACHED_COLOR;
		2381	bios_5_scratch \|= RADEON_CRT2_ON;
		2382	bios_5_scratch \|= RADEON_ACC_REQ_CRT2;
		2383	} else {
		2384	DRM_DEBUG("CRT2 disconnected\n");
		2385	bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
		2386	bios_5_scratch &= ~RADEON_CRT2_ON;
		2387	bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
		2388	}
		2389	}
		2390	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		2391	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		2392	if (connected) {
		2393	DRM_DEBUG("DFP1 connected\n");
		2394	bios_4_scratch \|= RADEON_DFP1_ATTACHED;
		2395	bios_5_scratch \|= RADEON_DFP1_ON;
		2396	bios_5_scratch \|= RADEON_ACC_REQ_DFP1;
		2397	} else {
		2398	DRM_DEBUG("DFP1 disconnected\n");
		2399	bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
		2400	bios_5_scratch &= ~RADEON_DFP1_ON;
		2401	bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
		2402	}
		2403	}
		2404	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		2405	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		2406	if (connected) {
		2407	DRM_DEBUG("DFP2 connected\n");
		2408	bios_4_scratch \|= RADEON_DFP2_ATTACHED;
		2409	bios_5_scratch \|= RADEON_DFP2_ON;
		2410	bios_5_scratch \|= RADEON_ACC_REQ_DFP2;
		2411	} else {
		2412	DRM_DEBUG("DFP2 disconnected\n");
		2413	bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
		2414	bios_5_scratch &= ~RADEON_DFP2_ON;
		2415	bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
		2416	}
		2417	}
		2418	WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
		2419	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		2420	}
		2421
		2422	void
		2423	radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		2424	{
		2425	struct drm_device *dev = encoder->dev;
		2426	struct radeon_device *rdev = dev->dev_private;
		2427	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2428	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
		2429
		2430	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2431	bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
		2432	bios_5_scratch \|= (crtc << RADEON_TV1_CRTC_SHIFT);
		2433	}
		2434	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		2435	bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
		2436	bios_5_scratch \|= (crtc << RADEON_CRT1_CRTC_SHIFT);
		2437	}
		2438	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		2439	bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
		2440	bios_5_scratch \|= (crtc << RADEON_CRT2_CRTC_SHIFT);
		2441	}
		2442	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		2443	bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
		2444	bios_5_scratch \|= (crtc << RADEON_LCD1_CRTC_SHIFT);
		2445	}
		2446	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		2447	bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
		2448	bios_5_scratch \|= (crtc << RADEON_DFP1_CRTC_SHIFT);
		2449	}
		2450	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		2451	bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
		2452	bios_5_scratch \|= (crtc << RADEON_DFP2_CRTC_SHIFT);
		2453	}
		2454	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
		2455	}
		2456
		2457	void
		2458	radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		2459	{
		2460	struct drm_device *dev = encoder->dev;
		2461	struct radeon_device *rdev = dev->dev_private;
		2462	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2463	uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2464
		2465	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
		2466	if (on)
		2467	bios_6_scratch \|= RADEON_TV_DPMS_ON;
		2468	else
		2469	bios_6_scratch &= ~RADEON_TV_DPMS_ON;
		2470	}
		2471	if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
		2472	if (on)
		2473	bios_6_scratch \|= RADEON_CRT_DPMS_ON;
		2474	else
		2475	bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
		2476	}
		2477	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		2478	if (on)
		2479	bios_6_scratch \|= RADEON_LCD_DPMS_ON;
		2480	else
		2481	bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
		2482	}
		2483	if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
		2484	if (on)
		2485	bios_6_scratch \|= RADEON_DFP_DPMS_ON;
		2486	else
		2487	bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
		2488	}
		2489	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2490	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_combios.c – Rev 1179