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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1123 | serge | 28 | #include "drmP.h" |
1117 | serge | 29 | #include "radeon_drm.h" |
30 | #include "radeon_reg.h" |
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31 | #include "radeon.h" |
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32 | #include "atom.h" |
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33 | |||
34 | /* 10 khz */ |
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1268 | serge | 35 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) |
1117 | serge | 36 | { |
37 | struct radeon_pll *spll = &rdev->clock.spll; |
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38 | uint32_t fb_div, ref_div, post_div, sclk; |
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39 | |||
40 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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41 | fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; |
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42 | fb_div <<= 1; |
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43 | fb_div *= spll->reference_freq; |
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44 | |||
45 | ref_div = |
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46 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
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1321 | serge | 47 | |
48 | if (ref_div == 0) |
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49 | return 0; |
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50 | |||
1117 | serge | 51 | sclk = fb_div / ref_div; |
52 | |||
53 | post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; |
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54 | if (post_div == 2) |
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55 | sclk >>= 1; |
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56 | else if (post_div == 3) |
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57 | sclk >>= 2; |
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58 | else if (post_div == 4) |
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1403 | serge | 59 | sclk >>= 3; |
1117 | serge | 60 | |
61 | return sclk; |
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62 | } |
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63 | |||
64 | /* 10 khz */ |
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1403 | serge | 65 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) |
1117 | serge | 66 | { |
67 | struct radeon_pll *mpll = &rdev->clock.mpll; |
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68 | uint32_t fb_div, ref_div, post_div, mclk; |
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69 | |||
70 | fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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71 | fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; |
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72 | fb_div <<= 1; |
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73 | fb_div *= mpll->reference_freq; |
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74 | |||
75 | ref_div = |
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76 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
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1321 | serge | 77 | |
78 | if (ref_div == 0) |
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79 | return 0; |
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80 | |||
1117 | serge | 81 | mclk = fb_div / ref_div; |
82 | |||
83 | post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; |
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84 | if (post_div == 2) |
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85 | mclk >>= 1; |
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86 | else if (post_div == 3) |
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87 | mclk >>= 2; |
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88 | else if (post_div == 4) |
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1403 | serge | 89 | mclk >>= 3; |
1117 | serge | 90 | |
91 | return mclk; |
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92 | } |
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93 | |||
1963 | serge | 94 | #ifdef CONFIG_OF |
95 | /* |
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96 | * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device |
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97 | * tree. Hopefully, ATI OF driver is kind enough to fill these |
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98 | */ |
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99 | static bool __devinit radeon_read_clocks_OF(struct drm_device *dev) |
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100 | { |
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101 | struct radeon_device *rdev = dev->dev_private; |
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102 | struct device_node *dp = rdev->pdev->dev.of_node; |
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103 | const u32 *val; |
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104 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
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105 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
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106 | struct radeon_pll *spll = &rdev->clock.spll; |
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107 | struct radeon_pll *mpll = &rdev->clock.mpll; |
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108 | |||
109 | if (dp == NULL) |
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110 | return false; |
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111 | val = of_get_property(dp, "ATY,RefCLK", NULL); |
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112 | if (!val || !*val) { |
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113 | printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); |
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114 | return false; |
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115 | } |
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116 | p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; |
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117 | p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
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118 | if (p1pll->reference_div < 2) |
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119 | p1pll->reference_div = 12; |
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120 | p2pll->reference_div = p1pll->reference_div; |
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121 | |||
122 | /* These aren't in the device-tree */ |
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123 | if (rdev->family >= CHIP_R420) { |
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124 | p1pll->pll_in_min = 100; |
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125 | p1pll->pll_in_max = 1350; |
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126 | p1pll->pll_out_min = 20000; |
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127 | p1pll->pll_out_max = 50000; |
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128 | p2pll->pll_in_min = 100; |
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129 | p2pll->pll_in_max = 1350; |
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130 | p2pll->pll_out_min = 20000; |
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131 | p2pll->pll_out_max = 50000; |
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132 | } else { |
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133 | p1pll->pll_in_min = 40; |
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134 | p1pll->pll_in_max = 500; |
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135 | p1pll->pll_out_min = 12500; |
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136 | p1pll->pll_out_max = 35000; |
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137 | p2pll->pll_in_min = 40; |
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138 | p2pll->pll_in_max = 500; |
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139 | p2pll->pll_out_min = 12500; |
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140 | p2pll->pll_out_max = 35000; |
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141 | } |
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142 | /* not sure what the max should be in all cases */ |
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143 | rdev->clock.max_pixel_clock = 35000; |
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144 | |||
145 | spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; |
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146 | spll->reference_div = mpll->reference_div = |
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147 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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148 | RADEON_M_SPLL_REF_DIV_MASK; |
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149 | |||
150 | val = of_get_property(dp, "ATY,SCLK", NULL); |
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151 | if (val && *val) |
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152 | rdev->clock.default_sclk = (*val) / 10; |
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153 | else |
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154 | rdev->clock.default_sclk = |
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155 | radeon_legacy_get_engine_clock(rdev); |
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156 | |||
157 | val = of_get_property(dp, "ATY,MCLK", NULL); |
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158 | if (val && *val) |
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159 | rdev->clock.default_mclk = (*val) / 10; |
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160 | else |
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161 | rdev->clock.default_mclk = |
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162 | radeon_legacy_get_memory_clock(rdev); |
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163 | |||
164 | DRM_INFO("Using device-tree clock info\n"); |
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165 | |||
166 | return true; |
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167 | } |
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168 | #else |
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169 | static bool radeon_read_clocks_OF(struct drm_device *dev) |
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170 | { |
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171 | return false; |
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172 | } |
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173 | #endif /* CONFIG_OF */ |
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174 | |||
1117 | serge | 175 | void radeon_get_clock_info(struct drm_device *dev) |
176 | { |
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177 | struct radeon_device *rdev = dev->dev_private; |
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178 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
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179 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
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1430 | serge | 180 | struct radeon_pll *dcpll = &rdev->clock.dcpll; |
1117 | serge | 181 | struct radeon_pll *spll = &rdev->clock.spll; |
182 | struct radeon_pll *mpll = &rdev->clock.mpll; |
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183 | int ret; |
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184 | |||
185 | if (rdev->is_atom_bios) |
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186 | ret = radeon_atom_get_clock_info(dev); |
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1128 | serge | 187 | else |
188 | ret = radeon_combios_get_clock_info(dev); |
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1963 | serge | 189 | if (!ret) |
190 | ret = radeon_read_clocks_OF(dev); |
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1117 | serge | 191 | |
192 | if (ret) { |
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1321 | serge | 193 | if (p1pll->reference_div < 2) { |
194 | if (!ASIC_IS_AVIVO(rdev)) { |
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195 | u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); |
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196 | if (ASIC_IS_R300(rdev)) |
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197 | p1pll->reference_div = |
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198 | (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; |
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199 | else |
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200 | p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; |
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1117 | serge | 201 | if (p1pll->reference_div < 2) |
202 | p1pll->reference_div = 12; |
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1321 | serge | 203 | } else |
204 | p1pll->reference_div = 12; |
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205 | } |
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1117 | serge | 206 | if (p2pll->reference_div < 2) |
207 | p2pll->reference_div = 12; |
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1179 | serge | 208 | if (rdev->family < CHIP_RS600) { |
1117 | serge | 209 | if (spll->reference_div < 2) |
210 | spll->reference_div = |
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211 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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212 | RADEON_M_SPLL_REF_DIV_MASK; |
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1179 | serge | 213 | } |
1117 | serge | 214 | if (mpll->reference_div < 2) |
215 | mpll->reference_div = spll->reference_div; |
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216 | } else { |
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217 | if (ASIC_IS_AVIVO(rdev)) { |
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218 | /* TODO FALLBACK */ |
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219 | } else { |
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220 | DRM_INFO("Using generic clock info\n"); |
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221 | |||
222 | if (rdev->flags & RADEON_IS_IGP) { |
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223 | p1pll->reference_freq = 1432; |
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224 | p2pll->reference_freq = 1432; |
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225 | spll->reference_freq = 1432; |
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226 | mpll->reference_freq = 1432; |
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227 | } else { |
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228 | p1pll->reference_freq = 2700; |
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229 | p2pll->reference_freq = 2700; |
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230 | spll->reference_freq = 2700; |
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231 | mpll->reference_freq = 2700; |
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232 | } |
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233 | p1pll->reference_div = |
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234 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
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235 | if (p1pll->reference_div < 2) |
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236 | p1pll->reference_div = 12; |
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237 | p2pll->reference_div = p1pll->reference_div; |
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238 | |||
239 | if (rdev->family >= CHIP_R420) { |
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240 | p1pll->pll_in_min = 100; |
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241 | p1pll->pll_in_max = 1350; |
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242 | p1pll->pll_out_min = 20000; |
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243 | p1pll->pll_out_max = 50000; |
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244 | p2pll->pll_in_min = 100; |
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245 | p2pll->pll_in_max = 1350; |
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246 | p2pll->pll_out_min = 20000; |
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247 | p2pll->pll_out_max = 50000; |
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248 | } else { |
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249 | p1pll->pll_in_min = 40; |
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250 | p1pll->pll_in_max = 500; |
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251 | p1pll->pll_out_min = 12500; |
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252 | p1pll->pll_out_max = 35000; |
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253 | p2pll->pll_in_min = 40; |
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254 | p2pll->pll_in_max = 500; |
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255 | p2pll->pll_out_min = 12500; |
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256 | p2pll->pll_out_max = 35000; |
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257 | } |
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258 | |||
259 | spll->reference_div = |
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260 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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261 | RADEON_M_SPLL_REF_DIV_MASK; |
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262 | mpll->reference_div = spll->reference_div; |
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263 | rdev->clock.default_sclk = |
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264 | radeon_legacy_get_engine_clock(rdev); |
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265 | rdev->clock.default_mclk = |
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266 | radeon_legacy_get_memory_clock(rdev); |
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267 | } |
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268 | } |
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269 | |||
270 | /* pixel clocks */ |
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271 | if (ASIC_IS_AVIVO(rdev)) { |
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272 | p1pll->min_post_div = 2; |
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273 | p1pll->max_post_div = 0x7f; |
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274 | p1pll->min_frac_feedback_div = 0; |
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275 | p1pll->max_frac_feedback_div = 9; |
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276 | p2pll->min_post_div = 2; |
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277 | p2pll->max_post_div = 0x7f; |
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278 | p2pll->min_frac_feedback_div = 0; |
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279 | p2pll->max_frac_feedback_div = 9; |
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280 | } else { |
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281 | p1pll->min_post_div = 1; |
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282 | p1pll->max_post_div = 16; |
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283 | p1pll->min_frac_feedback_div = 0; |
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284 | p1pll->max_frac_feedback_div = 0; |
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285 | p2pll->min_post_div = 1; |
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286 | p2pll->max_post_div = 12; |
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287 | p2pll->min_frac_feedback_div = 0; |
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288 | p2pll->max_frac_feedback_div = 0; |
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289 | } |
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290 | |||
1430 | serge | 291 | /* dcpll is DCE4 only */ |
292 | dcpll->min_post_div = 2; |
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293 | dcpll->max_post_div = 0x7f; |
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294 | dcpll->min_frac_feedback_div = 0; |
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295 | dcpll->max_frac_feedback_div = 9; |
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296 | dcpll->min_ref_div = 2; |
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297 | dcpll->max_ref_div = 0x3ff; |
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298 | dcpll->min_feedback_div = 4; |
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299 | dcpll->max_feedback_div = 0xfff; |
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300 | dcpll->best_vco = 0; |
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301 | |||
1117 | serge | 302 | p1pll->min_ref_div = 2; |
303 | p1pll->max_ref_div = 0x3ff; |
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304 | p1pll->min_feedback_div = 4; |
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305 | p1pll->max_feedback_div = 0x7ff; |
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306 | p1pll->best_vco = 0; |
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307 | |||
308 | p2pll->min_ref_div = 2; |
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309 | p2pll->max_ref_div = 0x3ff; |
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310 | p2pll->min_feedback_div = 4; |
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311 | p2pll->max_feedback_div = 0x7ff; |
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312 | p2pll->best_vco = 0; |
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313 | |||
314 | /* system clock */ |
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315 | spll->min_post_div = 1; |
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316 | spll->max_post_div = 1; |
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317 | spll->min_ref_div = 2; |
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318 | spll->max_ref_div = 0xff; |
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319 | spll->min_feedback_div = 4; |
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320 | spll->max_feedback_div = 0xff; |
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321 | spll->best_vco = 0; |
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322 | |||
323 | /* memory clock */ |
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324 | mpll->min_post_div = 1; |
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325 | mpll->max_post_div = 1; |
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326 | mpll->min_ref_div = 2; |
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327 | mpll->max_ref_div = 0xff; |
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328 | mpll->min_feedback_div = 4; |
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329 | mpll->max_feedback_div = 0xff; |
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330 | mpll->best_vco = 0; |
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331 | |||
1963 | serge | 332 | if (!rdev->clock.default_sclk) |
333 | rdev->clock.default_sclk = radeon_get_engine_clock(rdev); |
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334 | if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock) |
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335 | rdev->clock.default_mclk = radeon_get_memory_clock(rdev); |
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336 | |||
337 | rdev->pm.current_sclk = rdev->clock.default_sclk; |
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338 | rdev->pm.current_mclk = rdev->clock.default_mclk; |
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339 | |||
1117 | serge | 340 | } |
341 | |||
342 | /* 10 khz */ |
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343 | static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, |
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344 | uint32_t req_clock, |
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345 | int *fb_div, int *post_div) |
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346 | { |
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347 | struct radeon_pll *spll = &rdev->clock.spll; |
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348 | int ref_div = spll->reference_div; |
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349 | |||
350 | if (!ref_div) |
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351 | ref_div = |
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352 | RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
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353 | RADEON_M_SPLL_REF_DIV_MASK; |
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354 | |||
355 | if (req_clock < 15000) { |
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356 | *post_div = 8; |
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357 | req_clock *= 8; |
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358 | } else if (req_clock < 30000) { |
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359 | *post_div = 4; |
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360 | req_clock *= 4; |
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361 | } else if (req_clock < 60000) { |
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362 | *post_div = 2; |
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363 | req_clock *= 2; |
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364 | } else |
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365 | *post_div = 1; |
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366 | |||
367 | req_clock *= ref_div; |
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368 | req_clock += spll->reference_freq; |
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369 | req_clock /= (2 * spll->reference_freq); |
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370 | |||
371 | *fb_div = req_clock & 0xff; |
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372 | |||
373 | req_clock = (req_clock & 0xffff) << 1; |
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374 | req_clock *= spll->reference_freq; |
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375 | req_clock /= ref_div; |
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376 | req_clock /= *post_div; |
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377 | |||
378 | return req_clock; |
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379 | } |
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380 | |||
381 | /* 10 khz */ |
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382 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, |
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383 | uint32_t eng_clock) |
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384 | { |
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385 | uint32_t tmp; |
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386 | int fb_div, post_div; |
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387 | |||
388 | /* XXX: wait for idle */ |
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389 | |||
390 | eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); |
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391 | |||
392 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
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393 | tmp &= ~RADEON_DONT_USE_XTALIN; |
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394 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
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395 | |||
396 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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397 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
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398 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
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399 | |||
400 | udelay(10); |
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401 | |||
402 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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403 | tmp |= RADEON_SPLL_SLEEP; |
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404 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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405 | |||
406 | udelay(2); |
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407 | |||
408 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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409 | tmp |= RADEON_SPLL_RESET; |
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410 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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411 | |||
412 | udelay(200); |
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413 | |||
414 | tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
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415 | tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); |
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416 | tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; |
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417 | WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); |
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418 | |||
419 | /* XXX: verify on different asics */ |
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420 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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421 | tmp &= ~RADEON_SPLL_PVG_MASK; |
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422 | if ((eng_clock * post_div) >= 90000) |
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423 | tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); |
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424 | else |
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425 | tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); |
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426 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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427 | |||
428 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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429 | tmp &= ~RADEON_SPLL_SLEEP; |
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430 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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431 | |||
432 | udelay(2); |
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433 | |||
434 | tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
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435 | tmp &= ~RADEON_SPLL_RESET; |
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436 | WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
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437 | |||
438 | udelay(200); |
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439 | |||
440 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
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441 | tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
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442 | switch (post_div) { |
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443 | case 1: |
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444 | default: |
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445 | tmp |= 1; |
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446 | break; |
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447 | case 2: |
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448 | tmp |= 2; |
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449 | break; |
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450 | case 4: |
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451 | tmp |= 3; |
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452 | break; |
||
453 | case 8: |
||
454 | tmp |= 4; |
||
455 | break; |
||
456 | } |
||
457 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
458 | |||
459 | udelay(20); |
||
460 | |||
461 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
||
462 | tmp |= RADEON_DONT_USE_XTALIN; |
||
463 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
||
464 | |||
465 | udelay(10); |
||
466 | } |
||
467 | |||
468 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) |
||
469 | { |
||
470 | uint32_t tmp; |
||
471 | |||
472 | if (enable) { |
||
473 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
474 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
475 | if ((RREG32(RADEON_CONFIG_CNTL) & |
||
476 | RADEON_CFG_ATI_REV_ID_MASK) > |
||
477 | RADEON_CFG_ATI_REV_A13) { |
||
478 | tmp &= |
||
479 | ~(RADEON_SCLK_FORCE_CP | |
||
480 | RADEON_SCLK_FORCE_RB); |
||
481 | } |
||
482 | tmp &= |
||
483 | ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | |
||
484 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | |
||
485 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | |
||
486 | RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | |
||
487 | RADEON_SCLK_FORCE_TDM); |
||
488 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
489 | } else if (ASIC_IS_R300(rdev)) { |
||
490 | if ((rdev->family == CHIP_RS400) || |
||
491 | (rdev->family == CHIP_RS480)) { |
||
492 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
493 | tmp &= |
||
494 | ~(RADEON_SCLK_FORCE_DISP2 | |
||
495 | RADEON_SCLK_FORCE_CP | |
||
496 | RADEON_SCLK_FORCE_HDP | |
||
497 | RADEON_SCLK_FORCE_DISP1 | |
||
498 | RADEON_SCLK_FORCE_TOP | |
||
499 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
||
500 | | RADEON_SCLK_FORCE_IDCT | |
||
501 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
||
502 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
||
503 | | R300_SCLK_FORCE_US | |
||
504 | RADEON_SCLK_FORCE_TV_SCLK | |
||
505 | R300_SCLK_FORCE_SU | |
||
506 | RADEON_SCLK_FORCE_OV0); |
||
507 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
||
508 | tmp |= |
||
509 | RADEON_SCLK_FORCE_TOP | |
||
510 | RADEON_SCLK_FORCE_VIP; |
||
511 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
512 | |||
513 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
514 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
||
515 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
||
516 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
517 | |||
518 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
519 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
||
520 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
521 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
522 | |||
523 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
524 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
||
525 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
526 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
527 | R300_DVOCLK_ALWAYS_ONb | |
||
528 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
529 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
530 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
531 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
532 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
533 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
534 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
535 | R300_P2G2CLK_ALWAYS_ONb | |
||
1221 | serge | 536 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
1117 | serge | 537 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
538 | } else if (rdev->family >= CHIP_RV350) { |
||
539 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
540 | tmp &= ~(R300_SCLK_FORCE_TCL | |
||
541 | R300_SCLK_FORCE_GA | |
||
542 | R300_SCLK_FORCE_CBA); |
||
543 | tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | |
||
544 | R300_SCLK_GA_MAX_DYN_STOP_LAT | |
||
545 | R300_SCLK_CBA_MAX_DYN_STOP_LAT); |
||
546 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
547 | |||
548 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
549 | tmp &= |
||
550 | ~(RADEON_SCLK_FORCE_DISP2 | |
||
551 | RADEON_SCLK_FORCE_CP | |
||
552 | RADEON_SCLK_FORCE_HDP | |
||
553 | RADEON_SCLK_FORCE_DISP1 | |
||
554 | RADEON_SCLK_FORCE_TOP | |
||
555 | RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
||
556 | | RADEON_SCLK_FORCE_IDCT | |
||
557 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
||
558 | | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
||
559 | | R300_SCLK_FORCE_US | |
||
560 | RADEON_SCLK_FORCE_TV_SCLK | |
||
561 | R300_SCLK_FORCE_SU | |
||
562 | RADEON_SCLK_FORCE_OV0); |
||
563 | tmp |= RADEON_DYN_STOP_LAT_MASK; |
||
564 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
565 | |||
566 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
567 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
||
568 | tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
||
569 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
570 | |||
571 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
572 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
||
573 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
574 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
575 | |||
576 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
577 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
||
578 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
579 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
580 | R300_DVOCLK_ALWAYS_ONb | |
||
581 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
582 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
583 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
584 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
585 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
586 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
587 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
588 | R300_P2G2CLK_ALWAYS_ONb | |
||
1221 | serge | 589 | R300_P2G2CLK_DAC_ALWAYS_ONb); |
1117 | serge | 590 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
591 | |||
592 | tmp = RREG32_PLL(RADEON_MCLK_MISC); |
||
593 | tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
||
594 | RADEON_IO_MCLK_DYN_ENABLE); |
||
595 | WREG32_PLL(RADEON_MCLK_MISC, tmp); |
||
596 | |||
597 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
598 | tmp |= (RADEON_FORCEON_MCLKA | |
||
599 | RADEON_FORCEON_MCLKB); |
||
600 | |||
601 | tmp &= ~(RADEON_FORCEON_YCLKA | |
||
602 | RADEON_FORCEON_YCLKB | |
||
603 | RADEON_FORCEON_MC); |
||
604 | |||
605 | /* Some releases of vbios have set DISABLE_MC_MCLKA |
||
606 | and DISABLE_MC_MCLKB bits in the vbios table. Setting these |
||
607 | bits will cause H/W hang when reading video memory with dynamic clocking |
||
608 | enabled. */ |
||
609 | if ((tmp & R300_DISABLE_MC_MCLKA) && |
||
610 | (tmp & R300_DISABLE_MC_MCLKB)) { |
||
611 | /* If both bits are set, then check the active channels */ |
||
612 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
613 | if (rdev->mc.vram_width == 64) { |
||
614 | if (RREG32(RADEON_MEM_CNTL) & |
||
615 | R300_MEM_USE_CD_CH_ONLY) |
||
616 | tmp &= |
||
617 | ~R300_DISABLE_MC_MCLKB; |
||
618 | else |
||
619 | tmp &= |
||
620 | ~R300_DISABLE_MC_MCLKA; |
||
621 | } else { |
||
622 | tmp &= ~(R300_DISABLE_MC_MCLKA | |
||
623 | R300_DISABLE_MC_MCLKB); |
||
624 | } |
||
625 | } |
||
626 | |||
627 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
628 | } else { |
||
629 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
630 | tmp &= ~(R300_SCLK_FORCE_VAP); |
||
631 | tmp |= RADEON_SCLK_FORCE_CP; |
||
632 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
633 | udelay(15000); |
||
634 | |||
635 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
636 | tmp &= ~(R300_SCLK_FORCE_TCL | |
||
637 | R300_SCLK_FORCE_GA | |
||
638 | R300_SCLK_FORCE_CBA); |
||
639 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
640 | } |
||
641 | } else { |
||
642 | tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
||
643 | |||
644 | tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | |
||
645 | RADEON_DISP_DYN_STOP_LAT_MASK | |
||
646 | RADEON_DYN_STOP_MODE_MASK); |
||
647 | |||
648 | tmp |= (RADEON_ENGIN_DYNCLK_MODE | |
||
649 | (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); |
||
650 | WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); |
||
651 | udelay(15000); |
||
652 | |||
653 | tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
||
654 | tmp |= RADEON_SCLK_DYN_START_CNTL; |
||
655 | WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
||
656 | udelay(15000); |
||
657 | |||
658 | /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 |
||
659 | to lockup randomly, leave them as set by BIOS. |
||
660 | */ |
||
661 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
662 | /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ |
||
663 | tmp &= ~RADEON_SCLK_FORCEON_MASK; |
||
664 | |||
665 | /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */ |
||
666 | if (((rdev->family == CHIP_RV250) && |
||
667 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
668 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
669 | RADEON_CFG_ATI_REV_A13)) |
||
670 | || ((rdev->family == CHIP_RV100) |
||
671 | && |
||
672 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
673 | RADEON_CFG_ATI_REV_ID_MASK) <= |
||
674 | RADEON_CFG_ATI_REV_A13))) { |
||
675 | tmp |= RADEON_SCLK_FORCE_CP; |
||
676 | tmp |= RADEON_SCLK_FORCE_VIP; |
||
677 | } |
||
678 | |||
679 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
680 | |||
681 | if ((rdev->family == CHIP_RV200) || |
||
682 | (rdev->family == CHIP_RV250) || |
||
683 | (rdev->family == CHIP_RV280)) { |
||
684 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
685 | tmp &= ~RADEON_SCLK_MORE_FORCEON; |
||
686 | |||
687 | /* RV200::A11 A12 RV250::A11 A12 */ |
||
688 | if (((rdev->family == CHIP_RV200) || |
||
689 | (rdev->family == CHIP_RV250)) && |
||
690 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
691 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
692 | RADEON_CFG_ATI_REV_A13)) { |
||
693 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
694 | } |
||
695 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
696 | udelay(15000); |
||
697 | } |
||
698 | |||
699 | /* RV200::A11 A12, RV250::A11 A12 */ |
||
700 | if (((rdev->family == CHIP_RV200) || |
||
701 | (rdev->family == CHIP_RV250)) && |
||
702 | ((RREG32(RADEON_CONFIG_CNTL) & |
||
703 | RADEON_CFG_ATI_REV_ID_MASK) < |
||
704 | RADEON_CFG_ATI_REV_A13)) { |
||
705 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
||
706 | tmp |= RADEON_TCL_BYPASS_DISABLE; |
||
707 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
||
708 | } |
||
709 | udelay(15000); |
||
710 | |||
711 | /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ |
||
712 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
713 | tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
||
714 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
715 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
716 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
717 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
||
718 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
719 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
||
720 | |||
721 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
722 | udelay(15000); |
||
723 | |||
724 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
725 | tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
||
726 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
727 | |||
728 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
729 | udelay(15000); |
||
730 | } |
||
731 | } else { |
||
732 | /* Turn everything OFF (ForceON to everything) */ |
||
733 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
734 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
735 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | |
||
736 | RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
||
737 | | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | |
||
738 | RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | |
||
739 | RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | |
||
740 | RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | |
||
741 | RADEON_SCLK_FORCE_RB); |
||
742 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
743 | } else if ((rdev->family == CHIP_RS400) || |
||
744 | (rdev->family == CHIP_RS480)) { |
||
745 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
746 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
||
747 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
||
748 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
||
749 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
||
750 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
||
751 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
||
752 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
||
753 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
||
754 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
755 | |||
756 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
757 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
758 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
759 | |||
760 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
761 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
762 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
||
763 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
||
764 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
765 | |||
766 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
767 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
768 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
769 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
770 | R300_DVOCLK_ALWAYS_ONb | |
||
771 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
772 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
773 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
774 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
775 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
776 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
777 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
778 | R300_P2G2CLK_ALWAYS_ONb | |
||
1221 | serge | 779 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
1117 | serge | 780 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
781 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
782 | } else if (rdev->family >= CHIP_RV350) { |
||
783 | /* for RV350/M10, no delays are required. */ |
||
784 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
785 | tmp |= (R300_SCLK_FORCE_TCL | |
||
786 | R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); |
||
787 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
788 | |||
789 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
790 | tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
||
791 | RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
||
792 | | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
||
793 | R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
||
794 | RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
||
795 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
||
796 | R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
||
797 | R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
||
798 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
799 | |||
800 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
801 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
802 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
803 | |||
804 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
805 | tmp |= (RADEON_FORCEON_MCLKA | |
||
806 | RADEON_FORCEON_MCLKB | |
||
807 | RADEON_FORCEON_YCLKA | |
||
808 | RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC); |
||
809 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
810 | |||
811 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
812 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
813 | RADEON_PIXCLK_DAC_ALWAYS_ONb | |
||
814 | R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
||
815 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
816 | |||
817 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
818 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
819 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
820 | RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
||
821 | R300_DVOCLK_ALWAYS_ONb | |
||
822 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
823 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
824 | R300_PIXCLK_DVO_ALWAYS_ONb | |
||
825 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
826 | RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
||
827 | R300_PIXCLK_TRANS_ALWAYS_ONb | |
||
828 | R300_PIXCLK_TVO_ALWAYS_ONb | |
||
829 | R300_P2G2CLK_ALWAYS_ONb | |
||
1221 | serge | 830 | R300_P2G2CLK_DAC_ALWAYS_ONb | |
1117 | serge | 831 | R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
832 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
833 | } else { |
||
834 | tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
||
835 | tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |
||
836 | tmp |= RADEON_SCLK_FORCE_SE; |
||
837 | |||
838 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
||
839 | tmp |= (RADEON_SCLK_FORCE_RB | |
||
840 | RADEON_SCLK_FORCE_TDM | |
||
841 | RADEON_SCLK_FORCE_TAM | |
||
842 | RADEON_SCLK_FORCE_PB | |
||
843 | RADEON_SCLK_FORCE_RE | |
||
844 | RADEON_SCLK_FORCE_VIP | |
||
845 | RADEON_SCLK_FORCE_IDCT | |
||
846 | RADEON_SCLK_FORCE_TOP | |
||
847 | RADEON_SCLK_FORCE_DISP1 | |
||
848 | RADEON_SCLK_FORCE_DISP2 | |
||
849 | RADEON_SCLK_FORCE_HDP); |
||
850 | } else if ((rdev->family == CHIP_R300) || |
||
851 | (rdev->family == CHIP_R350)) { |
||
852 | tmp |= (RADEON_SCLK_FORCE_HDP | |
||
853 | RADEON_SCLK_FORCE_DISP1 | |
||
854 | RADEON_SCLK_FORCE_DISP2 | |
||
855 | RADEON_SCLK_FORCE_TOP | |
||
856 | RADEON_SCLK_FORCE_IDCT | |
||
857 | RADEON_SCLK_FORCE_VIP); |
||
858 | } |
||
859 | WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
||
860 | |||
861 | udelay(16000); |
||
862 | |||
863 | if ((rdev->family == CHIP_R300) || |
||
864 | (rdev->family == CHIP_R350)) { |
||
865 | tmp = RREG32_PLL(R300_SCLK_CNTL2); |
||
866 | tmp |= (R300_SCLK_FORCE_TCL | |
||
867 | R300_SCLK_FORCE_GA | |
||
868 | R300_SCLK_FORCE_CBA); |
||
869 | WREG32_PLL(R300_SCLK_CNTL2, tmp); |
||
870 | udelay(16000); |
||
871 | } |
||
872 | |||
873 | if (rdev->flags & RADEON_IS_IGP) { |
||
874 | tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
||
875 | tmp &= ~(RADEON_FORCEON_MCLKA | |
||
876 | RADEON_FORCEON_YCLKA); |
||
877 | WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
||
878 | udelay(16000); |
||
879 | } |
||
880 | |||
881 | if ((rdev->family == CHIP_RV200) || |
||
882 | (rdev->family == CHIP_RV250) || |
||
883 | (rdev->family == CHIP_RV280)) { |
||
884 | tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
||
885 | tmp |= RADEON_SCLK_MORE_FORCEON; |
||
886 | WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
||
887 | udelay(16000); |
||
888 | } |
||
889 | |||
890 | tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
||
891 | tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
||
892 | RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
||
893 | RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
||
894 | RADEON_PIXCLK_GV_ALWAYS_ONb | |
||
895 | RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
||
896 | RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
||
897 | RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
||
898 | |||
899 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
||
900 | udelay(16000); |
||
901 | |||
902 | tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
||
903 | tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
||
904 | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
||
905 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
||
906 | } |
||
907 | } |
||
908 | } |
||
909 |