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1117 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
2997 Serge 28
#include 
1117 serge 29
#include "radeon_reg.h"
30
#include "radeon.h"
31
#include "atom.h"
32
 
1963 serge 33
//#include 
34
#include 
1117 serge 35
/*
36
 * BIOS.
37
 */
1233 serge 38
 
39
/* If you boot an IGP board with a discrete card as the primary,
40
 * the IGP rom is not accessible via the rom bar as the IGP rom is
41
 * part of the system bios.  On boot, the system bios puts a
42
 * copy of the igp rom at the start of vram if a discrete card is
43
 * present.
44
 */
45
static bool igp_read_bios_from_vram(struct radeon_device *rdev)
46
{
47
	uint8_t __iomem *bios;
48
	resource_size_t vram_base;
49
	resource_size_t size = 256 * 1024; /* ??? */
50
 
1963 serge 51
	if (!(rdev->flags & RADEON_IS_IGP))
52
		if (!radeon_card_posted(rdev))
53
			return false;
54
 
1233 serge 55
	rdev->bios = NULL;
1963 serge 56
	vram_base = pci_resource_start(rdev->pdev, 0);
1233 serge 57
	bios = ioremap(vram_base, size);
58
	if (!bios) {
59
		return false;
60
	}
61
 
62
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
63
		iounmap(bios);
64
		return false;
65
	}
66
	rdev->bios = kmalloc(size, GFP_KERNEL);
67
	if (rdev->bios == NULL) {
68
		iounmap(bios);
69
		return false;
70
	}
71
	memcpy(rdev->bios, bios, size);
72
	iounmap(bios);
73
	return true;
74
}
75
 
1117 serge 76
static bool radeon_read_bios(struct radeon_device *rdev)
77
{
1179 serge 78
	uint8_t __iomem *bios;
1117 serge 79
    size_t    size;
80
 
81
	rdev->bios = NULL;
1221 serge 82
	/* XXX: some cards may return 0 for rom size? ddx has a workaround */
83
	bios = pci_map_rom(rdev->pdev, &size);
1117 serge 84
	if (!bios) {
85
		return false;
86
	}
87
 
88
	if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
89
//       pci_unmap_rom(rdev->pdev, bios);
90
		return false;
91
	}
1179 serge 92
	rdev->bios = kmalloc(size, GFP_KERNEL);
1117 serge 93
	if (rdev->bios == NULL) {
1268 serge 94
//        pci_unmap_rom(rdev->pdev, bios);
1117 serge 95
		return false;
96
	}
97
	memcpy(rdev->bios, bios, size);
1268 serge 98
//    pci_unmap_rom(rdev->pdev, bios);
1117 serge 99
	return true;
100
}
101
 
2997 Serge 102
#ifdef CONFIG_ACPI
1430 serge 103
/* ATRM is used to get the BIOS on the discrete cards in
104
 * dual-gpu systems.
105
 */
2997 Serge 106
/* retrieve the ROM in 4k blocks */
107
#define ATRM_BIOS_PAGE 4096
108
/**
109
 * radeon_atrm_call - fetch a chunk of the vbios
110
 *
111
 * @atrm_handle: acpi ATRM handle
112
 * @bios: vbios image pointer
113
 * @offset: offset of vbios image data to fetch
114
 * @len: length of vbios image data to fetch
115
 *
116
 * Executes ATRM to fetch a chunk of the discrete
117
 * vbios image on PX systems (all asics).
118
 * Returns the length of the buffer fetched.
119
 */
120
static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
121
			    int offset, int len)
122
{
123
	acpi_status status;
124
	union acpi_object atrm_arg_elements[2], *obj;
125
	struct acpi_object_list atrm_arg;
126
	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
127
 
128
	atrm_arg.count = 2;
129
	atrm_arg.pointer = &atrm_arg_elements[0];
130
 
131
	atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
132
	atrm_arg_elements[0].integer.value = offset;
133
 
134
	atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
135
	atrm_arg_elements[1].integer.value = len;
136
 
137
	status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
138
	if (ACPI_FAILURE(status)) {
139
		printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
140
		return -ENODEV;
141
	}
142
 
143
	obj = (union acpi_object *)buffer.pointer;
144
	memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
145
	len = obj->buffer.length;
146
	kfree(buffer.pointer);
147
	return len;
148
}
149
 
1430 serge 150
static bool radeon_atrm_get_bios(struct radeon_device *rdev)
151
{
152
	int ret;
2004 serge 153
	int size = 256 * 1024;
1430 serge 154
	int i;
2997 Serge 155
	struct pci_dev *pdev = NULL;
156
	acpi_handle dhandle, atrm_handle;
157
	acpi_status status;
158
	bool found = false;
1430 serge 159
 
2997 Serge 160
	/* ATRM is for the discrete card only */
161
	if (rdev->flags & RADEON_IS_IGP)
1430 serge 162
		return false;
163
 
2997 Serge 164
	while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
165
		dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
166
		if (!dhandle)
167
			continue;
168
 
169
		status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
170
		if (!ACPI_FAILURE(status)) {
171
			found = true;
172
			break;
173
		}
174
	}
175
 
176
	if (!found)
177
		return false;
178
 
1430 serge 179
	rdev->bios = kmalloc(size, GFP_KERNEL);
180
	if (!rdev->bios) {
181
		DRM_ERROR("Unable to allocate bios\n");
182
		return false;
183
	}
184
 
185
	for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
2997 Serge 186
		ret = radeon_atrm_call(atrm_handle,
187
				       rdev->bios,
1430 serge 188
						 (i * ATRM_BIOS_PAGE),
189
						 ATRM_BIOS_PAGE);
2997 Serge 190
		if (ret < ATRM_BIOS_PAGE)
1430 serge 191
			break;
192
	}
193
 
194
	if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
195
		kfree(rdev->bios);
196
		return false;
197
	}
198
	return true;
199
}
2997 Serge 200
#else
3120 serge 201
static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
2997 Serge 202
{
203
    return false;
204
}
205
#endif
1963 serge 206
 
207
static bool ni_read_disabled_bios(struct radeon_device *rdev)
208
{
209
	u32 bus_cntl;
210
	u32 d1vga_control;
211
	u32 d2vga_control;
212
	u32 vga_render_control;
213
	u32 rom_cntl;
214
	bool r;
215
 
216
	bus_cntl = RREG32(R600_BUS_CNTL);
217
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
218
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
219
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
220
	rom_cntl = RREG32(R600_ROM_CNTL);
221
 
222
	/* enable the rom */
223
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
224
	/* Disable VGA mode */
225
	WREG32(AVIVO_D1VGA_CONTROL,
226
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
227
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
228
	WREG32(AVIVO_D2VGA_CONTROL,
229
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
230
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
231
	WREG32(AVIVO_VGA_RENDER_CONTROL,
232
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
233
	WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
234
 
235
	r = radeon_read_bios(rdev);
236
 
237
	/* restore regs */
238
	WREG32(R600_BUS_CNTL, bus_cntl);
239
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
240
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
241
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
242
	WREG32(R600_ROM_CNTL, rom_cntl);
243
	return r;
244
}
245
 
1117 serge 246
static bool r700_read_disabled_bios(struct radeon_device *rdev)
247
{
248
	uint32_t viph_control;
249
	uint32_t bus_cntl;
250
	uint32_t d1vga_control;
251
	uint32_t d2vga_control;
252
	uint32_t vga_render_control;
253
	uint32_t rom_cntl;
254
	uint32_t cg_spll_func_cntl = 0;
255
	uint32_t cg_spll_status;
256
	bool r;
257
 
258
	viph_control = RREG32(RADEON_VIPH_CONTROL);
1963 serge 259
	bus_cntl = RREG32(R600_BUS_CNTL);
1117 serge 260
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
261
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
262
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
263
	rom_cntl = RREG32(R600_ROM_CNTL);
264
 
265
	/* disable VIP */
266
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
267
	/* enable the rom */
1963 serge 268
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1117 serge 269
	/* Disable VGA mode */
270
	WREG32(AVIVO_D1VGA_CONTROL,
271
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
272
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
273
	WREG32(AVIVO_D2VGA_CONTROL,
274
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
275
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
276
	WREG32(AVIVO_VGA_RENDER_CONTROL,
277
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
278
 
279
	if (rdev->family == CHIP_RV730) {
280
		cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
281
 
282
		/* enable bypass mode */
283
		WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
284
						R600_SPLL_BYPASS_EN));
285
 
286
		/* wait for SPLL_CHG_STATUS to change to 1 */
287
		cg_spll_status = 0;
288
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
289
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
290
 
291
		WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
292
	} else
293
		WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
294
 
295
	r = radeon_read_bios(rdev);
296
 
297
	/* restore regs */
298
	if (rdev->family == CHIP_RV730) {
299
		WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
300
 
301
		/* wait for SPLL_CHG_STATUS to change to 1 */
302
		cg_spll_status = 0;
303
		while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
304
			cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
305
	}
306
	WREG32(RADEON_VIPH_CONTROL, viph_control);
1963 serge 307
	WREG32(R600_BUS_CNTL, bus_cntl);
1117 serge 308
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
309
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
310
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
311
	WREG32(R600_ROM_CNTL, rom_cntl);
312
	return r;
313
}
314
 
315
static bool r600_read_disabled_bios(struct radeon_device *rdev)
316
{
317
	uint32_t viph_control;
318
	uint32_t bus_cntl;
319
	uint32_t d1vga_control;
320
	uint32_t d2vga_control;
321
	uint32_t vga_render_control;
322
	uint32_t rom_cntl;
323
	uint32_t general_pwrmgt;
324
	uint32_t low_vid_lower_gpio_cntl;
325
	uint32_t medium_vid_lower_gpio_cntl;
326
	uint32_t high_vid_lower_gpio_cntl;
327
	uint32_t ctxsw_vid_lower_gpio_cntl;
328
	uint32_t lower_gpio_enable;
329
	bool r;
330
 
331
	viph_control = RREG32(RADEON_VIPH_CONTROL);
1963 serge 332
	bus_cntl = RREG32(R600_BUS_CNTL);
1117 serge 333
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
334
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
335
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
336
	rom_cntl = RREG32(R600_ROM_CNTL);
337
	general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
338
	low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
339
	medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
340
	high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
341
	ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
342
	lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
343
 
344
	/* disable VIP */
345
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
346
	/* enable the rom */
1963 serge 347
	WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
1117 serge 348
	/* Disable VGA mode */
349
	WREG32(AVIVO_D1VGA_CONTROL,
350
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
351
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
352
	WREG32(AVIVO_D2VGA_CONTROL,
353
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
354
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
355
	WREG32(AVIVO_VGA_RENDER_CONTROL,
356
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
357
 
358
	WREG32(R600_ROM_CNTL,
359
	       ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
360
		(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
361
		R600_SCK_OVERWRITE));
362
 
363
	WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
364
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
365
	       (low_vid_lower_gpio_cntl & ~0x400));
366
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
367
	       (medium_vid_lower_gpio_cntl & ~0x400));
368
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
369
	       (high_vid_lower_gpio_cntl & ~0x400));
370
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
371
	       (ctxsw_vid_lower_gpio_cntl & ~0x400));
372
	WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
373
 
374
	r = radeon_read_bios(rdev);
375
 
376
	/* restore regs */
377
	WREG32(RADEON_VIPH_CONTROL, viph_control);
1963 serge 378
	WREG32(R600_BUS_CNTL, bus_cntl);
1117 serge 379
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
380
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
381
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
382
	WREG32(R600_ROM_CNTL, rom_cntl);
383
	WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
384
	WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
385
	WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
386
	WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
387
	WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
388
	WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
389
	return r;
390
}
391
 
392
static bool avivo_read_disabled_bios(struct radeon_device *rdev)
393
{
394
	uint32_t seprom_cntl1;
395
	uint32_t viph_control;
396
	uint32_t bus_cntl;
397
	uint32_t d1vga_control;
398
	uint32_t d2vga_control;
399
	uint32_t vga_render_control;
400
	uint32_t gpiopad_a;
401
	uint32_t gpiopad_en;
402
	uint32_t gpiopad_mask;
403
	bool r;
404
 
405
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
406
	viph_control = RREG32(RADEON_VIPH_CONTROL);
2005 serge 407
	bus_cntl = RREG32(RV370_BUS_CNTL);
1117 serge 408
	d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
409
	d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
410
	vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
411
	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
412
	gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
413
	gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
414
 
415
	WREG32(RADEON_SEPROM_CNTL1,
416
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
417
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
418
	WREG32(RADEON_GPIOPAD_A, 0);
419
	WREG32(RADEON_GPIOPAD_EN, 0);
420
	WREG32(RADEON_GPIOPAD_MASK, 0);
421
 
422
	/* disable VIP */
423
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
424
 
425
	/* enable the rom */
2005 serge 426
	WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
1117 serge 427
 
428
	/* Disable VGA mode */
429
	WREG32(AVIVO_D1VGA_CONTROL,
430
	       (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
431
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
432
	WREG32(AVIVO_D2VGA_CONTROL,
433
	       (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
434
		AVIVO_DVGA_CONTROL_TIMING_SELECT)));
435
	WREG32(AVIVO_VGA_RENDER_CONTROL,
436
	       (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
437
 
438
	r = radeon_read_bios(rdev);
439
 
440
	/* restore regs */
441
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
442
	WREG32(RADEON_VIPH_CONTROL, viph_control);
2005 serge 443
	WREG32(RV370_BUS_CNTL, bus_cntl);
1117 serge 444
	WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
445
	WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
446
	WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
447
	WREG32(RADEON_GPIOPAD_A, gpiopad_a);
448
	WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
449
	WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
450
	return r;
451
}
452
 
453
static bool legacy_read_disabled_bios(struct radeon_device *rdev)
454
{
455
	uint32_t seprom_cntl1;
456
	uint32_t viph_control;
457
	uint32_t bus_cntl;
458
	uint32_t crtc_gen_cntl;
459
	uint32_t crtc2_gen_cntl;
460
	uint32_t crtc_ext_cntl;
461
	uint32_t fp2_gen_cntl;
462
	bool r;
463
 
464
	seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
465
	viph_control = RREG32(RADEON_VIPH_CONTROL);
2005 serge 466
	if (rdev->flags & RADEON_IS_PCIE)
467
		bus_cntl = RREG32(RV370_BUS_CNTL);
468
	else
1117 serge 469
	bus_cntl = RREG32(RADEON_BUS_CNTL);
470
	crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
471
	crtc2_gen_cntl = 0;
472
	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
473
	fp2_gen_cntl = 0;
474
 
475
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
476
		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
477
	}
478
 
479
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
480
		crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
481
	}
482
 
483
	WREG32(RADEON_SEPROM_CNTL1,
484
	       ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
485
		(0xc << RADEON_SCK_PRESCALE_SHIFT)));
486
 
487
	/* disable VIP */
488
	WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
489
 
490
	/* enable the rom */
2005 serge 491
	if (rdev->flags & RADEON_IS_PCIE)
492
		WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
493
	else
1117 serge 494
	WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
495
 
496
	/* Turn off mem requests and CRTC for both controllers */
497
	WREG32(RADEON_CRTC_GEN_CNTL,
498
	       ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
499
		(RADEON_CRTC_DISP_REQ_EN_B |
500
		 RADEON_CRTC_EXT_DISP_EN)));
501
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
502
		WREG32(RADEON_CRTC2_GEN_CNTL,
503
		       ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
504
			RADEON_CRTC2_DISP_REQ_EN_B));
505
	}
506
	/* Turn off CRTC */
507
	WREG32(RADEON_CRTC_EXT_CNTL,
508
	       ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
509
		(RADEON_CRTC_SYNC_TRISTAT |
510
		 RADEON_CRTC_DISPLAY_DIS)));
511
 
512
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
513
		WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
514
	}
515
 
516
	r = radeon_read_bios(rdev);
517
 
518
	/* restore regs */
519
	WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
520
	WREG32(RADEON_VIPH_CONTROL, viph_control);
2005 serge 521
	if (rdev->flags & RADEON_IS_PCIE)
522
		WREG32(RV370_BUS_CNTL, bus_cntl);
523
	else
1117 serge 524
	WREG32(RADEON_BUS_CNTL, bus_cntl);
525
	WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
526
	if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
527
		WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
528
	}
529
	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
530
	if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
531
		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
532
	}
533
	return r;
534
}
535
 
536
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
537
{
1233 serge 538
	if (rdev->flags & RADEON_IS_IGP)
539
		return igp_read_bios_from_vram(rdev);
1963 serge 540
	else if (rdev->family >= CHIP_BARTS)
541
		return ni_read_disabled_bios(rdev);
1233 serge 542
	else if (rdev->family >= CHIP_RV770)
1117 serge 543
		return r700_read_disabled_bios(rdev);
544
	else if (rdev->family >= CHIP_R600)
545
		return r600_read_disabled_bios(rdev);
546
	else if (rdev->family >= CHIP_RS600)
547
		return avivo_read_disabled_bios(rdev);
548
	else
549
		return legacy_read_disabled_bios(rdev);
550
}
551
 
2997 Serge 552
#ifdef CONFIG_ACPI
553
static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
554
{
555
	bool ret = false;
556
	struct acpi_table_header *hdr;
557
	acpi_size tbl_size;
558
	UEFI_ACPI_VFCT *vfct;
559
	GOP_VBIOS_CONTENT *vbios;
560
	VFCT_IMAGE_HEADER *vhdr;
1430 serge 561
 
2997 Serge 562
	if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
563
		return false;
564
	if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
565
		DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
566
		goto out_unmap;
567
	}
568
 
569
	vfct = (UEFI_ACPI_VFCT *)hdr;
570
	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
571
		DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
572
		goto out_unmap;
573
	}
574
 
575
	vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
576
	vhdr = &vbios->VbiosHeader;
577
	DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
578
			vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
579
			vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
580
 
581
	if (vhdr->PCIBus != rdev->pdev->bus->number ||
582
	    vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
583
	    vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
584
	    vhdr->VendorID != rdev->pdev->vendor ||
585
	    vhdr->DeviceID != rdev->pdev->device) {
586
		DRM_INFO("ACPI VFCT table is not for this card\n");
587
		goto out_unmap;
588
	};
589
 
590
	if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
591
		DRM_ERROR("ACPI VFCT image truncated\n");
592
		goto out_unmap;
593
	}
594
 
595
	rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
596
	ret = !!rdev->bios;
597
 
598
out_unmap:
599
	return ret;
600
}
601
#else
602
static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
603
{
604
	return false;
605
}
606
#endif
607
 
1117 serge 608
bool radeon_get_bios(struct radeon_device *rdev)
609
{
610
	bool r;
611
	uint16_t tmp;
612
 
1430 serge 613
	r = radeon_atrm_get_bios(rdev);
614
	if (r == false)
2997 Serge 615
		r = radeon_acpi_vfct_bios(rdev);
616
	if (r == false)
1233 serge 617
		r = igp_read_bios_from_vram(rdev);
2997 Serge 618
    if (r == false)
619
        r = radeon_read_bios(rdev);
1129 serge 620
	if (r == false) {
621
		r = radeon_read_disabled_bios(rdev);
622
	}
1117 serge 623
	if (r == false || rdev->bios == NULL) {
624
		DRM_ERROR("Unable to locate a BIOS ROM\n");
625
		rdev->bios = NULL;
626
		return false;
627
	}
628
	if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
1430 serge 629
		printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
1117 serge 630
		goto free_bios;
631
	}
632
 
1430 serge 633
	tmp = RBIOS16(0x18);
634
	if (RBIOS8(tmp + 0x14) != 0x0) {
635
		DRM_INFO("Not an x86 BIOS ROM, not using.\n");
636
		goto free_bios;
637
	}
638
 
1117 serge 639
	rdev->bios_header_start = RBIOS16(0x48);
640
	if (!rdev->bios_header_start) {
641
		goto free_bios;
642
	}
643
	tmp = rdev->bios_header_start + 4;
644
	if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
645
	    !memcmp(rdev->bios + tmp, "MOTA", 4)) {
646
		rdev->is_atom_bios = true;
647
	} else {
648
		rdev->is_atom_bios = false;
649
	}
650
 
1179 serge 651
	DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
1117 serge 652
	return true;
653
free_bios:
654
	kfree(rdev->bios);
655
	rdev->bios = NULL;
656
	return false;
657
}