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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1123 | serge | 28 | #include "drmP.h" |
| 1117 | serge | 29 | #include "radeon_reg.h" |
| 30 | #include "radeon.h" |
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| 31 | #include "atom.h" |
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| 32 | |||
| 33 | /* |
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| 34 | * BIOS. |
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| 35 | */ |
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| 1233 | serge | 36 | |
| 37 | /* If you boot an IGP board with a discrete card as the primary, |
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| 38 | * the IGP rom is not accessible via the rom bar as the IGP rom is |
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| 39 | * part of the system bios. On boot, the system bios puts a |
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| 40 | * copy of the igp rom at the start of vram if a discrete card is |
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| 41 | * present. |
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| 42 | */ |
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| 43 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) |
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| 44 | { |
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| 45 | uint8_t __iomem *bios; |
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| 46 | resource_size_t vram_base; |
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| 47 | resource_size_t size = 256 * 1024; /* ??? */ |
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| 48 | |||
| 49 | rdev->bios = NULL; |
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| 50 | vram_base = drm_get_resource_start(rdev->ddev, 0); |
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| 51 | bios = ioremap(vram_base, size); |
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| 52 | if (!bios) { |
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| 53 | return false; |
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| 54 | } |
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| 55 | |||
| 56 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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| 57 | iounmap(bios); |
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| 58 | return false; |
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| 59 | } |
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| 60 | rdev->bios = kmalloc(size, GFP_KERNEL); |
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| 61 | if (rdev->bios == NULL) { |
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| 62 | iounmap(bios); |
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| 63 | return false; |
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| 64 | } |
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| 65 | memcpy(rdev->bios, bios, size); |
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| 66 | iounmap(bios); |
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| 67 | return true; |
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| 68 | } |
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| 69 | |||
| 1117 | serge | 70 | static bool radeon_read_bios(struct radeon_device *rdev) |
| 71 | { |
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| 1179 | serge | 72 | uint8_t __iomem *bios; |
| 1117 | serge | 73 | size_t size; |
| 74 | |||
| 75 | rdev->bios = NULL; |
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| 1221 | serge | 76 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
| 77 | bios = pci_map_rom(rdev->pdev, &size); |
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| 1117 | serge | 78 | if (!bios) { |
| 79 | return false; |
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| 80 | } |
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| 81 | |||
| 82 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
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| 83 | // pci_unmap_rom(rdev->pdev, bios); |
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| 84 | return false; |
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| 85 | } |
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| 1179 | serge | 86 | rdev->bios = kmalloc(size, GFP_KERNEL); |
| 1117 | serge | 87 | if (rdev->bios == NULL) { |
| 1268 | serge | 88 | // pci_unmap_rom(rdev->pdev, bios); |
| 1117 | serge | 89 | return false; |
| 90 | } |
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| 91 | memcpy(rdev->bios, bios, size); |
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| 1268 | serge | 92 | // pci_unmap_rom(rdev->pdev, bios); |
| 1117 | serge | 93 | return true; |
| 94 | } |
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| 95 | |||
| 96 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
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| 97 | { |
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| 98 | uint32_t viph_control; |
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| 99 | uint32_t bus_cntl; |
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| 100 | uint32_t d1vga_control; |
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| 101 | uint32_t d2vga_control; |
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| 102 | uint32_t vga_render_control; |
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| 103 | uint32_t rom_cntl; |
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| 104 | uint32_t cg_spll_func_cntl = 0; |
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| 105 | uint32_t cg_spll_status; |
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| 106 | bool r; |
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| 107 | |||
| 108 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 109 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 110 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 111 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 112 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 113 | rom_cntl = RREG32(R600_ROM_CNTL); |
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| 114 | |||
| 115 | /* disable VIP */ |
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| 116 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 117 | /* enable the rom */ |
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| 118 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 119 | /* Disable VGA mode */ |
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| 120 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 121 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 122 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 123 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 124 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 125 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 126 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 127 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 128 | |||
| 129 | if (rdev->family == CHIP_RV730) { |
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| 130 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); |
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| 131 | |||
| 132 | /* enable bypass mode */ |
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| 133 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | |
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| 134 | R600_SPLL_BYPASS_EN)); |
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| 135 | |||
| 136 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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| 137 | cg_spll_status = 0; |
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| 138 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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| 139 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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| 140 | |||
| 141 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); |
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| 142 | } else |
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| 143 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); |
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| 144 | |||
| 145 | r = radeon_read_bios(rdev); |
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| 146 | |||
| 147 | /* restore regs */ |
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| 148 | if (rdev->family == CHIP_RV730) { |
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| 149 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); |
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| 150 | |||
| 151 | /* wait for SPLL_CHG_STATUS to change to 1 */ |
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| 152 | cg_spll_status = 0; |
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| 153 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
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| 154 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
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| 155 | } |
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| 156 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 157 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 158 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 159 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 160 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 161 | WREG32(R600_ROM_CNTL, rom_cntl); |
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| 162 | return r; |
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| 163 | } |
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| 164 | |||
| 165 | static bool r600_read_disabled_bios(struct radeon_device *rdev) |
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| 166 | { |
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| 167 | uint32_t viph_control; |
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| 168 | uint32_t bus_cntl; |
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| 169 | uint32_t d1vga_control; |
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| 170 | uint32_t d2vga_control; |
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| 171 | uint32_t vga_render_control; |
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| 172 | uint32_t rom_cntl; |
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| 173 | uint32_t general_pwrmgt; |
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| 174 | uint32_t low_vid_lower_gpio_cntl; |
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| 175 | uint32_t medium_vid_lower_gpio_cntl; |
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| 176 | uint32_t high_vid_lower_gpio_cntl; |
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| 177 | uint32_t ctxsw_vid_lower_gpio_cntl; |
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| 178 | uint32_t lower_gpio_enable; |
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| 179 | bool r; |
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| 180 | |||
| 181 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 182 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 183 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 184 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 185 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 186 | rom_cntl = RREG32(R600_ROM_CNTL); |
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| 187 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); |
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| 188 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); |
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| 189 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); |
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| 190 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); |
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| 191 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); |
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| 192 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); |
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| 193 | |||
| 194 | /* disable VIP */ |
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| 195 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 196 | /* enable the rom */ |
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| 197 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 198 | /* Disable VGA mode */ |
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| 199 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 200 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 201 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 202 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 203 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 204 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 205 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 206 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 207 | |||
| 208 | WREG32(R600_ROM_CNTL, |
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| 209 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | |
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| 210 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | |
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| 211 | R600_SCK_OVERWRITE)); |
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| 212 | |||
| 213 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); |
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| 214 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, |
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| 215 | (low_vid_lower_gpio_cntl & ~0x400)); |
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| 216 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, |
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| 217 | (medium_vid_lower_gpio_cntl & ~0x400)); |
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| 218 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, |
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| 219 | (high_vid_lower_gpio_cntl & ~0x400)); |
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| 220 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, |
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| 221 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); |
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| 222 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); |
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| 223 | |||
| 224 | r = radeon_read_bios(rdev); |
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| 225 | |||
| 226 | /* restore regs */ |
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| 227 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 228 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 229 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 230 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 231 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 232 | WREG32(R600_ROM_CNTL, rom_cntl); |
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| 233 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); |
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| 234 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); |
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| 235 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); |
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| 236 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); |
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| 237 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); |
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| 238 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); |
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| 239 | return r; |
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| 240 | } |
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| 241 | |||
| 242 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) |
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| 243 | { |
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| 244 | uint32_t seprom_cntl1; |
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| 245 | uint32_t viph_control; |
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| 246 | uint32_t bus_cntl; |
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| 247 | uint32_t d1vga_control; |
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| 248 | uint32_t d2vga_control; |
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| 249 | uint32_t vga_render_control; |
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| 250 | uint32_t gpiopad_a; |
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| 251 | uint32_t gpiopad_en; |
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| 252 | uint32_t gpiopad_mask; |
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| 253 | bool r; |
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| 254 | |||
| 255 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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| 256 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 257 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 258 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
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| 259 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
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| 260 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
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| 261 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
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| 262 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); |
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| 263 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); |
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| 264 | |||
| 265 | WREG32(RADEON_SEPROM_CNTL1, |
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| 266 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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| 267 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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| 268 | WREG32(RADEON_GPIOPAD_A, 0); |
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| 269 | WREG32(RADEON_GPIOPAD_EN, 0); |
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| 270 | WREG32(RADEON_GPIOPAD_MASK, 0); |
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| 271 | |||
| 272 | /* disable VIP */ |
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| 273 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 274 | |||
| 275 | /* enable the rom */ |
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| 276 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 277 | |||
| 278 | /* Disable VGA mode */ |
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| 279 | WREG32(AVIVO_D1VGA_CONTROL, |
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| 280 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 281 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 282 | WREG32(AVIVO_D2VGA_CONTROL, |
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| 283 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
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| 284 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
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| 285 | WREG32(AVIVO_VGA_RENDER_CONTROL, |
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| 286 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
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| 287 | |||
| 288 | r = radeon_read_bios(rdev); |
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| 289 | |||
| 290 | /* restore regs */ |
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| 291 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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| 292 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 293 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 294 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
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| 295 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
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| 296 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
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| 297 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); |
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| 298 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); |
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| 299 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); |
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| 300 | return r; |
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| 301 | } |
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| 302 | |||
| 303 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) |
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| 304 | { |
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| 305 | uint32_t seprom_cntl1; |
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| 306 | uint32_t viph_control; |
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| 307 | uint32_t bus_cntl; |
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| 308 | uint32_t crtc_gen_cntl; |
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| 309 | uint32_t crtc2_gen_cntl; |
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| 310 | uint32_t crtc_ext_cntl; |
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| 311 | uint32_t fp2_gen_cntl; |
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| 312 | bool r; |
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| 313 | |||
| 314 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
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| 315 | viph_control = RREG32(RADEON_VIPH_CONTROL); |
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| 316 | bus_cntl = RREG32(RADEON_BUS_CNTL); |
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| 317 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
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| 318 | crtc2_gen_cntl = 0; |
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| 319 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
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| 320 | fp2_gen_cntl = 0; |
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| 321 | |||
| 322 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 323 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
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| 324 | } |
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| 325 | |||
| 326 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 327 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
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| 328 | } |
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| 329 | |||
| 330 | WREG32(RADEON_SEPROM_CNTL1, |
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| 331 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
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| 332 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
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| 333 | |||
| 334 | /* disable VIP */ |
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| 335 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
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| 336 | |||
| 337 | /* enable the rom */ |
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| 338 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
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| 339 | |||
| 340 | /* Turn off mem requests and CRTC for both controllers */ |
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| 341 | WREG32(RADEON_CRTC_GEN_CNTL, |
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| 342 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | |
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| 343 | (RADEON_CRTC_DISP_REQ_EN_B | |
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| 344 | RADEON_CRTC_EXT_DISP_EN))); |
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| 345 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 346 | WREG32(RADEON_CRTC2_GEN_CNTL, |
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| 347 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | |
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| 348 | RADEON_CRTC2_DISP_REQ_EN_B)); |
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| 349 | } |
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| 350 | /* Turn off CRTC */ |
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| 351 | WREG32(RADEON_CRTC_EXT_CNTL, |
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| 352 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | |
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| 353 | (RADEON_CRTC_SYNC_TRISTAT | |
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| 354 | RADEON_CRTC_DISPLAY_DIS))); |
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| 355 | |||
| 356 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 357 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
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| 358 | } |
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| 359 | |||
| 360 | r = radeon_read_bios(rdev); |
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| 361 | |||
| 362 | /* restore regs */ |
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| 363 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
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| 364 | WREG32(RADEON_VIPH_CONTROL, viph_control); |
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| 365 | WREG32(RADEON_BUS_CNTL, bus_cntl); |
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| 366 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
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| 367 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
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| 368 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
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| 369 | } |
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| 370 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
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| 371 | if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
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| 372 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
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| 373 | } |
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| 374 | return r; |
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| 375 | } |
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| 376 | |||
| 377 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) |
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| 378 | { |
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| 1233 | serge | 379 | if (rdev->flags & RADEON_IS_IGP) |
| 380 | return igp_read_bios_from_vram(rdev); |
||
| 381 | else if (rdev->family >= CHIP_RV770) |
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| 1117 | serge | 382 | return r700_read_disabled_bios(rdev); |
| 383 | else if (rdev->family >= CHIP_R600) |
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| 384 | return r600_read_disabled_bios(rdev); |
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| 385 | else if (rdev->family >= CHIP_RS600) |
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| 386 | return avivo_read_disabled_bios(rdev); |
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| 387 | else |
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| 388 | return legacy_read_disabled_bios(rdev); |
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| 389 | } |
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| 390 | |||
| 391 | bool radeon_get_bios(struct radeon_device *rdev) |
||
| 392 | { |
||
| 393 | bool r; |
||
| 394 | uint16_t tmp; |
||
| 395 | |||
| 1233 | serge | 396 | if (rdev->flags & RADEON_IS_IGP) { |
| 397 | r = igp_read_bios_from_vram(rdev); |
||
| 398 | if (r == false) |
||
| 399 | r = radeon_read_bios(rdev); |
||
| 400 | } else |
||
| 1117 | serge | 401 | r = radeon_read_bios(rdev); |
| 1129 | serge | 402 | if (r == false) { |
| 403 | r = radeon_read_disabled_bios(rdev); |
||
| 404 | } |
||
| 1117 | serge | 405 | if (r == false || rdev->bios == NULL) { |
| 406 | DRM_ERROR("Unable to locate a BIOS ROM\n"); |
||
| 407 | rdev->bios = NULL; |
||
| 408 | return false; |
||
| 409 | } |
||
| 410 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
||
| 411 | goto free_bios; |
||
| 412 | } |
||
| 413 | |||
| 414 | rdev->bios_header_start = RBIOS16(0x48); |
||
| 415 | if (!rdev->bios_header_start) { |
||
| 416 | goto free_bios; |
||
| 417 | } |
||
| 418 | tmp = rdev->bios_header_start + 4; |
||
| 419 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || |
||
| 420 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { |
||
| 421 | rdev->is_atom_bios = true; |
||
| 422 | } else { |
||
| 423 | rdev->is_atom_bios = false; |
||
| 424 | } |
||
| 425 | |||
| 1179 | serge | 426 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); |
| 1117 | serge | 427 | return true; |
| 428 | free_bios: |
||
| 429 | kfree(rdev->bios); |
||
| 430 | rdev->bios = NULL; |
||
| 431 | return false; |
||
| 432 | } |