WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
2997	Serge	26	#include
		27	#include
1117	serge	28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	extern void
1963	serge	34	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
		35	uint32_t supported_device, u16 caps);
1117	serge	36
		37	/* from radeon_legacy_encoder.c */
		38	extern void
1963	serge	39	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1117	serge	40	uint32_t supported_device);
		41
		42	union atom_supported_devices {
		43	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		44	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		45	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		46	};
		47
2997	Serge	48	static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
		49	ATOM_GPIO_I2C_ASSIGMENT *gpio,
		50	u8 index)
1117	serge	51	{
2997	Serge	52	/* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
		53	if ((rdev->family == CHIP_R420) \|\|
		54	(rdev->family == CHIP_R423) \|\|
		55	(rdev->family == CHIP_RV410)) {
		56	if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) \|\|
		57	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) \|\|
		58	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
		59	gpio->ucClkMaskShift = 0x19;
		60	gpio->ucDataMaskShift = 0x18;
		61	}
		62	}
1117	serge	63
1963	serge	64	/* some evergreen boards have bad data for this entry */
		65	if (ASIC_IS_DCE4(rdev)) {
2997	Serge	66	if ((index == 7) &&
1963	serge	67	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
		68	(gpio->sucI2cId.ucAccess == 0)) {
		69	gpio->sucI2cId.ucAccess = 0x97;
		70	gpio->ucDataMaskShift = 8;
		71	gpio->ucDataEnShift = 8;
		72	gpio->ucDataY_Shift = 8;
		73	gpio->ucDataA_Shift = 8;
		74	}
		75	}
		76
		77	/* some DCE3 boards have bad data for this entry */
		78	if (ASIC_IS_DCE3(rdev)) {
2997	Serge	79	if ((index == 4) &&
1963	serge	80	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
		81	(gpio->sucI2cId.ucAccess == 0x94))
		82	gpio->sucI2cId.ucAccess = 0x14;
		83	}
2997	Serge	84	}
1963	serge	85
2997	Serge	86	static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
		87	{
		88	struct radeon_i2c_bus_rec i2c;
		89
		90	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		91
1321	serge	92	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		93	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		94	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		95	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		96	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		97	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		98	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		99	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		100	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		101	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		102	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		103	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		104	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		105	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		106	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		107	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		108
		109	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		110	i2c.hw_capable = true;
		111	else
		112	i2c.hw_capable = false;
		113
		114	if (gpio->sucI2cId.ucAccess == 0xa0)
		115	i2c.mm_i2c = true;
		116	else
		117	i2c.mm_i2c = false;
		118
		119	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		120
1963	serge	121	if (i2c.mask_clk_reg)
1117	serge	122	i2c.valid = true;
2997	Serge	123	else
		124	i2c.valid = false;
1117	serge	125
		126	return i2c;
		127	}
		128
2997	Serge	129	static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		130	uint8_t id)
1963	serge	131	{
		132	struct atom_context *ctx = rdev->mode_info.atom_context;
		133	ATOM_GPIO_I2C_ASSIGMENT *gpio;
		134	struct radeon_i2c_bus_rec i2c;
		135	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		136	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		137	uint16_t data_offset, size;
		138	int i, num_indices;
		139
		140	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
2997	Serge	141	i2c.valid = false;
1963	serge	142
		143	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
		144	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		145
		146	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		147	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
		148
5078	serge	149	gpio = &i2c_info->asGPIO_Info[0];
1963	serge	150	for (i = 0; i < num_indices; i++) {
		151
2997	Serge	152	radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
		153
		154	if (gpio->sucI2cId.ucAccess == id) {
		155	i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
		156	break;
		157	}
5078	serge	158	gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
		159	((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
1963	serge	160	}
		161	}
		162
2997	Serge	163	return i2c;
		164	}
1963	serge	165
2997	Serge	166	void radeon_atombios_i2c_init(struct radeon_device *rdev)
		167	{
		168	struct atom_context *ctx = rdev->mode_info.atom_context;
		169	ATOM_GPIO_I2C_ASSIGMENT *gpio;
		170	struct radeon_i2c_bus_rec i2c;
		171	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		172	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		173	uint16_t data_offset, size;
		174	int i, num_indices;
		175	char stmp[32];
1963	serge	176
2997	Serge	177	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
		178	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
1963	serge	179
2997	Serge	180	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		181	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
1963	serge	182
5078	serge	183	gpio = &i2c_info->asGPIO_Info[0];
2997	Serge	184	for (i = 0; i < num_indices; i++) {
		185	radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
		186
		187	i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
		188
		189	if (i2c.valid) {
1963	serge	190	sprintf(stmp, "0x%x", i2c.i2c_id);
		191	rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
		192	}
5078	serge	193	gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
		194	((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
1963	serge	195	}
		196	}
		197	}
		198
2997	Serge	199	static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
1321	serge	200	u8 id)
		201	{
		202	struct atom_context *ctx = rdev->mode_info.atom_context;
		203	struct radeon_gpio_rec gpio;
		204	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		205	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		206	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		207	u16 data_offset, size;
		208	int i, num_indices;
		209
		210	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		211	gpio.valid = false;
		212
1963	serge	213	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
1321	serge	214	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		215
1963	serge	216	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		217	sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
1321	serge	218
5078	serge	219	pin = gpio_info->asGPIO_Pin;
1321	serge	220	for (i = 0; i < num_indices; i++) {
		221	if (id == pin->ucGPIO_ID) {
		222	gpio.id = pin->ucGPIO_ID;
1963	serge	223	gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
1321	serge	224	gpio.mask = (1 << pin->ucGpioPinBitShift);
		225	gpio.valid = true;
		226	break;
		227	}
5078	serge	228	pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
		229	((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
1321	serge	230	}
1963	serge	231	}
1321	serge	232
		233	return gpio;
		234	}
		235
		236	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		237	struct radeon_gpio_rec *gpio)
		238	{
		239	struct radeon_hpd hpd;
1430	serge	240	u32 reg;
		241
1963	serge	242	memset(&hpd, 0, sizeof(struct radeon_hpd));
		243
2997	Serge	244	if (ASIC_IS_DCE6(rdev))
		245	reg = SI_DC_GPIO_HPD_A;
		246	else if (ASIC_IS_DCE4(rdev))
1430	serge	247	reg = EVERGREEN_DC_GPIO_HPD_A;
		248	else
		249	reg = AVIVO_DC_GPIO_HPD_A;
		250
1321	serge	251	hpd.gpio = *gpio;
1430	serge	252	if (gpio->reg == reg) {
1321	serge	253	switch(gpio->mask) {
		254	case (1 << 0):
		255	hpd.hpd = RADEON_HPD_1;
		256	break;
		257	case (1 << 8):
		258	hpd.hpd = RADEON_HPD_2;
		259	break;
		260	case (1 << 16):
		261	hpd.hpd = RADEON_HPD_3;
		262	break;
		263	case (1 << 24):
		264	hpd.hpd = RADEON_HPD_4;
		265	break;
		266	case (1 << 26):
		267	hpd.hpd = RADEON_HPD_5;
		268	break;
		269	case (1 << 28):
		270	hpd.hpd = RADEON_HPD_6;
		271	break;
		272	default:
		273	hpd.hpd = RADEON_HPD_NONE;
		274	break;
		275	}
		276	} else
		277	hpd.hpd = RADEON_HPD_NONE;
		278	return hpd;
		279	}
		280
1117	serge	281	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		282	uint32_t supported_device,
		283	int *connector_type,
1179	serge	284	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	285	uint16_t *line_mux,
		286	struct radeon_hpd *hpd)
1117	serge	287	{
		288
		289	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		290	if ((dev->pdev->device == 0x791e) &&
		291	(dev->pdev->subsystem_vendor == 0x1043) &&
		292	(dev->pdev->subsystem_device == 0x826d)) {
		293	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		294	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		295	*connector_type = DRM_MODE_CONNECTOR_DVID;
		296	}
		297
1428	serge	298	/* Asrock RS600 board lists the DVI port as HDMI */
		299	if ((dev->pdev->device == 0x7941) &&
		300	(dev->pdev->subsystem_vendor == 0x1849) &&
		301	(dev->pdev->subsystem_device == 0x7941)) {
		302	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		303	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		304	*connector_type = DRM_MODE_CONNECTOR_DVID;
		305	}
		306
1963	serge	307	/* MSI K9A2GM V2/V3 board has no HDMI or DVI */
		308	if ((dev->pdev->device == 0x796e) &&
		309	(dev->pdev->subsystem_vendor == 0x1462) &&
		310	(dev->pdev->subsystem_device == 0x7302)) {
		311	if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) \|\|
		312	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		313	return false;
		314	}
		315
1117	serge	316	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		317	if ((dev->pdev->device == 0x7941) &&
		318	(dev->pdev->subsystem_vendor == 0x147b) &&
		319	(dev->pdev->subsystem_device == 0x2412)) {
		320	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		321	return false;
		322	}
		323
		324	/* Falcon NW laptop lists vga ddc line for LVDS */
		325	if ((dev->pdev->device == 0x5653) &&
		326	(dev->pdev->subsystem_vendor == 0x1462) &&
		327	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	328	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	329	i2c_bus->valid = false;
1179	serge	330	*line_mux = 53;
		331	}
1117	serge	332	}
		333
1321	serge	334	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		335	if ((dev->pdev->device == 0x7146) &&
		336	(dev->pdev->subsystem_vendor == 0x17af) &&
		337	(dev->pdev->subsystem_device == 0x2058)) {
		338	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		339	return false;
		340	}
		341
		342	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		343	if ((dev->pdev->device == 0x7142) &&
		344	(dev->pdev->subsystem_vendor == 0x1458) &&
		345	(dev->pdev->subsystem_device == 0x2134)) {
		346	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		347	return false;
		348	}
		349
		350
1117	serge	351	/* Funky macbooks */
		352	if ((dev->pdev->device == 0x71C5) &&
		353	(dev->pdev->subsystem_vendor == 0x106b) &&
		354	(dev->pdev->subsystem_device == 0x0080)) {
		355	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		356	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		357	return false;
1963	serge	358	if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
		359	*line_mux = 0x90;
1117	serge	360	}
		361
1963	serge	362	/* mac rv630, rv730, others */
		363	if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
		364	(*connector_type == DRM_MODE_CONNECTOR_DVII)) {
		365	*connector_type = DRM_MODE_CONNECTOR_9PinDIN;
		366	*line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
		367	}
		368
1117	serge	369	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		370	if ((dev->pdev->device == 0x9598) &&
		371	(dev->pdev->subsystem_vendor == 0x1043) &&
		372	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	373	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		374	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	375	}
		376	}
		377
1963	serge	378	/* ASUS HD 3600 board lists the DVI port as HDMI */
		379	if ((dev->pdev->device == 0x9598) &&
		380	(dev->pdev->subsystem_vendor == 0x1043) &&
		381	(dev->pdev->subsystem_device == 0x01e4)) {
		382	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		383	*connector_type = DRM_MODE_CONNECTOR_DVII;
		384	}
		385	}
		386
1179	serge	387	/* ASUS HD 3450 board lists the DVI port as HDMI */
		388	if ((dev->pdev->device == 0x95C5) &&
		389	(dev->pdev->subsystem_vendor == 0x1043) &&
		390	(dev->pdev->subsystem_device == 0x01e2)) {
		391	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		392	*connector_type = DRM_MODE_CONNECTOR_DVII;
		393	}
		394	}
		395
		396	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		397	* HDMI + VGA reporting as HDMI
		398	*/
		399	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		400	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		401	*connector_type = DRM_MODE_CONNECTOR_VGA;
		402	*line_mux = 0;
		403	}
		404	}
		405
1963	serge	406	/* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
		407	* on the laptop and a DVI port on the docking station and
		408	* both share the same encoder, hpd pin, and ddc line.
		409	* So while the bios table is technically correct,
		410	* we drop the DVI port here since xrandr has no concept of
		411	* encoders and will try and drive both connectors
		412	* with different crtcs which isn't possible on the hardware
		413	* side and leaves no crtcs for LVDS or VGA.
		414	*/
		415	if (((dev->pdev->device == 0x95c4) \|\| (dev->pdev->device == 0x9591)) &&
1321	serge	416	(dev->pdev->subsystem_vendor == 0x1025) &&
		417	(dev->pdev->subsystem_device == 0x013c)) {
		418	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
1963	serge	419	(supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
		420	/* actually it's a DVI-D port not DVI-I */
1321	serge	421	*connector_type = DRM_MODE_CONNECTOR_DVID;
1963	serge	422	return false;
		423	}
1321	serge	424	}
		425
1412	serge	426	/* XFX Pine Group device rv730 reports no VGA DDC lines
		427	* even though they are wired up to record 0x93
		428	*/
		429	if ((dev->pdev->device == 0x9498) &&
		430	(dev->pdev->subsystem_vendor == 0x1682) &&
2997	Serge	431	(dev->pdev->subsystem_device == 0x2452) &&
		432	(i2c_bus->valid == false) &&
		433	!(supported_device & (ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))) {
1412	serge	434	struct radeon_device *rdev = dev->dev_private;
		435	*i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
		436	}
2997	Serge	437
		438	/* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
		439	if (((dev->pdev->device == 0x9802) \|\| (dev->pdev->device == 0x9806)) &&
		440	(dev->pdev->subsystem_vendor == 0x1734) &&
		441	(dev->pdev->subsystem_device == 0x11bd)) {
		442	if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
		443	*connector_type = DRM_MODE_CONNECTOR_DVII;
		444	*line_mux = 0x3103;
		445	} else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
		446	*connector_type = DRM_MODE_CONNECTOR_DVII;
		447	}
		448	}
		449
5128	serge	450	/* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
		451	if ((dev->pdev->device == 0x9805) &&
		452	(dev->pdev->subsystem_vendor == 0x1734) &&
		453	(dev->pdev->subsystem_device == 0x11bd)) {
		454	if (*connector_type == DRM_MODE_CONNECTOR_VGA)
		455	return false;
		456	}
2997	Serge	457
1117	serge	458	return true;
		459	}
		460
		461	const int supported_devices_connector_convert[] = {
		462	DRM_MODE_CONNECTOR_Unknown,
		463	DRM_MODE_CONNECTOR_VGA,
		464	DRM_MODE_CONNECTOR_DVII,
		465	DRM_MODE_CONNECTOR_DVID,
		466	DRM_MODE_CONNECTOR_DVIA,
		467	DRM_MODE_CONNECTOR_SVIDEO,
		468	DRM_MODE_CONNECTOR_Composite,
		469	DRM_MODE_CONNECTOR_LVDS,
		470	DRM_MODE_CONNECTOR_Unknown,
		471	DRM_MODE_CONNECTOR_Unknown,
		472	DRM_MODE_CONNECTOR_HDMIA,
		473	DRM_MODE_CONNECTOR_HDMIB,
		474	DRM_MODE_CONNECTOR_Unknown,
		475	DRM_MODE_CONNECTOR_Unknown,
		476	DRM_MODE_CONNECTOR_9PinDIN,
		477	DRM_MODE_CONNECTOR_DisplayPort
		478	};
		479
1268	serge	480	const uint16_t supported_devices_connector_object_id_convert[] = {
		481	CONNECTOR_OBJECT_ID_NONE,
		482	CONNECTOR_OBJECT_ID_VGA,
		483	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		484	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		485	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		486	CONNECTOR_OBJECT_ID_COMPOSITE,
		487	CONNECTOR_OBJECT_ID_SVIDEO,
		488	CONNECTOR_OBJECT_ID_LVDS,
		489	CONNECTOR_OBJECT_ID_9PIN_DIN,
		490	CONNECTOR_OBJECT_ID_9PIN_DIN,
		491	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		492	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		493	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		494	CONNECTOR_OBJECT_ID_SVIDEO
		495	};
		496
1117	serge	497	const int object_connector_convert[] = {
		498	DRM_MODE_CONNECTOR_Unknown,
		499	DRM_MODE_CONNECTOR_DVII,
		500	DRM_MODE_CONNECTOR_DVII,
		501	DRM_MODE_CONNECTOR_DVID,
		502	DRM_MODE_CONNECTOR_DVID,
		503	DRM_MODE_CONNECTOR_VGA,
		504	DRM_MODE_CONNECTOR_Composite,
		505	DRM_MODE_CONNECTOR_SVIDEO,
		506	DRM_MODE_CONNECTOR_Unknown,
1179	serge	507	DRM_MODE_CONNECTOR_Unknown,
1117	serge	508	DRM_MODE_CONNECTOR_9PinDIN,
		509	DRM_MODE_CONNECTOR_Unknown,
		510	DRM_MODE_CONNECTOR_HDMIA,
		511	DRM_MODE_CONNECTOR_HDMIB,
		512	DRM_MODE_CONNECTOR_LVDS,
		513	DRM_MODE_CONNECTOR_9PinDIN,
		514	DRM_MODE_CONNECTOR_Unknown,
		515	DRM_MODE_CONNECTOR_Unknown,
		516	DRM_MODE_CONNECTOR_Unknown,
1404	serge	517	DRM_MODE_CONNECTOR_DisplayPort,
		518	DRM_MODE_CONNECTOR_eDP,
		519	DRM_MODE_CONNECTOR_Unknown
1117	serge	520	};
		521
		522	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		523	{
		524	struct radeon_device *rdev = dev->dev_private;
		525	struct radeon_mode_info *mode_info = &rdev->mode_info;
		526	struct atom_context *ctx = mode_info->atom_context;
		527	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	528	u16 size, data_offset;
		529	u8 frev, crev;
1117	serge	530	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
1963	serge	531	ATOM_ENCODER_OBJECT_TABLE *enc_obj;
		532	ATOM_OBJECT_TABLE *router_obj;
1117	serge	533	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		534	ATOM_OBJECT_HEADER *obj_header;
1963	serge	535	int i, j, k, path_size, device_support;
1117	serge	536	int connector_type;
1321	serge	537	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	538	struct radeon_i2c_bus_rec ddc_bus;
1963	serge	539	struct radeon_router router;
1321	serge	540	struct radeon_gpio_rec gpio;
		541	struct radeon_hpd hpd;
1117	serge	542
1963	serge	543	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
1117	serge	544	return false;
		545
		546	if (crev < 2)
		547	return false;
		548
		549	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		550	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		551	(ctx->bios + data_offset +
		552	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		553	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		554	(ctx->bios + data_offset +
		555	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
1963	serge	556	enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
		557	(ctx->bios + data_offset +
		558	le16_to_cpu(obj_header->usEncoderObjectTableOffset));
		559	router_obj = (ATOM_OBJECT_TABLE *)
		560	(ctx->bios + data_offset +
		561	le16_to_cpu(obj_header->usRouterObjectTableOffset));
1117	serge	562	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		563
		564	path_size = 0;
		565	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		566	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		567	ATOM_DISPLAY_OBJECT_PATH *path;
		568	addr += path_size;
		569	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		570	path_size += le16_to_cpu(path->usSize);
1963	serge	571
1117	serge	572	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		573	uint8_t con_obj_id, con_obj_num, con_obj_type;
		574
		575	con_obj_id =
		576	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		577	>> OBJECT_ID_SHIFT;
		578	con_obj_num =
		579	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		580	>> ENUM_ID_SHIFT;
		581	con_obj_type =
		582	(le16_to_cpu(path->usConnObjectId) &
		583	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		584
1221	serge	585	/* TODO CV support */
		586	if (le16_to_cpu(path->usDeviceTag) ==
		587	ATOM_DEVICE_CV_SUPPORT)
1117	serge	588	continue;
		589
1268	serge	590	/* IGP chips */
		591	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	592	(con_obj_id ==
		593	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		594	uint16_t igp_offset = 0;
		595	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		596
		597	index =
		598	GetIndexIntoMasterTable(DATA,
		599	IntegratedSystemInfo);
		600
1963	serge	601	if (atom_parse_data_header(ctx, index, &size, &frev,
		602	&crev, &igp_offset)) {
1117	serge	603
		604	if (crev >= 2) {
		605	igp_obj =
		606	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		607	*) (ctx->bios + igp_offset);
		608
		609	if (igp_obj) {
		610	uint32_t slot_config, ct;
		611
		612	if (con_obj_num == 1)
		613	slot_config =
		614	igp_obj->
		615	ulDDISlot1Config;
		616	else
		617	slot_config =
		618	igp_obj->
		619	ulDDISlot2Config;
		620
		621	ct = (slot_config >> 16) & 0xff;
		622	connector_type =
		623	object_connector_convert
		624	[ct];
1268	serge	625	connector_object_id = ct;
1117	serge	626	igp_lane_info =
		627	slot_config & 0xffff;
		628	} else
		629	continue;
		630	} else
		631	continue;
		632	} else {
		633	igp_lane_info = 0;
		634	connector_type =
		635	object_connector_convert[con_obj_id];
1268	serge	636	connector_object_id = con_obj_id;
1117	serge	637	}
1963	serge	638	} else {
		639	igp_lane_info = 0;
		640	connector_type =
		641	object_connector_convert[con_obj_id];
		642	connector_object_id = con_obj_id;
		643	}
1117	serge	644
		645	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		646	continue;
		647
1963	serge	648	router.ddc_valid = false;
		649	router.cd_valid = false;
		650	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
		651	uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
1117	serge	652
1963	serge	653	grph_obj_id =
1117	serge	654	(le16_to_cpu(path->usGraphicObjIds[j]) &
		655	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1963	serge	656	grph_obj_num =
1117	serge	657	(le16_to_cpu(path->usGraphicObjIds[j]) &
		658	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1963	serge	659	grph_obj_type =
1117	serge	660	(le16_to_cpu(path->usGraphicObjIds[j]) &
		661	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		662
1963	serge	663	if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		664	for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
		665	u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
		666	if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
		667	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		668	(ctx->bios + data_offset +
		669	le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
		670	ATOM_ENCODER_CAP_RECORD *cap_record;
		671	u16 caps = 0;
1117	serge	672
1963	serge	673	while (record->ucRecordSize > 0 &&
		674	record->ucRecordType > 0 &&
		675	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		676	switch (record->ucRecordType) {
		677	case ATOM_ENCODER_CAP_RECORD_TYPE:
		678	cap_record =(ATOM_ENCODER_CAP_RECORD *)
		679	record;
		680	caps = le16_to_cpu(cap_record->usEncoderCap);
		681	break;
		682	}
		683	record = (ATOM_COMMON_RECORD_HEADER *)
		684	((char *)record + record->ucRecordSize);
		685	}
1123	serge	686	radeon_add_atom_encoder(dev,
1963	serge	687	encoder_obj,
1123	serge	688	le16_to_cpu
		689	(path->
1963	serge	690	usDeviceTag),
		691	caps);
		692	}
		693	}
		694	} else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
		695	for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
		696	u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
		697	if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
		698	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		699	(ctx->bios + data_offset +
		700	le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
		701	ATOM_I2C_RECORD *i2c_record;
		702	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		703	ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
		704	ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
		705	ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
		706	(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
		707	(ctx->bios + data_offset +
		708	le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
5078	serge	709	u8 num_dst_objs = (u8 )
		710	((u8 *)router_src_dst_table + 1 +
		711	(router_src_dst_table->ucNumberOfSrc * 2));
		712	u16 dst_objs = (u16 )(num_dst_objs + 1);
1963	serge	713	int enum_id;
1117	serge	714
1963	serge	715	router.router_id = router_obj_id;
5078	serge	716	for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
1963	serge	717	if (le16_to_cpu(path->usConnObjectId) ==
5078	serge	718	le16_to_cpu(dst_objs[enum_id]))
1963	serge	719	break;
		720	}
		721
		722	while (record->ucRecordSize > 0 &&
		723	record->ucRecordType > 0 &&
		724	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		725	switch (record->ucRecordType) {
		726	case ATOM_I2C_RECORD_TYPE:
		727	i2c_record =
		728	(ATOM_I2C_RECORD *)
		729	record;
		730	i2c_config =
		731	(ATOM_I2C_ID_CONFIG_ACCESS *)
		732	&i2c_record->sucI2cId;
		733	router.i2c_info =
		734	radeon_lookup_i2c_gpio(rdev,
		735	i2c_config->
		736	ucAccess);
		737	router.i2c_addr = i2c_record->ucI2CAddr >> 1;
		738	break;
		739	case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
		740	ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
		741	record;
		742	router.ddc_valid = true;
		743	router.ddc_mux_type = ddc_path->ucMuxType;
		744	router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
		745	router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
		746	break;
		747	case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
		748	cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
		749	record;
		750	router.cd_valid = true;
		751	router.cd_mux_type = cd_path->ucMuxType;
		752	router.cd_mux_control_pin = cd_path->ucMuxControlPin;
		753	router.cd_mux_state = cd_path->ucMuxState[enum_id];
		754	break;
		755	}
		756	record = (ATOM_COMMON_RECORD_HEADER *)
		757	((char *)record + record->ucRecordSize);
		758	}
		759	}
		760	}
1117	serge	761	}
		762	}
		763
1321	serge	764	/* look up gpio for ddc, hpd */
1963	serge	765	ddc_bus.valid = false;
		766	hpd.hpd = RADEON_HPD_NONE;
1117	serge	767	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	768	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	769	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		770	if (le16_to_cpu(path->usConnObjectId) ==
		771	le16_to_cpu(con_obj->asObjects[j].
		772	usObjectID)) {
		773	ATOM_COMMON_RECORD_HEADER
		774	*record =
		775	(ATOM_COMMON_RECORD_HEADER
		776	*)
		777	(ctx->bios + data_offset +
		778	le16_to_cpu(con_obj->
		779	asObjects[j].
		780	usRecordOffset));
		781	ATOM_I2C_RECORD *i2c_record;
1321	serge	782	ATOM_HPD_INT_RECORD *hpd_record;
		783	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
1117	serge	784
1963	serge	785	while (record->ucRecordSize > 0 &&
		786	record->ucRecordType > 0 &&
		787	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	788	switch (record->ucRecordType) {
1117	serge	789	case ATOM_I2C_RECORD_TYPE:
		790	i2c_record =
1321	serge	791	(ATOM_I2C_RECORD *)
		792	record;
		793	i2c_config =
		794	(ATOM_I2C_ID_CONFIG_ACCESS *)
		795	&i2c_record->sucI2cId;
		796	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		797	i2c_config->
		798	ucAccess);
1117	serge	799	break;
1321	serge	800	case ATOM_HPD_INT_RECORD_TYPE:
		801	hpd_record =
		802	(ATOM_HPD_INT_RECORD *)
		803	record;
		804	gpio = radeon_lookup_gpio(rdev,
		805	hpd_record->ucHPDIntGPIOID);
		806	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		807	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		808	break;
1117	serge	809	}
		810	record =
		811	(ATOM_COMMON_RECORD_HEADER
		812	) ((char )record
		813	+
		814	record->
		815	ucRecordSize);
		816	}
		817	break;
		818	}
		819	}
1321	serge	820	}
1117	serge	821
1430	serge	822	/* needed for aux chan transactions */
1963	serge	823	ddc_bus.hpd = hpd.hpd;
1430	serge	824
1179	serge	825	conn_id = le16_to_cpu(path->usConnObjectId);
		826
		827	if (!radeon_atom_apply_quirks
		828	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	829	&ddc_bus, &conn_id, &hpd))
1179	serge	830	continue;
		831
1123	serge	832	radeon_add_atom_connector(dev,
1179	serge	833	conn_id,
1123	serge	834	le16_to_cpu(path->
		835	usDeviceTag),
		836	connector_type, &ddc_bus,
1963	serge	837	igp_lane_info,
1321	serge	838	connector_object_id,
1963	serge	839	&hpd,
		840	&router);
1117	serge	841
		842	}
		843	}
		844
1123	serge	845	radeon_link_encoder_connector(dev);
1117	serge	846
		847	return true;
		848	}
		849
1268	serge	850	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		851	int connector_type,
		852	uint16_t devices)
		853	{
		854	struct radeon_device *rdev = dev->dev_private;
		855
		856	if (rdev->flags & RADEON_IS_IGP) {
		857	return supported_devices_connector_object_id_convert
		858	[connector_type];
		859	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		860	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		861	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		862	struct radeon_mode_info *mode_info = &rdev->mode_info;
		863	struct atom_context *ctx = mode_info->atom_context;
		864	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		865	uint16_t size, data_offset;
		866	uint8_t frev, crev;
		867	ATOM_XTMDS_INFO *xtmds;
		868
1963	serge	869	if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
1268	serge	870	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		871
		872	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		873	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		874	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		875	else
		876	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		877	} else {
		878	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		879	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		880	else
		881	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		882	}
1963	serge	883	} else
		884	return supported_devices_connector_object_id_convert
		885	[connector_type];
1268	serge	886	} else {
		887	return supported_devices_connector_object_id_convert
		888	[connector_type];
		889	}
		890	}
		891
1117	serge	892	struct bios_connector {
		893	bool valid;
1179	serge	894	uint16_t line_mux;
1117	serge	895	uint16_t devices;
		896	int connector_type;
		897	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	898	struct radeon_hpd hpd;
1117	serge	899	};
		900
		901	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		902	drm_device
		903	*dev)
		904	{
		905	struct radeon_device *rdev = dev->dev_private;
		906	struct radeon_mode_info *mode_info = &rdev->mode_info;
		907	struct atom_context *ctx = mode_info->atom_context;
		908	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		909	uint16_t size, data_offset;
		910	uint8_t frev, crev;
		911	uint16_t device_support;
		912	uint8_t dac;
		913	union atom_supported_devices *supported_devices;
1321	serge	914	int i, j, max_device;
1963	serge	915	struct bios_connector *bios_connectors;
		916	size_t bc_size = sizeof(bios_connectors) ATOM_MAX_SUPPORTED_DEVICE;
		917	struct radeon_router router;
1117	serge	918
1963	serge	919	router.ddc_valid = false;
		920	router.cd_valid = false;
1128	serge	921
1963	serge	922	bios_connectors = kzalloc(bc_size, GFP_KERNEL);
		923	if (!bios_connectors)
		924	return false;
		925
		926	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
		927	&data_offset)) {
		928	kfree(bios_connectors);
		929	return false;
		930	}
		931
1117	serge	932	supported_devices =
		933	(union atom_supported_devices *)(ctx->bios + data_offset);
		934
		935	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		936
1321	serge	937	if (frev > 1)
		938	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		939	else
		940	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		941
		942	for (i = 0; i < max_device; i++) {
1117	serge	943	ATOM_CONNECTOR_INFO_I2C ci =
		944	supported_devices->info.asConnInfo[i];
		945
		946	bios_connectors[i].valid = false;
		947
		948	if (!(device_support & (1 << i))) {
		949	continue;
		950	}
		951
		952	if (i == ATOM_DEVICE_CV_INDEX) {
1963	serge	953	DRM_DEBUG_KMS("Skipping Component Video\n");
1117	serge	954	continue;
		955	}
		956
		957	bios_connectors[i].connector_type =
		958	supported_devices_connector_convert[ci.sucConnectorInfo.
		959	sbfAccess.
		960	bfConnectorType];
		961
		962	if (bios_connectors[i].connector_type ==
		963	DRM_MODE_CONNECTOR_Unknown)
		964	continue;
		965
		966	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		967
		968	bios_connectors[i].line_mux =
1321	serge	969	ci.sucI2cId.ucAccess;
1117	serge	970
		971	/* give tv unique connector ids */
		972	if (i == ATOM_DEVICE_TV1_INDEX) {
		973	bios_connectors[i].ddc_bus.valid = false;
		974	bios_connectors[i].line_mux = 50;
		975	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		976	bios_connectors[i].ddc_bus.valid = false;
		977	bios_connectors[i].line_mux = 51;
		978	} else if (i == ATOM_DEVICE_CV_INDEX) {
		979	bios_connectors[i].ddc_bus.valid = false;
		980	bios_connectors[i].line_mux = 52;
		981	} else
		982	bios_connectors[i].ddc_bus =
1321	serge	983	radeon_lookup_i2c_gpio(rdev,
1117	serge	984	bios_connectors[i].line_mux);
		985
1321	serge	986	if ((crev > 1) && (frev > 1)) {
		987	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		988	switch (isb) {
		989	case 0x4:
		990	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		991	break;
		992	case 0xa:
		993	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		994	break;
		995	default:
		996	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		997	break;
		998	}
		999	} else {
		1000	if (i == ATOM_DEVICE_DFP1_INDEX)
		1001	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		1002	else if (i == ATOM_DEVICE_DFP2_INDEX)
		1003	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		1004	else
		1005	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		1006	}
		1007
1117	serge	1008	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		1009	* shared with a DVI port, we'll pick up the DVI connector when we
		1010	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		1011	*/
		1012	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		1013	bios_connectors[i].connector_type =
		1014	DRM_MODE_CONNECTOR_VGA;
		1015
		1016	if (!radeon_atom_apply_quirks
		1017	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	1018	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		1019	&bios_connectors[i].hpd))
1117	serge	1020	continue;
		1021
		1022	bios_connectors[i].valid = true;
		1023	bios_connectors[i].devices = (1 << i);
		1024
1123	serge	1025	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		1026	radeon_add_atom_encoder(dev,
1963	serge	1027	radeon_get_encoder_enum(dev,
1123	serge	1028	(1 << i),
		1029	dac),
1963	serge	1030	(1 << i),
		1031	0);
1123	serge	1032	else
		1033	radeon_add_legacy_encoder(dev,
1963	serge	1034	radeon_get_encoder_enum(dev,
1404	serge	1035	(1 << i),
1123	serge	1036	dac),
		1037	(1 << i));
1117	serge	1038	}
		1039
		1040	/* combine shared connectors */
1321	serge	1041	for (i = 0; i < max_device; i++) {
1117	serge	1042	if (bios_connectors[i].valid) {
1321	serge	1043	for (j = 0; j < max_device; j++) {
1117	serge	1044	if (bios_connectors[j].valid && (i != j)) {
		1045	if (bios_connectors[i].line_mux ==
		1046	bios_connectors[j].line_mux) {
1404	serge	1047	/* make sure not to combine LVDS */
		1048	if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1049	bios_connectors[i].line_mux = 53;
		1050	bios_connectors[i].ddc_bus.valid = false;
		1051	continue;
		1052	}
		1053	if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1054	bios_connectors[j].line_mux = 53;
		1055	bios_connectors[j].ddc_bus.valid = false;
		1056	continue;
		1057	}
		1058	/* combine analog and digital for DVI-I */
		1059	if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1060	(bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) \|\|
		1061	((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1062	(bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
		1063	bios_connectors[i].devices \|=
		1064	bios_connectors[j].devices;
		1065	bios_connectors[i].connector_type =
1117	serge	1066	DRM_MODE_CONNECTOR_DVII;
1404	serge	1067	if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1321	serge	1068	bios_connectors[i].hpd =
		1069	bios_connectors[j].hpd;
1404	serge	1070	bios_connectors[j].valid = false;
1117	serge	1071	}
		1072	}
		1073	}
		1074	}
		1075	}
		1076	}
		1077
		1078	/* add the connectors */
1321	serge	1079	for (i = 0; i < max_device; i++) {
1268	serge	1080	if (bios_connectors[i].valid) {
		1081	uint16_t connector_object_id =
		1082	atombios_get_connector_object_id(dev,
		1083	bios_connectors[i].connector_type,
		1084	bios_connectors[i].devices);
1123	serge	1085	radeon_add_atom_connector(dev,
		1086	bios_connectors[i].line_mux,
		1087	bios_connectors[i].devices,
		1088	bios_connectors[i].
		1089	connector_type,
		1090	&bios_connectors[i].ddc_bus,
1963	serge	1091	0,
1321	serge	1092	connector_object_id,
1963	serge	1093	&bios_connectors[i].hpd,
		1094	&router);
1268	serge	1095	}
1123	serge	1096	}
1117	serge	1097
1123	serge	1098	radeon_link_encoder_connector(dev);
1128	serge	1099
1963	serge	1100	kfree(bios_connectors);
1117	serge	1101	return true;
		1102	}
		1103
		1104	union firmware_info {
		1105	ATOM_FIRMWARE_INFO info;
		1106	ATOM_FIRMWARE_INFO_V1_2 info_12;
		1107	ATOM_FIRMWARE_INFO_V1_3 info_13;
		1108	ATOM_FIRMWARE_INFO_V1_4 info_14;
1430	serge	1109	ATOM_FIRMWARE_INFO_V2_1 info_21;
1963	serge	1110	ATOM_FIRMWARE_INFO_V2_2 info_22;
1117	serge	1111	};
		1112
		1113	bool radeon_atom_get_clock_info(struct drm_device *dev)
		1114	{
		1115	struct radeon_device *rdev = dev->dev_private;
		1116	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1117	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		1118	union firmware_info *firmware_info;
		1119	uint8_t frev, crev;
		1120	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		1121	struct radeon_pll *p2pll = &rdev->clock.p2pll;
1430	serge	1122	struct radeon_pll *dcpll = &rdev->clock.dcpll;
1117	serge	1123	struct radeon_pll *spll = &rdev->clock.spll;
		1124	struct radeon_pll *mpll = &rdev->clock.mpll;
		1125	uint16_t data_offset;
		1126
1963	serge	1127	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1128	&frev, &crev, &data_offset)) {
1117	serge	1129	firmware_info =
		1130	(union firmware_info *)(mode_info->atom_context->bios +
		1131	data_offset);
		1132	/* pixel clocks */
		1133	p1pll->reference_freq =
		1134	le16_to_cpu(firmware_info->info.usReferenceClock);
		1135	p1pll->reference_div = 0;
		1136
1268	serge	1137	if (crev < 2)
1117	serge	1138	p1pll->pll_out_min =
		1139	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	1140	else
		1141	p1pll->pll_out_min =
		1142	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	1143	p1pll->pll_out_max =
		1144	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		1145
1963	serge	1146	if (crev >= 4) {
		1147	p1pll->lcd_pll_out_min =
		1148	le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
		1149	if (p1pll->lcd_pll_out_min == 0)
		1150	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1151	p1pll->lcd_pll_out_max =
		1152	le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
		1153	if (p1pll->lcd_pll_out_max == 0)
		1154	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1155	} else {
		1156	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1157	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1158	}
		1159
1117	serge	1160	if (p1pll->pll_out_min == 0) {
		1161	if (ASIC_IS_AVIVO(rdev))
		1162	p1pll->pll_out_min = 64800;
		1163	else
		1164	p1pll->pll_out_min = 20000;
		1165	}
		1166
		1167	p1pll->pll_in_min =
		1168	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		1169	p1pll->pll_in_max =
		1170	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		1171
		1172	p2pll = p1pll;
		1173
		1174	/* system clock */
1963	serge	1175	if (ASIC_IS_DCE4(rdev))
		1176	spll->reference_freq =
		1177	le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
		1178	else
1117	serge	1179	spll->reference_freq =
		1180	le16_to_cpu(firmware_info->info.usReferenceClock);
		1181	spll->reference_div = 0;
		1182
		1183	spll->pll_out_min =
		1184	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		1185	spll->pll_out_max =
		1186	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		1187
		1188	/* ??? */
		1189	if (spll->pll_out_min == 0) {
		1190	if (ASIC_IS_AVIVO(rdev))
		1191	spll->pll_out_min = 64800;
		1192	else
		1193	spll->pll_out_min = 20000;
		1194	}
		1195
		1196	spll->pll_in_min =
		1197	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		1198	spll->pll_in_max =
		1199	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		1200
		1201	/* memory clock */
1963	serge	1202	if (ASIC_IS_DCE4(rdev))
		1203	mpll->reference_freq =
		1204	le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
		1205	else
1117	serge	1206	mpll->reference_freq =
		1207	le16_to_cpu(firmware_info->info.usReferenceClock);
		1208	mpll->reference_div = 0;
		1209
		1210	mpll->pll_out_min =
		1211	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		1212	mpll->pll_out_max =
		1213	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		1214
		1215	/* ??? */
		1216	if (mpll->pll_out_min == 0) {
		1217	if (ASIC_IS_AVIVO(rdev))
		1218	mpll->pll_out_min = 64800;
		1219	else
		1220	mpll->pll_out_min = 20000;
		1221	}
		1222
		1223	mpll->pll_in_min =
		1224	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		1225	mpll->pll_in_max =
		1226	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		1227
		1228	rdev->clock.default_sclk =
		1229	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		1230	rdev->clock.default_mclk =
		1231	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		1232
1430	serge	1233	if (ASIC_IS_DCE4(rdev)) {
		1234	rdev->clock.default_dispclk =
		1235	le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1963	serge	1236	if (rdev->clock.default_dispclk == 0) {
5078	serge	1237	if (ASIC_IS_DCE6(rdev))
		1238	rdev->clock.default_dispclk = 60000; /* 600 Mhz */
		1239	else if (ASIC_IS_DCE5(rdev))
1963	serge	1240	rdev->clock.default_dispclk = 54000; /* 540 Mhz */
		1241	else
1430	serge	1242	rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1963	serge	1243	}
5078	serge	1244	/* set a reasonable default for DP */
		1245	if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
		1246	DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
		1247	rdev->clock.default_dispclk / 100);
		1248	rdev->clock.default_dispclk = 60000;
		1249	}
1430	serge	1250	rdev->clock.dp_extclk =
		1251	le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
5078	serge	1252	rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1430	serge	1253	}
		1254	dcpll = p1pll;
		1255
1963	serge	1256	rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
		1257	if (rdev->clock.max_pixel_clock == 0)
		1258	rdev->clock.max_pixel_clock = 40000;
		1259
2997	Serge	1260	/* not technically a clock, but... */
		1261	rdev->mode_info.firmware_flags =
		1262	le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
		1263
1117	serge	1264	return true;
		1265	}
1430	serge	1266
1117	serge	1267	return false;
		1268	}
		1269
1404	serge	1270	union igp_info {
		1271	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		1272	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2997	Serge	1273	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
		1274	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
5078	serge	1275	struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1404	serge	1276	};
		1277
		1278	bool radeon_atombios_sideport_present(struct radeon_device *rdev)
		1279	{
		1280	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1281	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1282	union igp_info *igp_info;
		1283	u8 frev, crev;
		1284	u16 data_offset;
		1285
1963	serge	1286	/* sideport is AMD only */
		1287	if (rdev->family == CHIP_RS600)
		1288	return false;
1404	serge	1289
1963	serge	1290	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1291	&frev, &crev, &data_offset)) {
1404	serge	1292	igp_info = (union igp_info *)(mode_info->atom_context->bios +
		1293	data_offset);
		1294	switch (crev) {
		1295	case 1:
1963	serge	1296	if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1404	serge	1297	return true;
		1298	break;
		1299	case 2:
1963	serge	1300	if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1404	serge	1301	return true;
		1302	break;
		1303	default:
		1304	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		1305	break;
		1306	}
		1307	}
		1308	return false;
		1309	}
		1310
1179	serge	1311	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		1312	struct radeon_encoder_int_tmds *tmds)
1117	serge	1313	{
		1314	struct drm_device *dev = encoder->base.dev;
		1315	struct radeon_device *rdev = dev->dev_private;
		1316	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1317	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		1318	uint16_t data_offset;
		1319	struct _ATOM_TMDS_INFO *tmds_info;
		1320	uint8_t frev, crev;
		1321	uint16_t maxfreq;
		1322	int i;
		1323
1963	serge	1324	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1325	&frev, &crev, &data_offset)) {
1117	serge	1326	tmds_info =
		1327	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		1328	data_offset);
		1329
		1330	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		1331	for (i = 0; i < 4; i++) {
		1332	tmds->tmds_pll[i].freq =
		1333	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		1334	tmds->tmds_pll[i].value =
		1335	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		1336	tmds->tmds_pll[i].value \|=
		1337	(tmds_info->asMiscInfo[i].
		1338	ucPLL_VCO_Gain & 0x3f) << 6;
		1339	tmds->tmds_pll[i].value \|=
		1340	(tmds_info->asMiscInfo[i].
		1341	ucPLL_DutyCycle & 0xf) << 12;
		1342	tmds->tmds_pll[i].value \|=
		1343	(tmds_info->asMiscInfo[i].
		1344	ucPLL_VoltageSwing & 0xf) << 16;
		1345
1963	serge	1346	DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1117	serge	1347	tmds->tmds_pll[i].freq,
		1348	tmds->tmds_pll[i].value);
		1349
		1350	if (maxfreq == tmds->tmds_pll[i].freq) {
		1351	tmds->tmds_pll[i].freq = 0xffffffff;
		1352	break;
		1353	}
		1354	}
1179	serge	1355	return true;
1117	serge	1356	}
1179	serge	1357	return false;
1117	serge	1358	}
		1359
1963	serge	1360	bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
		1361	struct radeon_atom_ss *ss,
1268	serge	1362	int id)
		1363	{
		1364	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1365	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1963	serge	1366	uint16_t data_offset, size;
1268	serge	1367	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
5078	serge	1368	struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1268	serge	1369	uint8_t frev, crev;
1963	serge	1370	int i, num_indices;
1268	serge	1371
1963	serge	1372	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1373	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1374	&frev, &crev, &data_offset)) {
1268	serge	1375	ss_info =
		1376	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1377
1963	serge	1378	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1379	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
5078	serge	1380	ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
		1381	((u8 *)&ss_info->asSS_Info[0]);
1963	serge	1382	for (i = 0; i < num_indices; i++) {
5078	serge	1383	if (ss_assign->ucSS_Id == id) {
1321	serge	1384	ss->percentage =
5078	serge	1385	le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
		1386	ss->type = ss_assign->ucSpreadSpectrumType;
		1387	ss->step = ss_assign->ucSS_Step;
		1388	ss->delay = ss_assign->ucSS_Delay;
		1389	ss->range = ss_assign->ucSS_Range;
		1390	ss->refdiv = ss_assign->ucRecommendedRef_Div;
1963	serge	1391	return true;
		1392	}
5078	serge	1393	ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
		1394	((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1963	serge	1395	}
1268	serge	1396	}
1963	serge	1397	return false;
		1398	}
		1399
		1400	static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
		1401	struct radeon_atom_ss *ss,
		1402	int id)
		1403	{
		1404	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1405	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1406	u16 data_offset, size;
2997	Serge	1407	union igp_info *igp_info;
1963	serge	1408	u8 frev, crev;
		1409	u16 percentage = 0, rate = 0;
		1410
		1411	/* get any igp specific overrides */
		1412	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1413	&frev, &crev, &data_offset)) {
2997	Serge	1414	igp_info = (union igp_info *)
1963	serge	1415	(mode_info->atom_context->bios + data_offset);
2997	Serge	1416	switch (crev) {
		1417	case 6:
		1418	switch (id) {
		1419	case ASIC_INTERNAL_SS_ON_TMDS:
		1420	percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
		1421	rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
		1422	break;
		1423	case ASIC_INTERNAL_SS_ON_HDMI:
		1424	percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
		1425	rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
		1426	break;
		1427	case ASIC_INTERNAL_SS_ON_LVDS:
		1428	percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
		1429	rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
		1430	break;
		1431	}
		1432	break;
		1433	case 7:
1963	serge	1434	switch (id) {
		1435	case ASIC_INTERNAL_SS_ON_TMDS:
2997	Serge	1436	percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
		1437	rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1963	serge	1438	break;
		1439	case ASIC_INTERNAL_SS_ON_HDMI:
2997	Serge	1440	percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
		1441	rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1963	serge	1442	break;
		1443	case ASIC_INTERNAL_SS_ON_LVDS:
2997	Serge	1444	percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
		1445	rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
		1446	break;
		1447	}
1963	serge	1448	break;
5078	serge	1449	case 8:
		1450	switch (id) {
		1451	case ASIC_INTERNAL_SS_ON_TMDS:
		1452	percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
		1453	rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
		1454	break;
		1455	case ASIC_INTERNAL_SS_ON_HDMI:
		1456	percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
		1457	rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
		1458	break;
		1459	case ASIC_INTERNAL_SS_ON_LVDS:
		1460	percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
		1461	rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
		1462	break;
		1463	}
		1464	break;
2997	Serge	1465	default:
		1466	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		1467	break;
1321	serge	1468	}
1963	serge	1469	if (percentage)
		1470	ss->percentage = percentage;
		1471	if (rate)
		1472	ss->rate = rate;
1321	serge	1473	}
1268	serge	1474	}
		1475
1963	serge	1476	union asic_ss_info {
		1477	struct _ATOM_ASIC_INTERNAL_SS_INFO info;
		1478	struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
		1479	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
		1480	};
		1481
5078	serge	1482	union asic_ss_assignment {
		1483	struct _ATOM_ASIC_SS_ASSIGNMENT v1;
		1484	struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
		1485	struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
		1486	};
		1487
1963	serge	1488	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
		1489	struct radeon_atom_ss *ss,
		1490	int id, u32 clock)
1430	serge	1491	{
1963	serge	1492	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1493	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
		1494	uint16_t data_offset, size;
		1495	union asic_ss_info *ss_info;
5078	serge	1496	union asic_ss_assignment *ss_assign;
1963	serge	1497	uint8_t frev, crev;
		1498	int i, num_indices;
1430	serge	1499
5078	serge	1500	if (id == ASIC_INTERNAL_MEMORY_SS) {
		1501	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
		1502	return false;
		1503	}
		1504	if (id == ASIC_INTERNAL_ENGINE_SS) {
		1505	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
		1506	return false;
		1507	}
		1508
1963	serge	1509	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1510	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1511	&frev, &crev, &data_offset)) {
		1512
		1513	ss_info =
		1514	(union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
		1515
		1516	switch (frev) {
		1517	case 1:
		1518	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1519	sizeof(ATOM_ASIC_SS_ASSIGNMENT);
		1520
5078	serge	1521	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info.asSpreadSpectrum[0]);
1963	serge	1522	for (i = 0; i < num_indices; i++) {
5078	serge	1523	if ((ss_assign->v1.ucClockIndication == id) &&
		1524	(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1963	serge	1525	ss->percentage =
5078	serge	1526	le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
		1527	ss->type = ss_assign->v1.ucSpreadSpectrumMode;
		1528	ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
		1529	ss->percentage_divider = 100;
1963	serge	1530	return true;
		1531	}
5078	serge	1532	ss_assign = (union asic_ss_assignment *)
		1533	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1963	serge	1534	}
		1535	break;
		1536	case 2:
		1537	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1538	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
5078	serge	1539	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_2.asSpreadSpectrum[0]);
1963	serge	1540	for (i = 0; i < num_indices; i++) {
5078	serge	1541	if ((ss_assign->v2.ucClockIndication == id) &&
		1542	(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1963	serge	1543	ss->percentage =
5078	serge	1544	le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
		1545	ss->type = ss_assign->v2.ucSpreadSpectrumMode;
		1546	ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
		1547	ss->percentage_divider = 100;
		1548	if ((crev == 2) &&
		1549	((id == ASIC_INTERNAL_ENGINE_SS) \|\|
		1550	(id == ASIC_INTERNAL_MEMORY_SS)))
		1551	ss->rate /= 100;
1963	serge	1552	return true;
		1553	}
5078	serge	1554	ss_assign = (union asic_ss_assignment *)
		1555	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1430	serge	1556	}
1963	serge	1557	break;
		1558	case 3:
		1559	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1560	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
5078	serge	1561	ss_assign = (union asic_ss_assignment )((u8 )&ss_info->info_3.asSpreadSpectrum[0]);
1963	serge	1562	for (i = 0; i < num_indices; i++) {
5078	serge	1563	if ((ss_assign->v3.ucClockIndication == id) &&
		1564	(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1963	serge	1565	ss->percentage =
5078	serge	1566	le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
		1567	ss->type = ss_assign->v3.ucSpreadSpectrumMode;
		1568	ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
		1569	if (ss_assign->v3.ucSpreadSpectrumMode &
		1570	SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
		1571	ss->percentage_divider = 1000;
		1572	else
		1573	ss->percentage_divider = 100;
		1574	if ((id == ASIC_INTERNAL_ENGINE_SS) \|\|
		1575	(id == ASIC_INTERNAL_MEMORY_SS))
		1576	ss->rate /= 100;
1963	serge	1577	if (rdev->flags & RADEON_IS_IGP)
		1578	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
		1579	return true;
		1580	}
5078	serge	1581	ss_assign = (union asic_ss_assignment *)
		1582	((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1963	serge	1583	}
		1584	break;
		1585	default:
		1586	DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
		1587	break;
		1588	}
1430	serge	1589
		1590	}
1963	serge	1591	return false;
1430	serge	1592	}
		1593
1117	serge	1594	union lvds_info {
		1595	struct _ATOM_LVDS_INFO info;
		1596	struct _ATOM_LVDS_INFO_V12 info_12;
		1597	};
		1598
		1599	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1600	radeon_encoder
		1601	*encoder)
		1602	{
		1603	struct drm_device *dev = encoder->base.dev;
		1604	struct radeon_device *rdev = dev->dev_private;
		1605	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1606	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1607	uint16_t data_offset, misc;
1117	serge	1608	union lvds_info *lvds_info;
		1609	uint8_t frev, crev;
		1610	struct radeon_encoder_atom_dig *lvds = NULL;
1963	serge	1611	int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1117	serge	1612
1963	serge	1613	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1614	&frev, &crev, &data_offset)) {
1117	serge	1615	lvds_info =
		1616	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1617	lvds =
		1618	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1619
		1620	if (!lvds)
		1621	return NULL;
		1622
1268	serge	1623	lvds->native_mode.clock =
1117	serge	1624	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1625	lvds->native_mode.hdisplay =
1117	serge	1626	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1627	lvds->native_mode.vdisplay =
1117	serge	1628	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1629	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1630	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1631	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1632	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1633	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1634	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1635	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1636	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1637	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1963	serge	1638	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1268	serge	1639	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1640	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1641	lvds->panel_pwr_delay =
		1642	le16_to_cpu(lvds_info->info.usOffDelayInMs);
1963	serge	1643	lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1644
		1645	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1646	if (misc & ATOM_VSYNC_POLARITY)
		1647	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1648	if (misc & ATOM_HSYNC_POLARITY)
		1649	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1650	if (misc & ATOM_COMPOSITESYNC)
		1651	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1652	if (misc & ATOM_INTERLACE)
		1653	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1654	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1655	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1656
1963	serge	1657	lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
		1658	lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
		1659
1268	serge	1660	/* set crtc values */
		1661	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1662
1963	serge	1663	lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1268	serge	1664
1963	serge	1665	encoder->native_mode = lvds->native_mode;
		1666
		1667	if (encoder_enum == 2)
		1668	lvds->linkb = true;
		1669	else
		1670	lvds->linkb = false;
		1671
		1672	/* parse the lcd record table */
		1673	if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
		1674	ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
		1675	ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
		1676	bool bad_record = false;
		1677	u8 *record;
		1678
		1679	if ((frev == 1) && (crev < 2))
		1680	/* absolute */
		1681	record = (u8 *)(mode_info->atom_context->bios +
		1682	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1430	serge	1683	else
1963	serge	1684	/* relative */
		1685	record = (u8 *)(mode_info->atom_context->bios +
		1686	data_offset +
		1687	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
		1688	while (*record != ATOM_RECORD_END_TYPE) {
		1689	switch (*record) {
		1690	case LCD_MODE_PATCH_RECORD_MODE_TYPE:
		1691	record += sizeof(ATOM_PATCH_RECORD_MODE);
		1692	break;
		1693	case LCD_RTS_RECORD_TYPE:
		1694	record += sizeof(ATOM_LCD_RTS_RECORD);
		1695	break;
		1696	case LCD_CAP_RECORD_TYPE:
		1697	record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
		1698	break;
		1699	case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
		1700	fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
		1701	if (fake_edid_record->ucFakeEDIDLength) {
		1702	struct edid *edid;
		1703	int edid_size =
		1704	max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
		1705	edid = kmalloc(edid_size, GFP_KERNEL);
		1706	if (edid) {
		1707	memcpy((u8 )edid, (u8 )&fake_edid_record->ucFakeEDIDString[0],
		1708	fake_edid_record->ucFakeEDIDLength);
		1709
		1710	if (drm_edid_is_valid(edid)) {
		1711	rdev->mode_info.bios_hardcoded_edid = edid;
		1712	rdev->mode_info.bios_hardcoded_edid_size = edid_size;
		1713	} else
		1714	kfree(edid);
		1715	}
		1716	}
5078	serge	1717	record += fake_edid_record->ucFakeEDIDLength ?
		1718	fake_edid_record->ucFakeEDIDLength + 2 :
		1719	sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1963	serge	1720	break;
		1721	case LCD_PANEL_RESOLUTION_RECORD_TYPE:
		1722	panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
		1723	lvds->native_mode.width_mm = panel_res_record->usHSize;
		1724	lvds->native_mode.height_mm = panel_res_record->usVSize;
		1725	record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
		1726	break;
		1727	default:
		1728	DRM_ERROR("Bad LCD record %d\n", *record);
		1729	bad_record = true;
		1730	break;
		1731	}
		1732	if (bad_record)
		1733	break;
		1734	}
1430	serge	1735	}
1117	serge	1736	}
		1737	return lvds;
		1738	}
		1739
		1740	struct radeon_encoder_primary_dac *
		1741	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1742	{
		1743	struct drm_device *dev = encoder->base.dev;
		1744	struct radeon_device *rdev = dev->dev_private;
		1745	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1746	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1747	uint16_t data_offset;
		1748	struct _COMPASSIONATE_DATA *dac_info;
		1749	uint8_t frev, crev;
		1750	uint8_t bg, dac;
		1751	struct radeon_encoder_primary_dac *p_dac = NULL;
		1752
1963	serge	1753	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1754	&frev, &crev, &data_offset)) {
		1755	dac_info = (struct _COMPASSIONATE_DATA *)
		1756	(mode_info->atom_context->bios + data_offset);
1117	serge	1757
		1758	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1759
		1760	if (!p_dac)
		1761	return NULL;
		1762
		1763	bg = dac_info->ucDAC1_BG_Adjustment;
		1764	dac = dac_info->ucDAC1_DAC_Adjustment;
		1765	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1766
		1767	}
		1768	return p_dac;
		1769	}
		1770
1179	serge	1771	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1772	struct drm_display_mode *mode)
1179	serge	1773	{
		1774	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1775	ATOM_ANALOG_TV_INFO *tv_info;
		1776	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1777	ATOM_DTD_FORMAT *dtd_timings;
		1778	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1779	u8 frev, crev;
1268	serge	1780	u16 data_offset, misc;
1179	serge	1781
1963	serge	1782	if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
		1783	&frev, &crev, &data_offset))
		1784	return false;
1179	serge	1785
		1786	switch (crev) {
		1787	case 1:
		1788	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1963	serge	1789	if (index >= MAX_SUPPORTED_TV_TIMING)
1179	serge	1790	return false;
		1791
1268	serge	1792	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1793	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1794	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1795	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1796	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1797
1268	serge	1798	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1799	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1800	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1801	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1802	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1803
1268	serge	1804	mode->flags = 0;
		1805	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1806	if (misc & ATOM_VSYNC_POLARITY)
		1807	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1808	if (misc & ATOM_HSYNC_POLARITY)
		1809	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1810	if (misc & ATOM_COMPOSITESYNC)
		1811	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1812	if (misc & ATOM_INTERLACE)
		1813	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1814	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1815	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1816
5078	serge	1817	mode->crtc_clock = mode->clock =
		1818	le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1819
		1820	if (index == 1) {
		1821	/* PAL timings appear to have wrong values for totals */
1268	serge	1822	mode->crtc_htotal -= 1;
		1823	mode->crtc_vtotal -= 1;
1179	serge	1824	}
		1825	break;
		1826	case 2:
		1827	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1963	serge	1828	if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1179	serge	1829	return false;
		1830
		1831	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1832	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1833	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1834	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1835	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1836	le16_to_cpu(dtd_timings->usHSyncOffset);
		1837	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1838	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1839
1268	serge	1840	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1841	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1842	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1843	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1844	le16_to_cpu(dtd_timings->usVSyncOffset);
		1845	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1846	le16_to_cpu(dtd_timings->usVSyncWidth);
		1847
		1848	mode->flags = 0;
		1849	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1850	if (misc & ATOM_VSYNC_POLARITY)
		1851	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1852	if (misc & ATOM_HSYNC_POLARITY)
		1853	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1854	if (misc & ATOM_COMPOSITESYNC)
		1855	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1856	if (misc & ATOM_INTERLACE)
		1857	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1858	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1859	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1860
5078	serge	1861	mode->crtc_clock = mode->clock =
		1862	le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1863	break;
		1864	}
		1865	return true;
		1866	}
		1867
1404	serge	1868	enum radeon_tv_std
		1869	radeon_atombios_get_tv_info(struct radeon_device *rdev)
		1870	{
		1871	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1872	int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1873	uint16_t data_offset;
		1874	uint8_t frev, crev;
		1875	struct _ATOM_ANALOG_TV_INFO *tv_info;
		1876	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1877
1963	serge	1878	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1879	&frev, &crev, &data_offset)) {
1404	serge	1880
1963	serge	1881	tv_info = (struct _ATOM_ANALOG_TV_INFO *)
		1882	(mode_info->atom_context->bios + data_offset);
1404	serge	1883
		1884	switch (tv_info->ucTV_BootUpDefaultStandard) {
		1885	case ATOM_TV_NTSC:
		1886	tv_std = TV_STD_NTSC;
1963	serge	1887	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1404	serge	1888	break;
		1889	case ATOM_TV_NTSCJ:
		1890	tv_std = TV_STD_NTSC_J;
1963	serge	1891	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1404	serge	1892	break;
		1893	case ATOM_TV_PAL:
		1894	tv_std = TV_STD_PAL;
1963	serge	1895	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1404	serge	1896	break;
		1897	case ATOM_TV_PALM:
		1898	tv_std = TV_STD_PAL_M;
1963	serge	1899	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1404	serge	1900	break;
		1901	case ATOM_TV_PALN:
		1902	tv_std = TV_STD_PAL_N;
1963	serge	1903	DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1404	serge	1904	break;
		1905	case ATOM_TV_PALCN:
		1906	tv_std = TV_STD_PAL_CN;
1963	serge	1907	DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1404	serge	1908	break;
		1909	case ATOM_TV_PAL60:
		1910	tv_std = TV_STD_PAL_60;
1963	serge	1911	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1404	serge	1912	break;
		1913	case ATOM_TV_SECAM:
		1914	tv_std = TV_STD_SECAM;
1963	serge	1915	DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1404	serge	1916	break;
		1917	default:
		1918	tv_std = TV_STD_NTSC;
1963	serge	1919	DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1404	serge	1920	break;
		1921	}
1963	serge	1922	}
1404	serge	1923	return tv_std;
		1924	}
		1925
1117	serge	1926	struct radeon_encoder_tv_dac *
		1927	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1928	{
		1929	struct drm_device *dev = encoder->base.dev;
		1930	struct radeon_device *rdev = dev->dev_private;
		1931	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1932	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1933	uint16_t data_offset;
		1934	struct _COMPASSIONATE_DATA *dac_info;
		1935	uint8_t frev, crev;
		1936	uint8_t bg, dac;
		1937	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1938
1963	serge	1939	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1940	&frev, &crev, &data_offset)) {
1117	serge	1941
1963	serge	1942	dac_info = (struct _COMPASSIONATE_DATA *)
		1943	(mode_info->atom_context->bios + data_offset);
1117	serge	1944
		1945	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1946
		1947	if (!tv_dac)
		1948	return NULL;
		1949
		1950	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1951	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1952	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1953
		1954	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1955	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1956	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1957
		1958	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1959	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1960	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1961
1404	serge	1962	tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1117	serge	1963	}
		1964	return tv_dac;
		1965	}
		1966
1963	serge	1967	static const char *thermal_controller_names[] = {
		1968	"NONE",
		1969	"lm63",
		1970	"adm1032",
		1971	"adm1030",
		1972	"max6649",
5078	serge	1973	"lm63", /* lm64 */
1963	serge	1974	"f75375",
		1975	"asc7xxx",
		1976	};
		1977
		1978	static const char *pp_lib_thermal_controller_names[] = {
		1979	"NONE",
		1980	"lm63",
		1981	"adm1032",
		1982	"adm1030",
		1983	"max6649",
5078	serge	1984	"lm63", /* lm64 */
1963	serge	1985	"f75375",
		1986	"RV6xx",
		1987	"RV770",
		1988	"adt7473",
		1989	"NONE",
		1990	"External GPIO",
		1991	"Evergreen",
		1992	"emc2103",
		1993	"Sumo",
		1994	"Northern Islands",
2997	Serge	1995	"Southern Islands",
		1996	"lm96163",
5078	serge	1997	"Sea Islands",
1963	serge	1998	};
		1999
1430	serge	2000	union power_info {
		2001	struct _ATOM_POWERPLAY_INFO info;
		2002	struct _ATOM_POWERPLAY_INFO_V2 info_2;
		2003	struct _ATOM_POWERPLAY_INFO_V3 info_3;
1963	serge	2004	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
		2005	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
		2006	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1430	serge	2007	};
		2008
1963	serge	2009	union pplib_clock_info {
		2010	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
		2011	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
		2012	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
		2013	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2997	Serge	2014	struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5078	serge	2015	struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
1963	serge	2016	};
		2017
		2018	union pplib_power_state {
		2019	struct _ATOM_PPLIB_STATE v1;
		2020	struct _ATOM_PPLIB_STATE_V2 v2;
		2021	};
		2022
		2023	static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
		2024	int state_index,
		2025	u32 misc, u32 misc2)
1117	serge	2026	{
1963	serge	2027	rdev->pm.power_state[state_index].misc = misc;
		2028	rdev->pm.power_state[state_index].misc2 = misc2;
		2029	/* order matters! */
		2030	if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
		2031	rdev->pm.power_state[state_index].type =
		2032	POWER_STATE_TYPE_POWERSAVE;
		2033	if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
		2034	rdev->pm.power_state[state_index].type =
		2035	POWER_STATE_TYPE_BATTERY;
		2036	if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
		2037	rdev->pm.power_state[state_index].type =
		2038	POWER_STATE_TYPE_BATTERY;
		2039	if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
		2040	rdev->pm.power_state[state_index].type =
		2041	POWER_STATE_TYPE_BALANCED;
		2042	if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
		2043	rdev->pm.power_state[state_index].type =
		2044	POWER_STATE_TYPE_PERFORMANCE;
		2045	rdev->pm.power_state[state_index].flags &=
		2046	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2047	}
		2048	if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
		2049	rdev->pm.power_state[state_index].type =
		2050	POWER_STATE_TYPE_BALANCED;
		2051	if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
		2052	rdev->pm.power_state[state_index].type =
		2053	POWER_STATE_TYPE_DEFAULT;
		2054	rdev->pm.default_power_state_index = state_index;
		2055	rdev->pm.power_state[state_index].default_clock_mode =
		2056	&rdev->pm.power_state[state_index].clock_info[0];
		2057	} else if (state_index == 0) {
		2058	rdev->pm.power_state[state_index].clock_info[0].flags \|=
		2059	RADEON_PM_MODE_NO_DISPLAY;
		2060	}
		2061	}
		2062
		2063	static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
		2064	{
1430	serge	2065	struct radeon_mode_info *mode_info = &rdev->mode_info;
1963	serge	2066	u32 misc, misc2 = 0;
		2067	int num_modes = 0, i;
		2068	int state_index = 0;
		2069	struct radeon_i2c_bus_rec i2c_bus;
		2070	union power_info *power_info;
1430	serge	2071	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2072	u16 data_offset;
		2073	u8 frev, crev;
1117	serge	2074
1963	serge	2075	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2076	&frev, &crev, &data_offset))
		2077	return state_index;
1430	serge	2078	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2079
1963	serge	2080	/* add the i2c bus for thermal/fan chip */
2997	Serge	2081	if ((power_info->info.ucOverdriveThermalController > 0) &&
		2082	(power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
1963	serge	2083	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		2084	thermal_controller_names[power_info->info.ucOverdriveThermalController],
		2085	power_info->info.ucOverdriveControllerAddress >> 1);
		2086	i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
		2087	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2088	if (rdev->pm.i2c_bus) {
		2089	struct i2c_board_info info = { };
		2090	const char *name = thermal_controller_names[power_info->info.
		2091	ucOverdriveThermalController];
		2092	info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
		2093	strlcpy(info.type, name, sizeof(info.type));
		2094	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		2095	}
		2096	}
1430	serge	2097	num_modes = power_info->info.ucNumOfPowerModeEntries;
		2098	if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
		2099	num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
3764	Serge	2100	if (num_modes == 0)
		2101	return state_index;
1963	serge	2102	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
		2103	if (!rdev->pm.power_state)
		2104	return state_index;
		2105	/* last mode is usually default, array is low to high */
1430	serge	2106	for (i = 0; i < num_modes; i++) {
2997	Serge	2107	rdev->pm.power_state[state_index].clock_info =
		2108	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2109	if (!rdev->pm.power_state[state_index].clock_info)
		2110	return state_index;
		2111	rdev->pm.power_state[state_index].num_clock_modes = 1;
1430	serge	2112	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2113	switch (frev) {
		2114	case 1:
		2115	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2116	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
		2117	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2118	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
		2119	/* skip invalid modes */
		2120	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2121	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2122	continue;
1963	serge	2123	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2124	power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
		2125	misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1963	serge	2126	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2127	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2128	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2129	VOLTAGE_GPIO;
		2130	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2131	radeon_lookup_gpio(rdev,
		2132	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
		2133	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2134	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2135	true;
		2136	else
		2137	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2138	false;
		2139	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2140	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2141	VOLTAGE_VDDC;
		2142	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2143	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
		2144	}
1963	serge	2145	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2146	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1430	serge	2147	state_index++;
		2148	break;
		2149	case 2:
		2150	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2151	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
		2152	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2153	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
		2154	/* skip invalid modes */
		2155	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2156	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2157	continue;
1963	serge	2158	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2159	power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
		2160	misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
		2161	misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2162	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2163	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2164	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2165	VOLTAGE_GPIO;
		2166	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2167	radeon_lookup_gpio(rdev,
		2168	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
		2169	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2170	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2171	true;
		2172	else
		2173	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2174	false;
		2175	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2176	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2177	VOLTAGE_VDDC;
		2178	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2179	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
		2180	}
1963	serge	2181	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2182	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2183	state_index++;
		2184	break;
		2185	case 3:
		2186	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2187	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
		2188	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2189	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
		2190	/* skip invalid modes */
		2191	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2192	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2193	continue;
1963	serge	2194	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2195	power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
		2196	misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
		2197	misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2198	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2199	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2200	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2201	VOLTAGE_GPIO;
		2202	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2203	radeon_lookup_gpio(rdev,
		2204	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
		2205	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2206	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2207	true;
		2208	else
		2209	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2210	false;
		2211	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2212	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2213	VOLTAGE_VDDC;
		2214	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2215	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
		2216	if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
		2217	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
		2218	true;
		2219	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
		2220	power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
		2221	}
		2222	}
1963	serge	2223	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2224	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2225	state_index++;
		2226	break;
		2227	}
		2228	}
1963	serge	2229	/* last mode is usually default */
		2230	if (rdev->pm.default_power_state_index == -1) {
		2231	rdev->pm.power_state[state_index - 1].type =
		2232	POWER_STATE_TYPE_DEFAULT;
		2233	rdev->pm.default_power_state_index = state_index - 1;
		2234	rdev->pm.power_state[state_index - 1].default_clock_mode =
		2235	&rdev->pm.power_state[state_index - 1].clock_info[0];
		2236	rdev->pm.power_state[state_index].flags &=
		2237	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2238	rdev->pm.power_state[state_index].misc = 0;
		2239	rdev->pm.power_state[state_index].misc2 = 0;
		2240	}
		2241	return state_index;
		2242	}
		2243
		2244	static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
		2245	ATOM_PPLIB_THERMALCONTROLLER *controller)
		2246	{
		2247	struct radeon_i2c_bus_rec i2c_bus;
		2248
		2249	/* add the i2c bus for thermal/fan chip */
		2250	if (controller->ucType > 0) {
		2251	if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
		2252	DRM_INFO("Internal thermal controller %s fan control\n",
		2253	(controller->ucFanParameters &
		2254	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2255	rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
		2256	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
		2257	DRM_INFO("Internal thermal controller %s fan control\n",
		2258	(controller->ucFanParameters &
		2259	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2260	rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
		2261	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
		2262	DRM_INFO("Internal thermal controller %s fan control\n",
		2263	(controller->ucFanParameters &
		2264	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2265	rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
		2266	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
		2267	DRM_INFO("Internal thermal controller %s fan control\n",
		2268	(controller->ucFanParameters &
		2269	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2270	rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
		2271	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
		2272	DRM_INFO("Internal thermal controller %s fan control\n",
		2273	(controller->ucFanParameters &
		2274	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2275	rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2997	Serge	2276	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
		2277	DRM_INFO("Internal thermal controller %s fan control\n",
		2278	(controller->ucFanParameters &
		2279	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2280	rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
5078	serge	2281	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
		2282	DRM_INFO("Internal thermal controller %s fan control\n",
		2283	(controller->ucFanParameters &
		2284	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2285	rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
		2286	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
		2287	DRM_INFO("Internal thermal controller %s fan control\n",
		2288	(controller->ucFanParameters &
		2289	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2290	rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
5128	serge	2291	} else if (controller->ucType ==
		2292	ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
		2293	DRM_INFO("External GPIO thermal controller %s fan control\n",
		2294	(controller->ucFanParameters &
		2295	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2296	rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
		2297	} else if (controller->ucType ==
		2298	ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
		2299	DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
		2300	(controller->ucFanParameters &
		2301	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2302	rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
		2303	} else if (controller->ucType ==
		2304	ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
		2305	DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
		2306	(controller->ucFanParameters &
		2307	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2308	rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2997	Serge	2309	} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
1963	serge	2310	DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
		2311	pp_lib_thermal_controller_names[controller->ucType],
		2312	controller->ucI2cAddress >> 1,
		2313	(controller->ucFanParameters &
		2314	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
5128	serge	2315	rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
1963	serge	2316	i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
		2317	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2318	if (rdev->pm.i2c_bus) {
		2319	struct i2c_board_info info = { };
		2320	const char *name = pp_lib_thermal_controller_names[controller->ucType];
		2321	info.addr = controller->ucI2cAddress >> 1;
		2322	strlcpy(info.type, name, sizeof(info.type));
		2323	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1430	serge	2324	}
2997	Serge	2325	} else {
		2326	DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
		2327	controller->ucType,
		2328	controller->ucI2cAddress >> 1,
		2329	(controller->ucFanParameters &
		2330	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1430	serge	2331	}
1963	serge	2332	}
		2333	}
		2334
5078	serge	2335	void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
		2336	u16 vddc, u16 vddci, u16 *mvdd)
1963	serge	2337	{
		2338	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2339	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		2340	u8 frev, crev;
		2341	u16 data_offset;
		2342	union firmware_info *firmware_info;
		2343
		2344	*vddc = 0;
		2345	*vddci = 0;
5078	serge	2346	*mvdd = 0;
1963	serge	2347
		2348	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2349	&frev, &crev, &data_offset)) {
		2350	firmware_info =
		2351	(union firmware_info *)(mode_info->atom_context->bios +
		2352	data_offset);
		2353	*vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
5078	serge	2354	if ((frev == 2) && (crev >= 2)) {
1963	serge	2355	*vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
5078	serge	2356	*mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
		2357	}
1963	serge	2358	}
		2359	}
		2360
		2361	static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
		2362	int state_index, int mode_index,
		2363	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
		2364	{
		2365	int j;
		2366	u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
		2367	u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
5078	serge	2368	u16 vddc, vddci, mvdd;
1963	serge	2369
5078	serge	2370	radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1963	serge	2371
		2372	rdev->pm.power_state[state_index].misc = misc;
		2373	rdev->pm.power_state[state_index].misc2 = misc2;
		2374	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2375	((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
		2376	ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
		2377	switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
		2378	case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
		2379	rdev->pm.power_state[state_index].type =
		2380	POWER_STATE_TYPE_BATTERY;
		2381	break;
		2382	case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
		2383	rdev->pm.power_state[state_index].type =
		2384	POWER_STATE_TYPE_BALANCED;
		2385	break;
		2386	case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
		2387	rdev->pm.power_state[state_index].type =
		2388	POWER_STATE_TYPE_PERFORMANCE;
		2389	break;
1963	serge	2390	case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
		2391	if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
		2392	rdev->pm.power_state[state_index].type =
		2393	POWER_STATE_TYPE_PERFORMANCE;
		2394	break;
1430	serge	2395	}
1963	serge	2396	rdev->pm.power_state[state_index].flags = 0;
		2397	if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
		2398	rdev->pm.power_state[state_index].flags \|=
		2399	RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2400	if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
		2401	rdev->pm.power_state[state_index].type =
		2402	POWER_STATE_TYPE_DEFAULT;
1963	serge	2403	rdev->pm.default_power_state_index = state_index;
1430	serge	2404	rdev->pm.power_state[state_index].default_clock_mode =
		2405	&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
3764	Serge	2406	if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
1963	serge	2407	/* NI chips post without MC ucode, so default clocks are strobe mode only */
		2408	rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
		2409	rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
		2410	rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
		2411	rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
		2412	} else {
5078	serge	2413	u16 max_vddci = 0;
		2414
		2415	if (ASIC_IS_DCE4(rdev))
		2416	radeon_atom_get_max_voltage(rdev,
		2417	SET_VOLTAGE_TYPE_ASIC_VDDCI,
		2418	&max_vddci);
		2419	/* patch the table values with the default sclk/mclk from firmware info */
1963	serge	2420	for (j = 0; j < mode_index; j++) {
		2421	rdev->pm.power_state[state_index].clock_info[j].mclk =
		2422	rdev->clock.default_mclk;
		2423	rdev->pm.power_state[state_index].clock_info[j].sclk =
		2424	rdev->clock.default_sclk;
		2425	if (vddc)
		2426	rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
		2427	vddc;
5078	serge	2428	if (max_vddci)
		2429	rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
		2430	max_vddci;
1963	serge	2431	}
1430	serge	2432	}
1963	serge	2433	}
		2434	}
		2435
		2436	static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
		2437	int state_index, int mode_index,
		2438	union pplib_clock_info *clock_info)
		2439	{
		2440	u32 sclk, mclk;
2997	Serge	2441	u16 vddc;
1963	serge	2442
		2443	if (rdev->flags & RADEON_IS_IGP) {
		2444	if (rdev->family >= CHIP_PALM) {
		2445	sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
		2446	sclk \|= clock_info->sumo.ucEngineClockHigh << 16;
		2447	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2448	} else {
		2449	sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
		2450	sclk \|= clock_info->rs780.ucLowEngineClockHigh << 16;
		2451	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2452	}
5078	serge	2453	} else if (rdev->family >= CHIP_BONAIRE) {
		2454	sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
		2455	sclk \|= clock_info->ci.ucEngineClockHigh << 16;
		2456	mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
		2457	mclk \|= clock_info->ci.ucMemoryClockHigh << 16;
		2458	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2459	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2460	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2461	VOLTAGE_NONE;
3764	Serge	2462	} else if (rdev->family >= CHIP_TAHITI) {
2997	Serge	2463	sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
		2464	sclk \|= clock_info->si.ucEngineClockHigh << 16;
		2465	mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
		2466	mclk \|= clock_info->si.ucMemoryClockHigh << 16;
		2467	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2468	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2469	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2470	VOLTAGE_SW;
		2471	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2472	le16_to_cpu(clock_info->si.usVDDC);
		2473	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
		2474	le16_to_cpu(clock_info->si.usVDDCI);
3764	Serge	2475	} else if (rdev->family >= CHIP_CEDAR) {
1963	serge	2476	sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
		2477	sclk \|= clock_info->evergreen.ucEngineClockHigh << 16;
		2478	mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
		2479	mclk \|= clock_info->evergreen.ucMemoryClockHigh << 16;
		2480	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2481	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2482	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2483	VOLTAGE_SW;
		2484	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2485	le16_to_cpu(clock_info->evergreen.usVDDC);
		2486	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
		2487	le16_to_cpu(clock_info->evergreen.usVDDCI);
		2488	} else {
		2489	sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
		2490	sclk \|= clock_info->r600.ucEngineClockHigh << 16;
		2491	mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
		2492	mclk \|= clock_info->r600.ucMemoryClockHigh << 16;
		2493	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2494	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2495	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2496	VOLTAGE_SW;
		2497	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2498	le16_to_cpu(clock_info->r600.usVDDC);
		2499	}
		2500
1986	serge	2501	/* patch up vddc if necessary */
2997	Serge	2502	switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
		2503	case ATOM_VIRTUAL_VOLTAGE_ID0:
		2504	case ATOM_VIRTUAL_VOLTAGE_ID1:
		2505	case ATOM_VIRTUAL_VOLTAGE_ID2:
		2506	case ATOM_VIRTUAL_VOLTAGE_ID3:
5078	serge	2507	case ATOM_VIRTUAL_VOLTAGE_ID4:
		2508	case ATOM_VIRTUAL_VOLTAGE_ID5:
		2509	case ATOM_VIRTUAL_VOLTAGE_ID6:
		2510	case ATOM_VIRTUAL_VOLTAGE_ID7:
2997	Serge	2511	if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
		2512	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
		2513	&vddc) == 0)
1986	serge	2514	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2997	Serge	2515	break;
		2516	default:
		2517	break;
1986	serge	2518	}
		2519
1963	serge	2520	if (rdev->flags & RADEON_IS_IGP) {
		2521	/* skip invalid modes */
		2522	if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
		2523	return false;
		2524	} else {
		2525	/* skip invalid modes */
		2526	if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) \|\|
		2527	(rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
		2528	return false;
		2529	}
		2530	return true;
		2531	}
		2532
		2533	static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
		2534	{
		2535	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2536	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2537	union pplib_power_state *power_state;
		2538	int i, j;
		2539	int state_index = 0, mode_index = 0;
		2540	union pplib_clock_info *clock_info;
		2541	bool valid;
		2542	union power_info *power_info;
		2543	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2544	u16 data_offset;
		2545	u8 frev, crev;
		2546
		2547	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2548	&frev, &crev, &data_offset))
		2549	return state_index;
		2550	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2551
		2552	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
3764	Serge	2553	if (power_info->pplib.ucNumStates == 0)
		2554	return state_index;
1963	serge	2555	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2556	power_info->pplib.ucNumStates, GFP_KERNEL);
		2557	if (!rdev->pm.power_state)
		2558	return state_index;
		2559	/* first mode is usually default, followed by low to high */
		2560	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
		2561	mode_index = 0;
		2562	power_state = (union pplib_power_state *)
		2563	(mode_info->atom_context->bios + data_offset +
		2564	le16_to_cpu(power_info->pplib.usStateArrayOffset) +
		2565	i * power_info->pplib.ucStateEntrySize);
		2566	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2567	(mode_info->atom_context->bios + data_offset +
		2568	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
		2569	(power_state->v1.ucNonClockStateIndex *
		2570	power_info->pplib.ucNonClockSize));
2997	Serge	2571	rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
		2572	((power_info->pplib.ucStateEntrySize - 1) ?
		2573	(power_info->pplib.ucStateEntrySize - 1) : 1),
		2574	GFP_KERNEL);
		2575	if (!rdev->pm.power_state[i].clock_info)
		2576	return state_index;
		2577	if (power_info->pplib.ucStateEntrySize - 1) {
1963	serge	2578	for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
		2579	clock_info = (union pplib_clock_info *)
		2580	(mode_info->atom_context->bios + data_offset +
		2581	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
		2582	(power_state->v1.ucClockStateIndices[j] *
		2583	power_info->pplib.ucClockInfoSize));
		2584	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2585	state_index, mode_index,
		2586	clock_info);
		2587	if (valid)
		2588	mode_index++;
		2589	}
2997	Serge	2590	} else {
		2591	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2592	rdev->clock.default_mclk;
		2593	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2594	rdev->clock.default_sclk;
		2595	mode_index++;
		2596	}
1963	serge	2597	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2598	if (mode_index) {
		2599	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2600	non_clock_info);
		2601	state_index++;
		2602	}
		2603	}
		2604	/* if multiple clock modes, mark the lowest as no display */
		2605	for (i = 0; i < state_index; i++) {
		2606	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2607	rdev->pm.power_state[i].clock_info[0].flags \|=
		2608	RADEON_PM_MODE_NO_DISPLAY;
		2609	}
		2610	/* first mode is usually default */
		2611	if (rdev->pm.default_power_state_index == -1) {
		2612	rdev->pm.power_state[0].type =
		2613	POWER_STATE_TYPE_DEFAULT;
		2614	rdev->pm.default_power_state_index = 0;
		2615	rdev->pm.power_state[0].default_clock_mode =
		2616	&rdev->pm.power_state[0].clock_info[0];
		2617	}
		2618	return state_index;
		2619	}
		2620
		2621	static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
		2622	{
		2623	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2624	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2625	union pplib_power_state *power_state;
		2626	int i, j, non_clock_array_index, clock_array_index;
		2627	int state_index = 0, mode_index = 0;
		2628	union pplib_clock_info *clock_info;
2997	Serge	2629	struct _StateArray *state_array;
		2630	struct _ClockInfoArray *clock_info_array;
		2631	struct _NonClockInfoArray *non_clock_info_array;
1963	serge	2632	bool valid;
		2633	union power_info *power_info;
		2634	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2635	u16 data_offset;
		2636	u8 frev, crev;
3764	Serge	2637	u8 *power_state_offset;
1963	serge	2638
		2639	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2640	&frev, &crev, &data_offset))
		2641	return state_index;
		2642	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2643
		2644	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2997	Serge	2645	state_array = (struct _StateArray *)
1963	serge	2646	(mode_info->atom_context->bios + data_offset +
		2647	le16_to_cpu(power_info->pplib.usStateArrayOffset));
2997	Serge	2648	clock_info_array = (struct _ClockInfoArray *)
1963	serge	2649	(mode_info->atom_context->bios + data_offset +
		2650	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2997	Serge	2651	non_clock_info_array = (struct _NonClockInfoArray *)
1963	serge	2652	(mode_info->atom_context->bios + data_offset +
		2653	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
3764	Serge	2654	if (state_array->ucNumEntries == 0)
		2655	return state_index;
1963	serge	2656	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2657	state_array->ucNumEntries, GFP_KERNEL);
		2658	if (!rdev->pm.power_state)
		2659	return state_index;
3764	Serge	2660	power_state_offset = (u8 *)state_array->states;
1963	serge	2661	for (i = 0; i < state_array->ucNumEntries; i++) {
		2662	mode_index = 0;
3764	Serge	2663	power_state = (union pplib_power_state *)power_state_offset;
		2664	non_clock_array_index = power_state->v2.nonClockInfoIndex;
1963	serge	2665	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2666	&non_clock_info_array->nonClockInfo[non_clock_array_index];
2997	Serge	2667	rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
		2668	(power_state->v2.ucNumDPMLevels ?
		2669	power_state->v2.ucNumDPMLevels : 1),
		2670	GFP_KERNEL);
		2671	if (!rdev->pm.power_state[i].clock_info)
		2672	return state_index;
		2673	if (power_state->v2.ucNumDPMLevels) {
1963	serge	2674	for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
		2675	clock_array_index = power_state->v2.clockInfoIndex[j];
		2676	clock_info = (union pplib_clock_info *)
2997	Serge	2677	&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1963	serge	2678	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2679	state_index, mode_index,
		2680	clock_info);
		2681	if (valid)
		2682	mode_index++;
		2683	}
2997	Serge	2684	} else {
		2685	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2686	rdev->clock.default_mclk;
		2687	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2688	rdev->clock.default_sclk;
		2689	mode_index++;
		2690	}
1963	serge	2691	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2692	if (mode_index) {
		2693	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2694	non_clock_info);
1430	serge	2695	state_index++;
		2696	}
3764	Serge	2697	power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1430	serge	2698	}
1963	serge	2699	/* if multiple clock modes, mark the lowest as no display */
		2700	for (i = 0; i < state_index; i++) {
		2701	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2702	rdev->pm.power_state[i].clock_info[0].flags \|=
		2703	RADEON_PM_MODE_NO_DISPLAY;
		2704	}
		2705	/* first mode is usually default */
		2706	if (rdev->pm.default_power_state_index == -1) {
		2707	rdev->pm.power_state[0].type =
		2708	POWER_STATE_TYPE_DEFAULT;
		2709	rdev->pm.default_power_state_index = 0;
		2710	rdev->pm.power_state[0].default_clock_mode =
		2711	&rdev->pm.power_state[0].clock_info[0];
		2712	}
		2713	return state_index;
		2714	}
		2715
		2716	void radeon_atombios_get_power_modes(struct radeon_device *rdev)
		2717	{
		2718	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2719	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2720	u16 data_offset;
		2721	u8 frev, crev;
		2722	int state_index = 0;
		2723
		2724	rdev->pm.default_power_state_index = -1;
		2725
		2726	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2727	&frev, &crev, &data_offset)) {
		2728	switch (frev) {
		2729	case 1:
		2730	case 2:
		2731	case 3:
		2732	state_index = radeon_atombios_parse_power_table_1_3(rdev);
		2733	break;
		2734	case 4:
		2735	case 5:
		2736	state_index = radeon_atombios_parse_power_table_4_5(rdev);
		2737	break;
		2738	case 6:
		2739	state_index = radeon_atombios_parse_power_table_6(rdev);
		2740	break;
		2741	default:
		2742	break;
1430	serge	2743	}
3764	Serge	2744	}
		2745
		2746	if (state_index == 0) {
1963	serge	2747	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
		2748	if (rdev->pm.power_state) {
2997	Serge	2749	rdev->pm.power_state[0].clock_info =
		2750	kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
		2751	if (rdev->pm.power_state[0].clock_info) {
1430	serge	2752	/* add the default mode */
		2753	rdev->pm.power_state[state_index].type =
		2754	POWER_STATE_TYPE_DEFAULT;
		2755	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2756	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2757	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2758	rdev->pm.power_state[state_index].default_clock_mode =
		2759	&rdev->pm.power_state[state_index].clock_info[0];
		2760	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2761	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2762	rdev->pm.default_power_state_index = state_index;
		2763	rdev->pm.power_state[state_index].flags = 0;
1430	serge	2764	state_index++;
		2765	}
1963	serge	2766	}
2997	Serge	2767	}
1963	serge	2768
1430	serge	2769	rdev->pm.num_power_states = state_index;
		2770
1963	serge	2771	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2772	rdev->pm.current_clock_mode_index = 0;
2997	Serge	2773	if (rdev->pm.default_power_state_index >= 0)
		2774	rdev->pm.current_vddc =
		2775	rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
		2776	else
		2777	rdev->pm.current_vddc = 0;
1117	serge	2778	}
		2779
3764	Serge	2780	union get_clock_dividers {
		2781	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
		2782	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
		2783	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
		2784	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
		2785	struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
5078	serge	2786	struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
		2787	struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
3764	Serge	2788	};
		2789
		2790	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		2791	u8 clock_type,
		2792	u32 clock,
		2793	bool strobe_mode,
		2794	struct atom_clock_dividers *dividers)
		2795	{
		2796	union get_clock_dividers args;
		2797	int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
		2798	u8 frev, crev;
		2799
		2800	memset(&args, 0, sizeof(args));
		2801	memset(dividers, 0, sizeof(struct atom_clock_dividers));
		2802
		2803	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2804	return -EINVAL;
		2805
		2806	switch (crev) {
		2807	case 1:
		2808	/* r4xx, r5xx */
		2809	args.v1.ucAction = clock_type;
		2810	args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
		2811
		2812	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2813
		2814	dividers->post_div = args.v1.ucPostDiv;
		2815	dividers->fb_div = args.v1.ucFbDiv;
		2816	dividers->enable_post_div = true;
		2817	break;
		2818	case 2:
		2819	case 3:
5078	serge	2820	case 5:
		2821	/* r6xx, r7xx, evergreen, ni, si */
3764	Serge	2822	if (rdev->family <= CHIP_RV770) {
		2823	args.v2.ucAction = clock_type;
		2824	args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
		2825
		2826	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2827
		2828	dividers->post_div = args.v2.ucPostDiv;
		2829	dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
		2830	dividers->ref_div = args.v2.ucAction;
		2831	if (rdev->family == CHIP_RV770) {
		2832	dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
		2833	true : false;
		2834	dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
		2835	} else
		2836	dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
		2837	} else {
		2838	if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
		2839	args.v3.ulClockParams = cpu_to_le32((clock_type << 24) \| clock);
		2840
		2841	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2842
		2843	dividers->post_div = args.v3.ucPostDiv;
		2844	dividers->enable_post_div = (args.v3.ucCntlFlag &
		2845	ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
		2846	dividers->enable_dithen = (args.v3.ucCntlFlag &
		2847	ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
5078	serge	2848	dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
3764	Serge	2849	dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
		2850	dividers->ref_div = args.v3.ucRefDiv;
		2851	dividers->vco_mode = (args.v3.ucCntlFlag &
		2852	ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
		2853	} else {
5078	serge	2854	/* for SI we use ComputeMemoryClockParam for memory plls */
		2855	if (rdev->family >= CHIP_TAHITI)
		2856	return -EINVAL;
3764	Serge	2857	args.v5.ulClockParams = cpu_to_le32((clock_type << 24) \| clock);
		2858	if (strobe_mode)
		2859	args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
		2860
		2861	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2862
		2863	dividers->post_div = args.v5.ucPostDiv;
		2864	dividers->enable_post_div = (args.v5.ucCntlFlag &
		2865	ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
		2866	dividers->enable_dithen = (args.v5.ucCntlFlag &
		2867	ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
		2868	dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
		2869	dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
		2870	dividers->ref_div = args.v5.ucRefDiv;
		2871	dividers->vco_mode = (args.v5.ucCntlFlag &
		2872	ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
		2873	}
		2874	}
		2875	break;
		2876	case 4:
		2877	/* fusion */
		2878	args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
		2879
		2880	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2881
5078	serge	2882	dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
3764	Serge	2883	dividers->real_clock = le32_to_cpu(args.v4.ulClock);
		2884	break;
5078	serge	2885	case 6:
		2886	/* CI */
		2887	/* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
		2888	args.v6_in.ulClock.ulComputeClockFlag = clock_type;
		2889	args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
		2890
		2891	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2892
		2893	dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
		2894	dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
		2895	dividers->ref_div = args.v6_out.ucPllRefDiv;
		2896	dividers->post_div = args.v6_out.ucPllPostDiv;
		2897	dividers->flags = args.v6_out.ucPllCntlFlag;
		2898	dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
		2899	dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
		2900	break;
3764	Serge	2901	default:
		2902	return -EINVAL;
		2903	}
		2904	return 0;
		2905	}
		2906
5078	serge	2907	int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
		2908	u32 clock,
		2909	bool strobe_mode,
		2910	struct atom_mpll_param *mpll_param)
		2911	{
		2912	COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
		2913	int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
		2914	u8 frev, crev;
		2915
		2916	memset(&args, 0, sizeof(args));
		2917	memset(mpll_param, 0, sizeof(struct atom_mpll_param));
		2918
		2919	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2920	return -EINVAL;
		2921
		2922	switch (frev) {
		2923	case 2:
		2924	switch (crev) {
		2925	case 1:
		2926	/* SI */
		2927	args.ulClock = cpu_to_le32(clock); /* 10 khz */
		2928	args.ucInputFlag = 0;
		2929	if (strobe_mode)
		2930	args.ucInputFlag \|= MPLL_INPUT_FLAG_STROBE_MODE_EN;
		2931
		2932	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2933
		2934	mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
		2935	mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
		2936	mpll_param->post_div = args.ucPostDiv;
		2937	mpll_param->dll_speed = args.ucDllSpeed;
		2938	mpll_param->bwcntl = args.ucBWCntl;
		2939	mpll_param->vco_mode =
		2940	(args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
		2941	mpll_param->yclk_sel =
		2942	(args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
		2943	mpll_param->qdr =
		2944	(args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
		2945	mpll_param->half_rate =
		2946	(args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
		2947	break;
		2948	default:
		2949	return -EINVAL;
		2950	}
		2951	break;
		2952	default:
		2953	return -EINVAL;
		2954	}
		2955	return 0;
		2956	}
		2957
1430	serge	2958	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1117	serge	2959	{
1430	serge	2960	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		2961	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1117	serge	2962
		2963	args.ucEnable = enable;
		2964
		2965	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2966	}
		2967
1268	serge	2968	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		2969	{
		2970	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		2971	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		2972
		2973	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2974	return le32_to_cpu(args.ulReturnEngineClock);
1268	serge	2975	}
		2976
		2977	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		2978	{
		2979	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		2980	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		2981
		2982	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2983	return le32_to_cpu(args.ulReturnMemoryClock);
1268	serge	2984	}
		2985
1117	serge	2986	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		2987	uint32_t eng_clock)
		2988	{
		2989	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		2990	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		2991
1963	serge	2992	args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
1117	serge	2993
		2994	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2995	}
		2996
		2997	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		2998	uint32_t mem_clock)
		2999	{
		3000	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		3001	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		3002
		3003	if (rdev->flags & RADEON_IS_IGP)
		3004	return;
		3005
1963	serge	3006	args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
1117	serge	3007
		3008	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3009	}
		3010
5078	serge	3011	void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
		3012	u32 eng_clock, u32 mem_clock)
		3013	{
		3014	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		3015	int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
		3016	u32 tmp;
		3017
		3018	memset(&args, 0, sizeof(args));
		3019
		3020	tmp = eng_clock & SET_CLOCK_FREQ_MASK;
		3021	tmp \|= (COMPUTE_ENGINE_PLL_PARAM << 24);
		3022
		3023	args.ulTargetEngineClock = cpu_to_le32(tmp);
		3024	if (mem_clock)
		3025	args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
		3026
		3027	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3028	}
		3029
		3030	void radeon_atom_update_memory_dll(struct radeon_device *rdev,
		3031	u32 mem_clock)
		3032	{
		3033	u32 args;
		3034	int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
		3035
		3036	args = cpu_to_le32(mem_clock); /* 10 khz */
		3037
		3038	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3039	}
		3040
		3041	void radeon_atom_set_ac_timing(struct radeon_device *rdev,
		3042	u32 mem_clock)
		3043	{
		3044	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		3045	int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
		3046	u32 tmp = mem_clock \| (COMPUTE_MEMORY_PLL_PARAM << 24);
		3047
		3048	args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
		3049
		3050	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3051	}
		3052
1963	serge	3053	union set_voltage {
		3054	struct _SET_VOLTAGE_PS_ALLOCATION alloc;
		3055	struct _SET_VOLTAGE_PARAMETERS v1;
		3056	struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2997	Serge	3057	struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1963	serge	3058	};
		3059
		3060	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
		3061	{
		3062	union set_voltage args;
		3063	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		3064	u8 frev, crev, volt_index = voltage_level;
		3065
		3066	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		3067	return;
		3068
1986	serge	3069	/* 0xff01 is a flag rather then an actual voltage */
		3070	if (voltage_level == 0xff01)
		3071	return;
		3072
1963	serge	3073	switch (crev) {
		3074	case 1:
		3075	args.v1.ucVoltageType = voltage_type;
		3076	args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
		3077	args.v1.ucVoltageIndex = volt_index;
		3078	break;
		3079	case 2:
		3080	args.v2.ucVoltageType = voltage_type;
		3081	args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
		3082	args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
		3083	break;
2997	Serge	3084	case 3:
		3085	args.v3.ucVoltageType = voltage_type;
		3086	args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
		3087	args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
		3088	break;
1963	serge	3089	default:
		3090	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3091	return;
		3092	}
		3093
		3094	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3095	}
		3096
5078	serge	3097	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2997	Serge	3098	u16 voltage_id, u16 *voltage)
1986	serge	3099	{
		3100	union set_voltage args;
		3101	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		3102	u8 frev, crev;
1963	serge	3103
1986	serge	3104	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		3105	return -EINVAL;
1963	serge	3106
1986	serge	3107	switch (crev) {
		3108	case 1:
		3109	return -EINVAL;
		3110	case 2:
		3111	args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
		3112	args.v2.ucVoltageMode = 0;
		3113	args.v2.usVoltageLevel = 0;
		3114
		3115	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3116
		3117	*voltage = le16_to_cpu(args.v2.usVoltageLevel);
		3118	break;
2997	Serge	3119	case 3:
		3120	args.v3.ucVoltageType = voltage_type;
		3121	args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
		3122	args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
		3123
		3124	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3125
		3126	*voltage = le16_to_cpu(args.v3.usVoltageLevel);
		3127	break;
1986	serge	3128	default:
		3129	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3130	return -EINVAL;
		3131	}
		3132
		3133	return 0;
		3134	}
		3135
5078	serge	3136	int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
		3137	u16 *voltage,
		3138	u16 leakage_idx)
		3139	{
		3140	return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
		3141	}
		3142
		3143	int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
		3144	u16 *leakage_id)
		3145	{
		3146	union set_voltage args;
		3147	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		3148	u8 frev, crev;
		3149
		3150	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		3151	return -EINVAL;
		3152
		3153	switch (crev) {
		3154	case 3:
		3155	case 4:
		3156	args.v3.ucVoltageType = 0;
		3157	args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
		3158	args.v3.usVoltageLevel = 0;
		3159
		3160	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3161
		3162	*leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
		3163	break;
		3164	default:
		3165	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3166	return -EINVAL;
		3167	}
		3168
		3169	return 0;
		3170	}
		3171
		3172	int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
		3173	u16 vddc, u16 vddci,
		3174	u16 virtual_voltage_id,
		3175	u16 vbios_voltage_id)
		3176	{
		3177	int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
		3178	u8 frev, crev;
		3179	u16 data_offset, size;
		3180	int i, j;
		3181	ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
		3182	u16 leakage_bin, vddc_id_buf, vddc_buf, vddci_id_buf, *vddci_buf;
		3183
		3184	*vddc = 0;
		3185	*vddci = 0;
		3186
		3187	if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3188	&frev, &crev, &data_offset))
		3189	return -EINVAL;
		3190
		3191	profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
		3192	(rdev->mode_info.atom_context->bios + data_offset);
		3193
		3194	switch (frev) {
		3195	case 1:
		3196	return -EINVAL;
		3197	case 2:
		3198	switch (crev) {
		3199	case 1:
		3200	if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
		3201	return -EINVAL;
		3202	leakage_bin = (u16 *)
		3203	(rdev->mode_info.atom_context->bios + data_offset +
		3204	le16_to_cpu(profile->usLeakageBinArrayOffset));
		3205	vddc_id_buf = (u16 *)
		3206	(rdev->mode_info.atom_context->bios + data_offset +
		3207	le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
		3208	vddc_buf = (u16 *)
		3209	(rdev->mode_info.atom_context->bios + data_offset +
		3210	le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
		3211	vddci_id_buf = (u16 *)
		3212	(rdev->mode_info.atom_context->bios + data_offset +
		3213	le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
		3214	vddci_buf = (u16 *)
		3215	(rdev->mode_info.atom_context->bios + data_offset +
		3216	le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
		3217
		3218	if (profile->ucElbVDDC_Num > 0) {
		3219	for (i = 0; i < profile->ucElbVDDC_Num; i++) {
		3220	if (vddc_id_buf[i] == virtual_voltage_id) {
		3221	for (j = 0; j < profile->ucLeakageBinNum; j++) {
		3222	if (vbios_voltage_id <= leakage_bin[j]) {
		3223	vddc = vddc_buf[j profile->ucElbVDDC_Num + i];
		3224	break;
		3225	}
		3226	}
		3227	break;
		3228	}
		3229	}
		3230	}
		3231	if (profile->ucElbVDDCI_Num > 0) {
		3232	for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
		3233	if (vddci_id_buf[i] == virtual_voltage_id) {
		3234	for (j = 0; j < profile->ucLeakageBinNum; j++) {
		3235	if (vbios_voltage_id <= leakage_bin[j]) {
		3236	vddci = vddci_buf[j profile->ucElbVDDCI_Num + i];
		3237	break;
		3238	}
		3239	}
		3240	break;
		3241	}
		3242	}
		3243	}
		3244	break;
		3245	default:
		3246	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3247	return -EINVAL;
		3248	}
		3249	break;
		3250	default:
		3251	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3252	return -EINVAL;
		3253	}
		3254
		3255	return 0;
		3256	}
		3257
		3258	union get_voltage_info {
		3259	struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
		3260	struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
		3261	};
		3262
		3263	int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
		3264	u16 virtual_voltage_id,
		3265	u16 *voltage)
		3266	{
		3267	int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
		3268	u32 entry_id;
		3269	u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
		3270	union get_voltage_info args;
		3271
		3272	for (entry_id = 0; entry_id < count; entry_id++) {
		3273	if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
		3274	virtual_voltage_id)
		3275	break;
		3276	}
		3277
		3278	if (entry_id >= count)
		3279	return -EINVAL;
		3280
		3281	args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
		3282	args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
		3283	args.in.ulSCLKFreq =
		3284	cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
		3285
		3286	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3287
		3288	*voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
		3289
		3290	return 0;
		3291	}
		3292
		3293	int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
		3294	u16 voltage_level, u8 voltage_type,
		3295	u32 gpio_value, u32 gpio_mask)
		3296	{
		3297	union set_voltage args;
		3298	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		3299	u8 frev, crev;
		3300
		3301	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		3302	return -EINVAL;
		3303
		3304	switch (crev) {
		3305	case 1:
		3306	return -EINVAL;
		3307	case 2:
		3308	args.v2.ucVoltageType = voltage_type;
		3309	args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
		3310	args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
		3311
		3312	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3313
		3314	gpio_mask = le32_to_cpu((u32 *)&args.v2);
		3315
		3316	args.v2.ucVoltageType = voltage_type;
		3317	args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
		3318	args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
		3319
		3320	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		3321
		3322	gpio_value = le32_to_cpu((u32 *)&args.v2);
		3323	break;
		3324	default:
		3325	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3326	return -EINVAL;
		3327	}
		3328
		3329	return 0;
		3330	}
		3331
		3332	union voltage_object_info {
		3333	struct _ATOM_VOLTAGE_OBJECT_INFO v1;
		3334	struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
		3335	struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
		3336	};
		3337
		3338	union voltage_object {
		3339	struct _ATOM_VOLTAGE_OBJECT v1;
		3340	struct _ATOM_VOLTAGE_OBJECT_V2 v2;
		3341	union _ATOM_VOLTAGE_OBJECT_V3 v3;
		3342	};
		3343
		3344	static ATOM_VOLTAGE_OBJECT atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO v1,
		3345	u8 voltage_type)
		3346	{
		3347	u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
		3348	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
		3349	u8 start = (u8 )v1;
		3350
		3351	while (offset < size) {
		3352	ATOM_VOLTAGE_OBJECT vo = (ATOM_VOLTAGE_OBJECT )(start + offset);
		3353	if (vo->ucVoltageType == voltage_type)
		3354	return vo;
		3355	offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
		3356	vo->asFormula.ucNumOfVoltageEntries;
		3357	}
		3358	return NULL;
		3359	}
		3360
		3361	static ATOM_VOLTAGE_OBJECT_V2 atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 v2,
		3362	u8 voltage_type)
		3363	{
		3364	u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
		3365	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
		3366	u8 start = (u8)v2;
		3367
		3368	while (offset < size) {
		3369	ATOM_VOLTAGE_OBJECT_V2 vo = (ATOM_VOLTAGE_OBJECT_V2 )(start + offset);
		3370	if (vo->ucVoltageType == voltage_type)
		3371	return vo;
		3372	offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
		3373	(vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
		3374	}
		3375	return NULL;
		3376	}
		3377
		3378	static ATOM_VOLTAGE_OBJECT_V3 atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3,
		3379	u8 voltage_type, u8 voltage_mode)
		3380	{
		3381	u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
		3382	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
		3383	u8 start = (u8)v3;
		3384
		3385	while (offset < size) {
		3386	ATOM_VOLTAGE_OBJECT_V3 vo = (ATOM_VOLTAGE_OBJECT_V3 )(start + offset);
		3387	if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
		3388	(vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
		3389	return vo;
		3390	offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
		3391	}
		3392	return NULL;
		3393	}
		3394
		3395	bool
		3396	radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
		3397	u8 voltage_type, u8 voltage_mode)
		3398	{
		3399	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3400	u8 frev, crev;
		3401	u16 data_offset, size;
		3402	union voltage_object_info *voltage_info;
		3403	union voltage_object *voltage_object = NULL;
		3404
		3405	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3406	&frev, &crev, &data_offset)) {
		3407	voltage_info = (union voltage_object_info *)
		3408	(rdev->mode_info.atom_context->bios + data_offset);
		3409
		3410	switch (frev) {
		3411	case 1:
		3412	case 2:
		3413	switch (crev) {
		3414	case 1:
		3415	voltage_object = (union voltage_object *)
		3416	atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
		3417	if (voltage_object &&
		3418	(voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
		3419	return true;
		3420	break;
		3421	case 2:
		3422	voltage_object = (union voltage_object *)
		3423	atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
		3424	if (voltage_object &&
		3425	(voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
		3426	return true;
		3427	break;
		3428	default:
		3429	DRM_ERROR("unknown voltage object table\n");
		3430	return false;
		3431	}
		3432	break;
		3433	case 3:
		3434	switch (crev) {
		3435	case 1:
		3436	if (atom_lookup_voltage_object_v3(&voltage_info->v3,
		3437	voltage_type, voltage_mode))
		3438	return true;
		3439	break;
		3440	default:
		3441	DRM_ERROR("unknown voltage object table\n");
		3442	return false;
		3443	}
		3444	break;
		3445	default:
		3446	DRM_ERROR("unknown voltage object table\n");
		3447	return false;
		3448	}
		3449
		3450	}
		3451	return false;
		3452	}
		3453
		3454	int radeon_atom_get_svi2_info(struct radeon_device *rdev,
		3455	u8 voltage_type,
		3456	u8 svd_gpio_id, u8 svc_gpio_id)
		3457	{
		3458	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3459	u8 frev, crev;
		3460	u16 data_offset, size;
		3461	union voltage_object_info *voltage_info;
		3462	union voltage_object *voltage_object = NULL;
		3463
		3464	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3465	&frev, &crev, &data_offset)) {
		3466	voltage_info = (union voltage_object_info *)
		3467	(rdev->mode_info.atom_context->bios + data_offset);
		3468
		3469	switch (frev) {
		3470	case 3:
		3471	switch (crev) {
		3472	case 1:
		3473	voltage_object = (union voltage_object *)
		3474	atom_lookup_voltage_object_v3(&voltage_info->v3,
		3475	voltage_type,
		3476	VOLTAGE_OBJ_SVID2);
		3477	if (voltage_object) {
		3478	*svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
		3479	*svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
		3480	} else {
		3481	return -EINVAL;
		3482	}
		3483	break;
		3484	default:
		3485	DRM_ERROR("unknown voltage object table\n");
		3486	return -EINVAL;
		3487	}
		3488	break;
		3489	default:
		3490	DRM_ERROR("unknown voltage object table\n");
		3491	return -EINVAL;
		3492	}
		3493
		3494	}
		3495	return 0;
		3496	}
		3497
		3498	int radeon_atom_get_max_voltage(struct radeon_device *rdev,
		3499	u8 voltage_type, u16 *max_voltage)
		3500	{
		3501	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3502	u8 frev, crev;
		3503	u16 data_offset, size;
		3504	union voltage_object_info *voltage_info;
		3505	union voltage_object *voltage_object = NULL;
		3506
		3507	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3508	&frev, &crev, &data_offset)) {
		3509	voltage_info = (union voltage_object_info *)
		3510	(rdev->mode_info.atom_context->bios + data_offset);
		3511
		3512	switch (crev) {
		3513	case 1:
		3514	voltage_object = (union voltage_object *)
		3515	atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
		3516	if (voltage_object) {
		3517	ATOM_VOLTAGE_FORMULA *formula =
		3518	&voltage_object->v1.asFormula;
		3519	if (formula->ucFlag & 1)
		3520	*max_voltage =
		3521	le16_to_cpu(formula->usVoltageBaseLevel) +
		3522	formula->ucNumOfVoltageEntries / 2 *
		3523	le16_to_cpu(formula->usVoltageStep);
		3524	else
		3525	*max_voltage =
		3526	le16_to_cpu(formula->usVoltageBaseLevel) +
		3527	(formula->ucNumOfVoltageEntries - 1) *
		3528	le16_to_cpu(formula->usVoltageStep);
		3529	return 0;
		3530	}
		3531	break;
		3532	case 2:
		3533	voltage_object = (union voltage_object *)
		3534	atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
		3535	if (voltage_object) {
		3536	ATOM_VOLTAGE_FORMULA_V2 *formula =
		3537	&voltage_object->v2.asFormula;
		3538	if (formula->ucNumOfVoltageEntries) {
		3539	VOLTAGE_LUT_ENTRY lut = (VOLTAGE_LUT_ENTRY )
		3540	((u8 *)&formula->asVIDAdjustEntries[0] +
		3541	(sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
		3542	*max_voltage =
		3543	le16_to_cpu(lut->usVoltageValue);
		3544	return 0;
		3545	}
		3546	}
		3547	break;
		3548	default:
		3549	DRM_ERROR("unknown voltage object table\n");
		3550	return -EINVAL;
		3551	}
		3552
		3553	}
		3554	return -EINVAL;
		3555	}
		3556
		3557	int radeon_atom_get_min_voltage(struct radeon_device *rdev,
		3558	u8 voltage_type, u16 *min_voltage)
		3559	{
		3560	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3561	u8 frev, crev;
		3562	u16 data_offset, size;
		3563	union voltage_object_info *voltage_info;
		3564	union voltage_object *voltage_object = NULL;
		3565
		3566	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3567	&frev, &crev, &data_offset)) {
		3568	voltage_info = (union voltage_object_info *)
		3569	(rdev->mode_info.atom_context->bios + data_offset);
		3570
		3571	switch (crev) {
		3572	case 1:
		3573	voltage_object = (union voltage_object *)
		3574	atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
		3575	if (voltage_object) {
		3576	ATOM_VOLTAGE_FORMULA *formula =
		3577	&voltage_object->v1.asFormula;
		3578	*min_voltage =
		3579	le16_to_cpu(formula->usVoltageBaseLevel);
		3580	return 0;
		3581	}
		3582	break;
		3583	case 2:
		3584	voltage_object = (union voltage_object *)
		3585	atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
		3586	if (voltage_object) {
		3587	ATOM_VOLTAGE_FORMULA_V2 *formula =
		3588	&voltage_object->v2.asFormula;
		3589	if (formula->ucNumOfVoltageEntries) {
		3590	*min_voltage =
		3591	le16_to_cpu(formula->asVIDAdjustEntries[
		3592
		3593	].usVoltageValue);
		3594	return 0;
		3595	}
		3596	}
		3597	break;
		3598	default:
		3599	DRM_ERROR("unknown voltage object table\n");
		3600	return -EINVAL;
		3601	}
		3602
		3603	}
		3604	return -EINVAL;
		3605	}
		3606
		3607	int radeon_atom_get_voltage_step(struct radeon_device *rdev,
		3608	u8 voltage_type, u16 *voltage_step)
		3609	{
		3610	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3611	u8 frev, crev;
		3612	u16 data_offset, size;
		3613	union voltage_object_info *voltage_info;
		3614	union voltage_object *voltage_object = NULL;
		3615
		3616	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3617	&frev, &crev, &data_offset)) {
		3618	voltage_info = (union voltage_object_info *)
		3619	(rdev->mode_info.atom_context->bios + data_offset);
		3620
		3621	switch (crev) {
		3622	case 1:
		3623	voltage_object = (union voltage_object *)
		3624	atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
		3625	if (voltage_object) {
		3626	ATOM_VOLTAGE_FORMULA *formula =
		3627	&voltage_object->v1.asFormula;
		3628	if (formula->ucFlag & 1)
		3629	*voltage_step =
		3630	(le16_to_cpu(formula->usVoltageStep) + 1) / 2;
		3631	else
		3632	*voltage_step =
		3633	le16_to_cpu(formula->usVoltageStep);
		3634	return 0;
		3635	}
		3636	break;
		3637	case 2:
		3638	return -EINVAL;
		3639	default:
		3640	DRM_ERROR("unknown voltage object table\n");
		3641	return -EINVAL;
		3642	}
		3643
		3644	}
		3645	return -EINVAL;
		3646	}
		3647
		3648	int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
		3649	u8 voltage_type,
		3650	u16 nominal_voltage,
		3651	u16 *true_voltage)
		3652	{
		3653	u16 min_voltage, max_voltage, voltage_step;
		3654
		3655	if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
		3656	return -EINVAL;
		3657	if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
		3658	return -EINVAL;
		3659	if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
		3660	return -EINVAL;
		3661
		3662	if (nominal_voltage <= min_voltage)
		3663	*true_voltage = min_voltage;
		3664	else if (nominal_voltage >= max_voltage)
		3665	*true_voltage = max_voltage;
		3666	else
		3667	*true_voltage = min_voltage +
		3668	((nominal_voltage - min_voltage) / voltage_step) *
		3669	voltage_step;
		3670
		3671	return 0;
		3672	}
		3673
		3674	int radeon_atom_get_voltage_table(struct radeon_device *rdev,
		3675	u8 voltage_type, u8 voltage_mode,
		3676	struct atom_voltage_table *voltage_table)
		3677	{
		3678	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
		3679	u8 frev, crev;
		3680	u16 data_offset, size;
		3681	int i, ret;
		3682	union voltage_object_info *voltage_info;
		3683	union voltage_object *voltage_object = NULL;
		3684
		3685	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3686	&frev, &crev, &data_offset)) {
		3687	voltage_info = (union voltage_object_info *)
		3688	(rdev->mode_info.atom_context->bios + data_offset);
		3689
		3690	switch (frev) {
		3691	case 1:
		3692	case 2:
		3693	switch (crev) {
		3694	case 1:
		3695	DRM_ERROR("old table version %d, %d\n", frev, crev);
		3696	return -EINVAL;
		3697	case 2:
		3698	voltage_object = (union voltage_object *)
		3699	atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
		3700	if (voltage_object) {
		3701	ATOM_VOLTAGE_FORMULA_V2 *formula =
		3702	&voltage_object->v2.asFormula;
		3703	VOLTAGE_LUT_ENTRY *lut;
		3704	if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
		3705	return -EINVAL;
		3706	lut = &formula->asVIDAdjustEntries[0];
		3707	for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
		3708	voltage_table->entries[i].value =
		3709	le16_to_cpu(lut->usVoltageValue);
		3710	ret = radeon_atom_get_voltage_gpio_settings(rdev,
		3711	voltage_table->entries[i].value,
		3712	voltage_type,
		3713	&voltage_table->entries[i].smio_low,
		3714	&voltage_table->mask_low);
		3715	if (ret)
		3716	return ret;
		3717	lut = (VOLTAGE_LUT_ENTRY *)
		3718	((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
		3719	}
		3720	voltage_table->count = formula->ucNumOfVoltageEntries;
		3721	return 0;
		3722	}
		3723	break;
		3724	default:
		3725	DRM_ERROR("unknown voltage object table\n");
		3726	return -EINVAL;
		3727	}
		3728	break;
		3729	case 3:
		3730	switch (crev) {
		3731	case 1:
		3732	voltage_object = (union voltage_object *)
		3733	atom_lookup_voltage_object_v3(&voltage_info->v3,
		3734	voltage_type, voltage_mode);
		3735	if (voltage_object) {
		3736	ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
		3737	&voltage_object->v3.asGpioVoltageObj;
		3738	VOLTAGE_LUT_ENTRY_V2 *lut;
		3739	if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
		3740	return -EINVAL;
		3741	lut = &gpio->asVolGpioLut[0];
		3742	for (i = 0; i < gpio->ucGpioEntryNum; i++) {
		3743	voltage_table->entries[i].value =
		3744	le16_to_cpu(lut->usVoltageValue);
		3745	voltage_table->entries[i].smio_low =
		3746	le32_to_cpu(lut->ulVoltageId);
		3747	lut = (VOLTAGE_LUT_ENTRY_V2 *)
		3748	((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
		3749	}
		3750	voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
		3751	voltage_table->count = gpio->ucGpioEntryNum;
		3752	voltage_table->phase_delay = gpio->ucPhaseDelay;
		3753	return 0;
		3754	}
		3755	break;
		3756	default:
		3757	DRM_ERROR("unknown voltage object table\n");
		3758	return -EINVAL;
		3759	}
		3760	break;
		3761	default:
		3762	DRM_ERROR("unknown voltage object table\n");
		3763	return -EINVAL;
		3764	}
		3765	}
		3766	return -EINVAL;
		3767	}
		3768
		3769	union vram_info {
		3770	struct _ATOM_VRAM_INFO_V3 v1_3;
		3771	struct _ATOM_VRAM_INFO_V4 v1_4;
		3772	struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
		3773	};
		3774
		3775	int radeon_atom_get_memory_info(struct radeon_device *rdev,
		3776	u8 module_index, struct atom_memory_info *mem_info)
		3777	{
		3778	int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
		3779	u8 frev, crev, i;
		3780	u16 data_offset, size;
		3781	union vram_info *vram_info;
		3782
		3783	memset(mem_info, 0, sizeof(struct atom_memory_info));
		3784
		3785	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3786	&frev, &crev, &data_offset)) {
		3787	vram_info = (union vram_info *)
		3788	(rdev->mode_info.atom_context->bios + data_offset);
		3789	switch (frev) {
		3790	case 1:
		3791	switch (crev) {
		3792	case 3:
		3793	/* r6xx */
		3794	if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
		3795	ATOM_VRAM_MODULE_V3 *vram_module =
		3796	(ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
		3797
		3798	for (i = 0; i < module_index; i++) {
		3799	if (le16_to_cpu(vram_module->usSize) == 0)
		3800	return -EINVAL;
		3801	vram_module = (ATOM_VRAM_MODULE_V3 *)
		3802	((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
		3803	}
		3804	mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
		3805	mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
		3806	} else
		3807	return -EINVAL;
		3808	break;
		3809	case 4:
		3810	/* r7xx, evergreen */
		3811	if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
		3812	ATOM_VRAM_MODULE_V4 *vram_module =
		3813	(ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
		3814
		3815	for (i = 0; i < module_index; i++) {
		3816	if (le16_to_cpu(vram_module->usModuleSize) == 0)
		3817	return -EINVAL;
		3818	vram_module = (ATOM_VRAM_MODULE_V4 *)
		3819	((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
		3820	}
		3821	mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
		3822	mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
		3823	} else
		3824	return -EINVAL;
		3825	break;
		3826	default:
		3827	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3828	return -EINVAL;
		3829	}
		3830	break;
		3831	case 2:
		3832	switch (crev) {
		3833	case 1:
		3834	/* ni */
		3835	if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
		3836	ATOM_VRAM_MODULE_V7 *vram_module =
		3837	(ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
		3838
		3839	for (i = 0; i < module_index; i++) {
		3840	if (le16_to_cpu(vram_module->usModuleSize) == 0)
		3841	return -EINVAL;
		3842	vram_module = (ATOM_VRAM_MODULE_V7 *)
		3843	((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
		3844	}
		3845	mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
		3846	mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
		3847	} else
		3848	return -EINVAL;
		3849	break;
		3850	default:
		3851	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3852	return -EINVAL;
		3853	}
		3854	break;
		3855	default:
		3856	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3857	return -EINVAL;
		3858	}
		3859	return 0;
		3860	}
		3861	return -EINVAL;
		3862	}
		3863
		3864	int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
		3865	bool gddr5, u8 module_index,
		3866	struct atom_memory_clock_range_table *mclk_range_table)
		3867	{
		3868	int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
		3869	u8 frev, crev, i;
		3870	u16 data_offset, size;
		3871	union vram_info *vram_info;
		3872	u32 mem_timing_size = gddr5 ?
		3873	sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
		3874
		3875	memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
		3876
		3877	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3878	&frev, &crev, &data_offset)) {
		3879	vram_info = (union vram_info *)
		3880	(rdev->mode_info.atom_context->bios + data_offset);
		3881	switch (frev) {
		3882	case 1:
		3883	switch (crev) {
		3884	case 3:
		3885	DRM_ERROR("old table version %d, %d\n", frev, crev);
		3886	return -EINVAL;
		3887	case 4:
		3888	/* r7xx, evergreen */
		3889	if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
		3890	ATOM_VRAM_MODULE_V4 *vram_module =
		3891	(ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
		3892	ATOM_MEMORY_TIMING_FORMAT *format;
		3893
		3894	for (i = 0; i < module_index; i++) {
		3895	if (le16_to_cpu(vram_module->usModuleSize) == 0)
		3896	return -EINVAL;
		3897	vram_module = (ATOM_VRAM_MODULE_V4 *)
		3898	((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
		3899	}
		3900	mclk_range_table->num_entries = (u8)
		3901	((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
		3902	mem_timing_size);
		3903	format = &vram_module->asMemTiming[0];
		3904	for (i = 0; i < mclk_range_table->num_entries; i++) {
		3905	mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
		3906	format = (ATOM_MEMORY_TIMING_FORMAT *)
		3907	((u8 *)format + mem_timing_size);
		3908	}
		3909	} else
		3910	return -EINVAL;
		3911	break;
		3912	default:
		3913	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3914	return -EINVAL;
		3915	}
		3916	break;
		3917	case 2:
		3918	DRM_ERROR("new table version %d, %d\n", frev, crev);
		3919	return -EINVAL;
		3920	default:
		3921	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		3922	return -EINVAL;
		3923	}
		3924	return 0;
		3925	}
		3926	return -EINVAL;
		3927	}
		3928
		3929	#define MEM_ID_MASK 0xff000000
		3930	#define MEM_ID_SHIFT 24
		3931	#define CLOCK_RANGE_MASK 0x00ffffff
		3932	#define CLOCK_RANGE_SHIFT 0
		3933	#define LOW_NIBBLE_MASK 0xf
		3934	#define DATA_EQU_PREV 0
		3935	#define DATA_FROM_TABLE 4
		3936
		3937	int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
		3938	u8 module_index,
		3939	struct atom_mc_reg_table *reg_table)
		3940	{
		3941	int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
		3942	u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
		3943	u32 i = 0, j;
		3944	u16 data_offset, size;
		3945	union vram_info *vram_info;
		3946
		3947	memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
		3948
		3949	if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
		3950	&frev, &crev, &data_offset)) {
		3951	vram_info = (union vram_info *)
		3952	(rdev->mode_info.atom_context->bios + data_offset);
		3953	switch (frev) {
		3954	case 1:
		3955	DRM_ERROR("old table version %d, %d\n", frev, crev);
		3956	return -EINVAL;
		3957	case 2:
		3958	switch (crev) {
		3959	case 1:
		3960	if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
		3961	ATOM_INIT_REG_BLOCK *reg_block =
		3962	(ATOM_INIT_REG_BLOCK *)
		3963	((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
		3964	ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
		3965	(ATOM_MEMORY_SETTING_DATA_BLOCK *)
		3966	((u8 )reg_block + (2 sizeof(u16)) +
		3967	le16_to_cpu(reg_block->usRegIndexTblSize));
		3968	ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
		3969	num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
		3970	sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
		3971	if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
		3972	return -EINVAL;
		3973	while (i < num_entries) {
		3974	if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
		3975	break;
		3976	reg_table->mc_reg_address[i].s1 =
		3977	(u16)(le16_to_cpu(format->usRegIndex));
		3978	reg_table->mc_reg_address[i].pre_reg_data =
		3979	(u8)(format->ucPreRegDataLength);
		3980	i++;
		3981	format = (ATOM_INIT_REG_INDEX_FORMAT *)
		3982	((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
		3983	}
		3984	reg_table->last = i;
		3985	while ((le32_to_cpu((u32 )reg_data) != END_OF_REG_DATA_BLOCK) &&
		3986	(num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
		3987	t_mem_id = (u8)((le32_to_cpu((u32 )reg_data) & MEM_ID_MASK)
		3988	>> MEM_ID_SHIFT);
		3989	if (module_index == t_mem_id) {
		3990	reg_table->mc_reg_table_entry[num_ranges].mclk_max =
		3991	(u32)((le32_to_cpu((u32 )reg_data) & CLOCK_RANGE_MASK)
		3992	>> CLOCK_RANGE_SHIFT);
		3993	for (i = 0, j = 1; i < reg_table->last; i++) {
		3994	if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
		3995	reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
		3996	(u32)le32_to_cpu(((u32 )reg_data + j));
		3997	j++;
		3998	} else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
		3999	reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
		4000	reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
		4001	}
		4002	}
		4003	num_ranges++;
		4004	}
		4005	reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
		4006	((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
		4007	}
		4008	if (le32_to_cpu((u32 )reg_data) != END_OF_REG_DATA_BLOCK)
		4009	return -EINVAL;
		4010	reg_table->num_entries = num_ranges;
		4011	} else
		4012	return -EINVAL;
		4013	break;
		4014	default:
		4015	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		4016	return -EINVAL;
		4017	}
		4018	break;
		4019	default:
		4020	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		4021	return -EINVAL;
		4022	}
		4023	return 0;
		4024	}
		4025	return -EINVAL;
		4026	}
		4027
1117	serge	4028	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		4029	{
		4030	struct radeon_device *rdev = dev->dev_private;
		4031	uint32_t bios_2_scratch, bios_6_scratch;
		4032
		4033	if (rdev->family >= CHIP_R600) {
1179	serge	4034	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	4035	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		4036	} else {
1179	serge	4037	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	4038	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		4039	}
		4040
		4041	/* let the bios control the backlight */
		4042	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		4043
		4044	/* tell the bios not to handle mode switching */
1963	serge	4045	bios_6_scratch \|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1117	serge	4046
5078	serge	4047	/* clear the vbios dpms state */
		4048	if (ASIC_IS_DCE4(rdev))
		4049	bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
		4050
1117	serge	4051	if (rdev->family >= CHIP_R600) {
		4052	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		4053	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		4054	} else {
		4055	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		4056	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		4057	}
		4058
		4059	}
		4060
1179	serge	4061	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		4062	{
		4063	uint32_t scratch_reg;
		4064	int i;
		4065
		4066	if (rdev->family >= CHIP_R600)
		4067	scratch_reg = R600_BIOS_0_SCRATCH;
		4068	else
		4069	scratch_reg = RADEON_BIOS_0_SCRATCH;
		4070
		4071	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		4072	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		4073	}
		4074
		4075	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		4076	{
		4077	uint32_t scratch_reg;
		4078	int i;
		4079
		4080	if (rdev->family >= CHIP_R600)
		4081	scratch_reg = R600_BIOS_0_SCRATCH;
		4082	else
		4083	scratch_reg = RADEON_BIOS_0_SCRATCH;
		4084
		4085	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		4086	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		4087	}
		4088
1117	serge	4089	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		4090	{
		4091	struct drm_device *dev = encoder->dev;
		4092	struct radeon_device *rdev = dev->dev_private;
		4093	uint32_t bios_6_scratch;
		4094
		4095	if (rdev->family >= CHIP_R600)
		4096	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		4097	else
		4098	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		4099
1963	serge	4100	if (lock) {
1117	serge	4101	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
1963	serge	4102	bios_6_scratch &= ~ATOM_S6_ACC_MODE;
		4103	} else {
1117	serge	4104	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1963	serge	4105	bios_6_scratch \|= ATOM_S6_ACC_MODE;
		4106	}
1117	serge	4107
		4108	if (rdev->family >= CHIP_R600)
		4109	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		4110	else
		4111	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		4112	}
		4113
		4114	/* at some point we may want to break this out into individual functions */
		4115	void
		4116	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		4117	struct drm_encoder *encoder,
		4118	bool connected)
		4119	{
		4120	struct drm_device *dev = connector->dev;
		4121	struct radeon_device *rdev = dev->dev_private;
		4122	struct radeon_connector *radeon_connector =
		4123	to_radeon_connector(connector);
		4124	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		4125	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		4126
		4127	if (rdev->family >= CHIP_R600) {
		4128	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		4129	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		4130	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		4131	} else {
		4132	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		4133	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		4134	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		4135	}
		4136
		4137	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		4138	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		4139	if (connected) {
1963	serge	4140	DRM_DEBUG_KMS("TV1 connected\n");
1117	serge	4141	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		4142	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		4143	} else {
1963	serge	4144	DRM_DEBUG_KMS("TV1 disconnected\n");
1117	serge	4145	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		4146	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		4147	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		4148	}
		4149	}
		4150	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		4151	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		4152	if (connected) {
1963	serge	4153	DRM_DEBUG_KMS("CV connected\n");
1117	serge	4154	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		4155	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		4156	} else {
1963	serge	4157	DRM_DEBUG_KMS("CV disconnected\n");
1117	serge	4158	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		4159	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		4160	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		4161	}
		4162	}
		4163	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		4164	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		4165	if (connected) {
1963	serge	4166	DRM_DEBUG_KMS("LCD1 connected\n");
1117	serge	4167	bios_0_scratch \|= ATOM_S0_LCD1;
		4168	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		4169	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		4170	} else {
1963	serge	4171	DRM_DEBUG_KMS("LCD1 disconnected\n");
1117	serge	4172	bios_0_scratch &= ~ATOM_S0_LCD1;
		4173	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		4174	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		4175	}
		4176	}
		4177	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		4178	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		4179	if (connected) {
1963	serge	4180	DRM_DEBUG_KMS("CRT1 connected\n");
1117	serge	4181	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		4182	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		4183	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		4184	} else {
1963	serge	4185	DRM_DEBUG_KMS("CRT1 disconnected\n");
1117	serge	4186	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		4187	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		4188	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		4189	}
		4190	}
		4191	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		4192	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		4193	if (connected) {
1963	serge	4194	DRM_DEBUG_KMS("CRT2 connected\n");
1117	serge	4195	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		4196	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		4197	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		4198	} else {
1963	serge	4199	DRM_DEBUG_KMS("CRT2 disconnected\n");
1117	serge	4200	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		4201	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		4202	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		4203	}
		4204	}
		4205	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		4206	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		4207	if (connected) {
1963	serge	4208	DRM_DEBUG_KMS("DFP1 connected\n");
1117	serge	4209	bios_0_scratch \|= ATOM_S0_DFP1;
		4210	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		4211	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		4212	} else {
1963	serge	4213	DRM_DEBUG_KMS("DFP1 disconnected\n");
1117	serge	4214	bios_0_scratch &= ~ATOM_S0_DFP1;
		4215	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		4216	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		4217	}
		4218	}
		4219	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		4220	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		4221	if (connected) {
1963	serge	4222	DRM_DEBUG_KMS("DFP2 connected\n");
1117	serge	4223	bios_0_scratch \|= ATOM_S0_DFP2;
		4224	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		4225	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		4226	} else {
1963	serge	4227	DRM_DEBUG_KMS("DFP2 disconnected\n");
1117	serge	4228	bios_0_scratch &= ~ATOM_S0_DFP2;
		4229	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		4230	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		4231	}
		4232	}
		4233	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		4234	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		4235	if (connected) {
1963	serge	4236	DRM_DEBUG_KMS("DFP3 connected\n");
1117	serge	4237	bios_0_scratch \|= ATOM_S0_DFP3;
		4238	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		4239	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		4240	} else {
1963	serge	4241	DRM_DEBUG_KMS("DFP3 disconnected\n");
1117	serge	4242	bios_0_scratch &= ~ATOM_S0_DFP3;
		4243	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		4244	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		4245	}
		4246	}
		4247	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		4248	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		4249	if (connected) {
1963	serge	4250	DRM_DEBUG_KMS("DFP4 connected\n");
1117	serge	4251	bios_0_scratch \|= ATOM_S0_DFP4;
		4252	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		4253	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		4254	} else {
1963	serge	4255	DRM_DEBUG_KMS("DFP4 disconnected\n");
1117	serge	4256	bios_0_scratch &= ~ATOM_S0_DFP4;
		4257	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		4258	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		4259	}
		4260	}
		4261	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		4262	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		4263	if (connected) {
1963	serge	4264	DRM_DEBUG_KMS("DFP5 connected\n");
1117	serge	4265	bios_0_scratch \|= ATOM_S0_DFP5;
		4266	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		4267	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		4268	} else {
1963	serge	4269	DRM_DEBUG_KMS("DFP5 disconnected\n");
1117	serge	4270	bios_0_scratch &= ~ATOM_S0_DFP5;
		4271	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		4272	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		4273	}
		4274	}
2997	Serge	4275	if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
		4276	(radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
		4277	if (connected) {
		4278	DRM_DEBUG_KMS("DFP6 connected\n");
		4279	bios_0_scratch \|= ATOM_S0_DFP6;
		4280	bios_3_scratch \|= ATOM_S3_DFP6_ACTIVE;
		4281	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP6;
		4282	} else {
		4283	DRM_DEBUG_KMS("DFP6 disconnected\n");
		4284	bios_0_scratch &= ~ATOM_S0_DFP6;
		4285	bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
		4286	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
		4287	}
		4288	}
1117	serge	4289
		4290	if (rdev->family >= CHIP_R600) {
		4291	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		4292	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		4293	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		4294	} else {
		4295	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		4296	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		4297	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		4298	}
		4299	}
		4300
		4301	void
		4302	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		4303	{
		4304	struct drm_device *dev = encoder->dev;
		4305	struct radeon_device *rdev = dev->dev_private;
		4306	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		4307	uint32_t bios_3_scratch;
		4308
2997	Serge	4309	if (ASIC_IS_DCE4(rdev))
		4310	return;
		4311
1117	serge	4312	if (rdev->family >= CHIP_R600)
		4313	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		4314	else
		4315	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		4316
		4317	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		4318	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		4319	bios_3_scratch \|= (crtc << 18);
		4320	}
		4321	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		4322	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		4323	bios_3_scratch \|= (crtc << 24);
		4324	}
		4325	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		4326	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		4327	bios_3_scratch \|= (crtc << 16);
		4328	}
		4329	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		4330	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		4331	bios_3_scratch \|= (crtc << 20);
		4332	}
		4333	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		4334	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		4335	bios_3_scratch \|= (crtc << 17);
		4336	}
		4337	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		4338	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		4339	bios_3_scratch \|= (crtc << 19);
		4340	}
		4341	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		4342	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		4343	bios_3_scratch \|= (crtc << 23);
		4344	}
		4345	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		4346	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		4347	bios_3_scratch \|= (crtc << 25);
		4348	}
		4349
		4350	if (rdev->family >= CHIP_R600)
		4351	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		4352	else
		4353	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		4354	}
		4355
		4356	void
		4357	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		4358	{
		4359	struct drm_device *dev = encoder->dev;
		4360	struct radeon_device *rdev = dev->dev_private;
		4361	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		4362	uint32_t bios_2_scratch;
		4363
2997	Serge	4364	if (ASIC_IS_DCE4(rdev))
		4365	return;
		4366
1117	serge	4367	if (rdev->family >= CHIP_R600)
		4368	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		4369	else
		4370	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		4371
		4372	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		4373	if (on)
		4374	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		4375	else
		4376	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		4377	}
		4378	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		4379	if (on)
		4380	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		4381	else
		4382	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		4383	}
		4384	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		4385	if (on)
		4386	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		4387	else
		4388	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		4389	}
		4390	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		4391	if (on)
		4392	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		4393	else
		4394	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		4395	}
		4396	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		4397	if (on)
		4398	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		4399	else
		4400	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		4401	}
		4402	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		4403	if (on)
		4404	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		4405	else
		4406	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		4407	}
		4408	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		4409	if (on)
		4410	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		4411	else
		4412	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		4413	}
		4414	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		4415	if (on)
		4416	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		4417	else
		4418	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		4419	}
		4420	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		4421	if (on)
		4422	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		4423	else
		4424	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		4425	}
		4426	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		4427	if (on)
		4428	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		4429	else
		4430	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		4431	}
		4432
		4433	if (rdev->family >= CHIP_R600)
		4434	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		4435	else
		4436	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		4437	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 5128