WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
1963	serge	35	radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
1117	serge	36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
1963	serge	39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
		40	uint32_t supported_device, u16 caps);
1117	serge	41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
1963	serge	49	uint32_t igp_lane_info,
1321	serge	50	uint16_t connector_object_id,
1963	serge	51	struct radeon_hpd *hpd,
		52	struct radeon_router *router);
1117	serge	53
		54	/* from radeon_legacy_encoder.c */
		55	extern void
1963	serge	56	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
1117	serge	57	uint32_t supported_device);
		58
		59	union atom_supported_devices {
		60	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		61	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		62	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		63	};
		64
1321	serge	65	static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		66	uint8_t id)
1117	serge	67	{
		68	struct atom_context *ctx = rdev->mode_info.atom_context;
1321	serge	69	ATOM_GPIO_I2C_ASSIGMENT *gpio;
1117	serge	70	struct radeon_i2c_bus_rec i2c;
		71	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		72	struct _ATOM_GPIO_I2C_INFO *i2c_info;
1963	serge	73	uint16_t data_offset, size;
		74	int i, num_indices;
1117	serge	75
		76	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		77	i2c.valid = false;
		78
1963	serge	79	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
1117	serge	80	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		81
1963	serge	82	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		83	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
1117	serge	84
1963	serge	85	for (i = 0; i < num_indices; i++) {
1321	serge	86	gpio = &i2c_info->asGPIO_Info[i];
		87
1963	serge	88	/* some evergreen boards have bad data for this entry */
		89	if (ASIC_IS_DCE4(rdev)) {
		90	if ((i == 7) &&
		91	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
		92	(gpio->sucI2cId.ucAccess == 0)) {
		93	gpio->sucI2cId.ucAccess = 0x97;
		94	gpio->ucDataMaskShift = 8;
		95	gpio->ucDataEnShift = 8;
		96	gpio->ucDataY_Shift = 8;
		97	gpio->ucDataA_Shift = 8;
		98	}
		99	}
		100
		101	/* some DCE3 boards have bad data for this entry */
		102	if (ASIC_IS_DCE3(rdev)) {
		103	if ((i == 4) &&
		104	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
		105	(gpio->sucI2cId.ucAccess == 0x94))
		106	gpio->sucI2cId.ucAccess = 0x14;
		107	}
		108
1321	serge	109	if (gpio->sucI2cId.ucAccess == id) {
		110	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		111	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		112	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		113	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		114	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		115	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		116	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		117	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		118	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		119	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		120	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		121	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		122	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		123	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		124	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		125	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		126
		127	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		128	i2c.hw_capable = true;
		129	else
		130	i2c.hw_capable = false;
		131
		132	if (gpio->sucI2cId.ucAccess == 0xa0)
		133	i2c.mm_i2c = true;
		134	else
		135	i2c.mm_i2c = false;
		136
		137	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		138
1963	serge	139	if (i2c.mask_clk_reg)
1117	serge	140	i2c.valid = true;
1404	serge	141	break;
1321	serge	142	}
		143	}
1963	serge	144	}
1117	serge	145
		146	return i2c;
		147	}
		148
1963	serge	149	void radeon_atombios_i2c_init(struct radeon_device *rdev)
		150	{
		151	struct atom_context *ctx = rdev->mode_info.atom_context;
		152	ATOM_GPIO_I2C_ASSIGMENT *gpio;
		153	struct radeon_i2c_bus_rec i2c;
		154	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		155	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		156	uint16_t data_offset, size;
		157	int i, num_indices;
		158	char stmp[32];
		159
		160	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		161
		162	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
		163	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		164
		165	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		166	sizeof(ATOM_GPIO_I2C_ASSIGMENT);
		167
		168	for (i = 0; i < num_indices; i++) {
		169	gpio = &i2c_info->asGPIO_Info[i];
		170	i2c.valid = false;
		171
		172	/* some evergreen boards have bad data for this entry */
		173	if (ASIC_IS_DCE4(rdev)) {
		174	if ((i == 7) &&
		175	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
		176	(gpio->sucI2cId.ucAccess == 0)) {
		177	gpio->sucI2cId.ucAccess = 0x97;
		178	gpio->ucDataMaskShift = 8;
		179	gpio->ucDataEnShift = 8;
		180	gpio->ucDataY_Shift = 8;
		181	gpio->ucDataA_Shift = 8;
		182	}
		183	}
		184
		185	/* some DCE3 boards have bad data for this entry */
		186	if (ASIC_IS_DCE3(rdev)) {
		187	if ((i == 4) &&
		188	(le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
		189	(gpio->sucI2cId.ucAccess == 0x94))
		190	gpio->sucI2cId.ucAccess = 0x14;
		191	}
		192
		193	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		194	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		195	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		196	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		197	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		198	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		199	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		200	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		201	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		202	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		203	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		204	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		205	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		206	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		207	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		208	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		209
		210	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		211	i2c.hw_capable = true;
		212	else
		213	i2c.hw_capable = false;
		214
		215	if (gpio->sucI2cId.ucAccess == 0xa0)
		216	i2c.mm_i2c = true;
		217	else
		218	i2c.mm_i2c = false;
		219
		220	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		221
		222	if (i2c.mask_clk_reg) {
		223	i2c.valid = true;
		224	sprintf(stmp, "0x%x", i2c.i2c_id);
		225	rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
		226	}
		227	}
		228	}
		229	}
		230
1321	serge	231	static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
		232	u8 id)
		233	{
		234	struct atom_context *ctx = rdev->mode_info.atom_context;
		235	struct radeon_gpio_rec gpio;
		236	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		237	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		238	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		239	u16 data_offset, size;
		240	int i, num_indices;
		241
		242	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		243	gpio.valid = false;
		244
1963	serge	245	if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
1321	serge	246	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		247
1963	serge	248	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		249	sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
1321	serge	250
		251	for (i = 0; i < num_indices; i++) {
		252	pin = &gpio_info->asGPIO_Pin[i];
		253	if (id == pin->ucGPIO_ID) {
		254	gpio.id = pin->ucGPIO_ID;
1963	serge	255	gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
1321	serge	256	gpio.mask = (1 << pin->ucGpioPinBitShift);
		257	gpio.valid = true;
		258	break;
		259	}
		260	}
1963	serge	261	}
1321	serge	262
		263	return gpio;
		264	}
		265
		266	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		267	struct radeon_gpio_rec *gpio)
		268	{
		269	struct radeon_hpd hpd;
1430	serge	270	u32 reg;
		271
1963	serge	272	memset(&hpd, 0, sizeof(struct radeon_hpd));
		273
1430	serge	274	if (ASIC_IS_DCE4(rdev))
		275	reg = EVERGREEN_DC_GPIO_HPD_A;
		276	else
		277	reg = AVIVO_DC_GPIO_HPD_A;
		278
1321	serge	279	hpd.gpio = *gpio;
1430	serge	280	if (gpio->reg == reg) {
1321	serge	281	switch(gpio->mask) {
		282	case (1 << 0):
		283	hpd.hpd = RADEON_HPD_1;
		284	break;
		285	case (1 << 8):
		286	hpd.hpd = RADEON_HPD_2;
		287	break;
		288	case (1 << 16):
		289	hpd.hpd = RADEON_HPD_3;
		290	break;
		291	case (1 << 24):
		292	hpd.hpd = RADEON_HPD_4;
		293	break;
		294	case (1 << 26):
		295	hpd.hpd = RADEON_HPD_5;
		296	break;
		297	case (1 << 28):
		298	hpd.hpd = RADEON_HPD_6;
		299	break;
		300	default:
		301	hpd.hpd = RADEON_HPD_NONE;
		302	break;
		303	}
		304	} else
		305	hpd.hpd = RADEON_HPD_NONE;
		306	return hpd;
		307	}
		308
1117	serge	309	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		310	uint32_t supported_device,
		311	int *connector_type,
1179	serge	312	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	313	uint16_t *line_mux,
		314	struct radeon_hpd *hpd)
1117	serge	315	{
		316
		317	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		318	if ((dev->pdev->device == 0x791e) &&
		319	(dev->pdev->subsystem_vendor == 0x1043) &&
		320	(dev->pdev->subsystem_device == 0x826d)) {
		321	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		322	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		323	*connector_type = DRM_MODE_CONNECTOR_DVID;
		324	}
		325
1428	serge	326	/* Asrock RS600 board lists the DVI port as HDMI */
		327	if ((dev->pdev->device == 0x7941) &&
		328	(dev->pdev->subsystem_vendor == 0x1849) &&
		329	(dev->pdev->subsystem_device == 0x7941)) {
		330	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		331	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		332	*connector_type = DRM_MODE_CONNECTOR_DVID;
		333	}
		334
1963	serge	335	/* MSI K9A2GM V2/V3 board has no HDMI or DVI */
		336	if ((dev->pdev->device == 0x796e) &&
		337	(dev->pdev->subsystem_vendor == 0x1462) &&
		338	(dev->pdev->subsystem_device == 0x7302)) {
		339	if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) \|\|
		340	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		341	return false;
		342	}
		343
1117	serge	344	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		345	if ((dev->pdev->device == 0x7941) &&
		346	(dev->pdev->subsystem_vendor == 0x147b) &&
		347	(dev->pdev->subsystem_device == 0x2412)) {
		348	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		349	return false;
		350	}
		351
		352	/* Falcon NW laptop lists vga ddc line for LVDS */
		353	if ((dev->pdev->device == 0x5653) &&
		354	(dev->pdev->subsystem_vendor == 0x1462) &&
		355	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	356	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	357	i2c_bus->valid = false;
1179	serge	358	*line_mux = 53;
		359	}
1117	serge	360	}
		361
1321	serge	362	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		363	if ((dev->pdev->device == 0x7146) &&
		364	(dev->pdev->subsystem_vendor == 0x17af) &&
		365	(dev->pdev->subsystem_device == 0x2058)) {
		366	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		367	return false;
		368	}
		369
		370	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		371	if ((dev->pdev->device == 0x7142) &&
		372	(dev->pdev->subsystem_vendor == 0x1458) &&
		373	(dev->pdev->subsystem_device == 0x2134)) {
		374	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		375	return false;
		376	}
		377
		378
1117	serge	379	/* Funky macbooks */
		380	if ((dev->pdev->device == 0x71C5) &&
		381	(dev->pdev->subsystem_vendor == 0x106b) &&
		382	(dev->pdev->subsystem_device == 0x0080)) {
		383	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		384	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		385	return false;
1963	serge	386	if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
		387	*line_mux = 0x90;
1117	serge	388	}
		389
1963	serge	390	/* mac rv630, rv730, others */
		391	if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
		392	(*connector_type == DRM_MODE_CONNECTOR_DVII)) {
		393	*connector_type = DRM_MODE_CONNECTOR_9PinDIN;
		394	*line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
		395	}
		396
1117	serge	397	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		398	if ((dev->pdev->device == 0x9598) &&
		399	(dev->pdev->subsystem_vendor == 0x1043) &&
		400	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	401	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		402	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	403	}
		404	}
		405
1963	serge	406	/* ASUS HD 3600 board lists the DVI port as HDMI */
		407	if ((dev->pdev->device == 0x9598) &&
		408	(dev->pdev->subsystem_vendor == 0x1043) &&
		409	(dev->pdev->subsystem_device == 0x01e4)) {
		410	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		411	*connector_type = DRM_MODE_CONNECTOR_DVII;
		412	}
		413	}
		414
1179	serge	415	/* ASUS HD 3450 board lists the DVI port as HDMI */
		416	if ((dev->pdev->device == 0x95C5) &&
		417	(dev->pdev->subsystem_vendor == 0x1043) &&
		418	(dev->pdev->subsystem_device == 0x01e2)) {
		419	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		420	*connector_type = DRM_MODE_CONNECTOR_DVII;
		421	}
		422	}
		423
		424	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		425	* HDMI + VGA reporting as HDMI
		426	*/
		427	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		428	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		429	*connector_type = DRM_MODE_CONNECTOR_VGA;
		430	*line_mux = 0;
		431	}
		432	}
		433
1963	serge	434	/* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
		435	* on the laptop and a DVI port on the docking station and
		436	* both share the same encoder, hpd pin, and ddc line.
		437	* So while the bios table is technically correct,
		438	* we drop the DVI port here since xrandr has no concept of
		439	* encoders and will try and drive both connectors
		440	* with different crtcs which isn't possible on the hardware
		441	* side and leaves no crtcs for LVDS or VGA.
		442	*/
		443	if (((dev->pdev->device == 0x95c4) \|\| (dev->pdev->device == 0x9591)) &&
1321	serge	444	(dev->pdev->subsystem_vendor == 0x1025) &&
		445	(dev->pdev->subsystem_device == 0x013c)) {
		446	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
1963	serge	447	(supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
		448	/* actually it's a DVI-D port not DVI-I */
1321	serge	449	*connector_type = DRM_MODE_CONNECTOR_DVID;
1963	serge	450	return false;
		451	}
1321	serge	452	}
		453
1412	serge	454	/* XFX Pine Group device rv730 reports no VGA DDC lines
		455	* even though they are wired up to record 0x93
		456	*/
		457	if ((dev->pdev->device == 0x9498) &&
		458	(dev->pdev->subsystem_vendor == 0x1682) &&
		459	(dev->pdev->subsystem_device == 0x2452)) {
		460	struct radeon_device *rdev = dev->dev_private;
		461	*i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
		462	}
1117	serge	463	return true;
		464	}
		465
		466	const int supported_devices_connector_convert[] = {
		467	DRM_MODE_CONNECTOR_Unknown,
		468	DRM_MODE_CONNECTOR_VGA,
		469	DRM_MODE_CONNECTOR_DVII,
		470	DRM_MODE_CONNECTOR_DVID,
		471	DRM_MODE_CONNECTOR_DVIA,
		472	DRM_MODE_CONNECTOR_SVIDEO,
		473	DRM_MODE_CONNECTOR_Composite,
		474	DRM_MODE_CONNECTOR_LVDS,
		475	DRM_MODE_CONNECTOR_Unknown,
		476	DRM_MODE_CONNECTOR_Unknown,
		477	DRM_MODE_CONNECTOR_HDMIA,
		478	DRM_MODE_CONNECTOR_HDMIB,
		479	DRM_MODE_CONNECTOR_Unknown,
		480	DRM_MODE_CONNECTOR_Unknown,
		481	DRM_MODE_CONNECTOR_9PinDIN,
		482	DRM_MODE_CONNECTOR_DisplayPort
		483	};
		484
1268	serge	485	const uint16_t supported_devices_connector_object_id_convert[] = {
		486	CONNECTOR_OBJECT_ID_NONE,
		487	CONNECTOR_OBJECT_ID_VGA,
		488	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		489	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		490	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		491	CONNECTOR_OBJECT_ID_COMPOSITE,
		492	CONNECTOR_OBJECT_ID_SVIDEO,
		493	CONNECTOR_OBJECT_ID_LVDS,
		494	CONNECTOR_OBJECT_ID_9PIN_DIN,
		495	CONNECTOR_OBJECT_ID_9PIN_DIN,
		496	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		497	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		498	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		499	CONNECTOR_OBJECT_ID_SVIDEO
		500	};
		501
1117	serge	502	const int object_connector_convert[] = {
		503	DRM_MODE_CONNECTOR_Unknown,
		504	DRM_MODE_CONNECTOR_DVII,
		505	DRM_MODE_CONNECTOR_DVII,
		506	DRM_MODE_CONNECTOR_DVID,
		507	DRM_MODE_CONNECTOR_DVID,
		508	DRM_MODE_CONNECTOR_VGA,
		509	DRM_MODE_CONNECTOR_Composite,
		510	DRM_MODE_CONNECTOR_SVIDEO,
		511	DRM_MODE_CONNECTOR_Unknown,
1179	serge	512	DRM_MODE_CONNECTOR_Unknown,
1117	serge	513	DRM_MODE_CONNECTOR_9PinDIN,
		514	DRM_MODE_CONNECTOR_Unknown,
		515	DRM_MODE_CONNECTOR_HDMIA,
		516	DRM_MODE_CONNECTOR_HDMIB,
		517	DRM_MODE_CONNECTOR_LVDS,
		518	DRM_MODE_CONNECTOR_9PinDIN,
		519	DRM_MODE_CONNECTOR_Unknown,
		520	DRM_MODE_CONNECTOR_Unknown,
		521	DRM_MODE_CONNECTOR_Unknown,
1404	serge	522	DRM_MODE_CONNECTOR_DisplayPort,
		523	DRM_MODE_CONNECTOR_eDP,
		524	DRM_MODE_CONNECTOR_Unknown
1117	serge	525	};
		526
		527	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		528	{
		529	struct radeon_device *rdev = dev->dev_private;
		530	struct radeon_mode_info *mode_info = &rdev->mode_info;
		531	struct atom_context *ctx = mode_info->atom_context;
		532	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	533	u16 size, data_offset;
		534	u8 frev, crev;
1117	serge	535	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
1963	serge	536	ATOM_ENCODER_OBJECT_TABLE *enc_obj;
		537	ATOM_OBJECT_TABLE *router_obj;
1117	serge	538	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		539	ATOM_OBJECT_HEADER *obj_header;
1963	serge	540	int i, j, k, path_size, device_support;
1117	serge	541	int connector_type;
1321	serge	542	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	543	struct radeon_i2c_bus_rec ddc_bus;
1963	serge	544	struct radeon_router router;
1321	serge	545	struct radeon_gpio_rec gpio;
		546	struct radeon_hpd hpd;
1117	serge	547
1963	serge	548	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
1117	serge	549	return false;
		550
		551	if (crev < 2)
		552	return false;
		553
		554	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		555	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		556	(ctx->bios + data_offset +
		557	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		558	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		559	(ctx->bios + data_offset +
		560	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
1963	serge	561	enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
		562	(ctx->bios + data_offset +
		563	le16_to_cpu(obj_header->usEncoderObjectTableOffset));
		564	router_obj = (ATOM_OBJECT_TABLE *)
		565	(ctx->bios + data_offset +
		566	le16_to_cpu(obj_header->usRouterObjectTableOffset));
1117	serge	567	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		568
		569	path_size = 0;
		570	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		571	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		572	ATOM_DISPLAY_OBJECT_PATH *path;
		573	addr += path_size;
		574	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		575	path_size += le16_to_cpu(path->usSize);
1963	serge	576
1117	serge	577	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		578	uint8_t con_obj_id, con_obj_num, con_obj_type;
		579
		580	con_obj_id =
		581	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		582	>> OBJECT_ID_SHIFT;
		583	con_obj_num =
		584	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		585	>> ENUM_ID_SHIFT;
		586	con_obj_type =
		587	(le16_to_cpu(path->usConnObjectId) &
		588	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		589
1221	serge	590	/* TODO CV support */
		591	if (le16_to_cpu(path->usDeviceTag) ==
		592	ATOM_DEVICE_CV_SUPPORT)
1117	serge	593	continue;
		594
1268	serge	595	/* IGP chips */
		596	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	597	(con_obj_id ==
		598	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		599	uint16_t igp_offset = 0;
		600	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		601
		602	index =
		603	GetIndexIntoMasterTable(DATA,
		604	IntegratedSystemInfo);
		605
1963	serge	606	if (atom_parse_data_header(ctx, index, &size, &frev,
		607	&crev, &igp_offset)) {
1117	serge	608
		609	if (crev >= 2) {
		610	igp_obj =
		611	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		612	*) (ctx->bios + igp_offset);
		613
		614	if (igp_obj) {
		615	uint32_t slot_config, ct;
		616
		617	if (con_obj_num == 1)
		618	slot_config =
		619	igp_obj->
		620	ulDDISlot1Config;
		621	else
		622	slot_config =
		623	igp_obj->
		624	ulDDISlot2Config;
		625
		626	ct = (slot_config >> 16) & 0xff;
		627	connector_type =
		628	object_connector_convert
		629	[ct];
1268	serge	630	connector_object_id = ct;
1117	serge	631	igp_lane_info =
		632	slot_config & 0xffff;
		633	} else
		634	continue;
		635	} else
		636	continue;
		637	} else {
		638	igp_lane_info = 0;
		639	connector_type =
		640	object_connector_convert[con_obj_id];
1268	serge	641	connector_object_id = con_obj_id;
1117	serge	642	}
1963	serge	643	} else {
		644	igp_lane_info = 0;
		645	connector_type =
		646	object_connector_convert[con_obj_id];
		647	connector_object_id = con_obj_id;
		648	}
1117	serge	649
		650	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		651	continue;
		652
1963	serge	653	router.ddc_valid = false;
		654	router.cd_valid = false;
		655	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
		656	uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
1117	serge	657
1963	serge	658	grph_obj_id =
1117	serge	659	(le16_to_cpu(path->usGraphicObjIds[j]) &
		660	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1963	serge	661	grph_obj_num =
1117	serge	662	(le16_to_cpu(path->usGraphicObjIds[j]) &
		663	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1963	serge	664	grph_obj_type =
1117	serge	665	(le16_to_cpu(path->usGraphicObjIds[j]) &
		666	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		667
1963	serge	668	if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		669	for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
		670	u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
		671	if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
		672	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		673	(ctx->bios + data_offset +
		674	le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
		675	ATOM_ENCODER_CAP_RECORD *cap_record;
		676	u16 caps = 0;
1117	serge	677
1963	serge	678	while (record->ucRecordSize > 0 &&
		679	record->ucRecordType > 0 &&
		680	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		681	switch (record->ucRecordType) {
		682	case ATOM_ENCODER_CAP_RECORD_TYPE:
		683	cap_record =(ATOM_ENCODER_CAP_RECORD *)
		684	record;
		685	caps = le16_to_cpu(cap_record->usEncoderCap);
		686	break;
		687	}
		688	record = (ATOM_COMMON_RECORD_HEADER *)
		689	((char *)record + record->ucRecordSize);
		690	}
1123	serge	691	radeon_add_atom_encoder(dev,
1963	serge	692	encoder_obj,
1123	serge	693	le16_to_cpu
		694	(path->
1963	serge	695	usDeviceTag),
		696	caps);
		697	}
		698	}
		699	} else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
		700	for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
		701	u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
		702	if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
		703	ATOM_COMMON_RECORD_HEADER record = (ATOM_COMMON_RECORD_HEADER )
		704	(ctx->bios + data_offset +
		705	le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
		706	ATOM_I2C_RECORD *i2c_record;
		707	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		708	ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
		709	ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
		710	ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
		711	(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
		712	(ctx->bios + data_offset +
		713	le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
		714	int enum_id;
1117	serge	715
1963	serge	716	router.router_id = router_obj_id;
		717	for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
		718	enum_id++) {
		719	if (le16_to_cpu(path->usConnObjectId) ==
		720	le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
		721	break;
		722	}
		723
		724	while (record->ucRecordSize > 0 &&
		725	record->ucRecordType > 0 &&
		726	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
		727	switch (record->ucRecordType) {
		728	case ATOM_I2C_RECORD_TYPE:
		729	i2c_record =
		730	(ATOM_I2C_RECORD *)
		731	record;
		732	i2c_config =
		733	(ATOM_I2C_ID_CONFIG_ACCESS *)
		734	&i2c_record->sucI2cId;
		735	router.i2c_info =
		736	radeon_lookup_i2c_gpio(rdev,
		737	i2c_config->
		738	ucAccess);
		739	router.i2c_addr = i2c_record->ucI2CAddr >> 1;
		740	break;
		741	case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
		742	ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
		743	record;
		744	router.ddc_valid = true;
		745	router.ddc_mux_type = ddc_path->ucMuxType;
		746	router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
		747	router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
		748	break;
		749	case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
		750	cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
		751	record;
		752	router.cd_valid = true;
		753	router.cd_mux_type = cd_path->ucMuxType;
		754	router.cd_mux_control_pin = cd_path->ucMuxControlPin;
		755	router.cd_mux_state = cd_path->ucMuxState[enum_id];
		756	break;
		757	}
		758	record = (ATOM_COMMON_RECORD_HEADER *)
		759	((char *)record + record->ucRecordSize);
		760	}
		761	}
		762	}
1117	serge	763	}
		764	}
		765
1321	serge	766	/* look up gpio for ddc, hpd */
1963	serge	767	ddc_bus.valid = false;
		768	hpd.hpd = RADEON_HPD_NONE;
1117	serge	769	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	770	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	771	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		772	if (le16_to_cpu(path->usConnObjectId) ==
		773	le16_to_cpu(con_obj->asObjects[j].
		774	usObjectID)) {
		775	ATOM_COMMON_RECORD_HEADER
		776	*record =
		777	(ATOM_COMMON_RECORD_HEADER
		778	*)
		779	(ctx->bios + data_offset +
		780	le16_to_cpu(con_obj->
		781	asObjects[j].
		782	usRecordOffset));
		783	ATOM_I2C_RECORD *i2c_record;
1321	serge	784	ATOM_HPD_INT_RECORD *hpd_record;
		785	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
1117	serge	786
1963	serge	787	while (record->ucRecordSize > 0 &&
		788	record->ucRecordType > 0 &&
		789	record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	790	switch (record->ucRecordType) {
1117	serge	791	case ATOM_I2C_RECORD_TYPE:
		792	i2c_record =
1321	serge	793	(ATOM_I2C_RECORD *)
		794	record;
		795	i2c_config =
		796	(ATOM_I2C_ID_CONFIG_ACCESS *)
		797	&i2c_record->sucI2cId;
		798	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		799	i2c_config->
		800	ucAccess);
1117	serge	801	break;
1321	serge	802	case ATOM_HPD_INT_RECORD_TYPE:
		803	hpd_record =
		804	(ATOM_HPD_INT_RECORD *)
		805	record;
		806	gpio = radeon_lookup_gpio(rdev,
		807	hpd_record->ucHPDIntGPIOID);
		808	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		809	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		810	break;
1117	serge	811	}
		812	record =
		813	(ATOM_COMMON_RECORD_HEADER
		814	) ((char )record
		815	+
		816	record->
		817	ucRecordSize);
		818	}
		819	break;
		820	}
		821	}
1321	serge	822	}
1117	serge	823
1430	serge	824	/* needed for aux chan transactions */
1963	serge	825	ddc_bus.hpd = hpd.hpd;
1430	serge	826
1179	serge	827	conn_id = le16_to_cpu(path->usConnObjectId);
		828
		829	if (!radeon_atom_apply_quirks
		830	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	831	&ddc_bus, &conn_id, &hpd))
1179	serge	832	continue;
		833
1123	serge	834	radeon_add_atom_connector(dev,
1179	serge	835	conn_id,
1123	serge	836	le16_to_cpu(path->
		837	usDeviceTag),
		838	connector_type, &ddc_bus,
1963	serge	839	igp_lane_info,
1321	serge	840	connector_object_id,
1963	serge	841	&hpd,
		842	&router);
1117	serge	843
		844	}
		845	}
		846
1123	serge	847	radeon_link_encoder_connector(dev);
1117	serge	848
		849	return true;
		850	}
		851
1268	serge	852	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		853	int connector_type,
		854	uint16_t devices)
		855	{
		856	struct radeon_device *rdev = dev->dev_private;
		857
		858	if (rdev->flags & RADEON_IS_IGP) {
		859	return supported_devices_connector_object_id_convert
		860	[connector_type];
		861	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		862	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		863	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		864	struct radeon_mode_info *mode_info = &rdev->mode_info;
		865	struct atom_context *ctx = mode_info->atom_context;
		866	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		867	uint16_t size, data_offset;
		868	uint8_t frev, crev;
		869	ATOM_XTMDS_INFO *xtmds;
		870
1963	serge	871	if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
1268	serge	872	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		873
		874	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		875	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		876	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		877	else
		878	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		879	} else {
		880	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		881	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		882	else
		883	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		884	}
1963	serge	885	} else
		886	return supported_devices_connector_object_id_convert
		887	[connector_type];
1268	serge	888	} else {
		889	return supported_devices_connector_object_id_convert
		890	[connector_type];
		891	}
		892	}
		893
1117	serge	894	struct bios_connector {
		895	bool valid;
1179	serge	896	uint16_t line_mux;
1117	serge	897	uint16_t devices;
		898	int connector_type;
		899	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	900	struct radeon_hpd hpd;
1117	serge	901	};
		902
		903	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		904	drm_device
		905	*dev)
		906	{
		907	struct radeon_device *rdev = dev->dev_private;
		908	struct radeon_mode_info *mode_info = &rdev->mode_info;
		909	struct atom_context *ctx = mode_info->atom_context;
		910	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		911	uint16_t size, data_offset;
		912	uint8_t frev, crev;
		913	uint16_t device_support;
		914	uint8_t dac;
		915	union atom_supported_devices *supported_devices;
1321	serge	916	int i, j, max_device;
1963	serge	917	struct bios_connector *bios_connectors;
		918	size_t bc_size = sizeof(bios_connectors) ATOM_MAX_SUPPORTED_DEVICE;
		919	struct radeon_router router;
1117	serge	920
1963	serge	921	router.ddc_valid = false;
		922	router.cd_valid = false;
1128	serge	923
1963	serge	924	bios_connectors = kzalloc(bc_size, GFP_KERNEL);
		925	if (!bios_connectors)
		926	return false;
		927
		928	if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
		929	&data_offset)) {
		930	kfree(bios_connectors);
		931	return false;
		932	}
		933
1117	serge	934	supported_devices =
		935	(union atom_supported_devices *)(ctx->bios + data_offset);
		936
		937	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		938
1321	serge	939	if (frev > 1)
		940	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		941	else
		942	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		943
		944	for (i = 0; i < max_device; i++) {
1117	serge	945	ATOM_CONNECTOR_INFO_I2C ci =
		946	supported_devices->info.asConnInfo[i];
		947
		948	bios_connectors[i].valid = false;
		949
		950	if (!(device_support & (1 << i))) {
		951	continue;
		952	}
		953
		954	if (i == ATOM_DEVICE_CV_INDEX) {
1963	serge	955	DRM_DEBUG_KMS("Skipping Component Video\n");
1117	serge	956	continue;
		957	}
		958
		959	bios_connectors[i].connector_type =
		960	supported_devices_connector_convert[ci.sucConnectorInfo.
		961	sbfAccess.
		962	bfConnectorType];
		963
		964	if (bios_connectors[i].connector_type ==
		965	DRM_MODE_CONNECTOR_Unknown)
		966	continue;
		967
		968	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		969
		970	bios_connectors[i].line_mux =
1321	serge	971	ci.sucI2cId.ucAccess;
1117	serge	972
		973	/* give tv unique connector ids */
		974	if (i == ATOM_DEVICE_TV1_INDEX) {
		975	bios_connectors[i].ddc_bus.valid = false;
		976	bios_connectors[i].line_mux = 50;
		977	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		978	bios_connectors[i].ddc_bus.valid = false;
		979	bios_connectors[i].line_mux = 51;
		980	} else if (i == ATOM_DEVICE_CV_INDEX) {
		981	bios_connectors[i].ddc_bus.valid = false;
		982	bios_connectors[i].line_mux = 52;
		983	} else
		984	bios_connectors[i].ddc_bus =
1321	serge	985	radeon_lookup_i2c_gpio(rdev,
1117	serge	986	bios_connectors[i].line_mux);
		987
1321	serge	988	if ((crev > 1) && (frev > 1)) {
		989	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		990	switch (isb) {
		991	case 0x4:
		992	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		993	break;
		994	case 0xa:
		995	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		996	break;
		997	default:
		998	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		999	break;
		1000	}
		1001	} else {
		1002	if (i == ATOM_DEVICE_DFP1_INDEX)
		1003	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		1004	else if (i == ATOM_DEVICE_DFP2_INDEX)
		1005	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		1006	else
		1007	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		1008	}
		1009
1117	serge	1010	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		1011	* shared with a DVI port, we'll pick up the DVI connector when we
		1012	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		1013	*/
		1014	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		1015	bios_connectors[i].connector_type =
		1016	DRM_MODE_CONNECTOR_VGA;
		1017
		1018	if (!radeon_atom_apply_quirks
		1019	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	1020	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		1021	&bios_connectors[i].hpd))
1117	serge	1022	continue;
		1023
		1024	bios_connectors[i].valid = true;
		1025	bios_connectors[i].devices = (1 << i);
		1026
1123	serge	1027	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		1028	radeon_add_atom_encoder(dev,
1963	serge	1029	radeon_get_encoder_enum(dev,
1123	serge	1030	(1 << i),
		1031	dac),
1963	serge	1032	(1 << i),
		1033	0);
1123	serge	1034	else
		1035	radeon_add_legacy_encoder(dev,
1963	serge	1036	radeon_get_encoder_enum(dev,
1404	serge	1037	(1 << i),
1123	serge	1038	dac),
		1039	(1 << i));
1117	serge	1040	}
		1041
		1042	/* combine shared connectors */
1321	serge	1043	for (i = 0; i < max_device; i++) {
1117	serge	1044	if (bios_connectors[i].valid) {
1321	serge	1045	for (j = 0; j < max_device; j++) {
1117	serge	1046	if (bios_connectors[j].valid && (i != j)) {
		1047	if (bios_connectors[i].line_mux ==
		1048	bios_connectors[j].line_mux) {
1404	serge	1049	/* make sure not to combine LVDS */
		1050	if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1051	bios_connectors[i].line_mux = 53;
		1052	bios_connectors[i].ddc_bus.valid = false;
		1053	continue;
		1054	}
		1055	if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		1056	bios_connectors[j].line_mux = 53;
		1057	bios_connectors[j].ddc_bus.valid = false;
		1058	continue;
		1059	}
		1060	/* combine analog and digital for DVI-I */
		1061	if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1062	(bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) \|\|
		1063	((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		1064	(bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
		1065	bios_connectors[i].devices \|=
		1066	bios_connectors[j].devices;
		1067	bios_connectors[i].connector_type =
1117	serge	1068	DRM_MODE_CONNECTOR_DVII;
1404	serge	1069	if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1321	serge	1070	bios_connectors[i].hpd =
		1071	bios_connectors[j].hpd;
1404	serge	1072	bios_connectors[j].valid = false;
1117	serge	1073	}
		1074	}
		1075	}
		1076	}
		1077	}
		1078	}
		1079
		1080	/* add the connectors */
1321	serge	1081	for (i = 0; i < max_device; i++) {
1268	serge	1082	if (bios_connectors[i].valid) {
		1083	uint16_t connector_object_id =
		1084	atombios_get_connector_object_id(dev,
		1085	bios_connectors[i].connector_type,
		1086	bios_connectors[i].devices);
1123	serge	1087	radeon_add_atom_connector(dev,
		1088	bios_connectors[i].line_mux,
		1089	bios_connectors[i].devices,
		1090	bios_connectors[i].
		1091	connector_type,
		1092	&bios_connectors[i].ddc_bus,
1963	serge	1093	0,
1321	serge	1094	connector_object_id,
1963	serge	1095	&bios_connectors[i].hpd,
		1096	&router);
1268	serge	1097	}
1123	serge	1098	}
1117	serge	1099
1123	serge	1100	radeon_link_encoder_connector(dev);
1128	serge	1101
1963	serge	1102	kfree(bios_connectors);
1117	serge	1103	return true;
		1104	}
		1105
		1106	union firmware_info {
		1107	ATOM_FIRMWARE_INFO info;
		1108	ATOM_FIRMWARE_INFO_V1_2 info_12;
		1109	ATOM_FIRMWARE_INFO_V1_3 info_13;
		1110	ATOM_FIRMWARE_INFO_V1_4 info_14;
1430	serge	1111	ATOM_FIRMWARE_INFO_V2_1 info_21;
1963	serge	1112	ATOM_FIRMWARE_INFO_V2_2 info_22;
1117	serge	1113	};
		1114
		1115	bool radeon_atom_get_clock_info(struct drm_device *dev)
		1116	{
		1117	struct radeon_device *rdev = dev->dev_private;
		1118	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1119	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		1120	union firmware_info *firmware_info;
		1121	uint8_t frev, crev;
		1122	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		1123	struct radeon_pll *p2pll = &rdev->clock.p2pll;
1430	serge	1124	struct radeon_pll *dcpll = &rdev->clock.dcpll;
1117	serge	1125	struct radeon_pll *spll = &rdev->clock.spll;
		1126	struct radeon_pll *mpll = &rdev->clock.mpll;
		1127	uint16_t data_offset;
		1128
1963	serge	1129	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1130	&frev, &crev, &data_offset)) {
1117	serge	1131	firmware_info =
		1132	(union firmware_info *)(mode_info->atom_context->bios +
		1133	data_offset);
		1134	/* pixel clocks */
		1135	p1pll->reference_freq =
		1136	le16_to_cpu(firmware_info->info.usReferenceClock);
		1137	p1pll->reference_div = 0;
		1138
1268	serge	1139	if (crev < 2)
1117	serge	1140	p1pll->pll_out_min =
		1141	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	1142	else
		1143	p1pll->pll_out_min =
		1144	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	1145	p1pll->pll_out_max =
		1146	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		1147
1963	serge	1148	if (crev >= 4) {
		1149	p1pll->lcd_pll_out_min =
		1150	le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
		1151	if (p1pll->lcd_pll_out_min == 0)
		1152	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1153	p1pll->lcd_pll_out_max =
		1154	le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
		1155	if (p1pll->lcd_pll_out_max == 0)
		1156	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1157	} else {
		1158	p1pll->lcd_pll_out_min = p1pll->pll_out_min;
		1159	p1pll->lcd_pll_out_max = p1pll->pll_out_max;
		1160	}
		1161
1117	serge	1162	if (p1pll->pll_out_min == 0) {
		1163	if (ASIC_IS_AVIVO(rdev))
		1164	p1pll->pll_out_min = 64800;
		1165	else
		1166	p1pll->pll_out_min = 20000;
		1167	}
		1168
		1169	p1pll->pll_in_min =
		1170	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		1171	p1pll->pll_in_max =
		1172	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		1173
		1174	p2pll = p1pll;
		1175
		1176	/* system clock */
1963	serge	1177	if (ASIC_IS_DCE4(rdev))
		1178	spll->reference_freq =
		1179	le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
		1180	else
1117	serge	1181	spll->reference_freq =
		1182	le16_to_cpu(firmware_info->info.usReferenceClock);
		1183	spll->reference_div = 0;
		1184
		1185	spll->pll_out_min =
		1186	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		1187	spll->pll_out_max =
		1188	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		1189
		1190	/* ??? */
		1191	if (spll->pll_out_min == 0) {
		1192	if (ASIC_IS_AVIVO(rdev))
		1193	spll->pll_out_min = 64800;
		1194	else
		1195	spll->pll_out_min = 20000;
		1196	}
		1197
		1198	spll->pll_in_min =
		1199	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		1200	spll->pll_in_max =
		1201	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		1202
		1203	/* memory clock */
1963	serge	1204	if (ASIC_IS_DCE4(rdev))
		1205	mpll->reference_freq =
		1206	le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
		1207	else
1117	serge	1208	mpll->reference_freq =
		1209	le16_to_cpu(firmware_info->info.usReferenceClock);
		1210	mpll->reference_div = 0;
		1211
		1212	mpll->pll_out_min =
		1213	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		1214	mpll->pll_out_max =
		1215	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		1216
		1217	/* ??? */
		1218	if (mpll->pll_out_min == 0) {
		1219	if (ASIC_IS_AVIVO(rdev))
		1220	mpll->pll_out_min = 64800;
		1221	else
		1222	mpll->pll_out_min = 20000;
		1223	}
		1224
		1225	mpll->pll_in_min =
		1226	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		1227	mpll->pll_in_max =
		1228	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		1229
		1230	rdev->clock.default_sclk =
		1231	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		1232	rdev->clock.default_mclk =
		1233	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		1234
1430	serge	1235	if (ASIC_IS_DCE4(rdev)) {
		1236	rdev->clock.default_dispclk =
		1237	le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1963	serge	1238	if (rdev->clock.default_dispclk == 0) {
		1239	if (ASIC_IS_DCE5(rdev))
		1240	rdev->clock.default_dispclk = 54000; /* 540 Mhz */
		1241	else
1430	serge	1242	rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1963	serge	1243	}
1430	serge	1244	rdev->clock.dp_extclk =
		1245	le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
		1246	}
		1247	dcpll = p1pll;
		1248
1963	serge	1249	rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
		1250	if (rdev->clock.max_pixel_clock == 0)
		1251	rdev->clock.max_pixel_clock = 40000;
		1252
1117	serge	1253	return true;
		1254	}
1430	serge	1255
1117	serge	1256	return false;
		1257	}
		1258
1404	serge	1259	union igp_info {
		1260	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		1261	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
		1262	};
		1263
		1264	bool radeon_atombios_sideport_present(struct radeon_device *rdev)
		1265	{
		1266	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1267	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1268	union igp_info *igp_info;
		1269	u8 frev, crev;
		1270	u16 data_offset;
		1271
1963	serge	1272	/* sideport is AMD only */
		1273	if (rdev->family == CHIP_RS600)
		1274	return false;
1404	serge	1275
1963	serge	1276	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1277	&frev, &crev, &data_offset)) {
1404	serge	1278	igp_info = (union igp_info *)(mode_info->atom_context->bios +
		1279	data_offset);
		1280	switch (crev) {
		1281	case 1:
1963	serge	1282	if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1404	serge	1283	return true;
		1284	break;
		1285	case 2:
1963	serge	1286	if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1404	serge	1287	return true;
		1288	break;
		1289	default:
		1290	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		1291	break;
		1292	}
		1293	}
		1294	return false;
		1295	}
		1296
1179	serge	1297	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		1298	struct radeon_encoder_int_tmds *tmds)
1117	serge	1299	{
		1300	struct drm_device *dev = encoder->base.dev;
		1301	struct radeon_device *rdev = dev->dev_private;
		1302	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1303	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		1304	uint16_t data_offset;
		1305	struct _ATOM_TMDS_INFO *tmds_info;
		1306	uint8_t frev, crev;
		1307	uint16_t maxfreq;
		1308	int i;
		1309
1963	serge	1310	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1311	&frev, &crev, &data_offset)) {
1117	serge	1312	tmds_info =
		1313	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		1314	data_offset);
		1315
		1316	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		1317	for (i = 0; i < 4; i++) {
		1318	tmds->tmds_pll[i].freq =
		1319	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		1320	tmds->tmds_pll[i].value =
		1321	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		1322	tmds->tmds_pll[i].value \|=
		1323	(tmds_info->asMiscInfo[i].
		1324	ucPLL_VCO_Gain & 0x3f) << 6;
		1325	tmds->tmds_pll[i].value \|=
		1326	(tmds_info->asMiscInfo[i].
		1327	ucPLL_DutyCycle & 0xf) << 12;
		1328	tmds->tmds_pll[i].value \|=
		1329	(tmds_info->asMiscInfo[i].
		1330	ucPLL_VoltageSwing & 0xf) << 16;
		1331
1963	serge	1332	DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1117	serge	1333	tmds->tmds_pll[i].freq,
		1334	tmds->tmds_pll[i].value);
		1335
		1336	if (maxfreq == tmds->tmds_pll[i].freq) {
		1337	tmds->tmds_pll[i].freq = 0xffffffff;
		1338	break;
		1339	}
		1340	}
1179	serge	1341	return true;
1117	serge	1342	}
1179	serge	1343	return false;
1117	serge	1344	}
		1345
1963	serge	1346	bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
		1347	struct radeon_atom_ss *ss,
1268	serge	1348	int id)
		1349	{
		1350	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1351	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1963	serge	1352	uint16_t data_offset, size;
1268	serge	1353	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1354	uint8_t frev, crev;
1963	serge	1355	int i, num_indices;
1268	serge	1356
1963	serge	1357	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1358	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1359	&frev, &crev, &data_offset)) {
1268	serge	1360	ss_info =
		1361	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1362
1963	serge	1363	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1364	sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1268	serge	1365
1963	serge	1366	for (i = 0; i < num_indices; i++) {
1321	serge	1367	if (ss_info->asSS_Info[i].ucSS_Id == id) {
		1368	ss->percentage =
		1369	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
		1370	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
		1371	ss->step = ss_info->asSS_Info[i].ucSS_Step;
		1372	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
		1373	ss->range = ss_info->asSS_Info[i].ucSS_Range;
		1374	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1963	serge	1375	return true;
		1376	}
		1377	}
1268	serge	1378	}
1963	serge	1379	return false;
		1380	}
		1381
		1382	static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
		1383	struct radeon_atom_ss *ss,
		1384	int id)
		1385	{
		1386	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1387	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		1388	u16 data_offset, size;
		1389	struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
		1390	u8 frev, crev;
		1391	u16 percentage = 0, rate = 0;
		1392
		1393	/* get any igp specific overrides */
		1394	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1395	&frev, &crev, &data_offset)) {
		1396	igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
		1397	(mode_info->atom_context->bios + data_offset);
		1398	switch (id) {
		1399	case ASIC_INTERNAL_SS_ON_TMDS:
		1400	percentage = le16_to_cpu(igp_info->usDVISSPercentage);
		1401	rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
		1402	break;
		1403	case ASIC_INTERNAL_SS_ON_HDMI:
		1404	percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
		1405	rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
		1406	break;
		1407	case ASIC_INTERNAL_SS_ON_LVDS:
		1408	percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
		1409	rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
		1410	break;
1321	serge	1411	}
1963	serge	1412	if (percentage)
		1413	ss->percentage = percentage;
		1414	if (rate)
		1415	ss->rate = rate;
1321	serge	1416	}
1268	serge	1417	}
		1418
1963	serge	1419	union asic_ss_info {
		1420	struct _ATOM_ASIC_INTERNAL_SS_INFO info;
		1421	struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
		1422	struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
		1423	};
		1424
		1425	bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
		1426	struct radeon_atom_ss *ss,
		1427	int id, u32 clock)
1430	serge	1428	{
1963	serge	1429	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1430	int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
		1431	uint16_t data_offset, size;
		1432	union asic_ss_info *ss_info;
		1433	uint8_t frev, crev;
		1434	int i, num_indices;
1430	serge	1435
1963	serge	1436	memset(ss, 0, sizeof(struct radeon_atom_ss));
		1437	if (atom_parse_data_header(mode_info->atom_context, index, &size,
		1438	&frev, &crev, &data_offset)) {
		1439
		1440	ss_info =
		1441	(union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
		1442
		1443	switch (frev) {
		1444	case 1:
		1445	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1446	sizeof(ATOM_ASIC_SS_ASSIGNMENT);
		1447
		1448	for (i = 0; i < num_indices; i++) {
		1449	if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
		1450	(clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
		1451	ss->percentage =
		1452	le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1453	ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1454	ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
		1455	return true;
		1456	}
		1457	}
		1458	break;
		1459	case 2:
		1460	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1461	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
		1462	for (i = 0; i < num_indices; i++) {
		1463	if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
		1464	(clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
		1465	ss->percentage =
		1466	le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1467	ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1468	ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
		1469	return true;
		1470	}
1430	serge	1471	}
1963	serge	1472	break;
		1473	case 3:
		1474	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
		1475	sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
		1476	for (i = 0; i < num_indices; i++) {
		1477	if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
		1478	(clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
		1479	ss->percentage =
		1480	le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
		1481	ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
		1482	ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
		1483	if (rdev->flags & RADEON_IS_IGP)
		1484	radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
		1485	return true;
		1486	}
		1487	}
		1488	break;
		1489	default:
		1490	DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
		1491	break;
		1492	}
1430	serge	1493
		1494	}
1963	serge	1495	return false;
1430	serge	1496	}
		1497
1117	serge	1498	union lvds_info {
		1499	struct _ATOM_LVDS_INFO info;
		1500	struct _ATOM_LVDS_INFO_V12 info_12;
		1501	};
		1502
		1503	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1504	radeon_encoder
		1505	*encoder)
		1506	{
		1507	struct drm_device *dev = encoder->base.dev;
		1508	struct radeon_device *rdev = dev->dev_private;
		1509	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1510	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1511	uint16_t data_offset, misc;
1117	serge	1512	union lvds_info *lvds_info;
		1513	uint8_t frev, crev;
		1514	struct radeon_encoder_atom_dig *lvds = NULL;
1963	serge	1515	int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1117	serge	1516
1963	serge	1517	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1518	&frev, &crev, &data_offset)) {
1117	serge	1519	lvds_info =
		1520	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1521	lvds =
		1522	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1523
		1524	if (!lvds)
		1525	return NULL;
		1526
1268	serge	1527	lvds->native_mode.clock =
1117	serge	1528	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1529	lvds->native_mode.hdisplay =
1117	serge	1530	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1531	lvds->native_mode.vdisplay =
1117	serge	1532	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1533	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1534	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1535	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1536	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1537	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1538	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1539	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1540	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1541	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1963	serge	1542	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1268	serge	1543	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1544	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1545	lvds->panel_pwr_delay =
		1546	le16_to_cpu(lvds_info->info.usOffDelayInMs);
1963	serge	1547	lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1548
		1549	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1550	if (misc & ATOM_VSYNC_POLARITY)
		1551	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1552	if (misc & ATOM_HSYNC_POLARITY)
		1553	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1554	if (misc & ATOM_COMPOSITESYNC)
		1555	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1556	if (misc & ATOM_INTERLACE)
		1557	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1558	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1559	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1560
1963	serge	1561	lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
		1562	lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
		1563
1268	serge	1564	/* set crtc values */
		1565	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1566
1963	serge	1567	lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1268	serge	1568
1963	serge	1569	encoder->native_mode = lvds->native_mode;
		1570
		1571	if (encoder_enum == 2)
		1572	lvds->linkb = true;
		1573	else
		1574	lvds->linkb = false;
		1575
		1576	/* parse the lcd record table */
		1577	if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
		1578	ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
		1579	ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
		1580	bool bad_record = false;
		1581	u8 *record;
		1582
		1583	if ((frev == 1) && (crev < 2))
		1584	/* absolute */
		1585	record = (u8 *)(mode_info->atom_context->bios +
		1586	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1430	serge	1587	else
1963	serge	1588	/* relative */
		1589	record = (u8 *)(mode_info->atom_context->bios +
		1590	data_offset +
		1591	le16_to_cpu(lvds_info->info.usModePatchTableOffset));
		1592	while (*record != ATOM_RECORD_END_TYPE) {
		1593	switch (*record) {
		1594	case LCD_MODE_PATCH_RECORD_MODE_TYPE:
		1595	record += sizeof(ATOM_PATCH_RECORD_MODE);
		1596	break;
		1597	case LCD_RTS_RECORD_TYPE:
		1598	record += sizeof(ATOM_LCD_RTS_RECORD);
		1599	break;
		1600	case LCD_CAP_RECORD_TYPE:
		1601	record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
		1602	break;
		1603	case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
		1604	fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
		1605	if (fake_edid_record->ucFakeEDIDLength) {
		1606	struct edid *edid;
		1607	int edid_size =
		1608	max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
		1609	edid = kmalloc(edid_size, GFP_KERNEL);
		1610	if (edid) {
		1611	memcpy((u8 )edid, (u8 )&fake_edid_record->ucFakeEDIDString[0],
		1612	fake_edid_record->ucFakeEDIDLength);
		1613
		1614	if (drm_edid_is_valid(edid)) {
		1615	rdev->mode_info.bios_hardcoded_edid = edid;
		1616	rdev->mode_info.bios_hardcoded_edid_size = edid_size;
		1617	} else
		1618	kfree(edid);
		1619	}
		1620	}
		1621	record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
		1622	break;
		1623	case LCD_PANEL_RESOLUTION_RECORD_TYPE:
		1624	panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
		1625	lvds->native_mode.width_mm = panel_res_record->usHSize;
		1626	lvds->native_mode.height_mm = panel_res_record->usVSize;
		1627	record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
		1628	break;
		1629	default:
		1630	DRM_ERROR("Bad LCD record %d\n", *record);
		1631	bad_record = true;
		1632	break;
		1633	}
		1634	if (bad_record)
		1635	break;
		1636	}
1430	serge	1637	}
1117	serge	1638	}
		1639	return lvds;
		1640	}
		1641
		1642	struct radeon_encoder_primary_dac *
		1643	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1644	{
		1645	struct drm_device *dev = encoder->base.dev;
		1646	struct radeon_device *rdev = dev->dev_private;
		1647	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1648	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1649	uint16_t data_offset;
		1650	struct _COMPASSIONATE_DATA *dac_info;
		1651	uint8_t frev, crev;
		1652	uint8_t bg, dac;
		1653	struct radeon_encoder_primary_dac *p_dac = NULL;
		1654
1963	serge	1655	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1656	&frev, &crev, &data_offset)) {
		1657	dac_info = (struct _COMPASSIONATE_DATA *)
		1658	(mode_info->atom_context->bios + data_offset);
1117	serge	1659
		1660	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1661
		1662	if (!p_dac)
		1663	return NULL;
		1664
		1665	bg = dac_info->ucDAC1_BG_Adjustment;
		1666	dac = dac_info->ucDAC1_DAC_Adjustment;
		1667	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1668
		1669	}
		1670	return p_dac;
		1671	}
		1672
1179	serge	1673	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1674	struct drm_display_mode *mode)
1179	serge	1675	{
		1676	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1677	ATOM_ANALOG_TV_INFO *tv_info;
		1678	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1679	ATOM_DTD_FORMAT *dtd_timings;
		1680	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1681	u8 frev, crev;
1268	serge	1682	u16 data_offset, misc;
1179	serge	1683
1963	serge	1684	if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
		1685	&frev, &crev, &data_offset))
		1686	return false;
1179	serge	1687
		1688	switch (crev) {
		1689	case 1:
		1690	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1963	serge	1691	if (index >= MAX_SUPPORTED_TV_TIMING)
1179	serge	1692	return false;
		1693
1268	serge	1694	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1695	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1696	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1697	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1698	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1699
1268	serge	1700	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1701	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1702	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1703	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1704	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1705
1268	serge	1706	mode->flags = 0;
		1707	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1708	if (misc & ATOM_VSYNC_POLARITY)
		1709	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1710	if (misc & ATOM_HSYNC_POLARITY)
		1711	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1712	if (misc & ATOM_COMPOSITESYNC)
		1713	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1714	if (misc & ATOM_INTERLACE)
		1715	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1716	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1717	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1718
1268	serge	1719	mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1720
		1721	if (index == 1) {
		1722	/* PAL timings appear to have wrong values for totals */
1268	serge	1723	mode->crtc_htotal -= 1;
		1724	mode->crtc_vtotal -= 1;
1179	serge	1725	}
		1726	break;
		1727	case 2:
		1728	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1963	serge	1729	if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1179	serge	1730	return false;
		1731
		1732	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1733	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1734	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1735	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1736	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1737	le16_to_cpu(dtd_timings->usHSyncOffset);
		1738	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1739	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1740
1268	serge	1741	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1742	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1743	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1744	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1745	le16_to_cpu(dtd_timings->usVSyncOffset);
		1746	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1747	le16_to_cpu(dtd_timings->usVSyncWidth);
		1748
		1749	mode->flags = 0;
		1750	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1751	if (misc & ATOM_VSYNC_POLARITY)
		1752	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1753	if (misc & ATOM_HSYNC_POLARITY)
		1754	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1755	if (misc & ATOM_COMPOSITESYNC)
		1756	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1757	if (misc & ATOM_INTERLACE)
		1758	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1759	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1760	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1761
		1762	mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1763	break;
		1764	}
		1765	return true;
		1766	}
		1767
1404	serge	1768	enum radeon_tv_std
		1769	radeon_atombios_get_tv_info(struct radeon_device *rdev)
		1770	{
		1771	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1772	int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1773	uint16_t data_offset;
		1774	uint8_t frev, crev;
		1775	struct _ATOM_ANALOG_TV_INFO *tv_info;
		1776	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1777
1963	serge	1778	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1779	&frev, &crev, &data_offset)) {
1404	serge	1780
1963	serge	1781	tv_info = (struct _ATOM_ANALOG_TV_INFO *)
		1782	(mode_info->atom_context->bios + data_offset);
1404	serge	1783
		1784	switch (tv_info->ucTV_BootUpDefaultStandard) {
		1785	case ATOM_TV_NTSC:
		1786	tv_std = TV_STD_NTSC;
1963	serge	1787	DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1404	serge	1788	break;
		1789	case ATOM_TV_NTSCJ:
		1790	tv_std = TV_STD_NTSC_J;
1963	serge	1791	DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1404	serge	1792	break;
		1793	case ATOM_TV_PAL:
		1794	tv_std = TV_STD_PAL;
1963	serge	1795	DRM_DEBUG_KMS("Default TV standard: PAL\n");
1404	serge	1796	break;
		1797	case ATOM_TV_PALM:
		1798	tv_std = TV_STD_PAL_M;
1963	serge	1799	DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1404	serge	1800	break;
		1801	case ATOM_TV_PALN:
		1802	tv_std = TV_STD_PAL_N;
1963	serge	1803	DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1404	serge	1804	break;
		1805	case ATOM_TV_PALCN:
		1806	tv_std = TV_STD_PAL_CN;
1963	serge	1807	DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1404	serge	1808	break;
		1809	case ATOM_TV_PAL60:
		1810	tv_std = TV_STD_PAL_60;
1963	serge	1811	DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1404	serge	1812	break;
		1813	case ATOM_TV_SECAM:
		1814	tv_std = TV_STD_SECAM;
1963	serge	1815	DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1404	serge	1816	break;
		1817	default:
		1818	tv_std = TV_STD_NTSC;
1963	serge	1819	DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1404	serge	1820	break;
		1821	}
1963	serge	1822	}
1404	serge	1823	return tv_std;
		1824	}
		1825
1117	serge	1826	struct radeon_encoder_tv_dac *
		1827	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1828	{
		1829	struct drm_device *dev = encoder->base.dev;
		1830	struct radeon_device *rdev = dev->dev_private;
		1831	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1832	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1833	uint16_t data_offset;
		1834	struct _COMPASSIONATE_DATA *dac_info;
		1835	uint8_t frev, crev;
		1836	uint8_t bg, dac;
		1837	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1838
1963	serge	1839	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		1840	&frev, &crev, &data_offset)) {
1117	serge	1841
1963	serge	1842	dac_info = (struct _COMPASSIONATE_DATA *)
		1843	(mode_info->atom_context->bios + data_offset);
1117	serge	1844
		1845	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1846
		1847	if (!tv_dac)
		1848	return NULL;
		1849
		1850	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1851	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1852	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1853
		1854	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1855	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1856	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1857
		1858	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1859	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1860	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1861
1404	serge	1862	tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1117	serge	1863	}
		1864	return tv_dac;
		1865	}
		1866
1963	serge	1867	static const char *thermal_controller_names[] = {
		1868	"NONE",
		1869	"lm63",
		1870	"adm1032",
		1871	"adm1030",
		1872	"max6649",
		1873	"lm64",
		1874	"f75375",
		1875	"asc7xxx",
		1876	};
		1877
		1878	static const char *pp_lib_thermal_controller_names[] = {
		1879	"NONE",
		1880	"lm63",
		1881	"adm1032",
		1882	"adm1030",
		1883	"max6649",
		1884	"lm64",
		1885	"f75375",
		1886	"RV6xx",
		1887	"RV770",
		1888	"adt7473",
		1889	"NONE",
		1890	"External GPIO",
		1891	"Evergreen",
		1892	"emc2103",
		1893	"Sumo",
		1894	"Northern Islands",
		1895	};
		1896
1430	serge	1897	union power_info {
		1898	struct _ATOM_POWERPLAY_INFO info;
		1899	struct _ATOM_POWERPLAY_INFO_V2 info_2;
		1900	struct _ATOM_POWERPLAY_INFO_V3 info_3;
1963	serge	1901	struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
		1902	struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
		1903	struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1430	serge	1904	};
		1905
1963	serge	1906	union pplib_clock_info {
		1907	struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
		1908	struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
		1909	struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
		1910	struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
		1911	};
		1912
		1913	union pplib_power_state {
		1914	struct _ATOM_PPLIB_STATE v1;
		1915	struct _ATOM_PPLIB_STATE_V2 v2;
		1916	};
		1917
		1918	static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
		1919	int state_index,
		1920	u32 misc, u32 misc2)
1117	serge	1921	{
1963	serge	1922	rdev->pm.power_state[state_index].misc = misc;
		1923	rdev->pm.power_state[state_index].misc2 = misc2;
		1924	/* order matters! */
		1925	if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
		1926	rdev->pm.power_state[state_index].type =
		1927	POWER_STATE_TYPE_POWERSAVE;
		1928	if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
		1929	rdev->pm.power_state[state_index].type =
		1930	POWER_STATE_TYPE_BATTERY;
		1931	if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
		1932	rdev->pm.power_state[state_index].type =
		1933	POWER_STATE_TYPE_BATTERY;
		1934	if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
		1935	rdev->pm.power_state[state_index].type =
		1936	POWER_STATE_TYPE_BALANCED;
		1937	if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
		1938	rdev->pm.power_state[state_index].type =
		1939	POWER_STATE_TYPE_PERFORMANCE;
		1940	rdev->pm.power_state[state_index].flags &=
		1941	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		1942	}
		1943	if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
		1944	rdev->pm.power_state[state_index].type =
		1945	POWER_STATE_TYPE_BALANCED;
		1946	if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
		1947	rdev->pm.power_state[state_index].type =
		1948	POWER_STATE_TYPE_DEFAULT;
		1949	rdev->pm.default_power_state_index = state_index;
		1950	rdev->pm.power_state[state_index].default_clock_mode =
		1951	&rdev->pm.power_state[state_index].clock_info[0];
		1952	} else if (state_index == 0) {
		1953	rdev->pm.power_state[state_index].clock_info[0].flags \|=
		1954	RADEON_PM_MODE_NO_DISPLAY;
		1955	}
		1956	}
		1957
		1958	static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
		1959	{
1430	serge	1960	struct radeon_mode_info *mode_info = &rdev->mode_info;
1963	serge	1961	u32 misc, misc2 = 0;
		1962	int num_modes = 0, i;
		1963	int state_index = 0;
		1964	struct radeon_i2c_bus_rec i2c_bus;
		1965	union power_info *power_info;
1430	serge	1966	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		1967	u16 data_offset;
		1968	u8 frev, crev;
1117	serge	1969
1963	serge	1970	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		1971	&frev, &crev, &data_offset))
		1972	return state_index;
1430	serge	1973	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		1974
1963	serge	1975	/* add the i2c bus for thermal/fan chip */
		1976	if (power_info->info.ucOverdriveThermalController > 0) {
		1977	DRM_INFO("Possible %s thermal controller at 0x%02x\n",
		1978	thermal_controller_names[power_info->info.ucOverdriveThermalController],
		1979	power_info->info.ucOverdriveControllerAddress >> 1);
		1980	i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
		1981	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		1982	if (rdev->pm.i2c_bus) {
		1983	struct i2c_board_info info = { };
		1984	const char *name = thermal_controller_names[power_info->info.
		1985	ucOverdriveThermalController];
		1986	info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
		1987	strlcpy(info.type, name, sizeof(info.type));
		1988	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
		1989	}
		1990	}
1430	serge	1991	num_modes = power_info->info.ucNumOfPowerModeEntries;
		1992	if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
		1993	num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1963	serge	1994	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
		1995	if (!rdev->pm.power_state)
		1996	return state_index;
		1997	/* last mode is usually default, array is low to high */
1430	serge	1998	for (i = 0; i < num_modes; i++) {
		1999	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
		2000	switch (frev) {
		2001	case 1:
		2002	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2003	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2004	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
		2005	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2006	le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
		2007	/* skip invalid modes */
		2008	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2009	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2010	continue;
1963	serge	2011	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2012	power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
		2013	misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1963	serge	2014	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2015	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2016	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2017	VOLTAGE_GPIO;
		2018	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2019	radeon_lookup_gpio(rdev,
		2020	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
		2021	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2022	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2023	true;
		2024	else
		2025	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2026	false;
		2027	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2028	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2029	VOLTAGE_VDDC;
		2030	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2031	power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
		2032	}
1963	serge	2033	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2034	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1430	serge	2035	state_index++;
		2036	break;
		2037	case 2:
		2038	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2039	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2040	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
		2041	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2042	le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
		2043	/* skip invalid modes */
		2044	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2045	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2046	continue;
1963	serge	2047	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2048	power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
		2049	misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
		2050	misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2051	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2052	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2053	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2054	VOLTAGE_GPIO;
		2055	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2056	radeon_lookup_gpio(rdev,
		2057	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
		2058	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2059	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2060	true;
		2061	else
		2062	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2063	false;
		2064	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2065	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2066	VOLTAGE_VDDC;
		2067	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2068	power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
		2069	}
1963	serge	2070	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2071	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2072	state_index++;
		2073	break;
		2074	case 3:
		2075	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2076	rdev->pm.power_state[state_index].clock_info[0].mclk =
		2077	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
		2078	rdev->pm.power_state[state_index].clock_info[0].sclk =
		2079	le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
		2080	/* skip invalid modes */
		2081	if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) \|\|
		2082	(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
		2083	continue;
1963	serge	2084	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2085	power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
		2086	misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
		2087	misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1963	serge	2088	if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) \|\|
		2089	(misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1430	serge	2090	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2091	VOLTAGE_GPIO;
		2092	rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
		2093	radeon_lookup_gpio(rdev,
		2094	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
		2095	if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
		2096	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2097	true;
		2098	else
		2099	rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
		2100	false;
		2101	} else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
		2102	rdev->pm.power_state[state_index].clock_info[0].voltage.type =
		2103	VOLTAGE_VDDC;
		2104	rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
		2105	power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
		2106	if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
		2107	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
		2108	true;
		2109	rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
		2110	power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
		2111	}
		2112	}
1963	serge	2113	rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2114	radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1430	serge	2115	state_index++;
		2116	break;
		2117	}
		2118	}
1963	serge	2119	/* last mode is usually default */
		2120	if (rdev->pm.default_power_state_index == -1) {
		2121	rdev->pm.power_state[state_index - 1].type =
		2122	POWER_STATE_TYPE_DEFAULT;
		2123	rdev->pm.default_power_state_index = state_index - 1;
		2124	rdev->pm.power_state[state_index - 1].default_clock_mode =
		2125	&rdev->pm.power_state[state_index - 1].clock_info[0];
		2126	rdev->pm.power_state[state_index].flags &=
		2127	~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
		2128	rdev->pm.power_state[state_index].misc = 0;
		2129	rdev->pm.power_state[state_index].misc2 = 0;
		2130	}
		2131	return state_index;
		2132	}
		2133
		2134	static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
		2135	ATOM_PPLIB_THERMALCONTROLLER *controller)
		2136	{
		2137	struct radeon_i2c_bus_rec i2c_bus;
		2138
		2139	/* add the i2c bus for thermal/fan chip */
		2140	if (controller->ucType > 0) {
		2141	if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
		2142	DRM_INFO("Internal thermal controller %s fan control\n",
		2143	(controller->ucFanParameters &
		2144	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2145	rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
		2146	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
		2147	DRM_INFO("Internal thermal controller %s fan control\n",
		2148	(controller->ucFanParameters &
		2149	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2150	rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
		2151	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
		2152	DRM_INFO("Internal thermal controller %s fan control\n",
		2153	(controller->ucFanParameters &
		2154	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2155	rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
		2156	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
		2157	DRM_INFO("Internal thermal controller %s fan control\n",
		2158	(controller->ucFanParameters &
		2159	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2160	rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
		2161	} else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
		2162	DRM_INFO("Internal thermal controller %s fan control\n",
		2163	(controller->ucFanParameters &
		2164	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2165	rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
		2166	} else if ((controller->ucType ==
		2167	ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) \|\|
		2168	(controller->ucType ==
		2169	ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) \|\|
		2170	(controller->ucType ==
		2171	ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
		2172	DRM_INFO("Special thermal controller config\n");
		2173	} else {
		2174	DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
		2175	pp_lib_thermal_controller_names[controller->ucType],
		2176	controller->ucI2cAddress >> 1,
		2177	(controller->ucFanParameters &
		2178	ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
		2179	i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
		2180	rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
		2181	if (rdev->pm.i2c_bus) {
		2182	struct i2c_board_info info = { };
		2183	const char *name = pp_lib_thermal_controller_names[controller->ucType];
		2184	info.addr = controller->ucI2cAddress >> 1;
		2185	strlcpy(info.type, name, sizeof(info.type));
		2186	i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1430	serge	2187	}
		2188	}
1963	serge	2189	}
		2190	}
		2191
		2192	static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
		2193	u16 vddc, u16 vddci)
		2194	{
		2195	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2196	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		2197	u8 frev, crev;
		2198	u16 data_offset;
		2199	union firmware_info *firmware_info;
		2200
		2201	*vddc = 0;
		2202	*vddci = 0;
		2203
		2204	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2205	&frev, &crev, &data_offset)) {
		2206	firmware_info =
		2207	(union firmware_info *)(mode_info->atom_context->bios +
		2208	data_offset);
		2209	*vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
		2210	if ((frev == 2) && (crev >= 2))
		2211	*vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
		2212	}
		2213	}
		2214
		2215	static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
		2216	int state_index, int mode_index,
		2217	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
		2218	{
		2219	int j;
		2220	u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
		2221	u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
		2222	u16 vddc, vddci;
		2223
		2224	radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
		2225
		2226	rdev->pm.power_state[state_index].misc = misc;
		2227	rdev->pm.power_state[state_index].misc2 = misc2;
		2228	rdev->pm.power_state[state_index].pcie_lanes =
1430	serge	2229	((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
		2230	ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
		2231	switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
		2232	case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
		2233	rdev->pm.power_state[state_index].type =
		2234	POWER_STATE_TYPE_BATTERY;
		2235	break;
		2236	case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
		2237	rdev->pm.power_state[state_index].type =
		2238	POWER_STATE_TYPE_BALANCED;
		2239	break;
		2240	case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
		2241	rdev->pm.power_state[state_index].type =
		2242	POWER_STATE_TYPE_PERFORMANCE;
		2243	break;
1963	serge	2244	case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
		2245	if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
		2246	rdev->pm.power_state[state_index].type =
		2247	POWER_STATE_TYPE_PERFORMANCE;
		2248	break;
1430	serge	2249	}
1963	serge	2250	rdev->pm.power_state[state_index].flags = 0;
		2251	if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
		2252	rdev->pm.power_state[state_index].flags \|=
		2253	RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1430	serge	2254	if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
		2255	rdev->pm.power_state[state_index].type =
		2256	POWER_STATE_TYPE_DEFAULT;
1963	serge	2257	rdev->pm.default_power_state_index = state_index;
1430	serge	2258	rdev->pm.power_state[state_index].default_clock_mode =
		2259	&rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1963	serge	2260	if (ASIC_IS_DCE5(rdev)) {
		2261	/* NI chips post without MC ucode, so default clocks are strobe mode only */
		2262	rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
		2263	rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
		2264	rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
		2265	rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
		2266	} else {
		2267	/* patch the table values with the default slck/mclk from firmware info */
		2268	for (j = 0; j < mode_index; j++) {
		2269	rdev->pm.power_state[state_index].clock_info[j].mclk =
		2270	rdev->clock.default_mclk;
		2271	rdev->pm.power_state[state_index].clock_info[j].sclk =
		2272	rdev->clock.default_sclk;
		2273	if (vddc)
		2274	rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
		2275	vddc;
		2276	}
1430	serge	2277	}
1963	serge	2278	}
		2279	}
		2280
		2281	static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
		2282	int state_index, int mode_index,
		2283	union pplib_clock_info *clock_info)
		2284	{
		2285	u32 sclk, mclk;
		2286
		2287	if (rdev->flags & RADEON_IS_IGP) {
		2288	if (rdev->family >= CHIP_PALM) {
		2289	sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
		2290	sclk \|= clock_info->sumo.ucEngineClockHigh << 16;
		2291	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2292	} else {
		2293	sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
		2294	sclk \|= clock_info->rs780.ucLowEngineClockHigh << 16;
		2295	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2296	}
		2297	} else if (ASIC_IS_DCE4(rdev)) {
		2298	sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
		2299	sclk \|= clock_info->evergreen.ucEngineClockHigh << 16;
		2300	mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
		2301	mclk \|= clock_info->evergreen.ucMemoryClockHigh << 16;
		2302	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2303	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2304	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2305	VOLTAGE_SW;
		2306	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2307	le16_to_cpu(clock_info->evergreen.usVDDC);
		2308	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
		2309	le16_to_cpu(clock_info->evergreen.usVDDCI);
		2310	} else {
		2311	sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
		2312	sclk \|= clock_info->r600.ucEngineClockHigh << 16;
		2313	mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
		2314	mclk \|= clock_info->r600.ucMemoryClockHigh << 16;
		2315	rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
		2316	rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
		2317	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
		2318	VOLTAGE_SW;
		2319	rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
		2320	le16_to_cpu(clock_info->r600.usVDDC);
		2321	}
		2322
		2323	if (rdev->flags & RADEON_IS_IGP) {
		2324	/* skip invalid modes */
		2325	if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
		2326	return false;
		2327	} else {
		2328	/* skip invalid modes */
		2329	if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) \|\|
		2330	(rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
		2331	return false;
		2332	}
		2333	return true;
		2334	}
		2335
		2336	static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
		2337	{
		2338	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2339	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2340	union pplib_power_state *power_state;
		2341	int i, j;
		2342	int state_index = 0, mode_index = 0;
		2343	union pplib_clock_info *clock_info;
		2344	bool valid;
		2345	union power_info *power_info;
		2346	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2347	u16 data_offset;
		2348	u8 frev, crev;
		2349
		2350	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2351	&frev, &crev, &data_offset))
		2352	return state_index;
		2353	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2354
		2355	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
		2356	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2357	power_info->pplib.ucNumStates, GFP_KERNEL);
		2358	if (!rdev->pm.power_state)
		2359	return state_index;
		2360	/* first mode is usually default, followed by low to high */
		2361	for (i = 0; i < power_info->pplib.ucNumStates; i++) {
		2362	mode_index = 0;
		2363	power_state = (union pplib_power_state *)
		2364	(mode_info->atom_context->bios + data_offset +
		2365	le16_to_cpu(power_info->pplib.usStateArrayOffset) +
		2366	i * power_info->pplib.ucStateEntrySize);
		2367	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2368	(mode_info->atom_context->bios + data_offset +
		2369	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
		2370	(power_state->v1.ucNonClockStateIndex *
		2371	power_info->pplib.ucNonClockSize));
		2372	for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
		2373	clock_info = (union pplib_clock_info *)
		2374	(mode_info->atom_context->bios + data_offset +
		2375	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
		2376	(power_state->v1.ucClockStateIndices[j] *
		2377	power_info->pplib.ucClockInfoSize));
		2378	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2379	state_index, mode_index,
		2380	clock_info);
		2381	if (valid)
		2382	mode_index++;
		2383	}
		2384	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2385	if (mode_index) {
		2386	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2387	non_clock_info);
		2388	state_index++;
		2389	}
		2390	}
		2391	/* if multiple clock modes, mark the lowest as no display */
		2392	for (i = 0; i < state_index; i++) {
		2393	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2394	rdev->pm.power_state[i].clock_info[0].flags \|=
		2395	RADEON_PM_MODE_NO_DISPLAY;
		2396	}
		2397	/* first mode is usually default */
		2398	if (rdev->pm.default_power_state_index == -1) {
		2399	rdev->pm.power_state[0].type =
		2400	POWER_STATE_TYPE_DEFAULT;
		2401	rdev->pm.default_power_state_index = 0;
		2402	rdev->pm.power_state[0].default_clock_mode =
		2403	&rdev->pm.power_state[0].clock_info[0];
		2404	}
		2405	return state_index;
		2406	}
		2407
		2408	static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
		2409	{
		2410	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2411	struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
		2412	union pplib_power_state *power_state;
		2413	int i, j, non_clock_array_index, clock_array_index;
		2414	int state_index = 0, mode_index = 0;
		2415	union pplib_clock_info *clock_info;
		2416	struct StateArray *state_array;
		2417	struct ClockInfoArray *clock_info_array;
		2418	struct NonClockInfoArray *non_clock_info_array;
		2419	bool valid;
		2420	union power_info *power_info;
		2421	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2422	u16 data_offset;
		2423	u8 frev, crev;
		2424
		2425	if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
		2426	&frev, &crev, &data_offset))
		2427	return state_index;
		2428	power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
		2429
		2430	radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
		2431	state_array = (struct StateArray *)
		2432	(mode_info->atom_context->bios + data_offset +
		2433	le16_to_cpu(power_info->pplib.usStateArrayOffset));
		2434	clock_info_array = (struct ClockInfoArray *)
		2435	(mode_info->atom_context->bios + data_offset +
		2436	le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
		2437	non_clock_info_array = (struct NonClockInfoArray *)
		2438	(mode_info->atom_context->bios + data_offset +
		2439	le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
		2440	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
		2441	state_array->ucNumEntries, GFP_KERNEL);
		2442	if (!rdev->pm.power_state)
		2443	return state_index;
		2444	for (i = 0; i < state_array->ucNumEntries; i++) {
		2445	mode_index = 0;
		2446	power_state = (union pplib_power_state *)&state_array->states[i];
		2447	/* XXX this might be an inagua bug... */
		2448	non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
		2449	non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
		2450	&non_clock_info_array->nonClockInfo[non_clock_array_index];
		2451	for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
		2452	clock_array_index = power_state->v2.clockInfoIndex[j];
		2453	/* XXX this might be an inagua bug... */
		2454	if (clock_array_index >= clock_info_array->ucNumEntries)
		2455	continue;
		2456	clock_info = (union pplib_clock_info *)
		2457	&clock_info_array->clockInfo[clock_array_index];
		2458	valid = radeon_atombios_parse_pplib_clock_info(rdev,
		2459	state_index, mode_index,
		2460	clock_info);
		2461	if (valid)
		2462	mode_index++;
		2463	}
		2464	rdev->pm.power_state[state_index].num_clock_modes = mode_index;
		2465	if (mode_index) {
		2466	radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
		2467	non_clock_info);
1430	serge	2468	state_index++;
		2469	}
		2470	}
1963	serge	2471	/* if multiple clock modes, mark the lowest as no display */
		2472	for (i = 0; i < state_index; i++) {
		2473	if (rdev->pm.power_state[i].num_clock_modes > 1)
		2474	rdev->pm.power_state[i].clock_info[0].flags \|=
		2475	RADEON_PM_MODE_NO_DISPLAY;
		2476	}
		2477	/* first mode is usually default */
		2478	if (rdev->pm.default_power_state_index == -1) {
		2479	rdev->pm.power_state[0].type =
		2480	POWER_STATE_TYPE_DEFAULT;
		2481	rdev->pm.default_power_state_index = 0;
		2482	rdev->pm.power_state[0].default_clock_mode =
		2483	&rdev->pm.power_state[0].clock_info[0];
		2484	}
		2485	return state_index;
		2486	}
		2487
		2488	void radeon_atombios_get_power_modes(struct radeon_device *rdev)
		2489	{
		2490	struct radeon_mode_info *mode_info = &rdev->mode_info;
		2491	int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
		2492	u16 data_offset;
		2493	u8 frev, crev;
		2494	int state_index = 0;
		2495
		2496	rdev->pm.default_power_state_index = -1;
		2497
		2498	if (atom_parse_data_header(mode_info->atom_context, index, NULL,
		2499	&frev, &crev, &data_offset)) {
		2500	switch (frev) {
		2501	case 1:
		2502	case 2:
		2503	case 3:
		2504	state_index = radeon_atombios_parse_power_table_1_3(rdev);
		2505	break;
		2506	case 4:
		2507	case 5:
		2508	state_index = radeon_atombios_parse_power_table_4_5(rdev);
		2509	break;
		2510	case 6:
		2511	state_index = radeon_atombios_parse_power_table_6(rdev);
		2512	break;
		2513	default:
		2514	break;
1430	serge	2515	}
		2516	} else {
1963	serge	2517	rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
		2518	if (rdev->pm.power_state) {
1430	serge	2519	/* add the default mode */
		2520	rdev->pm.power_state[state_index].type =
		2521	POWER_STATE_TYPE_DEFAULT;
		2522	rdev->pm.power_state[state_index].num_clock_modes = 1;
		2523	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
		2524	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
		2525	rdev->pm.power_state[state_index].default_clock_mode =
		2526	&rdev->pm.power_state[state_index].clock_info[0];
		2527	rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1963	serge	2528	rdev->pm.power_state[state_index].pcie_lanes = 16;
		2529	rdev->pm.default_power_state_index = state_index;
		2530	rdev->pm.power_state[state_index].flags = 0;
1430	serge	2531	state_index++;
		2532	}
1963	serge	2533	}
		2534
1430	serge	2535	rdev->pm.num_power_states = state_index;
		2536
1963	serge	2537	rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
		2538	rdev->pm.current_clock_mode_index = 0;
		2539	rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1117	serge	2540	}
		2541
1430	serge	2542	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1117	serge	2543	{
1430	serge	2544	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		2545	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1117	serge	2546
		2547	args.ucEnable = enable;
		2548
		2549	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2550	}
		2551
1268	serge	2552	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		2553	{
		2554	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		2555	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		2556
		2557	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2558	return le32_to_cpu(args.ulReturnEngineClock);
1268	serge	2559	}
		2560
		2561	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		2562	{
		2563	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		2564	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		2565
		2566	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1963	serge	2567	return le32_to_cpu(args.ulReturnMemoryClock);
1268	serge	2568	}
		2569
1117	serge	2570	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		2571	uint32_t eng_clock)
		2572	{
		2573	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		2574	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		2575
1963	serge	2576	args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
1117	serge	2577
		2578	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2579	}
		2580
		2581	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		2582	uint32_t mem_clock)
		2583	{
		2584	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		2585	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		2586
		2587	if (rdev->flags & RADEON_IS_IGP)
		2588	return;
		2589
1963	serge	2590	args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
1117	serge	2591
		2592	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2593	}
		2594
1963	serge	2595	union set_voltage {
		2596	struct _SET_VOLTAGE_PS_ALLOCATION alloc;
		2597	struct _SET_VOLTAGE_PARAMETERS v1;
		2598	struct _SET_VOLTAGE_PARAMETERS_V2 v2;
		2599	};
		2600
		2601	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
		2602	{
		2603	union set_voltage args;
		2604	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
		2605	u8 frev, crev, volt_index = voltage_level;
		2606
		2607	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
		2608	return;
		2609
		2610	switch (crev) {
		2611	case 1:
		2612	args.v1.ucVoltageType = voltage_type;
		2613	args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
		2614	args.v1.ucVoltageIndex = volt_index;
		2615	break;
		2616	case 2:
		2617	args.v2.ucVoltageType = voltage_type;
		2618	args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
		2619	args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
		2620	break;
		2621	default:
		2622	DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
		2623	return;
		2624	}
		2625
		2626	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		2627	}
		2628
		2629
		2630
1117	serge	2631	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		2632	{
		2633	struct radeon_device *rdev = dev->dev_private;
		2634	uint32_t bios_2_scratch, bios_6_scratch;
		2635
		2636	if (rdev->family >= CHIP_R600) {
1179	serge	2637	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	2638	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		2639	} else {
1179	serge	2640	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	2641	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2642	}
		2643
		2644	/* let the bios control the backlight */
		2645	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		2646
		2647	/* tell the bios not to handle mode switching */
1963	serge	2648	bios_6_scratch \|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1117	serge	2649
		2650	if (rdev->family >= CHIP_R600) {
		2651	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		2652	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		2653	} else {
		2654	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		2655	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2656	}
		2657
		2658	}
		2659
1179	serge	2660	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		2661	{
		2662	uint32_t scratch_reg;
		2663	int i;
		2664
		2665	if (rdev->family >= CHIP_R600)
		2666	scratch_reg = R600_BIOS_0_SCRATCH;
		2667	else
		2668	scratch_reg = RADEON_BIOS_0_SCRATCH;
		2669
		2670	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		2671	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		2672	}
		2673
		2674	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		2675	{
		2676	uint32_t scratch_reg;
		2677	int i;
		2678
		2679	if (rdev->family >= CHIP_R600)
		2680	scratch_reg = R600_BIOS_0_SCRATCH;
		2681	else
		2682	scratch_reg = RADEON_BIOS_0_SCRATCH;
		2683
		2684	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		2685	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		2686	}
		2687
1117	serge	2688	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		2689	{
		2690	struct drm_device *dev = encoder->dev;
		2691	struct radeon_device *rdev = dev->dev_private;
		2692	uint32_t bios_6_scratch;
		2693
		2694	if (rdev->family >= CHIP_R600)
		2695	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		2696	else
		2697	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2698
1963	serge	2699	if (lock) {
1117	serge	2700	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
1963	serge	2701	bios_6_scratch &= ~ATOM_S6_ACC_MODE;
		2702	} else {
1117	serge	2703	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1963	serge	2704	bios_6_scratch \|= ATOM_S6_ACC_MODE;
		2705	}
1117	serge	2706
		2707	if (rdev->family >= CHIP_R600)
		2708	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		2709	else
		2710	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2711	}
		2712
		2713	/* at some point we may want to break this out into individual functions */
		2714	void
		2715	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		2716	struct drm_encoder *encoder,
		2717	bool connected)
		2718	{
		2719	struct drm_device *dev = connector->dev;
		2720	struct radeon_device *rdev = dev->dev_private;
		2721	struct radeon_connector *radeon_connector =
		2722	to_radeon_connector(connector);
		2723	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2724	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		2725
		2726	if (rdev->family >= CHIP_R600) {
		2727	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		2728	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		2729	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		2730	} else {
		2731	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		2732	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		2733	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		2734	}
		2735
		2736	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		2737	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		2738	if (connected) {
1963	serge	2739	DRM_DEBUG_KMS("TV1 connected\n");
1117	serge	2740	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		2741	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		2742	} else {
1963	serge	2743	DRM_DEBUG_KMS("TV1 disconnected\n");
1117	serge	2744	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		2745	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		2746	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		2747	}
		2748	}
		2749	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		2750	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		2751	if (connected) {
1963	serge	2752	DRM_DEBUG_KMS("CV connected\n");
1117	serge	2753	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		2754	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		2755	} else {
1963	serge	2756	DRM_DEBUG_KMS("CV disconnected\n");
1117	serge	2757	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		2758	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		2759	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		2760	}
		2761	}
		2762	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		2763	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		2764	if (connected) {
1963	serge	2765	DRM_DEBUG_KMS("LCD1 connected\n");
1117	serge	2766	bios_0_scratch \|= ATOM_S0_LCD1;
		2767	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		2768	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		2769	} else {
1963	serge	2770	DRM_DEBUG_KMS("LCD1 disconnected\n");
1117	serge	2771	bios_0_scratch &= ~ATOM_S0_LCD1;
		2772	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		2773	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		2774	}
		2775	}
		2776	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		2777	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		2778	if (connected) {
1963	serge	2779	DRM_DEBUG_KMS("CRT1 connected\n");
1117	serge	2780	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		2781	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		2782	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		2783	} else {
1963	serge	2784	DRM_DEBUG_KMS("CRT1 disconnected\n");
1117	serge	2785	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		2786	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		2787	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		2788	}
		2789	}
		2790	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		2791	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		2792	if (connected) {
1963	serge	2793	DRM_DEBUG_KMS("CRT2 connected\n");
1117	serge	2794	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		2795	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		2796	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		2797	} else {
1963	serge	2798	DRM_DEBUG_KMS("CRT2 disconnected\n");
1117	serge	2799	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		2800	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		2801	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		2802	}
		2803	}
		2804	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		2805	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		2806	if (connected) {
1963	serge	2807	DRM_DEBUG_KMS("DFP1 connected\n");
1117	serge	2808	bios_0_scratch \|= ATOM_S0_DFP1;
		2809	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		2810	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		2811	} else {
1963	serge	2812	DRM_DEBUG_KMS("DFP1 disconnected\n");
1117	serge	2813	bios_0_scratch &= ~ATOM_S0_DFP1;
		2814	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		2815	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		2816	}
		2817	}
		2818	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		2819	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		2820	if (connected) {
1963	serge	2821	DRM_DEBUG_KMS("DFP2 connected\n");
1117	serge	2822	bios_0_scratch \|= ATOM_S0_DFP2;
		2823	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		2824	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		2825	} else {
1963	serge	2826	DRM_DEBUG_KMS("DFP2 disconnected\n");
1117	serge	2827	bios_0_scratch &= ~ATOM_S0_DFP2;
		2828	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		2829	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		2830	}
		2831	}
		2832	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		2833	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		2834	if (connected) {
1963	serge	2835	DRM_DEBUG_KMS("DFP3 connected\n");
1117	serge	2836	bios_0_scratch \|= ATOM_S0_DFP3;
		2837	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		2838	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		2839	} else {
1963	serge	2840	DRM_DEBUG_KMS("DFP3 disconnected\n");
1117	serge	2841	bios_0_scratch &= ~ATOM_S0_DFP3;
		2842	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		2843	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		2844	}
		2845	}
		2846	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		2847	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		2848	if (connected) {
1963	serge	2849	DRM_DEBUG_KMS("DFP4 connected\n");
1117	serge	2850	bios_0_scratch \|= ATOM_S0_DFP4;
		2851	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		2852	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		2853	} else {
1963	serge	2854	DRM_DEBUG_KMS("DFP4 disconnected\n");
1117	serge	2855	bios_0_scratch &= ~ATOM_S0_DFP4;
		2856	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		2857	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		2858	}
		2859	}
		2860	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		2861	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		2862	if (connected) {
1963	serge	2863	DRM_DEBUG_KMS("DFP5 connected\n");
1117	serge	2864	bios_0_scratch \|= ATOM_S0_DFP5;
		2865	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		2866	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		2867	} else {
1963	serge	2868	DRM_DEBUG_KMS("DFP5 disconnected\n");
1117	serge	2869	bios_0_scratch &= ~ATOM_S0_DFP5;
		2870	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		2871	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		2872	}
		2873	}
		2874
		2875	if (rdev->family >= CHIP_R600) {
		2876	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		2877	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		2878	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		2879	} else {
		2880	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		2881	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		2882	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		2883	}
		2884	}
		2885
		2886	void
		2887	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		2888	{
		2889	struct drm_device *dev = encoder->dev;
		2890	struct radeon_device *rdev = dev->dev_private;
		2891	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2892	uint32_t bios_3_scratch;
		2893
		2894	if (rdev->family >= CHIP_R600)
		2895	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		2896	else
		2897	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		2898
		2899	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2900	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		2901	bios_3_scratch \|= (crtc << 18);
		2902	}
		2903	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		2904	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		2905	bios_3_scratch \|= (crtc << 24);
		2906	}
		2907	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		2908	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		2909	bios_3_scratch \|= (crtc << 16);
		2910	}
		2911	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		2912	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		2913	bios_3_scratch \|= (crtc << 20);
		2914	}
		2915	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		2916	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		2917	bios_3_scratch \|= (crtc << 17);
		2918	}
		2919	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		2920	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		2921	bios_3_scratch \|= (crtc << 19);
		2922	}
		2923	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		2924	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		2925	bios_3_scratch \|= (crtc << 23);
		2926	}
		2927	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		2928	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		2929	bios_3_scratch \|= (crtc << 25);
		2930	}
		2931
		2932	if (rdev->family >= CHIP_R600)
		2933	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		2934	else
		2935	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		2936	}
		2937
		2938	void
		2939	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		2940	{
		2941	struct drm_device *dev = encoder->dev;
		2942	struct radeon_device *rdev = dev->dev_private;
		2943	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		2944	uint32_t bios_2_scratch;
		2945
		2946	if (rdev->family >= CHIP_R600)
		2947	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		2948	else
		2949	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		2950
		2951	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		2952	if (on)
		2953	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		2954	else
		2955	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		2956	}
		2957	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		2958	if (on)
		2959	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		2960	else
		2961	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		2962	}
		2963	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		2964	if (on)
		2965	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		2966	else
		2967	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		2968	}
		2969	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		2970	if (on)
		2971	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		2972	else
		2973	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		2974	}
		2975	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		2976	if (on)
		2977	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		2978	else
		2979	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		2980	}
		2981	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		2982	if (on)
		2983	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		2984	else
		2985	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		2986	}
		2987	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		2988	if (on)
		2989	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		2990	else
		2991	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		2992	}
		2993	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		2994	if (on)
		2995	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		2996	else
		2997	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		2998	}
		2999	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		3000	if (on)
		3001	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		3002	else
		3003	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		3004	}
		3005	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		3006	if (on)
		3007	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		3008	else
		3009	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		3010	}
		3011
		3012	if (rdev->family >= CHIP_R600)
		3013	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		3014	else
		3015	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		3016	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1963