WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
		39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
		40	uint32_t supported_device);
		41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
1268	serge	49	bool linkb, uint32_t igp_lane_info,
1321	serge	50	uint16_t connector_object_id,
		51	struct radeon_hpd *hpd);
1117	serge	52
		53	/* from radeon_legacy_encoder.c */
		54	extern void
		55	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		56	uint32_t supported_device);
		57
		58	union atom_supported_devices {
		59	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		60	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		61	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		62	};
		63
1321	serge	64	static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
		65	uint8_t id)
1117	serge	66	{
		67	struct atom_context *ctx = rdev->mode_info.atom_context;
1321	serge	68	ATOM_GPIO_I2C_ASSIGMENT *gpio;
1117	serge	69	struct radeon_i2c_bus_rec i2c;
		70	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		71	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		72	uint16_t data_offset;
1321	serge	73	int i;
1117	serge	74
		75	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		76	i2c.valid = false;
		77
		78	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
		79
		80	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		81
		82
1321	serge	83	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		84	gpio = &i2c_info->asGPIO_Info[i];
		85
		86	if (gpio->sucI2cId.ucAccess == id) {
		87	i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
		88	i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
		89	i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
		90	i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
		91	i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
		92	i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
		93	i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
		94	i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
		95	i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
		96	i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
		97	i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
		98	i2c.en_data_mask = (1 << gpio->ucDataEnShift);
		99	i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
		100	i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
		101	i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
		102	i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
		103
		104	if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
		105	i2c.hw_capable = true;
		106	else
		107	i2c.hw_capable = false;
		108
		109	if (gpio->sucI2cId.ucAccess == 0xa0)
		110	i2c.mm_i2c = true;
		111	else
		112	i2c.mm_i2c = false;
		113
		114	i2c.i2c_id = gpio->sucI2cId.ucAccess;
		115
1117	serge	116	i2c.valid = true;
1404	serge	117	break;
1321	serge	118	}
		119	}
1117	serge	120
		121	return i2c;
		122	}
		123
1321	serge	124	static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
		125	u8 id)
		126	{
		127	struct atom_context *ctx = rdev->mode_info.atom_context;
		128	struct radeon_gpio_rec gpio;
		129	int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
		130	struct _ATOM_GPIO_PIN_LUT *gpio_info;
		131	ATOM_GPIO_PIN_ASSIGNMENT *pin;
		132	u16 data_offset, size;
		133	int i, num_indices;
		134
		135	memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
		136	gpio.valid = false;
		137
		138	atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset);
		139
		140	gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
		141
		142	num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
		143
		144	for (i = 0; i < num_indices; i++) {
		145	pin = &gpio_info->asGPIO_Pin[i];
		146	if (id == pin->ucGPIO_ID) {
		147	gpio.id = pin->ucGPIO_ID;
		148	gpio.reg = pin->usGpioPin_AIndex * 4;
		149	gpio.mask = (1 << pin->ucGpioPinBitShift);
		150	gpio.valid = true;
		151	break;
		152	}
		153	}
		154
		155	return gpio;
		156	}
		157
		158	static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
		159	struct radeon_gpio_rec *gpio)
		160	{
		161	struct radeon_hpd hpd;
		162	hpd.gpio = *gpio;
		163	if (gpio->reg == AVIVO_DC_GPIO_HPD_A) {
		164	switch(gpio->mask) {
		165	case (1 << 0):
		166	hpd.hpd = RADEON_HPD_1;
		167	break;
		168	case (1 << 8):
		169	hpd.hpd = RADEON_HPD_2;
		170	break;
		171	case (1 << 16):
		172	hpd.hpd = RADEON_HPD_3;
		173	break;
		174	case (1 << 24):
		175	hpd.hpd = RADEON_HPD_4;
		176	break;
		177	case (1 << 26):
		178	hpd.hpd = RADEON_HPD_5;
		179	break;
		180	case (1 << 28):
		181	hpd.hpd = RADEON_HPD_6;
		182	break;
		183	default:
		184	hpd.hpd = RADEON_HPD_NONE;
		185	break;
		186	}
		187	} else
		188	hpd.hpd = RADEON_HPD_NONE;
		189	return hpd;
		190	}
		191
1117	serge	192	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		193	uint32_t supported_device,
		194	int *connector_type,
1179	serge	195	struct radeon_i2c_bus_rec *i2c_bus,
1321	serge	196	uint16_t *line_mux,
		197	struct radeon_hpd *hpd)
1117	serge	198	{
		199
		200	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		201	if ((dev->pdev->device == 0x791e) &&
		202	(dev->pdev->subsystem_vendor == 0x1043) &&
		203	(dev->pdev->subsystem_device == 0x826d)) {
		204	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		205	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		206	*connector_type = DRM_MODE_CONNECTOR_DVID;
		207	}
		208
		209	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		210	if ((dev->pdev->device == 0x7941) &&
		211	(dev->pdev->subsystem_vendor == 0x147b) &&
		212	(dev->pdev->subsystem_device == 0x2412)) {
		213	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		214	return false;
		215	}
		216
		217	/* Falcon NW laptop lists vga ddc line for LVDS */
		218	if ((dev->pdev->device == 0x5653) &&
		219	(dev->pdev->subsystem_vendor == 0x1462) &&
		220	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	221	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	222	i2c_bus->valid = false;
1179	serge	223	*line_mux = 53;
		224	}
1117	serge	225	}
		226
1321	serge	227	/* HIS X1300 is DVI+VGA, not DVI+DVI */
		228	if ((dev->pdev->device == 0x7146) &&
		229	(dev->pdev->subsystem_vendor == 0x17af) &&
		230	(dev->pdev->subsystem_device == 0x2058)) {
		231	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		232	return false;
		233	}
		234
		235	/* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
		236	if ((dev->pdev->device == 0x7142) &&
		237	(dev->pdev->subsystem_vendor == 0x1458) &&
		238	(dev->pdev->subsystem_device == 0x2134)) {
		239	if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
		240	return false;
		241	}
		242
		243
1117	serge	244	/* Funky macbooks */
		245	if ((dev->pdev->device == 0x71C5) &&
		246	(dev->pdev->subsystem_vendor == 0x106b) &&
		247	(dev->pdev->subsystem_device == 0x0080)) {
		248	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		249	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		250	return false;
		251	}
		252
		253	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		254	if ((dev->pdev->device == 0x9598) &&
		255	(dev->pdev->subsystem_vendor == 0x1043) &&
		256	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	257	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		258	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	259	}
		260	}
		261
1179	serge	262	/* ASUS HD 3450 board lists the DVI port as HDMI */
		263	if ((dev->pdev->device == 0x95C5) &&
		264	(dev->pdev->subsystem_vendor == 0x1043) &&
		265	(dev->pdev->subsystem_device == 0x01e2)) {
		266	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		267	*connector_type = DRM_MODE_CONNECTOR_DVII;
		268	}
		269	}
		270
		271	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		272	* HDMI + VGA reporting as HDMI
		273	*/
		274	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		275	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		276	*connector_type = DRM_MODE_CONNECTOR_VGA;
		277	*line_mux = 0;
		278	}
		279	}
		280
1321	serge	281	/* Acer laptop reports DVI-D as DVI-I */
		282	if ((dev->pdev->device == 0x95c4) &&
		283	(dev->pdev->subsystem_vendor == 0x1025) &&
		284	(dev->pdev->subsystem_device == 0x013c)) {
		285	if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
		286	(supported_device == ATOM_DEVICE_DFP1_SUPPORT))
		287	*connector_type = DRM_MODE_CONNECTOR_DVID;
		288	}
		289
1412	serge	290	/* XFX Pine Group device rv730 reports no VGA DDC lines
		291	* even though they are wired up to record 0x93
		292	*/
		293	if ((dev->pdev->device == 0x9498) &&
		294	(dev->pdev->subsystem_vendor == 0x1682) &&
		295	(dev->pdev->subsystem_device == 0x2452)) {
		296	struct radeon_device *rdev = dev->dev_private;
		297	*i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
		298	}
1117	serge	299	return true;
		300	}
		301
		302	const int supported_devices_connector_convert[] = {
		303	DRM_MODE_CONNECTOR_Unknown,
		304	DRM_MODE_CONNECTOR_VGA,
		305	DRM_MODE_CONNECTOR_DVII,
		306	DRM_MODE_CONNECTOR_DVID,
		307	DRM_MODE_CONNECTOR_DVIA,
		308	DRM_MODE_CONNECTOR_SVIDEO,
		309	DRM_MODE_CONNECTOR_Composite,
		310	DRM_MODE_CONNECTOR_LVDS,
		311	DRM_MODE_CONNECTOR_Unknown,
		312	DRM_MODE_CONNECTOR_Unknown,
		313	DRM_MODE_CONNECTOR_HDMIA,
		314	DRM_MODE_CONNECTOR_HDMIB,
		315	DRM_MODE_CONNECTOR_Unknown,
		316	DRM_MODE_CONNECTOR_Unknown,
		317	DRM_MODE_CONNECTOR_9PinDIN,
		318	DRM_MODE_CONNECTOR_DisplayPort
		319	};
		320
1268	serge	321	const uint16_t supported_devices_connector_object_id_convert[] = {
		322	CONNECTOR_OBJECT_ID_NONE,
		323	CONNECTOR_OBJECT_ID_VGA,
		324	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
		325	CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
		326	CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
		327	CONNECTOR_OBJECT_ID_COMPOSITE,
		328	CONNECTOR_OBJECT_ID_SVIDEO,
		329	CONNECTOR_OBJECT_ID_LVDS,
		330	CONNECTOR_OBJECT_ID_9PIN_DIN,
		331	CONNECTOR_OBJECT_ID_9PIN_DIN,
		332	CONNECTOR_OBJECT_ID_DISPLAYPORT,
		333	CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
		334	CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
		335	CONNECTOR_OBJECT_ID_SVIDEO
		336	};
		337
1117	serge	338	const int object_connector_convert[] = {
		339	DRM_MODE_CONNECTOR_Unknown,
		340	DRM_MODE_CONNECTOR_DVII,
		341	DRM_MODE_CONNECTOR_DVII,
		342	DRM_MODE_CONNECTOR_DVID,
		343	DRM_MODE_CONNECTOR_DVID,
		344	DRM_MODE_CONNECTOR_VGA,
		345	DRM_MODE_CONNECTOR_Composite,
		346	DRM_MODE_CONNECTOR_SVIDEO,
		347	DRM_MODE_CONNECTOR_Unknown,
1179	serge	348	DRM_MODE_CONNECTOR_Unknown,
1117	serge	349	DRM_MODE_CONNECTOR_9PinDIN,
		350	DRM_MODE_CONNECTOR_Unknown,
		351	DRM_MODE_CONNECTOR_HDMIA,
		352	DRM_MODE_CONNECTOR_HDMIB,
		353	DRM_MODE_CONNECTOR_LVDS,
		354	DRM_MODE_CONNECTOR_9PinDIN,
		355	DRM_MODE_CONNECTOR_Unknown,
		356	DRM_MODE_CONNECTOR_Unknown,
		357	DRM_MODE_CONNECTOR_Unknown,
1404	serge	358	DRM_MODE_CONNECTOR_DisplayPort,
		359	DRM_MODE_CONNECTOR_eDP,
		360	DRM_MODE_CONNECTOR_Unknown
1117	serge	361	};
		362
		363	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		364	{
		365	struct radeon_device *rdev = dev->dev_private;
		366	struct radeon_mode_info *mode_info = &rdev->mode_info;
		367	struct atom_context *ctx = mode_info->atom_context;
		368	int index = GetIndexIntoMasterTable(DATA, Object_Header);
1321	serge	369	u16 size, data_offset;
		370	u8 frev, crev;
1117	serge	371	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
		372	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		373	ATOM_OBJECT_HEADER *obj_header;
		374	int i, j, path_size, device_support;
		375	int connector_type;
1321	serge	376	u16 igp_lane_info, conn_id, connector_object_id;
1117	serge	377	bool linkb;
		378	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	379	struct radeon_gpio_rec gpio;
		380	struct radeon_hpd hpd;
1117	serge	381
		382	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		383
		384	if (data_offset == 0)
		385	return false;
		386
		387	if (crev < 2)
		388	return false;
		389
		390	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		391	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		392	(ctx->bios + data_offset +
		393	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		394	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		395	(ctx->bios + data_offset +
		396	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
		397	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		398
		399	path_size = 0;
		400	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		401	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		402	ATOM_DISPLAY_OBJECT_PATH *path;
		403	addr += path_size;
		404	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		405	path_size += le16_to_cpu(path->usSize);
		406	linkb = false;
		407	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		408	uint8_t con_obj_id, con_obj_num, con_obj_type;
		409
		410	con_obj_id =
		411	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		412	>> OBJECT_ID_SHIFT;
		413	con_obj_num =
		414	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		415	>> ENUM_ID_SHIFT;
		416	con_obj_type =
		417	(le16_to_cpu(path->usConnObjectId) &
		418	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		419
1221	serge	420	/* TODO CV support */
		421	if (le16_to_cpu(path->usDeviceTag) ==
		422	ATOM_DEVICE_CV_SUPPORT)
1117	serge	423	continue;
		424
1268	serge	425	/* IGP chips */
		426	if ((rdev->flags & RADEON_IS_IGP) &&
1117	serge	427	(con_obj_id ==
		428	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		429	uint16_t igp_offset = 0;
		430	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		431
		432	index =
		433	GetIndexIntoMasterTable(DATA,
		434	IntegratedSystemInfo);
		435
		436	atom_parse_data_header(ctx, index, &size, &frev,
		437	&crev, &igp_offset);
		438
		439	if (crev >= 2) {
		440	igp_obj =
		441	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		442	*) (ctx->bios + igp_offset);
		443
		444	if (igp_obj) {
		445	uint32_t slot_config, ct;
		446
		447	if (con_obj_num == 1)
		448	slot_config =
		449	igp_obj->
		450	ulDDISlot1Config;
		451	else
		452	slot_config =
		453	igp_obj->
		454	ulDDISlot2Config;
		455
		456	ct = (slot_config >> 16) & 0xff;
		457	connector_type =
		458	object_connector_convert
		459	[ct];
1268	serge	460	connector_object_id = ct;
1117	serge	461	igp_lane_info =
		462	slot_config & 0xffff;
		463	} else
		464	continue;
		465	} else
		466	continue;
		467	} else {
		468	igp_lane_info = 0;
		469	connector_type =
		470	object_connector_convert[con_obj_id];
1268	serge	471	connector_object_id = con_obj_id;
1117	serge	472	}
		473
		474	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		475	continue;
		476
		477	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
		478	j++) {
		479	uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
		480
		481	enc_obj_id =
		482	(le16_to_cpu(path->usGraphicObjIds[j]) &
		483	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		484	enc_obj_num =
		485	(le16_to_cpu(path->usGraphicObjIds[j]) &
		486	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		487	enc_obj_type =
		488	(le16_to_cpu(path->usGraphicObjIds[j]) &
		489	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		490
		491	/* FIXME: add support for router objects */
		492	if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		493	if (enc_obj_num == 2)
		494	linkb = true;
		495	else
		496	linkb = false;
		497
1123	serge	498	radeon_add_atom_encoder(dev,
		499	enc_obj_id,
		500	le16_to_cpu
		501	(path->
		502	usDeviceTag));
1117	serge	503
		504	}
		505	}
		506
1321	serge	507	/* look up gpio for ddc, hpd */
1117	serge	508	if ((le16_to_cpu(path->usDeviceTag) &
1321	serge	509	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT)) == 0) {
1117	serge	510	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		511	if (le16_to_cpu(path->usConnObjectId) ==
		512	le16_to_cpu(con_obj->asObjects[j].
		513	usObjectID)) {
		514	ATOM_COMMON_RECORD_HEADER
		515	*record =
		516	(ATOM_COMMON_RECORD_HEADER
		517	*)
		518	(ctx->bios + data_offset +
		519	le16_to_cpu(con_obj->
		520	asObjects[j].
		521	usRecordOffset));
		522	ATOM_I2C_RECORD *i2c_record;
1321	serge	523	ATOM_HPD_INT_RECORD *hpd_record;
		524	ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
		525	hpd.hpd = RADEON_HPD_NONE;
1117	serge	526
		527	while (record->ucRecordType > 0
		528	&& record->
		529	ucRecordType <=
		530	ATOM_MAX_OBJECT_RECORD_NUMBER) {
1321	serge	531	switch (record->ucRecordType) {
1117	serge	532	case ATOM_I2C_RECORD_TYPE:
		533	i2c_record =
1321	serge	534	(ATOM_I2C_RECORD *)
		535	record;
		536	i2c_config =
		537	(ATOM_I2C_ID_CONFIG_ACCESS *)
		538	&i2c_record->sucI2cId;
		539	ddc_bus = radeon_lookup_i2c_gpio(rdev,
		540	i2c_config->
		541	ucAccess);
1117	serge	542	break;
1321	serge	543	case ATOM_HPD_INT_RECORD_TYPE:
		544	hpd_record =
		545	(ATOM_HPD_INT_RECORD *)
		546	record;
		547	gpio = radeon_lookup_gpio(rdev,
		548	hpd_record->ucHPDIntGPIOID);
		549	hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
		550	hpd.plugged_state = hpd_record->ucPlugged_PinState;
		551	break;
1117	serge	552	}
		553	record =
		554	(ATOM_COMMON_RECORD_HEADER
		555	) ((char )record
		556	+
		557	record->
		558	ucRecordSize);
		559	}
		560	break;
		561	}
		562	}
1321	serge	563	} else {
		564	hpd.hpd = RADEON_HPD_NONE;
1117	serge	565	ddc_bus.valid = false;
1321	serge	566	}
1117	serge	567
1179	serge	568	conn_id = le16_to_cpu(path->usConnObjectId);
		569
		570	if (!radeon_atom_apply_quirks
		571	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
1321	serge	572	&ddc_bus, &conn_id, &hpd))
1179	serge	573	continue;
		574
1123	serge	575	radeon_add_atom_connector(dev,
1179	serge	576	conn_id,
1123	serge	577	le16_to_cpu(path->
		578	usDeviceTag),
		579	connector_type, &ddc_bus,
1268	serge	580	linkb, igp_lane_info,
1321	serge	581	connector_object_id,
		582	&hpd);
1117	serge	583
		584	}
		585	}
		586
1123	serge	587	radeon_link_encoder_connector(dev);
1117	serge	588
		589	return true;
		590	}
		591
1268	serge	592	static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
		593	int connector_type,
		594	uint16_t devices)
		595	{
		596	struct radeon_device *rdev = dev->dev_private;
		597
		598	if (rdev->flags & RADEON_IS_IGP) {
		599	return supported_devices_connector_object_id_convert
		600	[connector_type];
		601	} else if (((connector_type == DRM_MODE_CONNECTOR_DVII) \|\|
		602	(connector_type == DRM_MODE_CONNECTOR_DVID)) &&
		603	(devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		604	struct radeon_mode_info *mode_info = &rdev->mode_info;
		605	struct atom_context *ctx = mode_info->atom_context;
		606	int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
		607	uint16_t size, data_offset;
		608	uint8_t frev, crev;
		609	ATOM_XTMDS_INFO *xtmds;
		610
		611	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		612	xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
		613
		614	if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
		615	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		616	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
		617	else
		618	return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
		619	} else {
		620	if (connector_type == DRM_MODE_CONNECTOR_DVII)
		621	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
		622	else
		623	return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
		624	}
		625	} else {
		626	return supported_devices_connector_object_id_convert
		627	[connector_type];
		628	}
		629	}
		630
1117	serge	631	struct bios_connector {
		632	bool valid;
1179	serge	633	uint16_t line_mux;
1117	serge	634	uint16_t devices;
		635	int connector_type;
		636	struct radeon_i2c_bus_rec ddc_bus;
1321	serge	637	struct radeon_hpd hpd;
1117	serge	638	};
		639
		640	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		641	drm_device
		642	*dev)
		643	{
		644	struct radeon_device *rdev = dev->dev_private;
		645	struct radeon_mode_info *mode_info = &rdev->mode_info;
		646	struct atom_context *ctx = mode_info->atom_context;
		647	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		648	uint16_t size, data_offset;
		649	uint8_t frev, crev;
		650	uint16_t device_support;
		651	uint8_t dac;
		652	union atom_supported_devices *supported_devices;
1321	serge	653	int i, j, max_device;
1117	serge	654	struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
		655
		656	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
1128	serge	657
1117	serge	658	supported_devices =
		659	(union atom_supported_devices *)(ctx->bios + data_offset);
		660
		661	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		662
1321	serge	663	if (frev > 1)
		664	max_device = ATOM_MAX_SUPPORTED_DEVICE;
		665	else
		666	max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
		667
		668	for (i = 0; i < max_device; i++) {
1117	serge	669	ATOM_CONNECTOR_INFO_I2C ci =
		670	supported_devices->info.asConnInfo[i];
		671
		672	bios_connectors[i].valid = false;
		673
		674	if (!(device_support & (1 << i))) {
		675	continue;
		676	}
		677
		678	if (i == ATOM_DEVICE_CV_INDEX) {
		679	DRM_DEBUG("Skipping Component Video\n");
		680	continue;
		681	}
		682
		683	bios_connectors[i].connector_type =
		684	supported_devices_connector_convert[ci.sucConnectorInfo.
		685	sbfAccess.
		686	bfConnectorType];
		687
		688	if (bios_connectors[i].connector_type ==
		689	DRM_MODE_CONNECTOR_Unknown)
		690	continue;
		691
		692	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		693
		694	bios_connectors[i].line_mux =
1321	serge	695	ci.sucI2cId.ucAccess;
1117	serge	696
		697	/* give tv unique connector ids */
		698	if (i == ATOM_DEVICE_TV1_INDEX) {
		699	bios_connectors[i].ddc_bus.valid = false;
		700	bios_connectors[i].line_mux = 50;
		701	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		702	bios_connectors[i].ddc_bus.valid = false;
		703	bios_connectors[i].line_mux = 51;
		704	} else if (i == ATOM_DEVICE_CV_INDEX) {
		705	bios_connectors[i].ddc_bus.valid = false;
		706	bios_connectors[i].line_mux = 52;
		707	} else
		708	bios_connectors[i].ddc_bus =
1321	serge	709	radeon_lookup_i2c_gpio(rdev,
1117	serge	710	bios_connectors[i].line_mux);
		711
1321	serge	712	if ((crev > 1) && (frev > 1)) {
		713	u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
		714	switch (isb) {
		715	case 0x4:
		716	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		717	break;
		718	case 0xa:
		719	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		720	break;
		721	default:
		722	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		723	break;
		724	}
		725	} else {
		726	if (i == ATOM_DEVICE_DFP1_INDEX)
		727	bios_connectors[i].hpd.hpd = RADEON_HPD_1;
		728	else if (i == ATOM_DEVICE_DFP2_INDEX)
		729	bios_connectors[i].hpd.hpd = RADEON_HPD_2;
		730	else
		731	bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
		732	}
		733
1117	serge	734	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		735	* shared with a DVI port, we'll pick up the DVI connector when we
		736	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		737	*/
		738	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		739	bios_connectors[i].connector_type =
		740	DRM_MODE_CONNECTOR_VGA;
		741
		742	if (!radeon_atom_apply_quirks
		743	(dev, (1 << i), &bios_connectors[i].connector_type,
1321	serge	744	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
		745	&bios_connectors[i].hpd))
1117	serge	746	continue;
		747
		748	bios_connectors[i].valid = true;
		749	bios_connectors[i].devices = (1 << i);
		750
1123	serge	751	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		752	radeon_add_atom_encoder(dev,
		753	radeon_get_encoder_id(dev,
		754	(1 << i),
		755	dac),
		756	(1 << i));
		757	else
		758	radeon_add_legacy_encoder(dev,
		759	radeon_get_encoder_id(dev,
1404	serge	760	(1 << i),
1123	serge	761	dac),
		762	(1 << i));
1117	serge	763	}
		764
		765	/* combine shared connectors */
1321	serge	766	for (i = 0; i < max_device; i++) {
1117	serge	767	if (bios_connectors[i].valid) {
1321	serge	768	for (j = 0; j < max_device; j++) {
1117	serge	769	if (bios_connectors[j].valid && (i != j)) {
		770	if (bios_connectors[i].line_mux ==
		771	bios_connectors[j].line_mux) {
1404	serge	772	/* make sure not to combine LVDS */
		773	if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		774	bios_connectors[i].line_mux = 53;
		775	bios_connectors[i].ddc_bus.valid = false;
		776	continue;
		777	}
		778	if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		779	bios_connectors[j].line_mux = 53;
		780	bios_connectors[j].ddc_bus.valid = false;
		781	continue;
		782	}
		783	/* combine analog and digital for DVI-I */
		784	if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		785	(bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) \|\|
		786	((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
		787	(bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
		788	bios_connectors[i].devices \|=
		789	bios_connectors[j].devices;
		790	bios_connectors[i].connector_type =
1117	serge	791	DRM_MODE_CONNECTOR_DVII;
1404	serge	792	if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1321	serge	793	bios_connectors[i].hpd =
		794	bios_connectors[j].hpd;
1404	serge	795	bios_connectors[j].valid = false;
1117	serge	796	}
		797	}
		798	}
		799	}
		800	}
		801	}
		802
		803	/* add the connectors */
1321	serge	804	for (i = 0; i < max_device; i++) {
1268	serge	805	if (bios_connectors[i].valid) {
		806	uint16_t connector_object_id =
		807	atombios_get_connector_object_id(dev,
		808	bios_connectors[i].connector_type,
		809	bios_connectors[i].devices);
1123	serge	810	radeon_add_atom_connector(dev,
		811	bios_connectors[i].line_mux,
		812	bios_connectors[i].devices,
		813	bios_connectors[i].
		814	connector_type,
		815	&bios_connectors[i].ddc_bus,
1268	serge	816	false, 0,
1321	serge	817	connector_object_id,
		818	&bios_connectors[i].hpd);
1268	serge	819	}
1123	serge	820	}
1117	serge	821
1123	serge	822	radeon_link_encoder_connector(dev);
1128	serge	823
1117	serge	824	return true;
		825	}
		826
		827	union firmware_info {
		828	ATOM_FIRMWARE_INFO info;
		829	ATOM_FIRMWARE_INFO_V1_2 info_12;
		830	ATOM_FIRMWARE_INFO_V1_3 info_13;
		831	ATOM_FIRMWARE_INFO_V1_4 info_14;
		832	};
		833
		834	bool radeon_atom_get_clock_info(struct drm_device *dev)
		835	{
		836	struct radeon_device *rdev = dev->dev_private;
		837	struct radeon_mode_info *mode_info = &rdev->mode_info;
		838	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		839	union firmware_info *firmware_info;
		840	uint8_t frev, crev;
		841	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		842	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		843	struct radeon_pll *spll = &rdev->clock.spll;
		844	struct radeon_pll *mpll = &rdev->clock.mpll;
		845	uint16_t data_offset;
		846
		847	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		848	&crev, &data_offset);
		849
		850	firmware_info =
		851	(union firmware_info *)(mode_info->atom_context->bios +
		852	data_offset);
		853
		854	if (firmware_info) {
		855	/* pixel clocks */
		856	p1pll->reference_freq =
		857	le16_to_cpu(firmware_info->info.usReferenceClock);
		858	p1pll->reference_div = 0;
		859
1268	serge	860	if (crev < 2)
1117	serge	861	p1pll->pll_out_min =
		862	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1268	serge	863	else
		864	p1pll->pll_out_min =
		865	le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1117	serge	866	p1pll->pll_out_max =
		867	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		868
		869	if (p1pll->pll_out_min == 0) {
		870	if (ASIC_IS_AVIVO(rdev))
		871	p1pll->pll_out_min = 64800;
		872	else
		873	p1pll->pll_out_min = 20000;
1268	serge	874	} else if (p1pll->pll_out_min > 64800) {
		875	/* Limiting the pll output range is a good thing generally as
		876	* it limits the number of possible pll combinations for a given
		877	* frequency presumably to the ones that work best on each card.
		878	* However, certain duallink DVI monitors seem to like
		879	* pll combinations that would be limited by this at least on
		880	* pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
		881	* family.
		882	*/
1321	serge	883	if (!radeon_new_pll)
1268	serge	884	p1pll->pll_out_min = 64800;
1117	serge	885	}
		886
		887	p1pll->pll_in_min =
		888	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		889	p1pll->pll_in_max =
		890	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		891
		892	p2pll = p1pll;
		893
		894	/* system clock */
		895	spll->reference_freq =
		896	le16_to_cpu(firmware_info->info.usReferenceClock);
		897	spll->reference_div = 0;
		898
		899	spll->pll_out_min =
		900	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		901	spll->pll_out_max =
		902	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		903
		904	/* ??? */
		905	if (spll->pll_out_min == 0) {
		906	if (ASIC_IS_AVIVO(rdev))
		907	spll->pll_out_min = 64800;
		908	else
		909	spll->pll_out_min = 20000;
		910	}
		911
		912	spll->pll_in_min =
		913	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		914	spll->pll_in_max =
		915	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		916
		917	/* memory clock */
		918	mpll->reference_freq =
		919	le16_to_cpu(firmware_info->info.usReferenceClock);
		920	mpll->reference_div = 0;
		921
		922	mpll->pll_out_min =
		923	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		924	mpll->pll_out_max =
		925	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		926
		927	/* ??? */
		928	if (mpll->pll_out_min == 0) {
		929	if (ASIC_IS_AVIVO(rdev))
		930	mpll->pll_out_min = 64800;
		931	else
		932	mpll->pll_out_min = 20000;
		933	}
		934
		935	mpll->pll_in_min =
		936	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		937	mpll->pll_in_max =
		938	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		939
		940	rdev->clock.default_sclk =
		941	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		942	rdev->clock.default_mclk =
		943	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		944
		945	return true;
		946	}
		947	return false;
		948	}
		949
1404	serge	950	union igp_info {
		951	struct _ATOM_INTEGRATED_SYSTEM_INFO info;
		952	struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
		953	};
		954
		955	bool radeon_atombios_sideport_present(struct radeon_device *rdev)
		956	{
		957	struct radeon_mode_info *mode_info = &rdev->mode_info;
		958	int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
		959	union igp_info *igp_info;
		960	u8 frev, crev;
		961	u16 data_offset;
		962
		963	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		964	&crev, &data_offset);
		965
		966	igp_info = (union igp_info *)(mode_info->atom_context->bios +
		967	data_offset);
		968
		969	if (igp_info) {
		970	switch (crev) {
		971	case 1:
		972	if (igp_info->info.ucMemoryType & 0xf0)
		973	return true;
		974	break;
		975	case 2:
		976	if (igp_info->info_2.ucMemoryType & 0x0f)
		977	return true;
		978	break;
		979	default:
		980	DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
		981	break;
		982	}
		983	}
		984	return false;
		985	}
		986
1179	serge	987	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		988	struct radeon_encoder_int_tmds *tmds)
1117	serge	989	{
		990	struct drm_device *dev = encoder->base.dev;
		991	struct radeon_device *rdev = dev->dev_private;
		992	struct radeon_mode_info *mode_info = &rdev->mode_info;
		993	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		994	uint16_t data_offset;
		995	struct _ATOM_TMDS_INFO *tmds_info;
		996	uint8_t frev, crev;
		997	uint16_t maxfreq;
		998	int i;
		999
		1000	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1001	&crev, &data_offset);
		1002
		1003	tmds_info =
		1004	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		1005	data_offset);
		1006
		1007	if (tmds_info) {
		1008	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		1009	for (i = 0; i < 4; i++) {
		1010	tmds->tmds_pll[i].freq =
		1011	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		1012	tmds->tmds_pll[i].value =
		1013	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		1014	tmds->tmds_pll[i].value \|=
		1015	(tmds_info->asMiscInfo[i].
		1016	ucPLL_VCO_Gain & 0x3f) << 6;
		1017	tmds->tmds_pll[i].value \|=
		1018	(tmds_info->asMiscInfo[i].
		1019	ucPLL_DutyCycle & 0xf) << 12;
		1020	tmds->tmds_pll[i].value \|=
		1021	(tmds_info->asMiscInfo[i].
		1022	ucPLL_VoltageSwing & 0xf) << 16;
		1023
		1024	DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
		1025	tmds->tmds_pll[i].freq,
		1026	tmds->tmds_pll[i].value);
		1027
		1028	if (maxfreq == tmds->tmds_pll[i].freq) {
		1029	tmds->tmds_pll[i].freq = 0xffffffff;
		1030	break;
		1031	}
		1032	}
1179	serge	1033	return true;
1117	serge	1034	}
1179	serge	1035	return false;
1117	serge	1036	}
		1037
1268	serge	1038	static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
		1039	radeon_encoder
		1040	*encoder,
		1041	int id)
		1042	{
		1043	struct drm_device *dev = encoder->base.dev;
		1044	struct radeon_device *rdev = dev->dev_private;
		1045	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1046	int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
		1047	uint16_t data_offset;
		1048	struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
		1049	uint8_t frev, crev;
		1050	struct radeon_atom_ss *ss = NULL;
1321	serge	1051	int i;
1268	serge	1052
		1053	if (id > ATOM_MAX_SS_ENTRY)
		1054	return NULL;
		1055
		1056	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1057	&crev, &data_offset);
		1058
		1059	ss_info =
		1060	(struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
		1061
		1062	if (ss_info) {
		1063	ss =
		1064	kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
		1065
		1066	if (!ss)
		1067	return NULL;
		1068
1321	serge	1069	for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
		1070	if (ss_info->asSS_Info[i].ucSS_Id == id) {
		1071	ss->percentage =
		1072	le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
		1073	ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
		1074	ss->step = ss_info->asSS_Info[i].ucSS_Step;
		1075	ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
		1076	ss->range = ss_info->asSS_Info[i].ucSS_Range;
		1077	ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1404	serge	1078	break;
1268	serge	1079	}
1321	serge	1080	}
		1081	}
1268	serge	1082	return ss;
		1083	}
		1084
1117	serge	1085	union lvds_info {
		1086	struct _ATOM_LVDS_INFO info;
		1087	struct _ATOM_LVDS_INFO_V12 info_12;
		1088	};
		1089
		1090	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		1091	radeon_encoder
		1092	*encoder)
		1093	{
		1094	struct drm_device *dev = encoder->base.dev;
		1095	struct radeon_device *rdev = dev->dev_private;
		1096	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1097	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1321	serge	1098	uint16_t data_offset, misc;
1117	serge	1099	union lvds_info *lvds_info;
		1100	uint8_t frev, crev;
		1101	struct radeon_encoder_atom_dig *lvds = NULL;
		1102
		1103	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		1104	&crev, &data_offset);
		1105
		1106	lvds_info =
		1107	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		1108
		1109	if (lvds_info) {
		1110	lvds =
		1111	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		1112
		1113	if (!lvds)
		1114	return NULL;
		1115
1268	serge	1116	lvds->native_mode.clock =
1117	serge	1117	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1268	serge	1118	lvds->native_mode.hdisplay =
1117	serge	1119	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1268	serge	1120	lvds->native_mode.vdisplay =
1117	serge	1121	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1268	serge	1122	lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1117	serge	1123	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1268	serge	1124	lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1117	serge	1125	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1268	serge	1126	lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1117	serge	1127	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1268	serge	1128	lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1117	serge	1129	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1268	serge	1130	lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
		1131	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1132	lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1117	serge	1133	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		1134	lvds->panel_pwr_delay =
		1135	le16_to_cpu(lvds_info->info.usOffDelayInMs);
		1136	lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1321	serge	1137
		1138	misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
		1139	if (misc & ATOM_VSYNC_POLARITY)
		1140	lvds->native_mode.flags \|= DRM_MODE_FLAG_NVSYNC;
		1141	if (misc & ATOM_HSYNC_POLARITY)
		1142	lvds->native_mode.flags \|= DRM_MODE_FLAG_NHSYNC;
		1143	if (misc & ATOM_COMPOSITESYNC)
		1144	lvds->native_mode.flags \|= DRM_MODE_FLAG_CSYNC;
		1145	if (misc & ATOM_INTERLACE)
		1146	lvds->native_mode.flags \|= DRM_MODE_FLAG_INTERLACE;
		1147	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1148	lvds->native_mode.flags \|= DRM_MODE_FLAG_DBLSCAN;
		1149
1268	serge	1150	/* set crtc values */
		1151	drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1117	serge	1152
1268	serge	1153	lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
		1154
1117	serge	1155	encoder->native_mode = lvds->native_mode;
		1156	}
		1157	return lvds;
		1158	}
		1159
		1160	struct radeon_encoder_primary_dac *
		1161	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		1162	{
		1163	struct drm_device *dev = encoder->base.dev;
		1164	struct radeon_device *rdev = dev->dev_private;
		1165	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1166	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1167	uint16_t data_offset;
		1168	struct _COMPASSIONATE_DATA *dac_info;
		1169	uint8_t frev, crev;
		1170	uint8_t bg, dac;
		1171	struct radeon_encoder_primary_dac *p_dac = NULL;
		1172
		1173	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1174
		1175	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1176
		1177	if (dac_info) {
		1178	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		1179
		1180	if (!p_dac)
		1181	return NULL;
		1182
		1183	bg = dac_info->ucDAC1_BG_Adjustment;
		1184	dac = dac_info->ucDAC1_DAC_Adjustment;
		1185	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		1186
		1187	}
		1188	return p_dac;
		1189	}
		1190
1179	serge	1191	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1268	serge	1192	struct drm_display_mode *mode)
1179	serge	1193	{
		1194	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1195	ATOM_ANALOG_TV_INFO *tv_info;
		1196	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		1197	ATOM_DTD_FORMAT *dtd_timings;
		1198	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1199	u8 frev, crev;
1268	serge	1200	u16 data_offset, misc;
1179	serge	1201
		1202	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
		1203
		1204	switch (crev) {
		1205	case 1:
		1206	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		1207	if (index > MAX_SUPPORTED_TV_TIMING)
		1208	return false;
		1209
1268	serge	1210	mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		1211	mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		1212	mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		1213	mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
		1214	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1179	serge	1215
1268	serge	1216	mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		1217	mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		1218	mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		1219	mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
		1220	le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1179	serge	1221
1268	serge	1222	mode->flags = 0;
		1223	misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
		1224	if (misc & ATOM_VSYNC_POLARITY)
		1225	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1226	if (misc & ATOM_HSYNC_POLARITY)
		1227	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1228	if (misc & ATOM_COMPOSITESYNC)
		1229	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1230	if (misc & ATOM_INTERLACE)
		1231	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1232	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1233	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
1179	serge	1234
1268	serge	1235	mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1179	serge	1236
		1237	if (index == 1) {
		1238	/* PAL timings appear to have wrong values for totals */
1268	serge	1239	mode->crtc_htotal -= 1;
		1240	mode->crtc_vtotal -= 1;
1179	serge	1241	}
		1242	break;
		1243	case 2:
		1244	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
		1245	if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
		1246	return false;
		1247
		1248	dtd_timings = &tv_info_v1_2->aModeTimings[index];
1268	serge	1249	mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
		1250	le16_to_cpu(dtd_timings->usHBlanking_Time);
		1251	mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
		1252	mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
		1253	le16_to_cpu(dtd_timings->usHSyncOffset);
		1254	mode->crtc_hsync_end = mode->crtc_hsync_start +
		1255	le16_to_cpu(dtd_timings->usHSyncWidth);
1179	serge	1256
1268	serge	1257	mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
		1258	le16_to_cpu(dtd_timings->usVBlanking_Time);
		1259	mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
		1260	mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
		1261	le16_to_cpu(dtd_timings->usVSyncOffset);
		1262	mode->crtc_vsync_end = mode->crtc_vsync_start +
		1263	le16_to_cpu(dtd_timings->usVSyncWidth);
		1264
		1265	mode->flags = 0;
		1266	misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		1267	if (misc & ATOM_VSYNC_POLARITY)
		1268	mode->flags \|= DRM_MODE_FLAG_NVSYNC;
		1269	if (misc & ATOM_HSYNC_POLARITY)
		1270	mode->flags \|= DRM_MODE_FLAG_NHSYNC;
		1271	if (misc & ATOM_COMPOSITESYNC)
		1272	mode->flags \|= DRM_MODE_FLAG_CSYNC;
		1273	if (misc & ATOM_INTERLACE)
		1274	mode->flags \|= DRM_MODE_FLAG_INTERLACE;
		1275	if (misc & ATOM_DOUBLE_CLOCK_MODE)
		1276	mode->flags \|= DRM_MODE_FLAG_DBLSCAN;
		1277
		1278	mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1179	serge	1279	break;
		1280	}
		1281	return true;
		1282	}
		1283
1404	serge	1284	enum radeon_tv_std
		1285	radeon_atombios_get_tv_info(struct radeon_device *rdev)
		1286	{
		1287	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1288	int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		1289	uint16_t data_offset;
		1290	uint8_t frev, crev;
		1291	struct _ATOM_ANALOG_TV_INFO *tv_info;
		1292	enum radeon_tv_std tv_std = TV_STD_NTSC;
		1293
		1294	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1295
		1296	tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		1297
		1298	switch (tv_info->ucTV_BootUpDefaultStandard) {
		1299	case ATOM_TV_NTSC:
		1300	tv_std = TV_STD_NTSC;
		1301	DRM_INFO("Default TV standard: NTSC\n");
		1302	break;
		1303	case ATOM_TV_NTSCJ:
		1304	tv_std = TV_STD_NTSC_J;
		1305	DRM_INFO("Default TV standard: NTSC-J\n");
		1306	break;
		1307	case ATOM_TV_PAL:
		1308	tv_std = TV_STD_PAL;
		1309	DRM_INFO("Default TV standard: PAL\n");
		1310	break;
		1311	case ATOM_TV_PALM:
		1312	tv_std = TV_STD_PAL_M;
		1313	DRM_INFO("Default TV standard: PAL-M\n");
		1314	break;
		1315	case ATOM_TV_PALN:
		1316	tv_std = TV_STD_PAL_N;
		1317	DRM_INFO("Default TV standard: PAL-N\n");
		1318	break;
		1319	case ATOM_TV_PALCN:
		1320	tv_std = TV_STD_PAL_CN;
		1321	DRM_INFO("Default TV standard: PAL-CN\n");
		1322	break;
		1323	case ATOM_TV_PAL60:
		1324	tv_std = TV_STD_PAL_60;
		1325	DRM_INFO("Default TV standard: PAL-60\n");
		1326	break;
		1327	case ATOM_TV_SECAM:
		1328	tv_std = TV_STD_SECAM;
		1329	DRM_INFO("Default TV standard: SECAM\n");
		1330	break;
		1331	default:
		1332	tv_std = TV_STD_NTSC;
		1333	DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
		1334	break;
		1335	}
		1336	return tv_std;
		1337	}
		1338
1117	serge	1339	struct radeon_encoder_tv_dac *
		1340	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		1341	{
		1342	struct drm_device *dev = encoder->base.dev;
		1343	struct radeon_device *rdev = dev->dev_private;
		1344	struct radeon_mode_info *mode_info = &rdev->mode_info;
		1345	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		1346	uint16_t data_offset;
		1347	struct _COMPASSIONATE_DATA *dac_info;
		1348	uint8_t frev, crev;
		1349	uint8_t bg, dac;
		1350	struct radeon_encoder_tv_dac *tv_dac = NULL;
		1351
		1352	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		1353
		1354	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		1355
		1356	if (dac_info) {
		1357	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		1358
		1359	if (!tv_dac)
		1360	return NULL;
		1361
		1362	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		1363	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		1364	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		1365
		1366	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		1367	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		1368	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		1369
		1370	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		1371	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		1372	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		1373
1404	serge	1374	tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1117	serge	1375	}
		1376	return tv_dac;
		1377	}
		1378
		1379	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
		1380	{
		1381	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		1382	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
		1383
		1384	args.ucEnable = enable;
		1385
		1386	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1387	}
		1388
		1389	void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
		1390	{
		1391	ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
		1392	int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
		1393
		1394	args.ucEnable = enable;
		1395
		1396	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1397	}
		1398
1268	serge	1399	uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
		1400	{
		1401	GET_ENGINE_CLOCK_PS_ALLOCATION args;
		1402	int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
		1403
		1404	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1405	return args.ulReturnEngineClock;
		1406	}
		1407
		1408	uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
		1409	{
		1410	GET_MEMORY_CLOCK_PS_ALLOCATION args;
		1411	int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
		1412
		1413	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1414	return args.ulReturnMemoryClock;
		1415	}
		1416
1117	serge	1417	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		1418	uint32_t eng_clock)
		1419	{
		1420	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		1421	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		1422
		1423	args.ulTargetEngineClock = eng_clock; /* 10 khz */
		1424
		1425	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1426	}
		1427
		1428	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		1429	uint32_t mem_clock)
		1430	{
		1431	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		1432	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		1433
		1434	if (rdev->flags & RADEON_IS_IGP)
		1435	return;
		1436
		1437	args.ulTargetMemoryClock = mem_clock; /* 10 khz */
		1438
		1439	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1440	}
		1441
		1442	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		1443	{
		1444	struct radeon_device *rdev = dev->dev_private;
		1445	uint32_t bios_2_scratch, bios_6_scratch;
		1446
		1447	if (rdev->family >= CHIP_R600) {
1179	serge	1448	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	1449	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1450	} else {
1179	serge	1451	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	1452	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1453	}
		1454
		1455	/* let the bios control the backlight */
		1456	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		1457
		1458	/* tell the bios not to handle mode switching */
		1459	bios_6_scratch \|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH \| ATOM_S6_ACC_MODE);
		1460
		1461	if (rdev->family >= CHIP_R600) {
		1462	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1463	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1464	} else {
		1465	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1466	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1467	}
		1468
		1469	}
		1470
1179	serge	1471	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		1472	{
		1473	uint32_t scratch_reg;
		1474	int i;
		1475
		1476	if (rdev->family >= CHIP_R600)
		1477	scratch_reg = R600_BIOS_0_SCRATCH;
		1478	else
		1479	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1480
		1481	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1482	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		1483	}
		1484
		1485	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		1486	{
		1487	uint32_t scratch_reg;
		1488	int i;
		1489
		1490	if (rdev->family >= CHIP_R600)
		1491	scratch_reg = R600_BIOS_0_SCRATCH;
		1492	else
		1493	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1494
		1495	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1496	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		1497	}
		1498
1117	serge	1499	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		1500	{
		1501	struct drm_device *dev = encoder->dev;
		1502	struct radeon_device *rdev = dev->dev_private;
		1503	uint32_t bios_6_scratch;
		1504
		1505	if (rdev->family >= CHIP_R600)
		1506	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1507	else
		1508	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1509
		1510	if (lock)
		1511	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
		1512	else
		1513	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
		1514
		1515	if (rdev->family >= CHIP_R600)
		1516	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1517	else
		1518	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1519	}
		1520
		1521	/* at some point we may want to break this out into individual functions */
		1522	void
		1523	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		1524	struct drm_encoder *encoder,
		1525	bool connected)
		1526	{
		1527	struct drm_device *dev = connector->dev;
		1528	struct radeon_device *rdev = dev->dev_private;
		1529	struct radeon_connector *radeon_connector =
		1530	to_radeon_connector(connector);
		1531	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1532	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		1533
		1534	if (rdev->family >= CHIP_R600) {
		1535	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1536	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1537	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1538	} else {
		1539	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1540	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1541	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1542	}
		1543
		1544	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		1545	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		1546	if (connected) {
		1547	DRM_DEBUG("TV1 connected\n");
		1548	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		1549	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		1550	} else {
		1551	DRM_DEBUG("TV1 disconnected\n");
		1552	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		1553	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		1554	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		1555	}
		1556	}
		1557	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		1558	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		1559	if (connected) {
		1560	DRM_DEBUG("CV connected\n");
		1561	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		1562	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		1563	} else {
		1564	DRM_DEBUG("CV disconnected\n");
		1565	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		1566	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		1567	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		1568	}
		1569	}
		1570	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		1571	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		1572	if (connected) {
		1573	DRM_DEBUG("LCD1 connected\n");
		1574	bios_0_scratch \|= ATOM_S0_LCD1;
		1575	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		1576	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		1577	} else {
		1578	DRM_DEBUG("LCD1 disconnected\n");
		1579	bios_0_scratch &= ~ATOM_S0_LCD1;
		1580	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		1581	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		1582	}
		1583	}
		1584	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		1585	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		1586	if (connected) {
		1587	DRM_DEBUG("CRT1 connected\n");
		1588	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		1589	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		1590	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		1591	} else {
		1592	DRM_DEBUG("CRT1 disconnected\n");
		1593	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		1594	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		1595	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		1596	}
		1597	}
		1598	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		1599	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		1600	if (connected) {
		1601	DRM_DEBUG("CRT2 connected\n");
		1602	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		1603	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		1604	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		1605	} else {
		1606	DRM_DEBUG("CRT2 disconnected\n");
		1607	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		1608	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		1609	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		1610	}
		1611	}
		1612	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		1613	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		1614	if (connected) {
		1615	DRM_DEBUG("DFP1 connected\n");
		1616	bios_0_scratch \|= ATOM_S0_DFP1;
		1617	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		1618	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		1619	} else {
		1620	DRM_DEBUG("DFP1 disconnected\n");
		1621	bios_0_scratch &= ~ATOM_S0_DFP1;
		1622	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		1623	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		1624	}
		1625	}
		1626	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		1627	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		1628	if (connected) {
		1629	DRM_DEBUG("DFP2 connected\n");
		1630	bios_0_scratch \|= ATOM_S0_DFP2;
		1631	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		1632	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		1633	} else {
		1634	DRM_DEBUG("DFP2 disconnected\n");
		1635	bios_0_scratch &= ~ATOM_S0_DFP2;
		1636	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		1637	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		1638	}
		1639	}
		1640	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		1641	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		1642	if (connected) {
		1643	DRM_DEBUG("DFP3 connected\n");
		1644	bios_0_scratch \|= ATOM_S0_DFP3;
		1645	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		1646	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		1647	} else {
		1648	DRM_DEBUG("DFP3 disconnected\n");
		1649	bios_0_scratch &= ~ATOM_S0_DFP3;
		1650	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		1651	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		1652	}
		1653	}
		1654	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		1655	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		1656	if (connected) {
		1657	DRM_DEBUG("DFP4 connected\n");
		1658	bios_0_scratch \|= ATOM_S0_DFP4;
		1659	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		1660	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		1661	} else {
		1662	DRM_DEBUG("DFP4 disconnected\n");
		1663	bios_0_scratch &= ~ATOM_S0_DFP4;
		1664	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		1665	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		1666	}
		1667	}
		1668	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		1669	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		1670	if (connected) {
		1671	DRM_DEBUG("DFP5 connected\n");
		1672	bios_0_scratch \|= ATOM_S0_DFP5;
		1673	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		1674	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		1675	} else {
		1676	DRM_DEBUG("DFP5 disconnected\n");
		1677	bios_0_scratch &= ~ATOM_S0_DFP5;
		1678	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		1679	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		1680	}
		1681	}
		1682
		1683	if (rdev->family >= CHIP_R600) {
		1684	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		1685	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1686	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1687	} else {
		1688	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		1689	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1690	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1691	}
		1692	}
		1693
		1694	void
		1695	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		1696	{
		1697	struct drm_device *dev = encoder->dev;
		1698	struct radeon_device *rdev = dev->dev_private;
		1699	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1700	uint32_t bios_3_scratch;
		1701
		1702	if (rdev->family >= CHIP_R600)
		1703	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1704	else
		1705	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1706
		1707	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1708	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		1709	bios_3_scratch \|= (crtc << 18);
		1710	}
		1711	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1712	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		1713	bios_3_scratch \|= (crtc << 24);
		1714	}
		1715	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1716	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		1717	bios_3_scratch \|= (crtc << 16);
		1718	}
		1719	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1720	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		1721	bios_3_scratch \|= (crtc << 20);
		1722	}
		1723	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1724	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		1725	bios_3_scratch \|= (crtc << 17);
		1726	}
		1727	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1728	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		1729	bios_3_scratch \|= (crtc << 19);
		1730	}
		1731	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1732	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		1733	bios_3_scratch \|= (crtc << 23);
		1734	}
		1735	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1736	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		1737	bios_3_scratch \|= (crtc << 25);
		1738	}
		1739
		1740	if (rdev->family >= CHIP_R600)
		1741	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1742	else
		1743	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1744	}
		1745
		1746	void
		1747	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		1748	{
		1749	struct drm_device *dev = encoder->dev;
		1750	struct radeon_device *rdev = dev->dev_private;
		1751	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1752	uint32_t bios_2_scratch;
		1753
		1754	if (rdev->family >= CHIP_R600)
		1755	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		1756	else
		1757	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		1758
		1759	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1760	if (on)
		1761	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		1762	else
		1763	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		1764	}
		1765	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1766	if (on)
		1767	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		1768	else
		1769	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		1770	}
		1771	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1772	if (on)
		1773	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		1774	else
		1775	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		1776	}
		1777	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1778	if (on)
		1779	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		1780	else
		1781	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		1782	}
		1783	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1784	if (on)
		1785	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		1786	else
		1787	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		1788	}
		1789	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1790	if (on)
		1791	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		1792	else
		1793	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		1794	}
		1795	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1796	if (on)
		1797	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		1798	else
		1799	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		1800	}
		1801	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1802	if (on)
		1803	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		1804	else
		1805	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		1806	}
		1807	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		1808	if (on)
		1809	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		1810	else
		1811	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		1812	}
		1813	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		1814	if (on)
		1815	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		1816	else
		1817	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		1818	}
		1819
		1820	if (rdev->family >= CHIP_R600)
		1821	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1822	else
		1823	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1824	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1412