WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_atombios.c

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2007-8 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	*
		5	* Permission is hereby granted, free of charge, to any person obtaining a
		6	* copy of this software and associated documentation files (the "Software"),
		7	* to deal in the Software without restriction, including without limitation
		8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		9	* and/or sell copies of the Software, and to permit persons to whom the
		10	* Software is furnished to do so, subject to the following conditions:
		11	*
		12	* The above copyright notice and this permission notice shall be included in
		13	* all copies or substantial portions of the Software.
		14	*
		15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		21	* OTHER DEALINGS IN THE SOFTWARE.
		22	*
		23	* Authors: Dave Airlie
		24	* Alex Deucher
		25	*/
1123	serge	26	#include "drmP.h"
1117	serge	27	#include "radeon_drm.h"
		28	#include "radeon.h"
		29
		30	#include "atom.h"
		31	#include "atom-bits.h"
		32
		33	/* from radeon_encoder.c */
		34	extern uint32_t
		35	radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
		36	uint8_t dac);
		37	extern void radeon_link_encoder_connector(struct drm_device *dev);
		38	extern void
		39	radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
		40	uint32_t supported_device);
		41
		42	/* from radeon_connector.c */
		43	extern void
		44	radeon_add_atom_connector(struct drm_device *dev,
		45	uint32_t connector_id,
		46	uint32_t supported_device,
		47	int connector_type,
		48	struct radeon_i2c_bus_rec *i2c_bus,
		49	bool linkb, uint32_t igp_lane_info);
		50
		51	/* from radeon_legacy_encoder.c */
		52	extern void
		53	radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
		54	uint32_t supported_device);
		55
		56	union atom_supported_devices {
		57	struct _ATOM_SUPPORTED_DEVICES_INFO info;
		58	struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
		59	struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
		60	};
		61
		62	static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
		63	*dev, uint8_t id)
		64	{
		65	struct radeon_device *rdev = dev->dev_private;
		66	struct atom_context *ctx = rdev->mode_info.atom_context;
		67	ATOM_GPIO_I2C_ASSIGMENT gpio;
		68	struct radeon_i2c_bus_rec i2c;
		69	int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
		70	struct _ATOM_GPIO_I2C_INFO *i2c_info;
		71	uint16_t data_offset;
		72
		73	memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
		74	i2c.valid = false;
		75
		76	atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
		77
		78	i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
		79
		80	gpio = i2c_info->asGPIO_Info[id];
		81
		82	i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
		83	i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
		84	i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
		85	i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
		86	i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
		87	i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
		88	i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
		89	i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
		90	i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
		91	i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
		92	i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
		93	i2c.put_data_mask = (1 << gpio.ucDataEnShift);
		94	i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
		95	i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
		96	i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
		97	i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
		98	i2c.valid = true;
		99
		100	return i2c;
		101	}
		102
		103	static bool radeon_atom_apply_quirks(struct drm_device *dev,
		104	uint32_t supported_device,
		105	int *connector_type,
1179	serge	106	struct radeon_i2c_bus_rec *i2c_bus,
		107	uint16_t *line_mux)
1117	serge	108	{
		109
		110	/* Asus M2A-VM HDMI board lists the DVI port as HDMI */
		111	if ((dev->pdev->device == 0x791e) &&
		112	(dev->pdev->subsystem_vendor == 0x1043) &&
		113	(dev->pdev->subsystem_device == 0x826d)) {
		114	if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
		115	(supported_device == ATOM_DEVICE_DFP3_SUPPORT))
		116	*connector_type = DRM_MODE_CONNECTOR_DVID;
		117	}
		118
		119	/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
		120	if ((dev->pdev->device == 0x7941) &&
		121	(dev->pdev->subsystem_vendor == 0x147b) &&
		122	(dev->pdev->subsystem_device == 0x2412)) {
		123	if (*connector_type == DRM_MODE_CONNECTOR_DVII)
		124	return false;
		125	}
		126
		127	/* Falcon NW laptop lists vga ddc line for LVDS */
		128	if ((dev->pdev->device == 0x5653) &&
		129	(dev->pdev->subsystem_vendor == 0x1462) &&
		130	(dev->pdev->subsystem_device == 0x0291)) {
1179	serge	131	if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
1117	serge	132	i2c_bus->valid = false;
1179	serge	133	*line_mux = 53;
		134	}
1117	serge	135	}
		136
		137	/* Funky macbooks */
		138	if ((dev->pdev->device == 0x71C5) &&
		139	(dev->pdev->subsystem_vendor == 0x106b) &&
		140	(dev->pdev->subsystem_device == 0x0080)) {
		141	if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) \|\|
		142	(supported_device == ATOM_DEVICE_DFP2_SUPPORT))
		143	return false;
		144	}
		145
		146	/* ASUS HD 3600 XT board lists the DVI port as HDMI */
		147	if ((dev->pdev->device == 0x9598) &&
		148	(dev->pdev->subsystem_vendor == 0x1043) &&
		149	(dev->pdev->subsystem_device == 0x01da)) {
1179	serge	150	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		151	*connector_type = DRM_MODE_CONNECTOR_DVII;
1117	serge	152	}
		153	}
		154
1179	serge	155	/* ASUS HD 3450 board lists the DVI port as HDMI */
		156	if ((dev->pdev->device == 0x95C5) &&
		157	(dev->pdev->subsystem_vendor == 0x1043) &&
		158	(dev->pdev->subsystem_device == 0x01e2)) {
		159	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		160	*connector_type = DRM_MODE_CONNECTOR_DVII;
		161	}
		162	}
		163
		164	/* some BIOSes seem to report DAC on HDMI - usually this is a board with
		165	* HDMI + VGA reporting as HDMI
		166	*/
		167	if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
		168	if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
		169	*connector_type = DRM_MODE_CONNECTOR_VGA;
		170	*line_mux = 0;
		171	}
		172	}
		173
1117	serge	174	return true;
		175	}
		176
		177	const int supported_devices_connector_convert[] = {
		178	DRM_MODE_CONNECTOR_Unknown,
		179	DRM_MODE_CONNECTOR_VGA,
		180	DRM_MODE_CONNECTOR_DVII,
		181	DRM_MODE_CONNECTOR_DVID,
		182	DRM_MODE_CONNECTOR_DVIA,
		183	DRM_MODE_CONNECTOR_SVIDEO,
		184	DRM_MODE_CONNECTOR_Composite,
		185	DRM_MODE_CONNECTOR_LVDS,
		186	DRM_MODE_CONNECTOR_Unknown,
		187	DRM_MODE_CONNECTOR_Unknown,
		188	DRM_MODE_CONNECTOR_HDMIA,
		189	DRM_MODE_CONNECTOR_HDMIB,
		190	DRM_MODE_CONNECTOR_Unknown,
		191	DRM_MODE_CONNECTOR_Unknown,
		192	DRM_MODE_CONNECTOR_9PinDIN,
		193	DRM_MODE_CONNECTOR_DisplayPort
		194	};
		195
		196	const int object_connector_convert[] = {
		197	DRM_MODE_CONNECTOR_Unknown,
		198	DRM_MODE_CONNECTOR_DVII,
		199	DRM_MODE_CONNECTOR_DVII,
		200	DRM_MODE_CONNECTOR_DVID,
		201	DRM_MODE_CONNECTOR_DVID,
		202	DRM_MODE_CONNECTOR_VGA,
		203	DRM_MODE_CONNECTOR_Composite,
		204	DRM_MODE_CONNECTOR_SVIDEO,
		205	DRM_MODE_CONNECTOR_Unknown,
1179	serge	206	DRM_MODE_CONNECTOR_Unknown,
1117	serge	207	DRM_MODE_CONNECTOR_9PinDIN,
		208	DRM_MODE_CONNECTOR_Unknown,
		209	DRM_MODE_CONNECTOR_HDMIA,
		210	DRM_MODE_CONNECTOR_HDMIB,
		211	DRM_MODE_CONNECTOR_LVDS,
		212	DRM_MODE_CONNECTOR_9PinDIN,
		213	DRM_MODE_CONNECTOR_Unknown,
		214	DRM_MODE_CONNECTOR_Unknown,
		215	DRM_MODE_CONNECTOR_Unknown,
		216	DRM_MODE_CONNECTOR_DisplayPort
		217	};
		218
		219	bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
		220	{
		221	struct radeon_device *rdev = dev->dev_private;
		222	struct radeon_mode_info *mode_info = &rdev->mode_info;
		223	struct atom_context *ctx = mode_info->atom_context;
		224	int index = GetIndexIntoMasterTable(DATA, Object_Header);
		225	uint16_t size, data_offset;
		226	uint8_t frev, crev, line_mux = 0;
		227	ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
		228	ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
		229	ATOM_OBJECT_HEADER *obj_header;
		230	int i, j, path_size, device_support;
		231	int connector_type;
1179	serge	232	uint16_t igp_lane_info, conn_id;
1117	serge	233	bool linkb;
		234	struct radeon_i2c_bus_rec ddc_bus;
		235
		236	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
		237
		238	if (data_offset == 0)
		239	return false;
		240
		241	if (crev < 2)
		242	return false;
		243
		244	obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
		245	path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
		246	(ctx->bios + data_offset +
		247	le16_to_cpu(obj_header->usDisplayPathTableOffset));
		248	con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
		249	(ctx->bios + data_offset +
		250	le16_to_cpu(obj_header->usConnectorObjectTableOffset));
		251	device_support = le16_to_cpu(obj_header->usDeviceSupport);
		252
		253	path_size = 0;
		254	for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
		255	uint8_t addr = (uint8_t ) path_obj->asDispPath;
		256	ATOM_DISPLAY_OBJECT_PATH *path;
		257	addr += path_size;
		258	path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
		259	path_size += le16_to_cpu(path->usSize);
		260	linkb = false;
		261
		262	if (device_support & le16_to_cpu(path->usDeviceTag)) {
		263	uint8_t con_obj_id, con_obj_num, con_obj_type;
		264
		265	con_obj_id =
		266	(le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
		267	>> OBJECT_ID_SHIFT;
		268	con_obj_num =
		269	(le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
		270	>> ENUM_ID_SHIFT;
		271	con_obj_type =
		272	(le16_to_cpu(path->usConnObjectId) &
		273	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		274
1221	serge	275	/* TODO CV support */
		276	if (le16_to_cpu(path->usDeviceTag) ==
		277	ATOM_DEVICE_CV_SUPPORT)
1117	serge	278	continue;
		279
		280	if ((rdev->family == CHIP_RS780) &&
		281	(con_obj_id ==
		282	CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
		283	uint16_t igp_offset = 0;
		284	ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
		285
		286	index =
		287	GetIndexIntoMasterTable(DATA,
		288	IntegratedSystemInfo);
		289
		290	atom_parse_data_header(ctx, index, &size, &frev,
		291	&crev, &igp_offset);
		292
		293	if (crev >= 2) {
		294	igp_obj =
		295	(ATOM_INTEGRATED_SYSTEM_INFO_V2
		296	*) (ctx->bios + igp_offset);
		297
		298	if (igp_obj) {
		299	uint32_t slot_config, ct;
		300
		301	if (con_obj_num == 1)
		302	slot_config =
		303	igp_obj->
		304	ulDDISlot1Config;
		305	else
		306	slot_config =
		307	igp_obj->
		308	ulDDISlot2Config;
		309
		310	ct = (slot_config >> 16) & 0xff;
		311	connector_type =
		312	object_connector_convert
		313	[ct];
		314	igp_lane_info =
		315	slot_config & 0xffff;
		316	} else
		317	continue;
		318	} else
		319	continue;
		320	} else {
		321	igp_lane_info = 0;
		322	connector_type =
		323	object_connector_convert[con_obj_id];
		324	}
		325
		326	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
		327	continue;
		328
		329	for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
		330	j++) {
		331	uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
		332
		333	enc_obj_id =
		334	(le16_to_cpu(path->usGraphicObjIds[j]) &
		335	OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
		336	enc_obj_num =
		337	(le16_to_cpu(path->usGraphicObjIds[j]) &
		338	ENUM_ID_MASK) >> ENUM_ID_SHIFT;
		339	enc_obj_type =
		340	(le16_to_cpu(path->usGraphicObjIds[j]) &
		341	OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
		342
		343	/* FIXME: add support for router objects */
		344	if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
		345	if (enc_obj_num == 2)
		346	linkb = true;
		347	else
		348	linkb = false;
		349
1123	serge	350	radeon_add_atom_encoder(dev,
		351	enc_obj_id,
		352	le16_to_cpu
		353	(path->
		354	usDeviceTag));
1117	serge	355
		356	}
		357	}
		358
		359	/* look up gpio for ddc */
		360	if ((le16_to_cpu(path->usDeviceTag) &
		361	(ATOM_DEVICE_TV_SUPPORT \| ATOM_DEVICE_CV_SUPPORT))
		362	== 0) {
		363	for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
		364	if (le16_to_cpu(path->usConnObjectId) ==
		365	le16_to_cpu(con_obj->asObjects[j].
		366	usObjectID)) {
		367	ATOM_COMMON_RECORD_HEADER
		368	*record =
		369	(ATOM_COMMON_RECORD_HEADER
		370	*)
		371	(ctx->bios + data_offset +
		372	le16_to_cpu(con_obj->
		373	asObjects[j].
		374	usRecordOffset));
		375	ATOM_I2C_RECORD *i2c_record;
		376
		377	while (record->ucRecordType > 0
		378	&& record->
		379	ucRecordType <=
		380	ATOM_MAX_OBJECT_RECORD_NUMBER) {
		381	switch (record->
		382	ucRecordType) {
		383	case ATOM_I2C_RECORD_TYPE:
		384	i2c_record =
		385	(ATOM_I2C_RECORD
		386	*) record;
		387	line_mux =
		388	i2c_record->
		389	sucI2cId.
		390	bfI2C_LineMux;
		391	break;
		392	}
		393	record =
		394	(ATOM_COMMON_RECORD_HEADER
		395	) ((char )record
		396	+
		397	record->
		398	ucRecordSize);
		399	}
		400	break;
		401	}
		402	}
		403	} else
		404	line_mux = 0;
		405
		406	if ((le16_to_cpu(path->usDeviceTag) ==
		407	ATOM_DEVICE_TV1_SUPPORT)
		408	\|\| (le16_to_cpu(path->usDeviceTag) ==
		409	ATOM_DEVICE_TV2_SUPPORT)
		410	\|\| (le16_to_cpu(path->usDeviceTag) ==
		411	ATOM_DEVICE_CV_SUPPORT))
		412	ddc_bus.valid = false;
		413	else
		414	ddc_bus = radeon_lookup_gpio(dev, line_mux);
		415
1179	serge	416	conn_id = le16_to_cpu(path->usConnObjectId);
		417
		418	if (!radeon_atom_apply_quirks
		419	(dev, le16_to_cpu(path->usDeviceTag), &connector_type,
		420	&ddc_bus, &conn_id))
		421	continue;
		422
1123	serge	423	radeon_add_atom_connector(dev,
1179	serge	424	conn_id,
1123	serge	425	le16_to_cpu(path->
		426	usDeviceTag),
		427	connector_type, &ddc_bus,
		428	linkb, igp_lane_info);
1117	serge	429
		430	}
		431	}
		432
1123	serge	433	radeon_link_encoder_connector(dev);
1117	serge	434
		435	return true;
		436	}
		437
		438	struct bios_connector {
		439	bool valid;
1179	serge	440	uint16_t line_mux;
1117	serge	441	uint16_t devices;
		442	int connector_type;
		443	struct radeon_i2c_bus_rec ddc_bus;
		444	};
		445
		446	bool radeon_get_atom_connector_info_from_supported_devices_table(struct
		447	drm_device
		448	*dev)
		449	{
		450	struct radeon_device *rdev = dev->dev_private;
		451	struct radeon_mode_info *mode_info = &rdev->mode_info;
		452	struct atom_context *ctx = mode_info->atom_context;
		453	int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
		454	uint16_t size, data_offset;
		455	uint8_t frev, crev;
		456	uint16_t device_support;
		457	uint8_t dac;
		458	union atom_supported_devices *supported_devices;
		459	int i, j;
		460	struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
		461
		462	atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
1128	serge	463
1117	serge	464	supported_devices =
		465	(union atom_supported_devices *)(ctx->bios + data_offset);
		466
		467	device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
		468
		469	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		470	ATOM_CONNECTOR_INFO_I2C ci =
		471	supported_devices->info.asConnInfo[i];
		472
		473	bios_connectors[i].valid = false;
		474
		475	if (!(device_support & (1 << i))) {
		476	continue;
		477	}
		478
		479	if (i == ATOM_DEVICE_CV_INDEX) {
		480	DRM_DEBUG("Skipping Component Video\n");
		481	continue;
		482	}
		483
		484	bios_connectors[i].connector_type =
		485	supported_devices_connector_convert[ci.sucConnectorInfo.
		486	sbfAccess.
		487	bfConnectorType];
		488
		489	if (bios_connectors[i].connector_type ==
		490	DRM_MODE_CONNECTOR_Unknown)
		491	continue;
		492
		493	dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
		494
		495	if ((rdev->family == CHIP_RS690) \|\|
		496	(rdev->family == CHIP_RS740)) {
		497	if ((i == ATOM_DEVICE_DFP2_INDEX)
		498	&& (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
		499	bios_connectors[i].line_mux =
		500	ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
		501	else if ((i == ATOM_DEVICE_DFP3_INDEX)
		502	&& (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
		503	bios_connectors[i].line_mux =
		504	ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
		505	else
		506	bios_connectors[i].line_mux =
		507	ci.sucI2cId.sbfAccess.bfI2C_LineMux;
		508	} else
		509	bios_connectors[i].line_mux =
		510	ci.sucI2cId.sbfAccess.bfI2C_LineMux;
		511
		512	/* give tv unique connector ids */
		513	if (i == ATOM_DEVICE_TV1_INDEX) {
		514	bios_connectors[i].ddc_bus.valid = false;
		515	bios_connectors[i].line_mux = 50;
		516	} else if (i == ATOM_DEVICE_TV2_INDEX) {
		517	bios_connectors[i].ddc_bus.valid = false;
		518	bios_connectors[i].line_mux = 51;
		519	} else if (i == ATOM_DEVICE_CV_INDEX) {
		520	bios_connectors[i].ddc_bus.valid = false;
		521	bios_connectors[i].line_mux = 52;
		522	} else
		523	bios_connectors[i].ddc_bus =
		524	radeon_lookup_gpio(dev,
		525	bios_connectors[i].line_mux);
		526
		527	/* Always set the connector type to VGA for CRT1/CRT2. if they are
		528	* shared with a DVI port, we'll pick up the DVI connector when we
		529	* merge the outputs. Some bioses incorrectly list VGA ports as DVI.
		530	*/
		531	if (i == ATOM_DEVICE_CRT1_INDEX \|\| i == ATOM_DEVICE_CRT2_INDEX)
		532	bios_connectors[i].connector_type =
		533	DRM_MODE_CONNECTOR_VGA;
		534
		535	if (!radeon_atom_apply_quirks
		536	(dev, (1 << i), &bios_connectors[i].connector_type,
1179	serge	537	&bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
1117	serge	538	continue;
		539
		540	bios_connectors[i].valid = true;
		541	bios_connectors[i].devices = (1 << i);
		542
1123	serge	543	if (ASIC_IS_AVIVO(rdev) \|\| radeon_r4xx_atom)
		544	radeon_add_atom_encoder(dev,
		545	radeon_get_encoder_id(dev,
		546	(1 << i),
		547	dac),
		548	(1 << i));
		549	else
		550	radeon_add_legacy_encoder(dev,
		551	radeon_get_encoder_id(dev,
		552	(1 <<
		553	i),
		554	dac),
		555	(1 << i));
1117	serge	556	}
		557
		558	/* combine shared connectors */
		559	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		560	if (bios_connectors[i].valid) {
		561	for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
		562	if (bios_connectors[j].valid && (i != j)) {
		563	if (bios_connectors[i].line_mux ==
		564	bios_connectors[j].line_mux) {
		565	if (((bios_connectors[i].
		566	devices &
		567	(ATOM_DEVICE_DFP_SUPPORT))
		568	&& (bios_connectors[j].
		569	devices &
		570	(ATOM_DEVICE_CRT_SUPPORT)))
		571	\|\|
		572	((bios_connectors[j].
		573	devices &
		574	(ATOM_DEVICE_DFP_SUPPORT))
		575	&& (bios_connectors[i].
		576	devices &
		577	(ATOM_DEVICE_CRT_SUPPORT)))) {
		578	bios_connectors[i].
		579	devices \|=
		580	bios_connectors[j].
		581	devices;
		582	bios_connectors[i].
		583	connector_type =
		584	DRM_MODE_CONNECTOR_DVII;
		585	bios_connectors[j].
		586	valid = false;
		587	}
		588	}
		589	}
		590	}
		591	}
		592	}
		593
		594	/* add the connectors */
1123	serge	595	for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
		596	if (bios_connectors[i].valid)
		597	radeon_add_atom_connector(dev,
		598	bios_connectors[i].line_mux,
		599	bios_connectors[i].devices,
		600	bios_connectors[i].
		601	connector_type,
		602	&bios_connectors[i].ddc_bus,
		603	false, 0);
		604	}
1117	serge	605
1123	serge	606	radeon_link_encoder_connector(dev);
1128	serge	607
1117	serge	608	return true;
		609	}
		610
		611	union firmware_info {
		612	ATOM_FIRMWARE_INFO info;
		613	ATOM_FIRMWARE_INFO_V1_2 info_12;
		614	ATOM_FIRMWARE_INFO_V1_3 info_13;
		615	ATOM_FIRMWARE_INFO_V1_4 info_14;
		616	};
		617
		618	bool radeon_atom_get_clock_info(struct drm_device *dev)
		619	{
		620	struct radeon_device *rdev = dev->dev_private;
		621	struct radeon_mode_info *mode_info = &rdev->mode_info;
		622	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
		623	union firmware_info *firmware_info;
		624	uint8_t frev, crev;
		625	struct radeon_pll *p1pll = &rdev->clock.p1pll;
		626	struct radeon_pll *p2pll = &rdev->clock.p2pll;
		627	struct radeon_pll *spll = &rdev->clock.spll;
		628	struct radeon_pll *mpll = &rdev->clock.mpll;
		629	uint16_t data_offset;
		630
		631	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		632	&crev, &data_offset);
		633
		634	firmware_info =
		635	(union firmware_info *)(mode_info->atom_context->bios +
		636	data_offset);
		637
		638	if (firmware_info) {
		639	/* pixel clocks */
		640	p1pll->reference_freq =
		641	le16_to_cpu(firmware_info->info.usReferenceClock);
		642	p1pll->reference_div = 0;
		643
		644	p1pll->pll_out_min =
		645	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
		646	p1pll->pll_out_max =
		647	le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
		648
		649	if (p1pll->pll_out_min == 0) {
		650	if (ASIC_IS_AVIVO(rdev))
		651	p1pll->pll_out_min = 64800;
		652	else
		653	p1pll->pll_out_min = 20000;
		654	}
		655
		656	p1pll->pll_in_min =
		657	le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
		658	p1pll->pll_in_max =
		659	le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
		660
		661	p2pll = p1pll;
		662
		663	/* system clock */
		664	spll->reference_freq =
		665	le16_to_cpu(firmware_info->info.usReferenceClock);
		666	spll->reference_div = 0;
		667
		668	spll->pll_out_min =
		669	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
		670	spll->pll_out_max =
		671	le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
		672
		673	/* ??? */
		674	if (spll->pll_out_min == 0) {
		675	if (ASIC_IS_AVIVO(rdev))
		676	spll->pll_out_min = 64800;
		677	else
		678	spll->pll_out_min = 20000;
		679	}
		680
		681	spll->pll_in_min =
		682	le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
		683	spll->pll_in_max =
		684	le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
		685
		686	/* memory clock */
		687	mpll->reference_freq =
		688	le16_to_cpu(firmware_info->info.usReferenceClock);
		689	mpll->reference_div = 0;
		690
		691	mpll->pll_out_min =
		692	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
		693	mpll->pll_out_max =
		694	le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
		695
		696	/* ??? */
		697	if (mpll->pll_out_min == 0) {
		698	if (ASIC_IS_AVIVO(rdev))
		699	mpll->pll_out_min = 64800;
		700	else
		701	mpll->pll_out_min = 20000;
		702	}
		703
		704	mpll->pll_in_min =
		705	le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
		706	mpll->pll_in_max =
		707	le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
		708
		709	rdev->clock.default_sclk =
		710	le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
		711	rdev->clock.default_mclk =
		712	le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
		713
		714	return true;
		715	}
		716	return false;
		717	}
		718
1179	serge	719	bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
		720	struct radeon_encoder_int_tmds *tmds)
1117	serge	721	{
		722	struct drm_device *dev = encoder->base.dev;
		723	struct radeon_device *rdev = dev->dev_private;
		724	struct radeon_mode_info *mode_info = &rdev->mode_info;
		725	int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
		726	uint16_t data_offset;
		727	struct _ATOM_TMDS_INFO *tmds_info;
		728	uint8_t frev, crev;
		729	uint16_t maxfreq;
		730	int i;
		731
		732	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		733	&crev, &data_offset);
		734
		735	tmds_info =
		736	(struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
		737	data_offset);
		738
		739	if (tmds_info) {
		740	maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
		741	for (i = 0; i < 4; i++) {
		742	tmds->tmds_pll[i].freq =
		743	le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
		744	tmds->tmds_pll[i].value =
		745	tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
		746	tmds->tmds_pll[i].value \|=
		747	(tmds_info->asMiscInfo[i].
		748	ucPLL_VCO_Gain & 0x3f) << 6;
		749	tmds->tmds_pll[i].value \|=
		750	(tmds_info->asMiscInfo[i].
		751	ucPLL_DutyCycle & 0xf) << 12;
		752	tmds->tmds_pll[i].value \|=
		753	(tmds_info->asMiscInfo[i].
		754	ucPLL_VoltageSwing & 0xf) << 16;
		755
		756	DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
		757	tmds->tmds_pll[i].freq,
		758	tmds->tmds_pll[i].value);
		759
		760	if (maxfreq == tmds->tmds_pll[i].freq) {
		761	tmds->tmds_pll[i].freq = 0xffffffff;
		762	break;
		763	}
		764	}
1179	serge	765	return true;
1117	serge	766	}
1179	serge	767	return false;
1117	serge	768	}
		769
		770	union lvds_info {
		771	struct _ATOM_LVDS_INFO info;
		772	struct _ATOM_LVDS_INFO_V12 info_12;
		773	};
		774
		775	struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
		776	radeon_encoder
		777	*encoder)
		778	{
		779	struct drm_device *dev = encoder->base.dev;
		780	struct radeon_device *rdev = dev->dev_private;
		781	struct radeon_mode_info *mode_info = &rdev->mode_info;
		782	int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
		783	uint16_t data_offset;
		784	union lvds_info *lvds_info;
		785	uint8_t frev, crev;
		786	struct radeon_encoder_atom_dig *lvds = NULL;
		787
		788	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
		789	&crev, &data_offset);
		790
		791	lvds_info =
		792	(union lvds_info *)(mode_info->atom_context->bios + data_offset);
		793
		794	if (lvds_info) {
		795	lvds =
		796	kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
		797
		798	if (!lvds)
		799	return NULL;
		800
		801	lvds->native_mode.dotclock =
		802	le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
		803	lvds->native_mode.panel_xres =
		804	le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
		805	lvds->native_mode.panel_yres =
		806	le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
		807	lvds->native_mode.hblank =
		808	le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
		809	lvds->native_mode.hoverplus =
		810	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
		811	lvds->native_mode.hsync_width =
		812	le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
		813	lvds->native_mode.vblank =
		814	le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
		815	lvds->native_mode.voverplus =
		816	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
		817	lvds->native_mode.vsync_width =
		818	le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
		819	lvds->panel_pwr_delay =
		820	le16_to_cpu(lvds_info->info.usOffDelayInMs);
		821	lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
		822
		823	encoder->native_mode = lvds->native_mode;
		824	}
		825	return lvds;
		826	}
		827
		828	struct radeon_encoder_primary_dac *
		829	radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
		830	{
		831	struct drm_device *dev = encoder->base.dev;
		832	struct radeon_device *rdev = dev->dev_private;
		833	struct radeon_mode_info *mode_info = &rdev->mode_info;
		834	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		835	uint16_t data_offset;
		836	struct _COMPASSIONATE_DATA *dac_info;
		837	uint8_t frev, crev;
		838	uint8_t bg, dac;
		839	struct radeon_encoder_primary_dac *p_dac = NULL;
		840
		841	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		842
		843	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		844
		845	if (dac_info) {
		846	p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
		847
		848	if (!p_dac)
		849	return NULL;
		850
		851	bg = dac_info->ucDAC1_BG_Adjustment;
		852	dac = dac_info->ucDAC1_DAC_Adjustment;
		853	p_dac->ps2_pdac_adj = (bg << 8) \| (dac);
		854
		855	}
		856	return p_dac;
		857	}
		858
1179	serge	859	bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
		860	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
		861	int32_t *pixel_clock)
		862	{
		863	struct radeon_mode_info *mode_info = &rdev->mode_info;
		864	ATOM_ANALOG_TV_INFO *tv_info;
		865	ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
		866	ATOM_DTD_FORMAT *dtd_timings;
		867	int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
		868	u8 frev, crev;
		869	uint16_t data_offset;
		870
		871	atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
		872
		873	switch (crev) {
		874	case 1:
		875	tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
		876	if (index > MAX_SUPPORTED_TV_TIMING)
		877	return false;
		878
		879	crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
		880	crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
		881	crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
		882	crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
		883
		884	crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
		885	crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
		886	crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
		887	crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
		888
		889	crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
		890
		891	crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
		892	crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
		893	crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
		894	crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
		895	pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) 10;
		896
		897	if (index == 1) {
		898	/* PAL timings appear to have wrong values for totals */
		899	crtc_timing->usH_Total -= 1;
		900	crtc_timing->usV_Total -= 1;
		901	}
		902	break;
		903	case 2:
		904	tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
		905	if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
		906	return false;
		907
		908	dtd_timings = &tv_info_v1_2->aModeTimings[index];
		909	crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
		910	crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
		911	crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
		912	crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
		913	crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
		914	crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
		915	crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
		916	crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
		917
		918	crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
		919	pixel_clock = le16_to_cpu(dtd_timings->usPixClk) 10;
		920	break;
		921	}
		922	return true;
		923	}
		924
1117	serge	925	struct radeon_encoder_tv_dac *
		926	radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
		927	{
		928	struct drm_device *dev = encoder->base.dev;
		929	struct radeon_device *rdev = dev->dev_private;
		930	struct radeon_mode_info *mode_info = &rdev->mode_info;
		931	int index = GetIndexIntoMasterTable(DATA, CompassionateData);
		932	uint16_t data_offset;
		933	struct _COMPASSIONATE_DATA *dac_info;
		934	uint8_t frev, crev;
		935	uint8_t bg, dac;
		936	struct radeon_encoder_tv_dac *tv_dac = NULL;
		937
		938	atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
		939
		940	dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
		941
		942	if (dac_info) {
		943	tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
		944
		945	if (!tv_dac)
		946	return NULL;
		947
		948	bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
		949	dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
		950	tv_dac->ps2_tvdac_adj = (bg << 16) \| (dac << 20);
		951
		952	bg = dac_info->ucDAC2_PAL_BG_Adjustment;
		953	dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
		954	tv_dac->pal_tvdac_adj = (bg << 16) \| (dac << 20);
		955
		956	bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
		957	dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
		958	tv_dac->ntsc_tvdac_adj = (bg << 16) \| (dac << 20);
		959
		960	}
		961	return tv_dac;
		962	}
		963
		964	void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
		965	{
		966	DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
		967	int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
		968
		969	args.ucEnable = enable;
		970
		971	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		972	}
		973
		974	void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
		975	{
		976	ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
		977	int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
		978
		979	args.ucEnable = enable;
		980
		981	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		982	}
		983
		984	void radeon_atom_set_engine_clock(struct radeon_device *rdev,
		985	uint32_t eng_clock)
		986	{
		987	SET_ENGINE_CLOCK_PS_ALLOCATION args;
		988	int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
		989
		990	args.ulTargetEngineClock = eng_clock; /* 10 khz */
		991
		992	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		993	}
		994
		995	void radeon_atom_set_memory_clock(struct radeon_device *rdev,
		996	uint32_t mem_clock)
		997	{
		998	SET_MEMORY_CLOCK_PS_ALLOCATION args;
		999	int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
		1000
		1001	if (rdev->flags & RADEON_IS_IGP)
		1002	return;
		1003
		1004	args.ulTargetMemoryClock = mem_clock; /* 10 khz */
		1005
		1006	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
		1007	}
		1008
		1009	void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
		1010	{
		1011	struct radeon_device *rdev = dev->dev_private;
		1012	uint32_t bios_2_scratch, bios_6_scratch;
		1013
		1014	if (rdev->family >= CHIP_R600) {
1179	serge	1015	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1117	serge	1016	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1017	} else {
1179	serge	1018	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1117	serge	1019	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1020	}
		1021
		1022	/* let the bios control the backlight */
		1023	bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
		1024
		1025	/* tell the bios not to handle mode switching */
		1026	bios_6_scratch \|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH \| ATOM_S6_ACC_MODE);
		1027
		1028	if (rdev->family >= CHIP_R600) {
		1029	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1030	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1031	} else {
		1032	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1033	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1034	}
		1035
		1036	}
		1037
1179	serge	1038	void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
		1039	{
		1040	uint32_t scratch_reg;
		1041	int i;
		1042
		1043	if (rdev->family >= CHIP_R600)
		1044	scratch_reg = R600_BIOS_0_SCRATCH;
		1045	else
		1046	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1047
		1048	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1049	rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
		1050	}
		1051
		1052	void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
		1053	{
		1054	uint32_t scratch_reg;
		1055	int i;
		1056
		1057	if (rdev->family >= CHIP_R600)
		1058	scratch_reg = R600_BIOS_0_SCRATCH;
		1059	else
		1060	scratch_reg = RADEON_BIOS_0_SCRATCH;
		1061
		1062	for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
		1063	WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
		1064	}
		1065
1117	serge	1066	void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
		1067	{
		1068	struct drm_device *dev = encoder->dev;
		1069	struct radeon_device *rdev = dev->dev_private;
		1070	uint32_t bios_6_scratch;
		1071
		1072	if (rdev->family >= CHIP_R600)
		1073	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1074	else
		1075	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1076
		1077	if (lock)
		1078	bios_6_scratch \|= ATOM_S6_CRITICAL_STATE;
		1079	else
		1080	bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
		1081
		1082	if (rdev->family >= CHIP_R600)
		1083	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1084	else
		1085	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1086	}
		1087
		1088	/* at some point we may want to break this out into individual functions */
		1089	void
		1090	radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
		1091	struct drm_encoder *encoder,
		1092	bool connected)
		1093	{
		1094	struct drm_device *dev = connector->dev;
		1095	struct radeon_device *rdev = dev->dev_private;
		1096	struct radeon_connector *radeon_connector =
		1097	to_radeon_connector(connector);
		1098	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1099	uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
		1100
		1101	if (rdev->family >= CHIP_R600) {
		1102	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
		1103	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1104	bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
		1105	} else {
		1106	bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
		1107	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1108	bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
		1109	}
		1110
		1111	if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
		1112	(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
		1113	if (connected) {
		1114	DRM_DEBUG("TV1 connected\n");
		1115	bios_3_scratch \|= ATOM_S3_TV1_ACTIVE;
		1116	bios_6_scratch \|= ATOM_S6_ACC_REQ_TV1;
		1117	} else {
		1118	DRM_DEBUG("TV1 disconnected\n");
		1119	bios_0_scratch &= ~ATOM_S0_TV1_MASK;
		1120	bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
		1121	bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
		1122	}
		1123	}
		1124	if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
		1125	(radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
		1126	if (connected) {
		1127	DRM_DEBUG("CV connected\n");
		1128	bios_3_scratch \|= ATOM_S3_CV_ACTIVE;
		1129	bios_6_scratch \|= ATOM_S6_ACC_REQ_CV;
		1130	} else {
		1131	DRM_DEBUG("CV disconnected\n");
		1132	bios_0_scratch &= ~ATOM_S0_CV_MASK;
		1133	bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
		1134	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
		1135	}
		1136	}
		1137	if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
		1138	(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
		1139	if (connected) {
		1140	DRM_DEBUG("LCD1 connected\n");
		1141	bios_0_scratch \|= ATOM_S0_LCD1;
		1142	bios_3_scratch \|= ATOM_S3_LCD1_ACTIVE;
		1143	bios_6_scratch \|= ATOM_S6_ACC_REQ_LCD1;
		1144	} else {
		1145	DRM_DEBUG("LCD1 disconnected\n");
		1146	bios_0_scratch &= ~ATOM_S0_LCD1;
		1147	bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
		1148	bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
		1149	}
		1150	}
		1151	if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
		1152	(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
		1153	if (connected) {
		1154	DRM_DEBUG("CRT1 connected\n");
		1155	bios_0_scratch \|= ATOM_S0_CRT1_COLOR;
		1156	bios_3_scratch \|= ATOM_S3_CRT1_ACTIVE;
		1157	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT1;
		1158	} else {
		1159	DRM_DEBUG("CRT1 disconnected\n");
		1160	bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
		1161	bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
		1162	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
		1163	}
		1164	}
		1165	if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
		1166	(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
		1167	if (connected) {
		1168	DRM_DEBUG("CRT2 connected\n");
		1169	bios_0_scratch \|= ATOM_S0_CRT2_COLOR;
		1170	bios_3_scratch \|= ATOM_S3_CRT2_ACTIVE;
		1171	bios_6_scratch \|= ATOM_S6_ACC_REQ_CRT2;
		1172	} else {
		1173	DRM_DEBUG("CRT2 disconnected\n");
		1174	bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
		1175	bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
		1176	bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
		1177	}
		1178	}
		1179	if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
		1180	(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
		1181	if (connected) {
		1182	DRM_DEBUG("DFP1 connected\n");
		1183	bios_0_scratch \|= ATOM_S0_DFP1;
		1184	bios_3_scratch \|= ATOM_S3_DFP1_ACTIVE;
		1185	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP1;
		1186	} else {
		1187	DRM_DEBUG("DFP1 disconnected\n");
		1188	bios_0_scratch &= ~ATOM_S0_DFP1;
		1189	bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
		1190	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
		1191	}
		1192	}
		1193	if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
		1194	(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
		1195	if (connected) {
		1196	DRM_DEBUG("DFP2 connected\n");
		1197	bios_0_scratch \|= ATOM_S0_DFP2;
		1198	bios_3_scratch \|= ATOM_S3_DFP2_ACTIVE;
		1199	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP2;
		1200	} else {
		1201	DRM_DEBUG("DFP2 disconnected\n");
		1202	bios_0_scratch &= ~ATOM_S0_DFP2;
		1203	bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
		1204	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
		1205	}
		1206	}
		1207	if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
		1208	(radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
		1209	if (connected) {
		1210	DRM_DEBUG("DFP3 connected\n");
		1211	bios_0_scratch \|= ATOM_S0_DFP3;
		1212	bios_3_scratch \|= ATOM_S3_DFP3_ACTIVE;
		1213	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP3;
		1214	} else {
		1215	DRM_DEBUG("DFP3 disconnected\n");
		1216	bios_0_scratch &= ~ATOM_S0_DFP3;
		1217	bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
		1218	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
		1219	}
		1220	}
		1221	if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
		1222	(radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
		1223	if (connected) {
		1224	DRM_DEBUG("DFP4 connected\n");
		1225	bios_0_scratch \|= ATOM_S0_DFP4;
		1226	bios_3_scratch \|= ATOM_S3_DFP4_ACTIVE;
		1227	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP4;
		1228	} else {
		1229	DRM_DEBUG("DFP4 disconnected\n");
		1230	bios_0_scratch &= ~ATOM_S0_DFP4;
		1231	bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
		1232	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
		1233	}
		1234	}
		1235	if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
		1236	(radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
		1237	if (connected) {
		1238	DRM_DEBUG("DFP5 connected\n");
		1239	bios_0_scratch \|= ATOM_S0_DFP5;
		1240	bios_3_scratch \|= ATOM_S3_DFP5_ACTIVE;
		1241	bios_6_scratch \|= ATOM_S6_ACC_REQ_DFP5;
		1242	} else {
		1243	DRM_DEBUG("DFP5 disconnected\n");
		1244	bios_0_scratch &= ~ATOM_S0_DFP5;
		1245	bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
		1246	bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
		1247	}
		1248	}
		1249
		1250	if (rdev->family >= CHIP_R600) {
		1251	WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
		1252	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1253	WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
		1254	} else {
		1255	WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
		1256	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1257	WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
		1258	}
		1259	}
		1260
		1261	void
		1262	radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
		1263	{
		1264	struct drm_device *dev = encoder->dev;
		1265	struct radeon_device *rdev = dev->dev_private;
		1266	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1267	uint32_t bios_3_scratch;
		1268
		1269	if (rdev->family >= CHIP_R600)
		1270	bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
		1271	else
		1272	bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
		1273
		1274	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1275	bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
		1276	bios_3_scratch \|= (crtc << 18);
		1277	}
		1278	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1279	bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
		1280	bios_3_scratch \|= (crtc << 24);
		1281	}
		1282	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1283	bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
		1284	bios_3_scratch \|= (crtc << 16);
		1285	}
		1286	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1287	bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
		1288	bios_3_scratch \|= (crtc << 20);
		1289	}
		1290	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1291	bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
		1292	bios_3_scratch \|= (crtc << 17);
		1293	}
		1294	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1295	bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
		1296	bios_3_scratch \|= (crtc << 19);
		1297	}
		1298	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1299	bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
		1300	bios_3_scratch \|= (crtc << 23);
		1301	}
		1302	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1303	bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
		1304	bios_3_scratch \|= (crtc << 25);
		1305	}
		1306
		1307	if (rdev->family >= CHIP_R600)
		1308	WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
		1309	else
		1310	WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
		1311	}
		1312
		1313	void
		1314	radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
		1315	{
		1316	struct drm_device *dev = encoder->dev;
		1317	struct radeon_device *rdev = dev->dev_private;
		1318	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
		1319	uint32_t bios_2_scratch;
		1320
		1321	if (rdev->family >= CHIP_R600)
		1322	bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
		1323	else
		1324	bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
		1325
		1326	if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
		1327	if (on)
		1328	bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
		1329	else
		1330	bios_2_scratch \|= ATOM_S2_TV1_DPMS_STATE;
		1331	}
		1332	if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
		1333	if (on)
		1334	bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
		1335	else
		1336	bios_2_scratch \|= ATOM_S2_CV_DPMS_STATE;
		1337	}
		1338	if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
		1339	if (on)
		1340	bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
		1341	else
		1342	bios_2_scratch \|= ATOM_S2_CRT1_DPMS_STATE;
		1343	}
		1344	if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
		1345	if (on)
		1346	bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
		1347	else
		1348	bios_2_scratch \|= ATOM_S2_CRT2_DPMS_STATE;
		1349	}
		1350	if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
		1351	if (on)
		1352	bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
		1353	else
		1354	bios_2_scratch \|= ATOM_S2_LCD1_DPMS_STATE;
		1355	}
		1356	if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
		1357	if (on)
		1358	bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
		1359	else
		1360	bios_2_scratch \|= ATOM_S2_DFP1_DPMS_STATE;
		1361	}
		1362	if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
		1363	if (on)
		1364	bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
		1365	else
		1366	bios_2_scratch \|= ATOM_S2_DFP2_DPMS_STATE;
		1367	}
		1368	if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
		1369	if (on)
		1370	bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
		1371	else
		1372	bios_2_scratch \|= ATOM_S2_DFP3_DPMS_STATE;
		1373	}
		1374	if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
		1375	if (on)
		1376	bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
		1377	else
		1378	bios_2_scratch \|= ATOM_S2_DFP4_DPMS_STATE;
		1379	}
		1380	if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
		1381	if (on)
		1382	bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
		1383	else
		1384	bios_2_scratch \|= ATOM_S2_DFP5_DPMS_STATE;
		1385	}
		1386
		1387	if (rdev->family >= CHIP_R600)
		1388	WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
		1389	else
		1390	WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
		1391	}

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_atombios.c – Rev 1221