WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
6104	serge	33	#include
1963	serge	34	#include "radeon_reg.h"
		35	#include "radeon.h"
		36	#include "radeon_asic.h"
		37	#include "atom.h"
		38
		39	/*
		40	* Registers accessors functions.
		41	*/
2997	Serge	42	/**
		43	* radeon_invalid_rreg - dummy reg read function
		44	*
		45	* @rdev: radeon device pointer
		46	* @reg: offset of register
		47	*
		48	* Dummy register read function. Used for register blocks
		49	* that certain asics don't have (all asics).
		50	* Returns the value in the register.
		51	*/
1963	serge	52	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		53	{
		54	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		55	BUG_ON(1);
		56	return 0;
		57	}
		58
2997	Serge	59	/**
		60	* radeon_invalid_wreg - dummy reg write function
		61	*
		62	* @rdev: radeon device pointer
		63	* @reg: offset of register
		64	* @v: value to write to the register
		65	*
		66	* Dummy register read function. Used for register blocks
		67	* that certain asics don't have (all asics).
		68	*/
1963	serge	69	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		70	{
		71	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		72	reg, v);
		73	BUG_ON(1);
		74	}
		75
2997	Serge	76	/**
		77	* radeon_register_accessor_init - sets up the register accessor callbacks
		78	*
		79	* @rdev: radeon device pointer
		80	*
		81	* Sets up the register accessor callbacks for various register
		82	* apertures. Not all asics have all apertures (all asics).
		83	*/
1963	serge	84	static void radeon_register_accessor_init(struct radeon_device *rdev)
		85	{
		86	rdev->mc_rreg = &radeon_invalid_rreg;
		87	rdev->mc_wreg = &radeon_invalid_wreg;
		88	rdev->pll_rreg = &radeon_invalid_rreg;
		89	rdev->pll_wreg = &radeon_invalid_wreg;
		90	rdev->pciep_rreg = &radeon_invalid_rreg;
		91	rdev->pciep_wreg = &radeon_invalid_wreg;
		92
		93	/* Don't change order as we are overridding accessor. */
		94	if (rdev->family < CHIP_RV515) {
		95	rdev->pcie_reg_mask = 0xff;
		96	} else {
		97	rdev->pcie_reg_mask = 0x7ff;
		98	}
		99	/* FIXME: not sure here */
		100	if (rdev->family <= CHIP_R580) {
		101	rdev->pll_rreg = &r100_pll_rreg;
		102	rdev->pll_wreg = &r100_pll_wreg;
		103	}
		104	if (rdev->family >= CHIP_R420) {
		105	rdev->mc_rreg = &r420_mc_rreg;
		106	rdev->mc_wreg = &r420_mc_wreg;
		107	}
		108	if (rdev->family >= CHIP_RV515) {
		109	rdev->mc_rreg = &rv515_mc_rreg;
		110	rdev->mc_wreg = &rv515_mc_wreg;
		111	}
		112	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		113	rdev->mc_rreg = &rs400_mc_rreg;
		114	rdev->mc_wreg = &rs400_mc_wreg;
		115	}
		116	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		117	rdev->mc_rreg = &rs690_mc_rreg;
		118	rdev->mc_wreg = &rs690_mc_wreg;
		119	}
		120	if (rdev->family == CHIP_RS600) {
		121	rdev->mc_rreg = &rs600_mc_rreg;
		122	rdev->mc_wreg = &rs600_mc_wreg;
		123	}
3764	Serge	124	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
		125	rdev->mc_rreg = &rs780_mc_rreg;
		126	rdev->mc_wreg = &rs780_mc_wreg;
		127	}
5078	serge	128
		129	if (rdev->family >= CHIP_BONAIRE) {
		130	rdev->pciep_rreg = &cik_pciep_rreg;
		131	rdev->pciep_wreg = &cik_pciep_wreg;
		132	} else if (rdev->family >= CHIP_R600) {
1963	serge	133	rdev->pciep_rreg = &r600_pciep_rreg;
		134	rdev->pciep_wreg = &r600_pciep_wreg;
		135	}
		136	}
		137
6104	serge	138	static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
		139	u32 reg, u32 *val)
		140	{
		141	return -EINVAL;
		142	}
1963	serge	143
		144	/* helper to disable agp */
2997	Serge	145	/**
		146	* radeon_agp_disable - AGP disable helper function
		147	*
		148	* @rdev: radeon device pointer
		149	*
		150	* Removes AGP flags and changes the gart callbacks on AGP
		151	* cards when using the internal gart rather than AGP (all asics).
		152	*/
1963	serge	153	void radeon_agp_disable(struct radeon_device *rdev)
		154	{
		155	rdev->flags &= ~RADEON_IS_AGP;
		156	if (rdev->family >= CHIP_R600) {
		157	DRM_INFO("Forcing AGP to PCIE mode\n");
		158	rdev->flags \|= RADEON_IS_PCIE;
		159	} else if (rdev->family >= CHIP_RV515 \|\|
		160	rdev->family == CHIP_RV380 \|\|
		161	rdev->family == CHIP_RV410 \|\|
		162	rdev->family == CHIP_R423) {
		163	DRM_INFO("Forcing AGP to PCIE mode\n");
		164	rdev->flags \|= RADEON_IS_PCIE;
2997	Serge	165	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
6104	serge	166	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
2997	Serge	167	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1963	serge	168	} else {
		169	DRM_INFO("Forcing AGP to PCI mode\n");
		170	rdev->flags \|= RADEON_IS_PCI;
2997	Serge	171	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
6104	serge	172	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
2997	Serge	173	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1963	serge	174	}
		175	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		176	}
		177
		178	/*
		179	* ASIC
		180	*/
5078	serge	181
6938	serge	182	static const struct radeon_asic_ring r100_gfx_ring = {
5078	serge	183	.ib_execute = &r100_ring_ib_execute,
		184	.emit_fence = &r100_fence_ring_emit,
		185	.emit_semaphore = &r100_semaphore_ring_emit,
		186	.cs_parse = &r100_cs_parse,
		187	.ring_start = &r100_ring_start,
		188	.ring_test = &r100_ring_test,
		189	.ib_test = &r100_ib_test,
		190	.is_lockup = &r100_gpu_is_lockup,
		191	.get_rptr = &r100_gfx_get_rptr,
		192	.get_wptr = &r100_gfx_get_wptr,
		193	.set_wptr = &r100_gfx_set_wptr,
		194	};
		195
1963	serge	196	static struct radeon_asic r100_asic = {
		197	.init = &r100_init,
6104	serge	198	.fini = &r100_fini,
1963	serge	199	// .suspend = &r100_suspend,
		200	// .resume = &r100_resume,
		201	// .vga_set_state = &r100_vga_set_state,
		202	.asic_reset = &r100_asic_reset,
5078	serge	203	.mmio_hdp_flush = NULL,
2997	Serge	204	.gui_idle = &r100_gui_idle,
		205	.mc_wait_for_idle = &r100_mc_wait_for_idle,
6104	serge	206	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	207	.gart = {
		208	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	209	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	210	.set_page = &r100_pci_gart_set_page,
		211	},
		212	.ring = {
5078	serge	213	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	214	},
		215	.irq = {
		216	.set = &r100_irq_set,
		217	.process = &r100_irq_process,
		218	},
		219	.display = {
		220	.bandwidth_update = &r100_bandwidth_update,
		221	.get_vblank_counter = &r100_get_vblank_counter,
		222	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	223	.set_backlight_level = &radeon_legacy_set_backlight_level,
		224	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	225	},
		226	.copy = {
		227	.blit = &r100_copy_blit,
		228	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		229	.dma = NULL,
		230	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
6104	serge	231	.copy = &r100_copy_blit,
2997	Serge	232	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		233	},
		234	.surface = {
		235	.set_reg = r100_set_surface_reg,
		236	.clear_reg = r100_clear_surface_reg,
		237	},
		238	.hpd = {
5078	serge	239	.init = &r100_hpd_init,
		240	.fini = &r100_hpd_fini,
		241	.sense = &r100_hpd_sense,
		242	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	243	},
		244	.pm = {
5078	serge	245	.misc = &r100_pm_misc,
		246	.prepare = &r100_pm_prepare,
		247	.finish = &r100_pm_finish,
		248	.init_profile = &r100_pm_init_profile,
		249	.get_dynpm_state = &r100_pm_get_dynpm_state,
		250	.get_engine_clock = &radeon_legacy_get_engine_clock,
		251	.set_engine_clock = &radeon_legacy_set_engine_clock,
		252	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	253	.set_memory_clock = NULL,
		254	.get_pcie_lanes = NULL,
		255	.set_pcie_lanes = NULL,
5078	serge	256	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	257	},
		258	.pflip = {
6321	serge	259
2997	Serge	260	},
1963	serge	261	};
		262
		263	static struct radeon_asic r200_asic = {
		264	.init = &r100_init,
6104	serge	265	.fini = &r100_fini,
1963	serge	266	// .suspend = &r100_suspend,
		267	// .resume = &r100_resume,
		268	// .vga_set_state = &r100_vga_set_state,
		269	.asic_reset = &r100_asic_reset,
5078	serge	270	.mmio_hdp_flush = NULL,
2007	serge	271	.gui_idle = &r100_gui_idle,
2997	Serge	272	.mc_wait_for_idle = &r100_mc_wait_for_idle,
6104	serge	273	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	274	.gart = {
		275	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	276	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	277	.set_page = &r100_pci_gart_set_page,
		278	},
		279	.ring = {
5078	serge	280	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	281	},
		282	.irq = {
		283	.set = &r100_irq_set,
		284	.process = &r100_irq_process,
		285	},
		286	.display = {
		287	.bandwidth_update = &r100_bandwidth_update,
		288	.get_vblank_counter = &r100_get_vblank_counter,
		289	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	290	.set_backlight_level = &radeon_legacy_set_backlight_level,
		291	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	292	},
		293	.copy = {
		294	.blit = &r100_copy_blit,
		295	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		296	.dma = &r200_copy_dma,
		297	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		298	.copy = &r100_copy_blit,
		299	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		300	},
		301	.surface = {
		302	.set_reg = r100_set_surface_reg,
		303	.clear_reg = r100_clear_surface_reg,
		304	},
		305	.hpd = {
5078	serge	306	.init = &r100_hpd_init,
		307	.fini = &r100_hpd_fini,
		308	.sense = &r100_hpd_sense,
		309	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	310	},
		311	.pm = {
5078	serge	312	.misc = &r100_pm_misc,
		313	.prepare = &r100_pm_prepare,
		314	.finish = &r100_pm_finish,
		315	.init_profile = &r100_pm_init_profile,
		316	.get_dynpm_state = &r100_pm_get_dynpm_state,
		317	.get_engine_clock = &radeon_legacy_get_engine_clock,
		318	.set_engine_clock = &radeon_legacy_set_engine_clock,
		319	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	320	.set_memory_clock = NULL,
		321	.get_pcie_lanes = NULL,
		322	.set_pcie_lanes = NULL,
5078	serge	323	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	324	},
		325	.pflip = {
		326	// .pre_page_flip = &r100_pre_page_flip,
		327	// .page_flip = &r100_page_flip,
		328	},
1963	serge	329	};
		330
6938	serge	331	static const struct radeon_asic_ring r300_gfx_ring = {
5078	serge	332	.ib_execute = &r100_ring_ib_execute,
		333	.emit_fence = &r300_fence_ring_emit,
		334	.emit_semaphore = &r100_semaphore_ring_emit,
		335	.cs_parse = &r300_cs_parse,
		336	.ring_start = &r300_ring_start,
		337	.ring_test = &r100_ring_test,
		338	.ib_test = &r100_ib_test,
		339	.is_lockup = &r100_gpu_is_lockup,
		340	.get_rptr = &r100_gfx_get_rptr,
		341	.get_wptr = &r100_gfx_get_wptr,
		342	.set_wptr = &r100_gfx_set_wptr,
		343	};
		344
6938	serge	345	static const struct radeon_asic_ring rv515_gfx_ring = {
6104	serge	346	.ib_execute = &r100_ring_ib_execute,
		347	.emit_fence = &r300_fence_ring_emit,
		348	.emit_semaphore = &r100_semaphore_ring_emit,
		349	.cs_parse = &r300_cs_parse,
		350	.ring_start = &rv515_ring_start,
		351	.ring_test = &r100_ring_test,
		352	.ib_test = &r100_ib_test,
		353	.is_lockup = &r100_gpu_is_lockup,
		354	.get_rptr = &r100_gfx_get_rptr,
		355	.get_wptr = &r100_gfx_get_wptr,
		356	.set_wptr = &r100_gfx_set_wptr,
		357	};
		358
1963	serge	359	static struct radeon_asic r300_asic = {
		360	.init = &r300_init,
6104	serge	361	.fini = &r300_fini,
1963	serge	362	// .suspend = &r300_suspend,
		363	// .resume = &r300_resume,
		364	// .vga_set_state = &r100_vga_set_state,
		365	.asic_reset = &r300_asic_reset,
5078	serge	366	.mmio_hdp_flush = NULL,
2007	serge	367	.gui_idle = &r100_gui_idle,
2997	Serge	368	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	369	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	370	.gart = {
		371	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	372	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	373	.set_page = &r100_pci_gart_set_page,
		374	},
		375	.ring = {
5078	serge	376	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	377	},
		378	.irq = {
		379	.set = &r100_irq_set,
		380	.process = &r100_irq_process,
		381	},
		382	.display = {
		383	.bandwidth_update = &r100_bandwidth_update,
		384	.get_vblank_counter = &r100_get_vblank_counter,
		385	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	386	.set_backlight_level = &radeon_legacy_set_backlight_level,
		387	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	388	},
		389	.copy = {
		390	.blit = &r100_copy_blit,
		391	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		392	.dma = &r200_copy_dma,
		393	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		394	.copy = &r100_copy_blit,
		395	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		396	},
		397	.surface = {
		398	.set_reg = r100_set_surface_reg,
		399	.clear_reg = r100_clear_surface_reg,
		400	},
		401	.hpd = {
5078	serge	402	.init = &r100_hpd_init,
		403	.fini = &r100_hpd_fini,
		404	.sense = &r100_hpd_sense,
		405	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	406	},
		407	.pm = {
5078	serge	408	.misc = &r100_pm_misc,
		409	.prepare = &r100_pm_prepare,
		410	.finish = &r100_pm_finish,
		411	.init_profile = &r100_pm_init_profile,
		412	.get_dynpm_state = &r100_pm_get_dynpm_state,
		413	.get_engine_clock = &radeon_legacy_get_engine_clock,
		414	.set_engine_clock = &radeon_legacy_set_engine_clock,
		415	.get_memory_clock = &radeon_legacy_get_memory_clock,
		416	.set_memory_clock = NULL,
		417	.get_pcie_lanes = &rv370_get_pcie_lanes,
		418	.set_pcie_lanes = &rv370_set_pcie_lanes,
		419	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	420	},
		421	.pflip = {
		422	// .pre_page_flip = &r100_pre_page_flip,
		423	// .page_flip = &r100_page_flip,
		424	},
1963	serge	425	};
		426
		427	static struct radeon_asic r300_asic_pcie = {
		428	.init = &r300_init,
6104	serge	429	.fini = &r300_fini,
1963	serge	430	// .suspend = &r300_suspend,
		431	// .resume = &r300_resume,
		432	// .vga_set_state = &r100_vga_set_state,
		433	.asic_reset = &r300_asic_reset,
5078	serge	434	.mmio_hdp_flush = NULL,
2007	serge	435	.gui_idle = &r100_gui_idle,
2997	Serge	436	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	437	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	438	.gart = {
		439	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	440	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	441	.set_page = &rv370_pcie_gart_set_page,
		442	},
		443	.ring = {
5078	serge	444	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	445	},
		446	.irq = {
		447	.set = &r100_irq_set,
		448	.process = &r100_irq_process,
		449	},
		450	.display = {
		451	.bandwidth_update = &r100_bandwidth_update,
		452	.get_vblank_counter = &r100_get_vblank_counter,
		453	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	454	.set_backlight_level = &radeon_legacy_set_backlight_level,
		455	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	456	},
		457	.copy = {
		458	.blit = &r100_copy_blit,
		459	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		460	.dma = &r200_copy_dma,
		461	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		462	.copy = &r100_copy_blit,
		463	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		464	},
		465	.surface = {
		466	.set_reg = r100_set_surface_reg,
		467	.clear_reg = r100_clear_surface_reg,
		468	},
		469	.hpd = {
		470	.init = &r100_hpd_init,
		471	.fini = &r100_hpd_fini,
		472	.sense = &r100_hpd_sense,
		473	.set_polarity = &r100_hpd_set_polarity,
		474	},
		475	.pm = {
5078	serge	476	.misc = &r100_pm_misc,
		477	.prepare = &r100_pm_prepare,
		478	.finish = &r100_pm_finish,
		479	.init_profile = &r100_pm_init_profile,
		480	.get_dynpm_state = &r100_pm_get_dynpm_state,
		481	.get_engine_clock = &radeon_legacy_get_engine_clock,
		482	.set_engine_clock = &radeon_legacy_set_engine_clock,
		483	.get_memory_clock = &radeon_legacy_get_memory_clock,
		484	.set_memory_clock = NULL,
		485	.get_pcie_lanes = &rv370_get_pcie_lanes,
		486	.set_pcie_lanes = &rv370_set_pcie_lanes,
		487	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	488	},
		489	.pflip = {
		490	// .pre_page_flip = &r100_pre_page_flip,
		491	// .page_flip = &r100_page_flip,
		492	},
1963	serge	493	};
		494
		495	static struct radeon_asic r420_asic = {
		496	.init = &r420_init,
6104	serge	497	.fini = &r420_fini,
1963	serge	498	// .suspend = &r420_suspend,
		499	// .resume = &r420_resume,
		500	// .vga_set_state = &r100_vga_set_state,
		501	.asic_reset = &r300_asic_reset,
5078	serge	502	.mmio_hdp_flush = NULL,
2160	serge	503	.gui_idle = &r100_gui_idle,
2997	Serge	504	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	505	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	506	.gart = {
		507	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	508	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	509	.set_page = &rv370_pcie_gart_set_page,
		510	},
		511	.ring = {
5078	serge	512	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	513	},
		514	.irq = {
		515	.set = &r100_irq_set,
		516	.process = &r100_irq_process,
		517	},
		518	.display = {
		519	.bandwidth_update = &r100_bandwidth_update,
		520	.get_vblank_counter = &r100_get_vblank_counter,
		521	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	522	.set_backlight_level = &atombios_set_backlight_level,
		523	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	524	},
		525	.copy = {
		526	.blit = &r100_copy_blit,
		527	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		528	.dma = &r200_copy_dma,
		529	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		530	.copy = &r100_copy_blit,
		531	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		532	},
		533	.surface = {
		534	.set_reg = r100_set_surface_reg,
		535	.clear_reg = r100_clear_surface_reg,
		536	},
		537	.hpd = {
5078	serge	538	.init = &r100_hpd_init,
		539	.fini = &r100_hpd_fini,
		540	.sense = &r100_hpd_sense,
		541	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	542	},
		543	.pm = {
5078	serge	544	.misc = &r100_pm_misc,
		545	.prepare = &r100_pm_prepare,
		546	.finish = &r100_pm_finish,
		547	.init_profile = &r420_pm_init_profile,
		548	.get_dynpm_state = &r100_pm_get_dynpm_state,
		549	.get_engine_clock = &radeon_atom_get_engine_clock,
		550	.set_engine_clock = &radeon_atom_set_engine_clock,
		551	.get_memory_clock = &radeon_atom_get_memory_clock,
		552	.set_memory_clock = &radeon_atom_set_memory_clock,
		553	.get_pcie_lanes = &rv370_get_pcie_lanes,
		554	.set_pcie_lanes = &rv370_set_pcie_lanes,
		555	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	556	},
		557	.pflip = {
		558	// .pre_page_flip = &r100_pre_page_flip,
		559	// .page_flip = &r100_page_flip,
		560	},
1963	serge	561	};
		562
		563	static struct radeon_asic rs400_asic = {
		564	.init = &rs400_init,
6104	serge	565	.fini = &rs400_fini,
1963	serge	566	// .suspend = &rs400_suspend,
		567	// .resume = &rs400_resume,
		568	// .vga_set_state = &r100_vga_set_state,
		569	.asic_reset = &r300_asic_reset,
5078	serge	570	.mmio_hdp_flush = NULL,
2160	serge	571	.gui_idle = &r100_gui_idle,
2997	Serge	572	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
6104	serge	573	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	574	.gart = {
		575	.tlb_flush = &rs400_gart_tlb_flush,
6104	serge	576	.get_page_entry = &rs400_gart_get_page_entry,
2997	Serge	577	.set_page = &rs400_gart_set_page,
		578	},
		579	.ring = {
5078	serge	580	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	581	},
		582	.irq = {
		583	.set = &r100_irq_set,
		584	.process = &r100_irq_process,
		585	},
		586	.display = {
		587	.bandwidth_update = &r100_bandwidth_update,
		588	.get_vblank_counter = &r100_get_vblank_counter,
		589	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	590	.set_backlight_level = &radeon_legacy_set_backlight_level,
		591	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	592	},
		593	.copy = {
		594	.blit = &r100_copy_blit,
		595	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		596	.dma = &r200_copy_dma,
		597	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		598	.copy = &r100_copy_blit,
		599	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		600	},
		601	.surface = {
		602	.set_reg = r100_set_surface_reg,
		603	.clear_reg = r100_clear_surface_reg,
		604	},
		605	.hpd = {
5078	serge	606	.init = &r100_hpd_init,
		607	.fini = &r100_hpd_fini,
		608	.sense = &r100_hpd_sense,
		609	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	610	},
		611	.pm = {
5078	serge	612	.misc = &r100_pm_misc,
		613	.prepare = &r100_pm_prepare,
		614	.finish = &r100_pm_finish,
		615	.init_profile = &r100_pm_init_profile,
		616	.get_dynpm_state = &r100_pm_get_dynpm_state,
		617	.get_engine_clock = &radeon_legacy_get_engine_clock,
		618	.set_engine_clock = &radeon_legacy_set_engine_clock,
		619	.get_memory_clock = &radeon_legacy_get_memory_clock,
		620	.set_memory_clock = NULL,
		621	.get_pcie_lanes = NULL,
		622	.set_pcie_lanes = NULL,
		623	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	624	},
		625	.pflip = {
		626	// .pre_page_flip = &r100_pre_page_flip,
		627	// .page_flip = &r100_page_flip,
		628	},
1963	serge	629	};
		630
		631	static struct radeon_asic rs600_asic = {
		632	.init = &rs600_init,
6104	serge	633	.fini = &rs600_fini,
1963	serge	634	// .suspend = &rs600_suspend,
		635	// .resume = &rs600_resume,
		636	// .vga_set_state = &r100_vga_set_state,
		637	.asic_reset = &rs600_asic_reset,
5078	serge	638	.mmio_hdp_flush = NULL,
2160	serge	639	.gui_idle = &r100_gui_idle,
2997	Serge	640	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
6104	serge	641	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	642	.gart = {
		643	.tlb_flush = &rs600_gart_tlb_flush,
6104	serge	644	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	645	.set_page = &rs600_gart_set_page,
		646	},
		647	.ring = {
5078	serge	648	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	649	},
		650	.irq = {
		651	.set = &rs600_irq_set,
		652	.process = &rs600_irq_process,
		653	},
		654	.display = {
		655	.bandwidth_update = &rs600_bandwidth_update,
		656	.get_vblank_counter = &rs600_get_vblank_counter,
		657	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	658	.set_backlight_level = &atombios_set_backlight_level,
		659	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	660	},
		661	.copy = {
		662	.blit = &r100_copy_blit,
		663	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		664	.dma = &r200_copy_dma,
		665	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		666	.copy = &r100_copy_blit,
		667	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		668	},
		669	.surface = {
		670	.set_reg = r100_set_surface_reg,
		671	.clear_reg = r100_clear_surface_reg,
		672	},
		673	.hpd = {
5078	serge	674	.init = &rs600_hpd_init,
		675	.fini = &rs600_hpd_fini,
		676	.sense = &rs600_hpd_sense,
		677	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	678	},
		679	.pm = {
5078	serge	680	.misc = &rs600_pm_misc,
		681	.prepare = &rs600_pm_prepare,
		682	.finish = &rs600_pm_finish,
		683	.init_profile = &r420_pm_init_profile,
		684	.get_dynpm_state = &r100_pm_get_dynpm_state,
		685	.get_engine_clock = &radeon_atom_get_engine_clock,
		686	.set_engine_clock = &radeon_atom_set_engine_clock,
		687	.get_memory_clock = &radeon_atom_get_memory_clock,
		688	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	689	.get_pcie_lanes = NULL,
		690	.set_pcie_lanes = NULL,
5078	serge	691	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	692	},
		693	.pflip = {
		694	// .pre_page_flip = &rs600_pre_page_flip,
		695	// .page_flip = &rs600_page_flip,
		696	},
1963	serge	697	};
		698
		699	static struct radeon_asic rs690_asic = {
		700	.init = &rs690_init,
6104	serge	701	.fini = &rs690_fini,
1963	serge	702	// .suspend = &rs690_suspend,
		703	// .resume = &rs690_resume,
		704	// .vga_set_state = &r100_vga_set_state,
		705	.asic_reset = &rs600_asic_reset,
5078	serge	706	.mmio_hdp_flush = NULL,
2160	serge	707	.gui_idle = &r100_gui_idle,
2997	Serge	708	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
6104	serge	709	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	710	.gart = {
		711	.tlb_flush = &rs400_gart_tlb_flush,
6104	serge	712	.get_page_entry = &rs400_gart_get_page_entry,
2997	Serge	713	.set_page = &rs400_gart_set_page,
		714	},
		715	.ring = {
5078	serge	716	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	717	},
		718	.irq = {
		719	.set = &rs600_irq_set,
		720	.process = &rs600_irq_process,
		721	},
		722	.display = {
		723	.get_vblank_counter = &rs600_get_vblank_counter,
		724	.bandwidth_update = &rs690_bandwidth_update,
		725	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	726	.set_backlight_level = &atombios_set_backlight_level,
		727	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	728	},
		729	.copy = {
		730	.blit = &r100_copy_blit,
		731	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		732	.dma = &r200_copy_dma,
		733	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		734	.copy = &r200_copy_dma,
		735	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		736	},
		737	.surface = {
		738	.set_reg = r100_set_surface_reg,
		739	.clear_reg = r100_clear_surface_reg,
		740	},
		741	.hpd = {
5078	serge	742	.init = &rs600_hpd_init,
		743	.fini = &rs600_hpd_fini,
2997	Serge	744	.sense = &rs600_hpd_sense,
		745	.set_polarity = &rs600_hpd_set_polarity,
		746	},
		747	.pm = {
5078	serge	748	.misc = &rs600_pm_misc,
		749	.prepare = &rs600_pm_prepare,
		750	.finish = &rs600_pm_finish,
		751	.init_profile = &r420_pm_init_profile,
		752	.get_dynpm_state = &r100_pm_get_dynpm_state,
		753	.get_engine_clock = &radeon_atom_get_engine_clock,
		754	.set_engine_clock = &radeon_atom_set_engine_clock,
		755	.get_memory_clock = &radeon_atom_get_memory_clock,
		756	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	757	.get_pcie_lanes = NULL,
		758	.set_pcie_lanes = NULL,
5078	serge	759	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	760	},
		761	.pflip = {
		762	// .pre_page_flip = &rs600_pre_page_flip,
		763	// .page_flip = &rs600_page_flip,
		764	},
1963	serge	765	};
		766
		767	static struct radeon_asic rv515_asic = {
		768	.init = &rv515_init,
6104	serge	769	.fini = &rv515_fini,
1963	serge	770	// .suspend = &rv515_suspend,
		771	// .resume = &rv515_resume,
		772	// .vga_set_state = &r100_vga_set_state,
		773	.asic_reset = &rs600_asic_reset,
5078	serge	774	.mmio_hdp_flush = NULL,
2160	serge	775	.gui_idle = &r100_gui_idle,
2997	Serge	776	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
6104	serge	777	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	778	.gart = {
		779	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	780	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	781	.set_page = &rv370_pcie_gart_set_page,
		782	},
		783	.ring = {
6104	serge	784	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
2997	Serge	785	},
		786	.irq = {
		787	.set = &rs600_irq_set,
		788	.process = &rs600_irq_process,
		789	},
		790	.display = {
		791	.get_vblank_counter = &rs600_get_vblank_counter,
		792	.bandwidth_update = &rv515_bandwidth_update,
		793	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	794	.set_backlight_level = &atombios_set_backlight_level,
		795	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	796	},
		797	.copy = {
		798	.blit = &r100_copy_blit,
		799	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		800	.dma = &r200_copy_dma,
		801	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		802	.copy = &r100_copy_blit,
		803	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		804	},
		805	.surface = {
		806	.set_reg = r100_set_surface_reg,
		807	.clear_reg = r100_clear_surface_reg,
		808	},
		809	.hpd = {
5078	serge	810	.init = &rs600_hpd_init,
		811	.fini = &rs600_hpd_fini,
		812	.sense = &rs600_hpd_sense,
		813	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	814	},
		815	.pm = {
5078	serge	816	.misc = &rs600_pm_misc,
		817	.prepare = &rs600_pm_prepare,
		818	.finish = &rs600_pm_finish,
		819	.init_profile = &r420_pm_init_profile,
		820	.get_dynpm_state = &r100_pm_get_dynpm_state,
		821	.get_engine_clock = &radeon_atom_get_engine_clock,
		822	.set_engine_clock = &radeon_atom_set_engine_clock,
		823	.get_memory_clock = &radeon_atom_get_memory_clock,
		824	.set_memory_clock = &radeon_atom_set_memory_clock,
		825	.get_pcie_lanes = &rv370_get_pcie_lanes,
		826	.set_pcie_lanes = &rv370_set_pcie_lanes,
		827	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	828	},
		829	.pflip = {
		830	// .pre_page_flip = &rs600_pre_page_flip,
		831	// .page_flip = &rs600_page_flip,
		832	},
1963	serge	833	};
		834
		835	static struct radeon_asic r520_asic = {
		836	.init = &r520_init,
6104	serge	837	.fini = &rv515_fini,
1963	serge	838	// .suspend = &rv515_suspend,
		839	// .resume = &r520_resume,
		840	// .vga_set_state = &r100_vga_set_state,
		841	.asic_reset = &rs600_asic_reset,
5078	serge	842	.mmio_hdp_flush = NULL,
2160	serge	843	.gui_idle = &r100_gui_idle,
2997	Serge	844	.mc_wait_for_idle = &r520_mc_wait_for_idle,
6104	serge	845	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	846	.gart = {
		847	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	848	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	849	.set_page = &rv370_pcie_gart_set_page,
		850	},
		851	.ring = {
6104	serge	852	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
2997	Serge	853	},
		854	.irq = {
		855	.set = &rs600_irq_set,
		856	.process = &rs600_irq_process,
		857	},
		858	.display = {
		859	.bandwidth_update = &rv515_bandwidth_update,
		860	.get_vblank_counter = &rs600_get_vblank_counter,
		861	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	862	.set_backlight_level = &atombios_set_backlight_level,
		863	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	864	},
		865	.copy = {
		866	.blit = &r100_copy_blit,
		867	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		868	.dma = &r200_copy_dma,
		869	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		870	.copy = &r100_copy_blit,
		871	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		872	},
		873	.surface = {
		874	.set_reg = r100_set_surface_reg,
		875	.clear_reg = r100_clear_surface_reg,
		876	},
		877	.hpd = {
5078	serge	878	.init = &rs600_hpd_init,
		879	.fini = &rs600_hpd_fini,
		880	.sense = &rs600_hpd_sense,
		881	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	882	},
		883	.pm = {
5078	serge	884	.misc = &rs600_pm_misc,
		885	.prepare = &rs600_pm_prepare,
		886	.finish = &rs600_pm_finish,
		887	.init_profile = &r420_pm_init_profile,
		888	.get_dynpm_state = &r100_pm_get_dynpm_state,
		889	.get_engine_clock = &radeon_atom_get_engine_clock,
		890	.set_engine_clock = &radeon_atom_set_engine_clock,
		891	.get_memory_clock = &radeon_atom_get_memory_clock,
		892	.set_memory_clock = &radeon_atom_set_memory_clock,
		893	.get_pcie_lanes = &rv370_get_pcie_lanes,
		894	.set_pcie_lanes = &rv370_set_pcie_lanes,
		895	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	896	},
		897	.pflip = {
		898	// .pre_page_flip = &rs600_pre_page_flip,
		899	// .page_flip = &rs600_page_flip,
		900	},
1963	serge	901	};
		902
6938	serge	903	static const struct radeon_asic_ring r600_gfx_ring = {
5078	serge	904	.ib_execute = &r600_ring_ib_execute,
		905	.emit_fence = &r600_fence_ring_emit,
		906	.emit_semaphore = &r600_semaphore_ring_emit,
		907	.cs_parse = &r600_cs_parse,
		908	.ring_test = &r600_ring_test,
		909	.ib_test = &r600_ib_test,
		910	.is_lockup = &r600_gfx_is_lockup,
		911	.get_rptr = &r600_gfx_get_rptr,
		912	.get_wptr = &r600_gfx_get_wptr,
		913	.set_wptr = &r600_gfx_set_wptr,
		914	};
		915
6938	serge	916	static const struct radeon_asic_ring r600_dma_ring = {
5078	serge	917	.ib_execute = &r600_dma_ring_ib_execute,
		918	.emit_fence = &r600_dma_fence_ring_emit,
		919	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		920	.cs_parse = &r600_dma_cs_parse,
		921	.ring_test = &r600_dma_ring_test,
		922	.ib_test = &r600_dma_ib_test,
		923	.is_lockup = &r600_dma_is_lockup,
		924	.get_rptr = &r600_dma_get_rptr,
		925	.get_wptr = &r600_dma_get_wptr,
		926	.set_wptr = &r600_dma_set_wptr,
		927	};
		928
1963	serge	929	static struct radeon_asic r600_asic = {
		930	.init = &r600_init,
6104	serge	931	.fini = &r600_fini,
1963	serge	932	// .suspend = &r600_suspend,
		933	// .resume = &r600_resume,
2997	Serge	934	// .vga_set_state = &r600_vga_set_state,
1963	serge	935	.asic_reset = &r600_asic_reset,
5078	serge	936	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	937	.gui_idle = &r600_gui_idle,
		938	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	939	.get_xclk = &r600_get_xclk,
		940	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	941	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	942	.gart = {
		943	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	944	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	945	.set_page = &rs600_gart_set_page,
		946	},
		947	.ring = {
5078	serge	948	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		949	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	950	},
		951	.irq = {
		952	.set = &r600_irq_set,
		953	.process = &r600_irq_process,
		954	},
		955	.display = {
		956	.bandwidth_update = &rv515_bandwidth_update,
		957	.get_vblank_counter = &rs600_get_vblank_counter,
		958	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	959	.set_backlight_level = &atombios_set_backlight_level,
		960	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	961	},
		962	.copy = {
5078	serge	963	.blit = &r600_copy_cpdma,
2997	Serge	964	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	965	.dma = &r600_copy_dma,
		966	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	967	.copy = &r600_copy_cpdma,
		968	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	969	},
		970	.surface = {
		971	.set_reg = r600_set_surface_reg,
		972	.clear_reg = r600_clear_surface_reg,
		973	},
		974	.hpd = {
5078	serge	975	.init = &r600_hpd_init,
		976	.fini = &r600_hpd_fini,
		977	.sense = &r600_hpd_sense,
		978	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	979	},
		980	.pm = {
5078	serge	981	.misc = &r600_pm_misc,
		982	.prepare = &rs600_pm_prepare,
		983	.finish = &rs600_pm_finish,
		984	.init_profile = &r600_pm_init_profile,
		985	.get_dynpm_state = &r600_pm_get_dynpm_state,
		986	.get_engine_clock = &radeon_atom_get_engine_clock,
		987	.set_engine_clock = &radeon_atom_set_engine_clock,
		988	.get_memory_clock = &radeon_atom_get_memory_clock,
		989	.set_memory_clock = &radeon_atom_set_memory_clock,
		990	.get_pcie_lanes = &r600_get_pcie_lanes,
		991	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	992	.set_clock_gating = NULL,
5078	serge	993	.get_temperature = &rv6xx_get_temp,
2997	Serge	994	},
		995	.pflip = {
		996	// .pre_page_flip = &rs600_pre_page_flip,
		997	// .page_flip = &rs600_page_flip,
		998	},
1963	serge	999	};
		1000
6938	serge	1001	static const struct radeon_asic_ring rv6xx_uvd_ring = {
6104	serge	1002	.ib_execute = &uvd_v1_0_ib_execute,
		1003	.emit_fence = &uvd_v1_0_fence_emit,
		1004	.emit_semaphore = &uvd_v1_0_semaphore_emit,
		1005	.cs_parse = &radeon_uvd_cs_parse,
		1006	.ring_test = &uvd_v1_0_ring_test,
		1007	.ib_test = &uvd_v1_0_ib_test,
		1008	.is_lockup = &radeon_ring_test_lockup,
		1009	.get_rptr = &uvd_v1_0_get_rptr,
		1010	.get_wptr = &uvd_v1_0_get_wptr,
		1011	.set_wptr = &uvd_v1_0_set_wptr,
		1012	};
		1013
5078	serge	1014	static struct radeon_asic rv6xx_asic = {
		1015	.init = &r600_init,
6104	serge	1016	.fini = &r600_fini,
5078	serge	1017	// .suspend = &r600_suspend,
		1018	// .resume = &r600_resume,
		1019	// .vga_set_state = &r600_vga_set_state,
		1020	.asic_reset = &r600_asic_reset,
		1021	.mmio_hdp_flush = r600_mmio_hdp_flush,
		1022	.gui_idle = &r600_gui_idle,
		1023	.mc_wait_for_idle = &r600_mc_wait_for_idle,
		1024	.get_xclk = &r600_get_xclk,
		1025	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1026	.get_allowed_info_register = r600_get_allowed_info_register,
5078	serge	1027	.gart = {
		1028	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1029	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	1030	.set_page = &rs600_gart_set_page,
		1031	},
		1032	.ring = {
		1033	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1034	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
6104	serge	1035	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
5078	serge	1036	},
		1037	.irq = {
		1038	.set = &r600_irq_set,
		1039	.process = &r600_irq_process,
		1040	},
		1041	.display = {
		1042	.bandwidth_update = &rv515_bandwidth_update,
		1043	.get_vblank_counter = &rs600_get_vblank_counter,
		1044	.wait_for_vblank = &avivo_wait_for_vblank,
		1045	.set_backlight_level = &atombios_set_backlight_level,
		1046	.get_backlight_level = &atombios_get_backlight_level,
		1047	},
		1048	.copy = {
		1049	.blit = &r600_copy_cpdma,
		1050	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1051	.dma = &r600_copy_dma,
		1052	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1053	.copy = &r600_copy_cpdma,
		1054	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1055	},
		1056	.surface = {
		1057	.set_reg = r600_set_surface_reg,
		1058	.clear_reg = r600_clear_surface_reg,
		1059	},
		1060	.hpd = {
		1061	.init = &r600_hpd_init,
		1062	.fini = &r600_hpd_fini,
		1063	.sense = &r600_hpd_sense,
		1064	.set_polarity = &r600_hpd_set_polarity,
		1065	},
		1066	.pm = {
		1067	.misc = &r600_pm_misc,
		1068	.prepare = &rs600_pm_prepare,
		1069	.finish = &rs600_pm_finish,
		1070	.init_profile = &r600_pm_init_profile,
		1071	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1072	.get_engine_clock = &radeon_atom_get_engine_clock,
		1073	.set_engine_clock = &radeon_atom_set_engine_clock,
		1074	.get_memory_clock = &radeon_atom_get_memory_clock,
		1075	.set_memory_clock = &radeon_atom_set_memory_clock,
		1076	.get_pcie_lanes = &r600_get_pcie_lanes,
		1077	.set_pcie_lanes = &r600_set_pcie_lanes,
		1078	.set_clock_gating = NULL,
		1079	.get_temperature = &rv6xx_get_temp,
		1080	.set_uvd_clocks = &r600_set_uvd_clocks,
		1081	},
		1082	.dpm = {
		1083	.init = &rv6xx_dpm_init,
		1084	.setup_asic = &rv6xx_setup_asic,
		1085	.enable = &rv6xx_dpm_enable,
		1086	.late_enable = &r600_dpm_late_enable,
		1087	.disable = &rv6xx_dpm_disable,
		1088	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1089	.set_power_state = &rv6xx_dpm_set_power_state,
		1090	.post_set_power_state = &r600_dpm_post_set_power_state,
		1091	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
		1092	.fini = &rv6xx_dpm_fini,
		1093	.get_sclk = &rv6xx_dpm_get_sclk,
		1094	.get_mclk = &rv6xx_dpm_get_mclk,
		1095	.print_power_state = &rv6xx_dpm_print_power_state,
		1096	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
		1097	.force_performance_level = &rv6xx_dpm_force_performance_level,
6104	serge	1098	.get_current_sclk = &rv6xx_dpm_get_current_sclk,
		1099	.get_current_mclk = &rv6xx_dpm_get_current_mclk,
5078	serge	1100	},
		1101	.pflip = {
		1102	// .pre_page_flip = &rs600_pre_page_flip,
		1103	// .page_flip = &rs600_page_flip,
		1104	},
		1105	};
		1106
1963	serge	1107	static struct radeon_asic rs780_asic = {
		1108	.init = &r600_init,
6104	serge	1109	.fini = &r600_fini,
1963	serge	1110	// .suspend = &r600_suspend,
		1111	// .resume = &r600_resume,
2997	Serge	1112	// .vga_set_state = &r600_vga_set_state,
1963	serge	1113	.asic_reset = &r600_asic_reset,
5078	serge	1114	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1115	.gui_idle = &r600_gui_idle,
		1116	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1117	.get_xclk = &r600_get_xclk,
		1118	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1119	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	1120	.gart = {
		1121	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1122	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1123	.set_page = &rs600_gart_set_page,
		1124	},
		1125	.ring = {
5078	serge	1126	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1127	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
6104	serge	1128	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
2997	Serge	1129	},
		1130	.irq = {
		1131	.set = &r600_irq_set,
		1132	.process = &r600_irq_process,
		1133	},
		1134	.display = {
		1135	.bandwidth_update = &rs690_bandwidth_update,
		1136	.get_vblank_counter = &rs600_get_vblank_counter,
		1137	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1138	.set_backlight_level = &atombios_set_backlight_level,
		1139	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1140	},
		1141	.copy = {
5078	serge	1142	.blit = &r600_copy_cpdma,
2997	Serge	1143	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1144	.dma = &r600_copy_dma,
		1145	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	1146	.copy = &r600_copy_cpdma,
		1147	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	1148	},
		1149	.surface = {
		1150	.set_reg = r600_set_surface_reg,
		1151	.clear_reg = r600_clear_surface_reg,
		1152	},
		1153	.hpd = {
5078	serge	1154	.init = &r600_hpd_init,
		1155	.fini = &r600_hpd_fini,
		1156	.sense = &r600_hpd_sense,
		1157	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1158	},
		1159	.pm = {
5078	serge	1160	.misc = &r600_pm_misc,
		1161	.prepare = &rs600_pm_prepare,
		1162	.finish = &rs600_pm_finish,
		1163	.init_profile = &rs780_pm_init_profile,
		1164	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1165	.get_engine_clock = &radeon_atom_get_engine_clock,
		1166	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1167	.get_memory_clock = NULL,
		1168	.set_memory_clock = NULL,
		1169	.get_pcie_lanes = NULL,
		1170	.set_pcie_lanes = NULL,
		1171	.set_clock_gating = NULL,
5078	serge	1172	.get_temperature = &rv6xx_get_temp,
		1173	.set_uvd_clocks = &r600_set_uvd_clocks,
2997	Serge	1174	},
5078	serge	1175	.dpm = {
		1176	.init = &rs780_dpm_init,
		1177	.setup_asic = &rs780_dpm_setup_asic,
		1178	.enable = &rs780_dpm_enable,
		1179	.late_enable = &r600_dpm_late_enable,
		1180	.disable = &rs780_dpm_disable,
		1181	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1182	.set_power_state = &rs780_dpm_set_power_state,
		1183	.post_set_power_state = &r600_dpm_post_set_power_state,
		1184	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
		1185	.fini = &rs780_dpm_fini,
		1186	.get_sclk = &rs780_dpm_get_sclk,
		1187	.get_mclk = &rs780_dpm_get_mclk,
		1188	.print_power_state = &rs780_dpm_print_power_state,
		1189	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
		1190	.force_performance_level = &rs780_dpm_force_performance_level,
6104	serge	1191	.get_current_sclk = &rs780_dpm_get_current_sclk,
		1192	.get_current_mclk = &rs780_dpm_get_current_mclk,
5078	serge	1193	},
2997	Serge	1194	.pflip = {
		1195	// .pre_page_flip = &rs600_pre_page_flip,
		1196	// .page_flip = &rs600_page_flip,
		1197	},
1963	serge	1198	};
		1199
6938	serge	1200	static const struct radeon_asic_ring rv770_uvd_ring = {
5078	serge	1201	.ib_execute = &uvd_v1_0_ib_execute,
		1202	.emit_fence = &uvd_v2_2_fence_emit,
6104	serge	1203	.emit_semaphore = &uvd_v2_2_semaphore_emit,
5078	serge	1204	.cs_parse = &radeon_uvd_cs_parse,
		1205	.ring_test = &uvd_v1_0_ring_test,
		1206	.ib_test = &uvd_v1_0_ib_test,
		1207	.is_lockup = &radeon_ring_test_lockup,
		1208	.get_rptr = &uvd_v1_0_get_rptr,
		1209	.get_wptr = &uvd_v1_0_get_wptr,
		1210	.set_wptr = &uvd_v1_0_set_wptr,
		1211	};
		1212
1963	serge	1213	static struct radeon_asic rv770_asic = {
		1214	.init = &rv770_init,
6104	serge	1215	.fini = &rv770_fini,
1963	serge	1216	// .suspend = &rv770_suspend,
		1217	// .resume = &rv770_resume,
		1218	.asic_reset = &r600_asic_reset,
2997	Serge	1219	// .vga_set_state = &r600_vga_set_state,
5078	serge	1220	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1221	.gui_idle = &r600_gui_idle,
		1222	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1223	.get_xclk = &rv770_get_xclk,
		1224	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1225	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	1226	.gart = {
		1227	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1228	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1229	.set_page = &rs600_gart_set_page,
		1230	},
		1231	.ring = {
5078	serge	1232	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1233	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		1234	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1235	},
		1236	.irq = {
		1237	.set = &r600_irq_set,
		1238	.process = &r600_irq_process,
		1239	},
		1240	.display = {
		1241	.bandwidth_update = &rv515_bandwidth_update,
		1242	.get_vblank_counter = &rs600_get_vblank_counter,
		1243	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1244	.set_backlight_level = &atombios_set_backlight_level,
		1245	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1246	},
		1247	.copy = {
5078	serge	1248	.blit = &r600_copy_cpdma,
2997	Serge	1249	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3764	Serge	1250	.dma = &rv770_copy_dma,
3192	Serge	1251	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
3764	Serge	1252	.copy = &rv770_copy_dma,
3192	Serge	1253	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1254	},
		1255	.surface = {
		1256	.set_reg = r600_set_surface_reg,
		1257	.clear_reg = r600_clear_surface_reg,
		1258	},
		1259	.hpd = {
5078	serge	1260	.init = &r600_hpd_init,
		1261	.fini = &r600_hpd_fini,
		1262	.sense = &r600_hpd_sense,
		1263	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1264	},
		1265	.pm = {
5078	serge	1266	.misc = &rv770_pm_misc,
		1267	.prepare = &rs600_pm_prepare,
		1268	.finish = &rs600_pm_finish,
		1269	.init_profile = &r600_pm_init_profile,
		1270	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1271	.get_engine_clock = &radeon_atom_get_engine_clock,
		1272	.set_engine_clock = &radeon_atom_set_engine_clock,
		1273	.get_memory_clock = &radeon_atom_get_memory_clock,
		1274	.set_memory_clock = &radeon_atom_set_memory_clock,
		1275	.get_pcie_lanes = &r600_get_pcie_lanes,
		1276	.set_pcie_lanes = &r600_set_pcie_lanes,
		1277	.set_clock_gating = &radeon_atom_set_clock_gating,
3764	Serge	1278	.set_uvd_clocks = &rv770_set_uvd_clocks,
5078	serge	1279	.get_temperature = &rv770_get_temp,
2997	Serge	1280	},
5078	serge	1281	.dpm = {
		1282	.init = &rv770_dpm_init,
		1283	.setup_asic = &rv770_dpm_setup_asic,
		1284	.enable = &rv770_dpm_enable,
		1285	.late_enable = &rv770_dpm_late_enable,
		1286	.disable = &rv770_dpm_disable,
		1287	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1288	.set_power_state = &rv770_dpm_set_power_state,
		1289	.post_set_power_state = &r600_dpm_post_set_power_state,
		1290	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
		1291	.fini = &rv770_dpm_fini,
		1292	.get_sclk = &rv770_dpm_get_sclk,
		1293	.get_mclk = &rv770_dpm_get_mclk,
		1294	.print_power_state = &rv770_dpm_print_power_state,
		1295	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1296	.force_performance_level = &rv770_dpm_force_performance_level,
		1297	.vblank_too_short = &rv770_dpm_vblank_too_short,
6104	serge	1298	.get_current_sclk = &rv770_dpm_get_current_sclk,
		1299	.get_current_mclk = &rv770_dpm_get_current_mclk,
5078	serge	1300	},
2997	Serge	1301	.pflip = {
		1302	// .pre_page_flip = &rs600_pre_page_flip,
		1303	// .page_flip = &rv770_page_flip,
		1304	},
1963	serge	1305	};
1986	serge	1306
6938	serge	1307	static const struct radeon_asic_ring evergreen_gfx_ring = {
5078	serge	1308	.ib_execute = &evergreen_ring_ib_execute,
		1309	.emit_fence = &r600_fence_ring_emit,
		1310	.emit_semaphore = &r600_semaphore_ring_emit,
		1311	.cs_parse = &evergreen_cs_parse,
		1312	.ring_test = &r600_ring_test,
		1313	.ib_test = &r600_ib_test,
		1314	.is_lockup = &evergreen_gfx_is_lockup,
		1315	.get_rptr = &r600_gfx_get_rptr,
		1316	.get_wptr = &r600_gfx_get_wptr,
		1317	.set_wptr = &r600_gfx_set_wptr,
		1318	};
		1319
6938	serge	1320	static const struct radeon_asic_ring evergreen_dma_ring = {
5078	serge	1321	.ib_execute = &evergreen_dma_ring_ib_execute,
		1322	.emit_fence = &evergreen_dma_fence_ring_emit,
		1323	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1324	.cs_parse = &evergreen_dma_cs_parse,
		1325	.ring_test = &r600_dma_ring_test,
		1326	.ib_test = &r600_dma_ib_test,
		1327	.is_lockup = &evergreen_dma_is_lockup,
		1328	.get_rptr = &r600_dma_get_rptr,
		1329	.get_wptr = &r600_dma_get_wptr,
		1330	.set_wptr = &r600_dma_set_wptr,
		1331	};
		1332
1963	serge	1333	static struct radeon_asic evergreen_asic = {
		1334	.init = &evergreen_init,
6104	serge	1335	.fini = &evergreen_fini,
1963	serge	1336	// .suspend = &evergreen_suspend,
		1337	// .resume = &evergreen_resume,
		1338	.asic_reset = &evergreen_asic_reset,
2997	Serge	1339	// .vga_set_state = &r600_vga_set_state,
5078	serge	1340	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1341	.gui_idle = &r600_gui_idle,
		1342	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1343	.get_xclk = &rv770_get_xclk,
		1344	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1345	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1346	.gart = {
		1347	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1348	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1349	.set_page = &rs600_gart_set_page,
		1350	},
		1351	.ring = {
5078	serge	1352	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1353	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1354	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1355	},
		1356	.irq = {
		1357	.set = &evergreen_irq_set,
		1358	.process = &evergreen_irq_process,
		1359	},
		1360	.display = {
		1361	.bandwidth_update = &evergreen_bandwidth_update,
		1362	.get_vblank_counter = &evergreen_get_vblank_counter,
		1363	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1364	.set_backlight_level = &atombios_set_backlight_level,
		1365	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1366	},
		1367	.copy = {
5078	serge	1368	.blit = &r600_copy_cpdma,
2997	Serge	1369	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1370	.dma = &evergreen_copy_dma,
		1371	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1372	.copy = &evergreen_copy_dma,
		1373	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1374	},
		1375	.surface = {
		1376	.set_reg = r600_set_surface_reg,
		1377	.clear_reg = r600_clear_surface_reg,
		1378	},
		1379	.hpd = {
5078	serge	1380	.init = &evergreen_hpd_init,
		1381	.fini = &evergreen_hpd_fini,
		1382	.sense = &evergreen_hpd_sense,
		1383	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1384	},
		1385	.pm = {
5078	serge	1386	.misc = &evergreen_pm_misc,
		1387	.prepare = &evergreen_pm_prepare,
		1388	.finish = &evergreen_pm_finish,
		1389	.init_profile = &r600_pm_init_profile,
		1390	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1391	.get_engine_clock = &radeon_atom_get_engine_clock,
		1392	.set_engine_clock = &radeon_atom_set_engine_clock,
		1393	.get_memory_clock = &radeon_atom_get_memory_clock,
		1394	.set_memory_clock = &radeon_atom_set_memory_clock,
		1395	.get_pcie_lanes = &r600_get_pcie_lanes,
		1396	.set_pcie_lanes = &r600_set_pcie_lanes,
		1397	.set_clock_gating = NULL,
3764	Serge	1398	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1399	.get_temperature = &evergreen_get_temp,
2997	Serge	1400	},
5078	serge	1401	.dpm = {
		1402	.init = &cypress_dpm_init,
		1403	.setup_asic = &cypress_dpm_setup_asic,
		1404	.enable = &cypress_dpm_enable,
		1405	.late_enable = &rv770_dpm_late_enable,
		1406	.disable = &cypress_dpm_disable,
		1407	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1408	.set_power_state = &cypress_dpm_set_power_state,
		1409	.post_set_power_state = &r600_dpm_post_set_power_state,
		1410	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1411	.fini = &cypress_dpm_fini,
		1412	.get_sclk = &rv770_dpm_get_sclk,
		1413	.get_mclk = &rv770_dpm_get_mclk,
		1414	.print_power_state = &rv770_dpm_print_power_state,
		1415	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1416	.force_performance_level = &rv770_dpm_force_performance_level,
		1417	.vblank_too_short = &cypress_dpm_vblank_too_short,
6104	serge	1418	.get_current_sclk = &rv770_dpm_get_current_sclk,
		1419	.get_current_mclk = &rv770_dpm_get_current_mclk,
5078	serge	1420	},
2997	Serge	1421	.pflip = {
		1422	},
1986	serge	1423	};
1990	serge	1424
1986	serge	1425	static struct radeon_asic sumo_asic = {
		1426	.init = &evergreen_init,
6104	serge	1427	.fini = &evergreen_fini,
1990	serge	1428	// .suspend = &evergreen_suspend,
		1429	// .resume = &evergreen_resume,
1986	serge	1430	.asic_reset = &evergreen_asic_reset,
2997	Serge	1431	// .vga_set_state = &r600_vga_set_state,
5078	serge	1432	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1433	.gui_idle = &r600_gui_idle,
		1434	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1435	.get_xclk = &r600_get_xclk,
		1436	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1437	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1438	.gart = {
		1439	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1440	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1441	.set_page = &rs600_gart_set_page,
		1442	},
		1443	.ring = {
5078	serge	1444	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1445	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1446	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1447	},
		1448	.irq = {
		1449	.set = &evergreen_irq_set,
		1450	.process = &evergreen_irq_process,
		1451	},
		1452	.display = {
		1453	.bandwidth_update = &evergreen_bandwidth_update,
		1454	.get_vblank_counter = &evergreen_get_vblank_counter,
		1455	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1456	.set_backlight_level = &atombios_set_backlight_level,
		1457	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1458	},
		1459	.copy = {
5078	serge	1460	.blit = &r600_copy_cpdma,
2997	Serge	1461	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1462	.dma = &evergreen_copy_dma,
		1463	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1464	.copy = &evergreen_copy_dma,
		1465	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1466	},
		1467	.surface = {
		1468	.set_reg = r600_set_surface_reg,
		1469	.clear_reg = r600_clear_surface_reg,
		1470	},
		1471	.hpd = {
5078	serge	1472	.init = &evergreen_hpd_init,
		1473	.fini = &evergreen_hpd_fini,
		1474	.sense = &evergreen_hpd_sense,
		1475	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1476	},
		1477	.pm = {
5078	serge	1478	.misc = &evergreen_pm_misc,
		1479	.prepare = &evergreen_pm_prepare,
		1480	.finish = &evergreen_pm_finish,
		1481	.init_profile = &sumo_pm_init_profile,
		1482	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1483	.get_engine_clock = &radeon_atom_get_engine_clock,
		1484	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1485	.get_memory_clock = NULL,
		1486	.set_memory_clock = NULL,
		1487	.get_pcie_lanes = NULL,
		1488	.set_pcie_lanes = NULL,
		1489	.set_clock_gating = NULL,
3764	Serge	1490	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1491	.get_temperature = &sumo_get_temp,
2997	Serge	1492	},
5078	serge	1493	.dpm = {
		1494	.init = &sumo_dpm_init,
		1495	.setup_asic = &sumo_dpm_setup_asic,
		1496	.enable = &sumo_dpm_enable,
		1497	.late_enable = &sumo_dpm_late_enable,
		1498	.disable = &sumo_dpm_disable,
		1499	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
		1500	.set_power_state = &sumo_dpm_set_power_state,
		1501	.post_set_power_state = &sumo_dpm_post_set_power_state,
		1502	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
		1503	.fini = &sumo_dpm_fini,
		1504	.get_sclk = &sumo_dpm_get_sclk,
		1505	.get_mclk = &sumo_dpm_get_mclk,
		1506	.print_power_state = &sumo_dpm_print_power_state,
		1507	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
		1508	.force_performance_level = &sumo_dpm_force_performance_level,
6104	serge	1509	.get_current_sclk = &sumo_dpm_get_current_sclk,
		1510	.get_current_mclk = &sumo_dpm_get_current_mclk,
5078	serge	1511	},
2997	Serge	1512	.pflip = {
		1513	// .pre_page_flip = &evergreen_pre_page_flip,
		1514	// .page_flip = &evergreen_page_flip,
		1515	},
1986	serge	1516	};
		1517
		1518	static struct radeon_asic btc_asic = {
		1519	.init = &evergreen_init,
6104	serge	1520	.fini = &evergreen_fini,
1990	serge	1521	// .suspend = &evergreen_suspend,
		1522	// .resume = &evergreen_resume,
1986	serge	1523	.asic_reset = &evergreen_asic_reset,
2997	Serge	1524	// .vga_set_state = &r600_vga_set_state,
5078	serge	1525	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1526	.gui_idle = &r600_gui_idle,
		1527	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1528	.get_xclk = &rv770_get_xclk,
		1529	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1530	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1531	.gart = {
		1532	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1533	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1534	.set_page = &rs600_gart_set_page,
		1535	},
		1536	.ring = {
5078	serge	1537	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1538	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1539	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1540	},
		1541	.irq = {
		1542	.set = &evergreen_irq_set,
		1543	.process = &evergreen_irq_process,
		1544	},
		1545	.display = {
		1546	.bandwidth_update = &evergreen_bandwidth_update,
		1547	.get_vblank_counter = &evergreen_get_vblank_counter,
		1548	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1549	.set_backlight_level = &atombios_set_backlight_level,
		1550	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1551	},
		1552	.copy = {
5078	serge	1553	.blit = &r600_copy_cpdma,
2997	Serge	1554	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1555	.dma = &evergreen_copy_dma,
		1556	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1557	.copy = &evergreen_copy_dma,
		1558	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1559	},
		1560	.surface = {
		1561	.set_reg = r600_set_surface_reg,
		1562	.clear_reg = r600_clear_surface_reg,
		1563	},
		1564	.hpd = {
5078	serge	1565	.init = &evergreen_hpd_init,
		1566	.fini = &evergreen_hpd_fini,
		1567	.sense = &evergreen_hpd_sense,
		1568	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1569	},
		1570	.pm = {
5078	serge	1571	.misc = &evergreen_pm_misc,
		1572	.prepare = &evergreen_pm_prepare,
		1573	.finish = &evergreen_pm_finish,
		1574	.init_profile = &btc_pm_init_profile,
		1575	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1576	.get_engine_clock = &radeon_atom_get_engine_clock,
		1577	.set_engine_clock = &radeon_atom_set_engine_clock,
		1578	.get_memory_clock = &radeon_atom_get_memory_clock,
		1579	.set_memory_clock = &radeon_atom_set_memory_clock,
		1580	.get_pcie_lanes = &r600_get_pcie_lanes,
		1581	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1582	.set_clock_gating = NULL,
3764	Serge	1583	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1584	.get_temperature = &evergreen_get_temp,
2997	Serge	1585	},
5078	serge	1586	.dpm = {
		1587	.init = &btc_dpm_init,
		1588	.setup_asic = &btc_dpm_setup_asic,
		1589	.enable = &btc_dpm_enable,
		1590	.late_enable = &rv770_dpm_late_enable,
		1591	.disable = &btc_dpm_disable,
		1592	.pre_set_power_state = &btc_dpm_pre_set_power_state,
		1593	.set_power_state = &btc_dpm_set_power_state,
		1594	.post_set_power_state = &btc_dpm_post_set_power_state,
		1595	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1596	.fini = &btc_dpm_fini,
		1597	.get_sclk = &btc_dpm_get_sclk,
		1598	.get_mclk = &btc_dpm_get_mclk,
		1599	.print_power_state = &rv770_dpm_print_power_state,
		1600	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
		1601	.force_performance_level = &rv770_dpm_force_performance_level,
		1602	.vblank_too_short = &btc_dpm_vblank_too_short,
6104	serge	1603	.get_current_sclk = &btc_dpm_get_current_sclk,
		1604	.get_current_mclk = &btc_dpm_get_current_mclk,
5078	serge	1605	},
2997	Serge	1606	.pflip = {
		1607	// .pre_page_flip = &evergreen_pre_page_flip,
		1608	// .page_flip = &evergreen_page_flip,
		1609	},
1986	serge	1610	};
		1611
6938	serge	1612	static const struct radeon_asic_ring cayman_gfx_ring = {
5078	serge	1613	.ib_execute = &cayman_ring_ib_execute,
		1614	.ib_parse = &evergreen_ib_parse,
		1615	.emit_fence = &cayman_fence_ring_emit,
		1616	.emit_semaphore = &r600_semaphore_ring_emit,
		1617	.cs_parse = &evergreen_cs_parse,
		1618	.ring_test = &r600_ring_test,
		1619	.ib_test = &r600_ib_test,
		1620	.is_lockup = &cayman_gfx_is_lockup,
		1621	.vm_flush = &cayman_vm_flush,
		1622	.get_rptr = &cayman_gfx_get_rptr,
		1623	.get_wptr = &cayman_gfx_get_wptr,
		1624	.set_wptr = &cayman_gfx_set_wptr,
		1625	};
		1626
6938	serge	1627	static const struct radeon_asic_ring cayman_dma_ring = {
5078	serge	1628	.ib_execute = &cayman_dma_ring_ib_execute,
		1629	.ib_parse = &evergreen_dma_ib_parse,
		1630	.emit_fence = &evergreen_dma_fence_ring_emit,
		1631	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1632	.cs_parse = &evergreen_dma_cs_parse,
		1633	.ring_test = &r600_dma_ring_test,
		1634	.ib_test = &r600_dma_ib_test,
		1635	.is_lockup = &cayman_dma_is_lockup,
		1636	.vm_flush = &cayman_dma_vm_flush,
		1637	.get_rptr = &cayman_dma_get_rptr,
		1638	.get_wptr = &cayman_dma_get_wptr,
		1639	.set_wptr = &cayman_dma_set_wptr
		1640	};
		1641
6938	serge	1642	static const struct radeon_asic_ring cayman_uvd_ring = {
5078	serge	1643	.ib_execute = &uvd_v1_0_ib_execute,
		1644	.emit_fence = &uvd_v2_2_fence_emit,
		1645	.emit_semaphore = &uvd_v3_1_semaphore_emit,
		1646	.cs_parse = &radeon_uvd_cs_parse,
		1647	.ring_test = &uvd_v1_0_ring_test,
		1648	.ib_test = &uvd_v1_0_ib_test,
		1649	.is_lockup = &radeon_ring_test_lockup,
		1650	.get_rptr = &uvd_v1_0_get_rptr,
		1651	.get_wptr = &uvd_v1_0_get_wptr,
		1652	.set_wptr = &uvd_v1_0_set_wptr,
		1653	};
		1654
1986	serge	1655	static struct radeon_asic cayman_asic = {
		1656	.init = &cayman_init,
6104	serge	1657	.fini = &cayman_fini,
2997	Serge	1658	// .suspend = &cayman_suspend,
		1659	// .resume = &cayman_resume,
1986	serge	1660	.asic_reset = &cayman_asic_reset,
2997	Serge	1661	// .vga_set_state = &r600_vga_set_state,
5078	serge	1662	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1663	.gui_idle = &r600_gui_idle,
		1664	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1665	.get_xclk = &rv770_get_xclk,
		1666	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1667	.get_allowed_info_register = cayman_get_allowed_info_register,
2997	Serge	1668	.gart = {
		1669	.tlb_flush = &cayman_pcie_gart_tlb_flush,
6104	serge	1670	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1671	.set_page = &rs600_gart_set_page,
		1672	},
		1673	.vm = {
		1674	.init = &cayman_vm_init,
		1675	.fini = &cayman_vm_fini,
5078	serge	1676	.copy_pages = &cayman_dma_vm_copy_pages,
		1677	.write_pages = &cayman_dma_vm_write_pages,
		1678	.set_pages = &cayman_dma_vm_set_pages,
		1679	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1680	},
		1681	.ring = {
5078	serge	1682	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1683	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1684	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1685	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1686	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1687	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1688	},
		1689	.irq = {
		1690	.set = &evergreen_irq_set,
		1691	.process = &evergreen_irq_process,
		1692	},
		1693	.display = {
		1694	.bandwidth_update = &evergreen_bandwidth_update,
		1695	.get_vblank_counter = &evergreen_get_vblank_counter,
		1696	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1697	.set_backlight_level = &atombios_set_backlight_level,
		1698	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1699	},
		1700	.copy = {
5078	serge	1701	.blit = &r600_copy_cpdma,
2997	Serge	1702	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1703	.dma = &evergreen_copy_dma,
		1704	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1705	.copy = &evergreen_copy_dma,
		1706	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1707	},
		1708	.surface = {
		1709	.set_reg = r600_set_surface_reg,
		1710	.clear_reg = r600_clear_surface_reg,
		1711	},
		1712	.hpd = {
5078	serge	1713	.init = &evergreen_hpd_init,
		1714	.fini = &evergreen_hpd_fini,
		1715	.sense = &evergreen_hpd_sense,
		1716	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1717	},
		1718	.pm = {
5078	serge	1719	.misc = &evergreen_pm_misc,
		1720	.prepare = &evergreen_pm_prepare,
		1721	.finish = &evergreen_pm_finish,
		1722	.init_profile = &btc_pm_init_profile,
		1723	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1724	.get_engine_clock = &radeon_atom_get_engine_clock,
		1725	.set_engine_clock = &radeon_atom_set_engine_clock,
		1726	.get_memory_clock = &radeon_atom_get_memory_clock,
		1727	.set_memory_clock = &radeon_atom_set_memory_clock,
		1728	.get_pcie_lanes = &r600_get_pcie_lanes,
		1729	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1730	.set_clock_gating = NULL,
3764	Serge	1731	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1732	.get_temperature = &evergreen_get_temp,
2997	Serge	1733	},
5078	serge	1734	.dpm = {
		1735	.init = &ni_dpm_init,
		1736	.setup_asic = &ni_dpm_setup_asic,
		1737	.enable = &ni_dpm_enable,
		1738	.late_enable = &rv770_dpm_late_enable,
		1739	.disable = &ni_dpm_disable,
		1740	.pre_set_power_state = &ni_dpm_pre_set_power_state,
		1741	.set_power_state = &ni_dpm_set_power_state,
		1742	.post_set_power_state = &ni_dpm_post_set_power_state,
		1743	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1744	.fini = &ni_dpm_fini,
		1745	.get_sclk = &ni_dpm_get_sclk,
		1746	.get_mclk = &ni_dpm_get_mclk,
		1747	.print_power_state = &ni_dpm_print_power_state,
		1748	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
		1749	.force_performance_level = &ni_dpm_force_performance_level,
		1750	.vblank_too_short = &ni_dpm_vblank_too_short,
6104	serge	1751	.get_current_sclk = &ni_dpm_get_current_sclk,
		1752	.get_current_mclk = &ni_dpm_get_current_mclk,
5078	serge	1753	},
2997	Serge	1754	.pflip = {
		1755	// .pre_page_flip = &evergreen_pre_page_flip,
		1756	// .page_flip = &evergreen_page_flip,
		1757	},
1963	serge	1758	};
		1759
6938	serge	1760	static const struct radeon_asic_ring trinity_vce_ring = {
6104	serge	1761	.ib_execute = &radeon_vce_ib_execute,
		1762	.emit_fence = &radeon_vce_fence_emit,
		1763	.emit_semaphore = &radeon_vce_semaphore_emit,
		1764	.cs_parse = &radeon_vce_cs_parse,
		1765	.ring_test = &radeon_vce_ring_test,
		1766	.ib_test = &radeon_vce_ib_test,
		1767	.is_lockup = &radeon_ring_test_lockup,
		1768	.get_rptr = &vce_v1_0_get_rptr,
		1769	.get_wptr = &vce_v1_0_get_wptr,
		1770	.set_wptr = &vce_v1_0_set_wptr,
		1771	};
		1772
2997	Serge	1773	static struct radeon_asic trinity_asic = {
		1774	.init = &cayman_init,
6104	serge	1775	.fini = &cayman_fini,
2997	Serge	1776	// .suspend = &cayman_suspend,
		1777	// .resume = &cayman_resume,
		1778	.asic_reset = &cayman_asic_reset,
		1779	// .vga_set_state = &r600_vga_set_state,
5078	serge	1780	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1781	.gui_idle = &r600_gui_idle,
		1782	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1783	.get_xclk = &r600_get_xclk,
		1784	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1785	.get_allowed_info_register = cayman_get_allowed_info_register,
2997	Serge	1786	.gart = {
		1787	.tlb_flush = &cayman_pcie_gart_tlb_flush,
6104	serge	1788	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1789	.set_page = &rs600_gart_set_page,
		1790	},
		1791	.vm = {
		1792	.init = &cayman_vm_init,
		1793	.fini = &cayman_vm_fini,
5078	serge	1794	.copy_pages = &cayman_dma_vm_copy_pages,
		1795	.write_pages = &cayman_dma_vm_write_pages,
		1796	.set_pages = &cayman_dma_vm_set_pages,
		1797	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1798	},
		1799	.ring = {
5078	serge	1800	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1801	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1802	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1803	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1804	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1805	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
6104	serge	1806	[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		1807	[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
2997	Serge	1808	},
		1809	.irq = {
		1810	.set = &evergreen_irq_set,
		1811	.process = &evergreen_irq_process,
		1812	},
		1813	.display = {
		1814	.bandwidth_update = &dce6_bandwidth_update,
		1815	.get_vblank_counter = &evergreen_get_vblank_counter,
		1816	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1817	.set_backlight_level = &atombios_set_backlight_level,
		1818	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1819	},
		1820	.copy = {
5078	serge	1821	.blit = &r600_copy_cpdma,
2997	Serge	1822	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1823	.dma = &evergreen_copy_dma,
		1824	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1825	.copy = &evergreen_copy_dma,
		1826	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1827	},
		1828	.surface = {
		1829	.set_reg = r600_set_surface_reg,
		1830	.clear_reg = r600_clear_surface_reg,
		1831	},
		1832	.hpd = {
5078	serge	1833	.init = &evergreen_hpd_init,
		1834	.fini = &evergreen_hpd_fini,
		1835	.sense = &evergreen_hpd_sense,
		1836	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1837	},
		1838	.pm = {
5078	serge	1839	.misc = &evergreen_pm_misc,
		1840	.prepare = &evergreen_pm_prepare,
		1841	.finish = &evergreen_pm_finish,
		1842	.init_profile = &sumo_pm_init_profile,
		1843	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1844	.get_engine_clock = &radeon_atom_get_engine_clock,
		1845	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1846	.get_memory_clock = NULL,
		1847	.set_memory_clock = NULL,
		1848	.get_pcie_lanes = NULL,
		1849	.set_pcie_lanes = NULL,
		1850	.set_clock_gating = NULL,
3764	Serge	1851	.set_uvd_clocks = &sumo_set_uvd_clocks,
6104	serge	1852	.set_vce_clocks = &tn_set_vce_clocks,
5078	serge	1853	.get_temperature = &tn_get_temp,
2997	Serge	1854	},
5078	serge	1855	.dpm = {
		1856	.init = &trinity_dpm_init,
		1857	.setup_asic = &trinity_dpm_setup_asic,
		1858	.enable = &trinity_dpm_enable,
		1859	.late_enable = &trinity_dpm_late_enable,
		1860	.disable = &trinity_dpm_disable,
		1861	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
		1862	.set_power_state = &trinity_dpm_set_power_state,
		1863	.post_set_power_state = &trinity_dpm_post_set_power_state,
		1864	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
		1865	.fini = &trinity_dpm_fini,
		1866	.get_sclk = &trinity_dpm_get_sclk,
		1867	.get_mclk = &trinity_dpm_get_mclk,
		1868	.print_power_state = &trinity_dpm_print_power_state,
		1869	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
		1870	.force_performance_level = &trinity_dpm_force_performance_level,
		1871	.enable_bapm = &trinity_dpm_enable_bapm,
6104	serge	1872	.get_current_sclk = &trinity_dpm_get_current_sclk,
		1873	.get_current_mclk = &trinity_dpm_get_current_mclk,
5078	serge	1874	},
2997	Serge	1875	.pflip = {
		1876	// .pre_page_flip = &evergreen_pre_page_flip,
		1877	// .page_flip = &evergreen_page_flip,
		1878	},
		1879	};
		1880
6938	serge	1881	static const struct radeon_asic_ring si_gfx_ring = {
5078	serge	1882	.ib_execute = &si_ring_ib_execute,
		1883	.ib_parse = &si_ib_parse,
		1884	.emit_fence = &si_fence_ring_emit,
		1885	.emit_semaphore = &r600_semaphore_ring_emit,
		1886	.cs_parse = NULL,
		1887	.ring_test = &r600_ring_test,
		1888	.ib_test = &r600_ib_test,
		1889	.is_lockup = &si_gfx_is_lockup,
		1890	.vm_flush = &si_vm_flush,
		1891	.get_rptr = &cayman_gfx_get_rptr,
		1892	.get_wptr = &cayman_gfx_get_wptr,
		1893	.set_wptr = &cayman_gfx_set_wptr,
		1894	};
		1895
6938	serge	1896	static const struct radeon_asic_ring si_dma_ring = {
5078	serge	1897	.ib_execute = &cayman_dma_ring_ib_execute,
		1898	.ib_parse = &evergreen_dma_ib_parse,
		1899	.emit_fence = &evergreen_dma_fence_ring_emit,
		1900	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1901	.cs_parse = NULL,
		1902	.ring_test = &r600_dma_ring_test,
		1903	.ib_test = &r600_dma_ib_test,
		1904	.is_lockup = &si_dma_is_lockup,
		1905	.vm_flush = &si_dma_vm_flush,
		1906	.get_rptr = &cayman_dma_get_rptr,
		1907	.get_wptr = &cayman_dma_get_wptr,
		1908	.set_wptr = &cayman_dma_set_wptr,
		1909	};
		1910
2997	Serge	1911	static struct radeon_asic si_asic = {
		1912	.init = &si_init,
6104	serge	1913	.fini = &si_fini,
2997	Serge	1914	// .suspend = &si_suspend,
6104	serge	1915	.resume = &si_resume,
2997	Serge	1916	.asic_reset = &si_asic_reset,
		1917	// .vga_set_state = &r600_vga_set_state,
5078	serge	1918	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1919	.gui_idle = &r600_gui_idle,
		1920	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1921	.get_xclk = &si_get_xclk,
		1922	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
6104	serge	1923	.get_allowed_info_register = si_get_allowed_info_register,
2997	Serge	1924	.gart = {
		1925	.tlb_flush = &si_pcie_gart_tlb_flush,
6104	serge	1926	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1927	.set_page = &rs600_gart_set_page,
		1928	},
		1929	.vm = {
		1930	.init = &si_vm_init,
		1931	.fini = &si_vm_fini,
5078	serge	1932	.copy_pages = &si_dma_vm_copy_pages,
		1933	.write_pages = &si_dma_vm_write_pages,
		1934	.set_pages = &si_dma_vm_set_pages,
		1935	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1936	},
		1937	.ring = {
5078	serge	1938	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
		1939	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
		1940	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
		1941	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
		1942	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
		1943	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
6104	serge	1944	[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		1945	[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
2997	Serge	1946	},
		1947	.irq = {
		1948	.set = &si_irq_set,
		1949	.process = &si_irq_process,
		1950	},
		1951	.display = {
		1952	.bandwidth_update = &dce6_bandwidth_update,
		1953	.get_vblank_counter = &evergreen_get_vblank_counter,
		1954	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1955	.set_backlight_level = &atombios_set_backlight_level,
		1956	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1957	},
		1958	.copy = {
5078	serge	1959	.blit = &r600_copy_cpdma,
2997	Serge	1960	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1961	.dma = &si_copy_dma,
		1962	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1963	.copy = &si_copy_dma,
		1964	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1965	},
		1966	.surface = {
		1967	.set_reg = r600_set_surface_reg,
		1968	.clear_reg = r600_clear_surface_reg,
		1969	},
		1970	.hpd = {
		1971	.init = &evergreen_hpd_init,
		1972	.fini = &evergreen_hpd_fini,
		1973	.sense = &evergreen_hpd_sense,
		1974	.set_polarity = &evergreen_hpd_set_polarity,
		1975	},
		1976	.pm = {
5078	serge	1977	.misc = &evergreen_pm_misc,
		1978	.prepare = &evergreen_pm_prepare,
		1979	.finish = &evergreen_pm_finish,
		1980	.init_profile = &sumo_pm_init_profile,
		1981	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1982	.get_engine_clock = &radeon_atom_get_engine_clock,
		1983	.set_engine_clock = &radeon_atom_set_engine_clock,
		1984	.get_memory_clock = &radeon_atom_get_memory_clock,
		1985	.set_memory_clock = &radeon_atom_set_memory_clock,
		1986	.get_pcie_lanes = &r600_get_pcie_lanes,
		1987	.set_pcie_lanes = &r600_set_pcie_lanes,
		1988	.set_clock_gating = NULL,
		1989	.set_uvd_clocks = &si_set_uvd_clocks,
6104	serge	1990	.set_vce_clocks = &si_set_vce_clocks,
5078	serge	1991	.get_temperature = &si_get_temp,
		1992	},
		1993	.dpm = {
		1994	.init = &si_dpm_init,
		1995	.setup_asic = &si_dpm_setup_asic,
		1996	.enable = &si_dpm_enable,
		1997	.late_enable = &si_dpm_late_enable,
		1998	.disable = &si_dpm_disable,
		1999	.pre_set_power_state = &si_dpm_pre_set_power_state,
		2000	.set_power_state = &si_dpm_set_power_state,
		2001	.post_set_power_state = &si_dpm_post_set_power_state,
		2002	.display_configuration_changed = &si_dpm_display_configuration_changed,
		2003	.fini = &si_dpm_fini,
		2004	.get_sclk = &ni_dpm_get_sclk,
		2005	.get_mclk = &ni_dpm_get_mclk,
		2006	.print_power_state = &ni_dpm_print_power_state,
		2007	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
		2008	.force_performance_level = &si_dpm_force_performance_level,
		2009	.vblank_too_short = &ni_dpm_vblank_too_short,
6104	serge	2010	.fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
		2011	.fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
		2012	.get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
		2013	.set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
		2014	.get_current_sclk = &si_dpm_get_current_sclk,
		2015	.get_current_mclk = &si_dpm_get_current_mclk,
5078	serge	2016	},
		2017	.pflip = {
		2018	// .pre_page_flip = &evergreen_pre_page_flip,
		2019	// .page_flip = &evergreen_page_flip,
		2020	},
		2021	};
		2022
6938	serge	2023	static const struct radeon_asic_ring ci_gfx_ring = {
5078	serge	2024	.ib_execute = &cik_ring_ib_execute,
		2025	.ib_parse = &cik_ib_parse,
		2026	.emit_fence = &cik_fence_gfx_ring_emit,
		2027	.emit_semaphore = &cik_semaphore_ring_emit,
		2028	.cs_parse = NULL,
		2029	.ring_test = &cik_ring_test,
		2030	.ib_test = &cik_ib_test,
		2031	.is_lockup = &cik_gfx_is_lockup,
		2032	.vm_flush = &cik_vm_flush,
		2033	.get_rptr = &cik_gfx_get_rptr,
		2034	.get_wptr = &cik_gfx_get_wptr,
		2035	.set_wptr = &cik_gfx_set_wptr,
		2036	};
		2037
6938	serge	2038	static const struct radeon_asic_ring ci_cp_ring = {
5078	serge	2039	.ib_execute = &cik_ring_ib_execute,
		2040	.ib_parse = &cik_ib_parse,
		2041	.emit_fence = &cik_fence_compute_ring_emit,
		2042	.emit_semaphore = &cik_semaphore_ring_emit,
		2043	.cs_parse = NULL,
		2044	.ring_test = &cik_ring_test,
		2045	.ib_test = &cik_ib_test,
		2046	.is_lockup = &cik_gfx_is_lockup,
		2047	.vm_flush = &cik_vm_flush,
		2048	.get_rptr = &cik_compute_get_rptr,
		2049	.get_wptr = &cik_compute_get_wptr,
		2050	.set_wptr = &cik_compute_set_wptr,
		2051	};
		2052
6938	serge	2053	static const struct radeon_asic_ring ci_dma_ring = {
5078	serge	2054	.ib_execute = &cik_sdma_ring_ib_execute,
		2055	.ib_parse = &cik_ib_parse,
		2056	.emit_fence = &cik_sdma_fence_ring_emit,
		2057	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
		2058	.cs_parse = NULL,
		2059	.ring_test = &cik_sdma_ring_test,
		2060	.ib_test = &cik_sdma_ib_test,
		2061	.is_lockup = &cik_sdma_is_lockup,
		2062	.vm_flush = &cik_dma_vm_flush,
		2063	.get_rptr = &cik_sdma_get_rptr,
		2064	.get_wptr = &cik_sdma_get_wptr,
		2065	.set_wptr = &cik_sdma_set_wptr,
		2066	};
		2067
6938	serge	2068	static const struct radeon_asic_ring ci_vce_ring = {
5078	serge	2069	.ib_execute = &radeon_vce_ib_execute,
		2070	.emit_fence = &radeon_vce_fence_emit,
		2071	.emit_semaphore = &radeon_vce_semaphore_emit,
		2072	.cs_parse = &radeon_vce_cs_parse,
		2073	.ring_test = &radeon_vce_ring_test,
		2074	.ib_test = &radeon_vce_ib_test,
		2075	.is_lockup = &radeon_ring_test_lockup,
		2076	.get_rptr = &vce_v1_0_get_rptr,
		2077	.get_wptr = &vce_v1_0_get_wptr,
		2078	.set_wptr = &vce_v1_0_set_wptr,
		2079	};
		2080
		2081	static struct radeon_asic ci_asic = {
		2082	.init = &cik_init,
6104	serge	2083	.fini = &cik_fini,
		2084	// .suspend = &cik_suspend,
		2085	// .resume = &cik_resume,
5078	serge	2086	.asic_reset = &cik_asic_reset,
		2087	// .vga_set_state = &r600_vga_set_state,
		2088	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2089	.gui_idle = &r600_gui_idle,
		2090	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2091	.get_xclk = &cik_get_xclk,
		2092	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
6104	serge	2093	.get_allowed_info_register = cik_get_allowed_info_register,
5078	serge	2094	.gart = {
		2095	.tlb_flush = &cik_pcie_gart_tlb_flush,
6104	serge	2096	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	2097	.set_page = &rs600_gart_set_page,
		2098	},
		2099	.vm = {
		2100	.init = &cik_vm_init,
		2101	.fini = &cik_vm_fini,
		2102	.copy_pages = &cik_sdma_vm_copy_pages,
		2103	.write_pages = &cik_sdma_vm_write_pages,
		2104	.set_pages = &cik_sdma_vm_set_pages,
		2105	.pad_ib = &cik_sdma_vm_pad_ib,
		2106	},
		2107	.ring = {
		2108	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2109	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2110	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2111	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2112	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2113	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2114	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2115	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2116	},
		2117	.irq = {
		2118	.set = &cik_irq_set,
		2119	.process = &cik_irq_process,
		2120	},
		2121	.display = {
		2122	.bandwidth_update = &dce8_bandwidth_update,
		2123	.get_vblank_counter = &evergreen_get_vblank_counter,
		2124	.wait_for_vblank = &dce4_wait_for_vblank,
		2125	.set_backlight_level = &atombios_set_backlight_level,
		2126	.get_backlight_level = &atombios_get_backlight_level,
		2127	},
		2128	.copy = {
		2129	.blit = &cik_copy_cpdma,
		2130	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2131	.dma = &cik_copy_dma,
		2132	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2133	.copy = &cik_copy_dma,
		2134	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2135	},
		2136	.surface = {
		2137	.set_reg = r600_set_surface_reg,
		2138	.clear_reg = r600_clear_surface_reg,
		2139	},
		2140	.hpd = {
		2141	.init = &evergreen_hpd_init,
		2142	.fini = &evergreen_hpd_fini,
		2143	.sense = &evergreen_hpd_sense,
		2144	.set_polarity = &evergreen_hpd_set_polarity,
		2145	},
		2146	.pm = {
		2147	.misc = &evergreen_pm_misc,
		2148	.prepare = &evergreen_pm_prepare,
		2149	.finish = &evergreen_pm_finish,
		2150	.init_profile = &sumo_pm_init_profile,
		2151	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2152	.get_engine_clock = &radeon_atom_get_engine_clock,
		2153	.set_engine_clock = &radeon_atom_set_engine_clock,
		2154	.get_memory_clock = &radeon_atom_get_memory_clock,
		2155	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	2156	.get_pcie_lanes = NULL,
		2157	.set_pcie_lanes = NULL,
		2158	.set_clock_gating = NULL,
5078	serge	2159	.set_uvd_clocks = &cik_set_uvd_clocks,
		2160	.set_vce_clocks = &cik_set_vce_clocks,
		2161	.get_temperature = &ci_get_temp,
2997	Serge	2162	},
5078	serge	2163	.dpm = {
		2164	.init = &ci_dpm_init,
		2165	.setup_asic = &ci_dpm_setup_asic,
		2166	.enable = &ci_dpm_enable,
		2167	.late_enable = &ci_dpm_late_enable,
		2168	.disable = &ci_dpm_disable,
		2169	.pre_set_power_state = &ci_dpm_pre_set_power_state,
		2170	.set_power_state = &ci_dpm_set_power_state,
		2171	.post_set_power_state = &ci_dpm_post_set_power_state,
		2172	.display_configuration_changed = &ci_dpm_display_configuration_changed,
		2173	.fini = &ci_dpm_fini,
		2174	.get_sclk = &ci_dpm_get_sclk,
		2175	.get_mclk = &ci_dpm_get_mclk,
		2176	.print_power_state = &ci_dpm_print_power_state,
		2177	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
		2178	.force_performance_level = &ci_dpm_force_performance_level,
		2179	.vblank_too_short = &ci_dpm_vblank_too_short,
		2180	.powergate_uvd = &ci_dpm_powergate_uvd,
6104	serge	2181	.fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
		2182	.fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
		2183	.get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
		2184	.set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
		2185	.get_current_sclk = &ci_dpm_get_current_sclk,
		2186	.get_current_mclk = &ci_dpm_get_current_mclk,
5078	serge	2187	},
2997	Serge	2188	.pflip = {
		2189	// .pre_page_flip = &evergreen_pre_page_flip,
		2190	// .page_flip = &evergreen_page_flip,
		2191	},
		2192	};
		2193
5078	serge	2194	static struct radeon_asic kv_asic = {
		2195	.init = &cik_init,
6104	serge	2196	.fini = &cik_fini,
		2197	// .suspend = &cik_suspend,
		2198	// .resume = &cik_resume,
5078	serge	2199	.asic_reset = &cik_asic_reset,
		2200	// .vga_set_state = &r600_vga_set_state,
		2201	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2202	.gui_idle = &r600_gui_idle,
		2203	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2204	.get_xclk = &cik_get_xclk,
		2205	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
6104	serge	2206	.get_allowed_info_register = cik_get_allowed_info_register,
5078	serge	2207	.gart = {
		2208	.tlb_flush = &cik_pcie_gart_tlb_flush,
6104	serge	2209	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	2210	.set_page = &rs600_gart_set_page,
		2211	},
		2212	.vm = {
		2213	.init = &cik_vm_init,
		2214	.fini = &cik_vm_fini,
		2215	.copy_pages = &cik_sdma_vm_copy_pages,
		2216	.write_pages = &cik_sdma_vm_write_pages,
		2217	.set_pages = &cik_sdma_vm_set_pages,
		2218	.pad_ib = &cik_sdma_vm_pad_ib,
		2219	},
		2220	.ring = {
		2221	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2222	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2223	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2224	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2225	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2226	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2227	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2228	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2229	},
		2230	.irq = {
		2231	.set = &cik_irq_set,
		2232	.process = &cik_irq_process,
		2233	},
		2234	.display = {
		2235	.bandwidth_update = &dce8_bandwidth_update,
		2236	.get_vblank_counter = &evergreen_get_vblank_counter,
		2237	.wait_for_vblank = &dce4_wait_for_vblank,
		2238	.set_backlight_level = &atombios_set_backlight_level,
		2239	.get_backlight_level = &atombios_get_backlight_level,
		2240	},
		2241	.copy = {
		2242	.blit = &cik_copy_cpdma,
		2243	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2244	.dma = &cik_copy_dma,
		2245	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2246	.copy = &cik_copy_dma,
		2247	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2248	},
		2249	.surface = {
		2250	.set_reg = r600_set_surface_reg,
		2251	.clear_reg = r600_clear_surface_reg,
		2252	},
		2253	.hpd = {
		2254	.init = &evergreen_hpd_init,
		2255	.fini = &evergreen_hpd_fini,
		2256	.sense = &evergreen_hpd_sense,
		2257	.set_polarity = &evergreen_hpd_set_polarity,
		2258	},
		2259	.pm = {
		2260	.misc = &evergreen_pm_misc,
		2261	.prepare = &evergreen_pm_prepare,
		2262	.finish = &evergreen_pm_finish,
		2263	.init_profile = &sumo_pm_init_profile,
		2264	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2265	.get_engine_clock = &radeon_atom_get_engine_clock,
		2266	.set_engine_clock = &radeon_atom_set_engine_clock,
		2267	.get_memory_clock = &radeon_atom_get_memory_clock,
		2268	.set_memory_clock = &radeon_atom_set_memory_clock,
		2269	.get_pcie_lanes = NULL,
		2270	.set_pcie_lanes = NULL,
		2271	.set_clock_gating = NULL,
		2272	.set_uvd_clocks = &cik_set_uvd_clocks,
		2273	.set_vce_clocks = &cik_set_vce_clocks,
		2274	.get_temperature = &kv_get_temp,
		2275	},
		2276	.dpm = {
		2277	.init = &kv_dpm_init,
		2278	.setup_asic = &kv_dpm_setup_asic,
		2279	.enable = &kv_dpm_enable,
		2280	.late_enable = &kv_dpm_late_enable,
		2281	.disable = &kv_dpm_disable,
		2282	.pre_set_power_state = &kv_dpm_pre_set_power_state,
		2283	.set_power_state = &kv_dpm_set_power_state,
		2284	.post_set_power_state = &kv_dpm_post_set_power_state,
		2285	.display_configuration_changed = &kv_dpm_display_configuration_changed,
		2286	.fini = &kv_dpm_fini,
		2287	.get_sclk = &kv_dpm_get_sclk,
		2288	.get_mclk = &kv_dpm_get_mclk,
		2289	.print_power_state = &kv_dpm_print_power_state,
		2290	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
		2291	.force_performance_level = &kv_dpm_force_performance_level,
		2292	.powergate_uvd = &kv_dpm_powergate_uvd,
		2293	.enable_bapm = &kv_dpm_enable_bapm,
6104	serge	2294	.get_current_sclk = &kv_dpm_get_current_sclk,
		2295	.get_current_mclk = &kv_dpm_get_current_mclk,
5078	serge	2296	},
		2297	.pflip = {
		2298	// .pre_page_flip = &evergreen_pre_page_flip,
		2299	// .page_flip = &evergreen_page_flip,
		2300	},
		2301	};
		2302
2997	Serge	2303	/**
		2304	* radeon_asic_init - register asic specific callbacks
		2305	*
		2306	* @rdev: radeon device pointer
		2307	*
		2308	* Registers the appropriate asic specific callbacks for each
		2309	* chip family. Also sets other asics specific info like the number
		2310	* of crtcs and the register aperture accessors (all asics).
		2311	* Returns 0 for success.
		2312	*/
1963	serge	2313	int radeon_asic_init(struct radeon_device *rdev)
		2314	{
		2315	radeon_register_accessor_init(rdev);
1986	serge	2316
		2317	/* set the number of crtcs */
		2318	if (rdev->flags & RADEON_SINGLE_CRTC)
		2319	rdev->num_crtc = 1;
		2320	else
		2321	rdev->num_crtc = 2;
		2322
3764	Serge	2323	rdev->has_uvd = false;
		2324
1963	serge	2325	switch (rdev->family) {
		2326	case CHIP_R100:
		2327	case CHIP_RV100:
		2328	case CHIP_RS100:
		2329	case CHIP_RV200:
		2330	case CHIP_RS200:
		2331	rdev->asic = &r100_asic;
		2332	break;
		2333	case CHIP_R200:
		2334	case CHIP_RV250:
		2335	case CHIP_RS300:
		2336	case CHIP_RV280:
		2337	rdev->asic = &r200_asic;
		2338	break;
		2339	case CHIP_R300:
		2340	case CHIP_R350:
		2341	case CHIP_RV350:
		2342	case CHIP_RV380:
		2343	if (rdev->flags & RADEON_IS_PCIE)
		2344	rdev->asic = &r300_asic_pcie;
		2345	else
		2346	rdev->asic = &r300_asic;
		2347	break;
		2348	case CHIP_R420:
		2349	case CHIP_R423:
		2350	case CHIP_RV410:
		2351	rdev->asic = &r420_asic;
		2352	/* handle macs */
		2353	if (rdev->bios == NULL) {
2997	Serge	2354	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
		2355	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
		2356	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
		2357	rdev->asic->pm.set_memory_clock = NULL;
		2358	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1963	serge	2359	}
		2360	break;
		2361	case CHIP_RS400:
		2362	case CHIP_RS480:
		2363	rdev->asic = &rs400_asic;
		2364	break;
		2365	case CHIP_RS600:
		2366	rdev->asic = &rs600_asic;
		2367	break;
		2368	case CHIP_RS690:
		2369	case CHIP_RS740:
		2370	rdev->asic = &rs690_asic;
		2371	break;
		2372	case CHIP_RV515:
		2373	rdev->asic = &rv515_asic;
		2374	break;
		2375	case CHIP_R520:
		2376	case CHIP_RV530:
		2377	case CHIP_RV560:
		2378	case CHIP_RV570:
		2379	case CHIP_R580:
		2380	rdev->asic = &r520_asic;
		2381	break;
		2382	case CHIP_R600:
5078	serge	2383	rdev->asic = &r600_asic;
		2384	break;
1963	serge	2385	case CHIP_RV610:
		2386	case CHIP_RV630:
		2387	case CHIP_RV620:
		2388	case CHIP_RV635:
		2389	case CHIP_RV670:
5078	serge	2390	rdev->asic = &rv6xx_asic;
6104	serge	2391	rdev->has_uvd = true;
1963	serge	2392	break;
		2393	case CHIP_RS780:
		2394	case CHIP_RS880:
		2395	rdev->asic = &rs780_asic;
5271	serge	2396	/* 760G/780V/880V don't have UVD */
		2397	if ((rdev->pdev->device == 0x9616)\|\|
		2398	(rdev->pdev->device == 0x9611)\|\|
		2399	(rdev->pdev->device == 0x9613)\|\|
		2400	(rdev->pdev->device == 0x9711)\|\|
		2401	(rdev->pdev->device == 0x9713))
		2402	rdev->has_uvd = false;
		2403	else
6104	serge	2404	rdev->has_uvd = true;
1963	serge	2405	break;
		2406	case CHIP_RV770:
		2407	case CHIP_RV730:
		2408	case CHIP_RV710:
		2409	case CHIP_RV740:
		2410	rdev->asic = &rv770_asic;
3764	Serge	2411	rdev->has_uvd = true;
1963	serge	2412	break;
1986	serge	2413	case CHIP_CEDAR:
		2414	case CHIP_REDWOOD:
		2415	case CHIP_JUNIPER:
		2416	case CHIP_CYPRESS:
		2417	case CHIP_HEMLOCK:
		2418	/* set num crtcs */
		2419	if (rdev->family == CHIP_CEDAR)
		2420	rdev->num_crtc = 4;
		2421	else
		2422	rdev->num_crtc = 6;
		2423	rdev->asic = &evergreen_asic;
3764	Serge	2424	rdev->has_uvd = true;
1986	serge	2425	break;
1990	serge	2426	case CHIP_PALM:
		2427	case CHIP_SUMO:
		2428	case CHIP_SUMO2:
		2429	rdev->asic = &sumo_asic;
3764	Serge	2430	rdev->has_uvd = true;
1990	serge	2431	break;
		2432	case CHIP_BARTS:
		2433	case CHIP_TURKS:
		2434	case CHIP_CAICOS:
		2435	/* set num crtcs */
		2436	if (rdev->family == CHIP_CAICOS)
		2437	rdev->num_crtc = 4;
		2438	else
		2439	rdev->num_crtc = 6;
		2440	rdev->asic = &btc_asic;
3764	Serge	2441	rdev->has_uvd = true;
1990	serge	2442	break;
2004	serge	2443	case CHIP_CAYMAN:
		2444	rdev->asic = &cayman_asic;
		2445	/* set num crtcs */
		2446	rdev->num_crtc = 6;
3764	Serge	2447	rdev->has_uvd = true;
2004	serge	2448	break;
2997	Serge	2449	case CHIP_ARUBA:
		2450	rdev->asic = &trinity_asic;
		2451	/* set num crtcs */
		2452	rdev->num_crtc = 4;
3764	Serge	2453	rdev->has_uvd = true;
6104	serge	2454	rdev->cg_flags =
		2455	RADEON_CG_SUPPORT_VCE_MGCG;
2997	Serge	2456	break;
		2457	case CHIP_TAHITI:
		2458	case CHIP_PITCAIRN:
		2459	case CHIP_VERDE:
3764	Serge	2460	case CHIP_OLAND:
		2461	case CHIP_HAINAN:
2997	Serge	2462	rdev->asic = &si_asic;
		2463	/* set num crtcs */
3764	Serge	2464	if (rdev->family == CHIP_HAINAN)
		2465	rdev->num_crtc = 0;
		2466	else if (rdev->family == CHIP_OLAND)
		2467	rdev->num_crtc = 2;
		2468	else
6104	serge	2469	rdev->num_crtc = 6;
3764	Serge	2470	if (rdev->family == CHIP_HAINAN)
		2471	rdev->has_uvd = false;
		2472	else
		2473	rdev->has_uvd = true;
5078	serge	2474	switch (rdev->family) {
		2475	case CHIP_TAHITI:
		2476	rdev->cg_flags =
		2477	RADEON_CG_SUPPORT_GFX_MGCG \|
		2478	RADEON_CG_SUPPORT_GFX_MGLS \|
		2479	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2480	RADEON_CG_SUPPORT_GFX_CGLS \|
		2481	RADEON_CG_SUPPORT_GFX_CGTS \|
		2482	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2483	RADEON_CG_SUPPORT_MC_MGCG \|
		2484	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2485	RADEON_CG_SUPPORT_BIF_LS \|
		2486	RADEON_CG_SUPPORT_VCE_MGCG \|
		2487	RADEON_CG_SUPPORT_UVD_MGCG \|
		2488	RADEON_CG_SUPPORT_HDP_LS \|
		2489	RADEON_CG_SUPPORT_HDP_MGCG;
		2490	rdev->pg_flags = 0;
		2491	break;
		2492	case CHIP_PITCAIRN:
		2493	rdev->cg_flags =
		2494	RADEON_CG_SUPPORT_GFX_MGCG \|
		2495	RADEON_CG_SUPPORT_GFX_MGLS \|
		2496	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2497	RADEON_CG_SUPPORT_GFX_CGLS \|
		2498	RADEON_CG_SUPPORT_GFX_CGTS \|
		2499	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2500	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2501	RADEON_CG_SUPPORT_MC_LS \|
		2502	RADEON_CG_SUPPORT_MC_MGCG \|
		2503	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2504	RADEON_CG_SUPPORT_BIF_LS \|
		2505	RADEON_CG_SUPPORT_VCE_MGCG \|
		2506	RADEON_CG_SUPPORT_UVD_MGCG \|
		2507	RADEON_CG_SUPPORT_HDP_LS \|
		2508	RADEON_CG_SUPPORT_HDP_MGCG;
		2509	rdev->pg_flags = 0;
		2510	break;
		2511	case CHIP_VERDE:
		2512	rdev->cg_flags =
		2513	RADEON_CG_SUPPORT_GFX_MGCG \|
		2514	RADEON_CG_SUPPORT_GFX_MGLS \|
		2515	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2516	RADEON_CG_SUPPORT_GFX_CGLS \|
		2517	RADEON_CG_SUPPORT_GFX_CGTS \|
		2518	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2519	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2520	RADEON_CG_SUPPORT_MC_LS \|
		2521	RADEON_CG_SUPPORT_MC_MGCG \|
		2522	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2523	RADEON_CG_SUPPORT_BIF_LS \|
		2524	RADEON_CG_SUPPORT_VCE_MGCG \|
		2525	RADEON_CG_SUPPORT_UVD_MGCG \|
		2526	RADEON_CG_SUPPORT_HDP_LS \|
		2527	RADEON_CG_SUPPORT_HDP_MGCG;
		2528	rdev->pg_flags = 0 \|
		2529	/RADEON_PG_SUPPORT_GFX_PG \| /
		2530	RADEON_PG_SUPPORT_SDMA;
		2531	break;
		2532	case CHIP_OLAND:
		2533	rdev->cg_flags =
		2534	RADEON_CG_SUPPORT_GFX_MGCG \|
		2535	RADEON_CG_SUPPORT_GFX_MGLS \|
		2536	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2537	RADEON_CG_SUPPORT_GFX_CGLS \|
		2538	RADEON_CG_SUPPORT_GFX_CGTS \|
		2539	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2540	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2541	RADEON_CG_SUPPORT_MC_LS \|
		2542	RADEON_CG_SUPPORT_MC_MGCG \|
		2543	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2544	RADEON_CG_SUPPORT_BIF_LS \|
		2545	RADEON_CG_SUPPORT_UVD_MGCG \|
		2546	RADEON_CG_SUPPORT_HDP_LS \|
		2547	RADEON_CG_SUPPORT_HDP_MGCG;
		2548	rdev->pg_flags = 0;
		2549	break;
		2550	case CHIP_HAINAN:
		2551	rdev->cg_flags =
		2552	RADEON_CG_SUPPORT_GFX_MGCG \|
		2553	RADEON_CG_SUPPORT_GFX_MGLS \|
		2554	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2555	RADEON_CG_SUPPORT_GFX_CGLS \|
		2556	RADEON_CG_SUPPORT_GFX_CGTS \|
		2557	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2558	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2559	RADEON_CG_SUPPORT_MC_LS \|
		2560	RADEON_CG_SUPPORT_MC_MGCG \|
		2561	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2562	RADEON_CG_SUPPORT_BIF_LS \|
		2563	RADEON_CG_SUPPORT_HDP_LS \|
		2564	RADEON_CG_SUPPORT_HDP_MGCG;
		2565	rdev->pg_flags = 0;
		2566	break;
		2567	default:
		2568	rdev->cg_flags = 0;
		2569	rdev->pg_flags = 0;
		2570	break;
		2571	}
2997	Serge	2572	break;
5078	serge	2573	case CHIP_BONAIRE:
		2574	case CHIP_HAWAII:
		2575	rdev->asic = &ci_asic;
		2576	rdev->num_crtc = 6;
		2577	rdev->has_uvd = true;
		2578	if (rdev->family == CHIP_BONAIRE) {
		2579	rdev->cg_flags =
		2580	RADEON_CG_SUPPORT_GFX_MGCG \|
		2581	RADEON_CG_SUPPORT_GFX_MGLS \|
		2582	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2583	RADEON_CG_SUPPORT_GFX_CGLS \|
		2584	RADEON_CG_SUPPORT_GFX_CGTS \|
		2585	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2586	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2587	RADEON_CG_SUPPORT_MC_LS \|
		2588	RADEON_CG_SUPPORT_MC_MGCG \|
		2589	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2590	RADEON_CG_SUPPORT_SDMA_LS \|
		2591	RADEON_CG_SUPPORT_BIF_LS \|
		2592	RADEON_CG_SUPPORT_VCE_MGCG \|
		2593	RADEON_CG_SUPPORT_UVD_MGCG \|
		2594	RADEON_CG_SUPPORT_HDP_LS \|
		2595	RADEON_CG_SUPPORT_HDP_MGCG;
		2596	rdev->pg_flags = 0;
		2597	} else {
		2598	rdev->cg_flags =
		2599	RADEON_CG_SUPPORT_GFX_MGCG \|
		2600	RADEON_CG_SUPPORT_GFX_MGLS \|
		2601	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2602	RADEON_CG_SUPPORT_GFX_CGLS \|
		2603	RADEON_CG_SUPPORT_GFX_CGTS \|
		2604	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2605	RADEON_CG_SUPPORT_MC_LS \|
		2606	RADEON_CG_SUPPORT_MC_MGCG \|
		2607	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2608	RADEON_CG_SUPPORT_SDMA_LS \|
		2609	RADEON_CG_SUPPORT_BIF_LS \|
		2610	RADEON_CG_SUPPORT_VCE_MGCG \|
		2611	RADEON_CG_SUPPORT_UVD_MGCG \|
		2612	RADEON_CG_SUPPORT_HDP_LS \|
		2613	RADEON_CG_SUPPORT_HDP_MGCG;
		2614	rdev->pg_flags = 0;
		2615	}
		2616	break;
		2617	case CHIP_KAVERI:
		2618	case CHIP_KABINI:
		2619	case CHIP_MULLINS:
		2620	rdev->asic = &kv_asic;
		2621	/* set num crtcs */
		2622	if (rdev->family == CHIP_KAVERI) {
		2623	rdev->num_crtc = 4;
		2624	rdev->cg_flags =
		2625	RADEON_CG_SUPPORT_GFX_MGCG \|
		2626	RADEON_CG_SUPPORT_GFX_MGLS \|
		2627	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2628	RADEON_CG_SUPPORT_GFX_CGLS \|
		2629	RADEON_CG_SUPPORT_GFX_CGTS \|
		2630	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2631	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2632	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2633	RADEON_CG_SUPPORT_SDMA_LS \|
		2634	RADEON_CG_SUPPORT_BIF_LS \|
		2635	RADEON_CG_SUPPORT_VCE_MGCG \|
		2636	RADEON_CG_SUPPORT_UVD_MGCG \|
		2637	RADEON_CG_SUPPORT_HDP_LS \|
		2638	RADEON_CG_SUPPORT_HDP_MGCG;
		2639	rdev->pg_flags = 0;
		2640	/*RADEON_PG_SUPPORT_GFX_PG \|
		2641	RADEON_PG_SUPPORT_GFX_SMG \|
		2642	RADEON_PG_SUPPORT_GFX_DMG \|
		2643	RADEON_PG_SUPPORT_UVD \|
		2644	RADEON_PG_SUPPORT_VCE \|
		2645	RADEON_PG_SUPPORT_CP \|
		2646	RADEON_PG_SUPPORT_GDS \|
		2647	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2648	RADEON_PG_SUPPORT_ACP \|
		2649	RADEON_PG_SUPPORT_SAMU;*/
		2650	} else {
		2651	rdev->num_crtc = 2;
		2652	rdev->cg_flags =
		2653	RADEON_CG_SUPPORT_GFX_MGCG \|
		2654	RADEON_CG_SUPPORT_GFX_MGLS \|
		2655	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2656	RADEON_CG_SUPPORT_GFX_CGLS \|
		2657	RADEON_CG_SUPPORT_GFX_CGTS \|
		2658	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2659	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2660	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2661	RADEON_CG_SUPPORT_SDMA_LS \|
		2662	RADEON_CG_SUPPORT_BIF_LS \|
		2663	RADEON_CG_SUPPORT_VCE_MGCG \|
		2664	RADEON_CG_SUPPORT_UVD_MGCG \|
		2665	RADEON_CG_SUPPORT_HDP_LS \|
		2666	RADEON_CG_SUPPORT_HDP_MGCG;
		2667	rdev->pg_flags = 0;
		2668	/*RADEON_PG_SUPPORT_GFX_PG \|
		2669	RADEON_PG_SUPPORT_GFX_SMG \|
		2670	RADEON_PG_SUPPORT_UVD \|
		2671	RADEON_PG_SUPPORT_VCE \|
		2672	RADEON_PG_SUPPORT_CP \|
		2673	RADEON_PG_SUPPORT_GDS \|
		2674	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2675	RADEON_PG_SUPPORT_SAMU;*/
		2676	}
		2677	rdev->has_uvd = true;
		2678	break;
1963	serge	2679	default:
		2680	/* FIXME: not supported yet */
		2681	return -EINVAL;
		2682	}
		2683
		2684	if (rdev->flags & RADEON_IS_IGP) {
2997	Serge	2685	rdev->asic->pm.get_memory_clock = NULL;
		2686	rdev->asic->pm.set_memory_clock = NULL;
1963	serge	2687	}
		2688
		2689	return 0;
		2690	}
		2691

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 6938