WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
6104	serge	33	#include
1963	serge	34	#include "radeon_reg.h"
		35	#include "radeon.h"
		36	#include "radeon_asic.h"
		37	#include "atom.h"
		38
		39	/*
		40	* Registers accessors functions.
		41	*/
2997	Serge	42	/**
		43	* radeon_invalid_rreg - dummy reg read function
		44	*
		45	* @rdev: radeon device pointer
		46	* @reg: offset of register
		47	*
		48	* Dummy register read function. Used for register blocks
		49	* that certain asics don't have (all asics).
		50	* Returns the value in the register.
		51	*/
1963	serge	52	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		53	{
		54	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		55	BUG_ON(1);
		56	return 0;
		57	}
		58
2997	Serge	59	/**
		60	* radeon_invalid_wreg - dummy reg write function
		61	*
		62	* @rdev: radeon device pointer
		63	* @reg: offset of register
		64	* @v: value to write to the register
		65	*
		66	* Dummy register read function. Used for register blocks
		67	* that certain asics don't have (all asics).
		68	*/
1963	serge	69	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		70	{
		71	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		72	reg, v);
		73	BUG_ON(1);
		74	}
		75
2997	Serge	76	/**
		77	* radeon_register_accessor_init - sets up the register accessor callbacks
		78	*
		79	* @rdev: radeon device pointer
		80	*
		81	* Sets up the register accessor callbacks for various register
		82	* apertures. Not all asics have all apertures (all asics).
		83	*/
1963	serge	84	static void radeon_register_accessor_init(struct radeon_device *rdev)
		85	{
		86	rdev->mc_rreg = &radeon_invalid_rreg;
		87	rdev->mc_wreg = &radeon_invalid_wreg;
		88	rdev->pll_rreg = &radeon_invalid_rreg;
		89	rdev->pll_wreg = &radeon_invalid_wreg;
		90	rdev->pciep_rreg = &radeon_invalid_rreg;
		91	rdev->pciep_wreg = &radeon_invalid_wreg;
		92
		93	/* Don't change order as we are overridding accessor. */
		94	if (rdev->family < CHIP_RV515) {
		95	rdev->pcie_reg_mask = 0xff;
		96	} else {
		97	rdev->pcie_reg_mask = 0x7ff;
		98	}
		99	/* FIXME: not sure here */
		100	if (rdev->family <= CHIP_R580) {
		101	rdev->pll_rreg = &r100_pll_rreg;
		102	rdev->pll_wreg = &r100_pll_wreg;
		103	}
		104	if (rdev->family >= CHIP_R420) {
		105	rdev->mc_rreg = &r420_mc_rreg;
		106	rdev->mc_wreg = &r420_mc_wreg;
		107	}
		108	if (rdev->family >= CHIP_RV515) {
		109	rdev->mc_rreg = &rv515_mc_rreg;
		110	rdev->mc_wreg = &rv515_mc_wreg;
		111	}
		112	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		113	rdev->mc_rreg = &rs400_mc_rreg;
		114	rdev->mc_wreg = &rs400_mc_wreg;
		115	}
		116	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		117	rdev->mc_rreg = &rs690_mc_rreg;
		118	rdev->mc_wreg = &rs690_mc_wreg;
		119	}
		120	if (rdev->family == CHIP_RS600) {
		121	rdev->mc_rreg = &rs600_mc_rreg;
		122	rdev->mc_wreg = &rs600_mc_wreg;
		123	}
3764	Serge	124	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
		125	rdev->mc_rreg = &rs780_mc_rreg;
		126	rdev->mc_wreg = &rs780_mc_wreg;
		127	}
5078	serge	128
		129	if (rdev->family >= CHIP_BONAIRE) {
		130	rdev->pciep_rreg = &cik_pciep_rreg;
		131	rdev->pciep_wreg = &cik_pciep_wreg;
		132	} else if (rdev->family >= CHIP_R600) {
1963	serge	133	rdev->pciep_rreg = &r600_pciep_rreg;
		134	rdev->pciep_wreg = &r600_pciep_wreg;
		135	}
		136	}
		137
6104	serge	138	static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
		139	u32 reg, u32 *val)
		140	{
		141	return -EINVAL;
		142	}
1963	serge	143
		144	/* helper to disable agp */
2997	Serge	145	/**
		146	* radeon_agp_disable - AGP disable helper function
		147	*
		148	* @rdev: radeon device pointer
		149	*
		150	* Removes AGP flags and changes the gart callbacks on AGP
		151	* cards when using the internal gart rather than AGP (all asics).
		152	*/
1963	serge	153	void radeon_agp_disable(struct radeon_device *rdev)
		154	{
		155	rdev->flags &= ~RADEON_IS_AGP;
		156	if (rdev->family >= CHIP_R600) {
		157	DRM_INFO("Forcing AGP to PCIE mode\n");
		158	rdev->flags \|= RADEON_IS_PCIE;
		159	} else if (rdev->family >= CHIP_RV515 \|\|
		160	rdev->family == CHIP_RV380 \|\|
		161	rdev->family == CHIP_RV410 \|\|
		162	rdev->family == CHIP_R423) {
		163	DRM_INFO("Forcing AGP to PCIE mode\n");
		164	rdev->flags \|= RADEON_IS_PCIE;
2997	Serge	165	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
6104	serge	166	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
2997	Serge	167	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1963	serge	168	} else {
		169	DRM_INFO("Forcing AGP to PCI mode\n");
		170	rdev->flags \|= RADEON_IS_PCI;
2997	Serge	171	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
6104	serge	172	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
2997	Serge	173	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1963	serge	174	}
		175	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		176	}
		177
		178	/*
		179	* ASIC
		180	*/
5078	serge	181
		182	static struct radeon_asic_ring r100_gfx_ring = {
		183	.ib_execute = &r100_ring_ib_execute,
		184	.emit_fence = &r100_fence_ring_emit,
		185	.emit_semaphore = &r100_semaphore_ring_emit,
		186	.cs_parse = &r100_cs_parse,
		187	.ring_start = &r100_ring_start,
		188	.ring_test = &r100_ring_test,
		189	.ib_test = &r100_ib_test,
		190	.is_lockup = &r100_gpu_is_lockup,
		191	.get_rptr = &r100_gfx_get_rptr,
		192	.get_wptr = &r100_gfx_get_wptr,
		193	.set_wptr = &r100_gfx_set_wptr,
		194	};
		195
1963	serge	196	static struct radeon_asic r100_asic = {
		197	.init = &r100_init,
6104	serge	198	.fini = &r100_fini,
1963	serge	199	// .suspend = &r100_suspend,
		200	// .resume = &r100_resume,
		201	// .vga_set_state = &r100_vga_set_state,
		202	.asic_reset = &r100_asic_reset,
5078	serge	203	.mmio_hdp_flush = NULL,
2997	Serge	204	.gui_idle = &r100_gui_idle,
		205	.mc_wait_for_idle = &r100_mc_wait_for_idle,
6104	serge	206	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	207	.gart = {
		208	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	209	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	210	.set_page = &r100_pci_gart_set_page,
		211	},
		212	.ring = {
5078	serge	213	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	214	},
		215	.irq = {
		216	.set = &r100_irq_set,
		217	.process = &r100_irq_process,
		218	},
		219	.display = {
		220	.bandwidth_update = &r100_bandwidth_update,
		221	.get_vblank_counter = &r100_get_vblank_counter,
		222	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	223	.set_backlight_level = &radeon_legacy_set_backlight_level,
		224	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	225	},
		226	.copy = {
		227	.blit = &r100_copy_blit,
		228	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		229	.dma = NULL,
		230	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
6104	serge	231	.copy = &r100_copy_blit,
2997	Serge	232	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		233	},
		234	.surface = {
		235	.set_reg = r100_set_surface_reg,
		236	.clear_reg = r100_clear_surface_reg,
		237	},
		238	.hpd = {
5078	serge	239	.init = &r100_hpd_init,
		240	.fini = &r100_hpd_fini,
		241	.sense = &r100_hpd_sense,
		242	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	243	},
		244	.pm = {
5078	serge	245	.misc = &r100_pm_misc,
		246	.prepare = &r100_pm_prepare,
		247	.finish = &r100_pm_finish,
		248	.init_profile = &r100_pm_init_profile,
		249	.get_dynpm_state = &r100_pm_get_dynpm_state,
		250	.get_engine_clock = &radeon_legacy_get_engine_clock,
		251	.set_engine_clock = &radeon_legacy_set_engine_clock,
		252	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	253	.set_memory_clock = NULL,
		254	.get_pcie_lanes = NULL,
		255	.set_pcie_lanes = NULL,
5078	serge	256	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	257	},
		258	.pflip = {
		259	// .pre_page_flip = &r100_pre_page_flip,
		260	// .page_flip = &r100_page_flip,
		261	},
1963	serge	262	};
		263
		264	static struct radeon_asic r200_asic = {
		265	.init = &r100_init,
6104	serge	266	.fini = &r100_fini,
1963	serge	267	// .suspend = &r100_suspend,
		268	// .resume = &r100_resume,
		269	// .vga_set_state = &r100_vga_set_state,
		270	.asic_reset = &r100_asic_reset,
5078	serge	271	.mmio_hdp_flush = NULL,
2007	serge	272	.gui_idle = &r100_gui_idle,
2997	Serge	273	.mc_wait_for_idle = &r100_mc_wait_for_idle,
6104	serge	274	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	275	.gart = {
		276	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	277	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	278	.set_page = &r100_pci_gart_set_page,
		279	},
		280	.ring = {
5078	serge	281	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	282	},
		283	.irq = {
		284	.set = &r100_irq_set,
		285	.process = &r100_irq_process,
		286	},
		287	.display = {
		288	.bandwidth_update = &r100_bandwidth_update,
		289	.get_vblank_counter = &r100_get_vblank_counter,
		290	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	291	.set_backlight_level = &radeon_legacy_set_backlight_level,
		292	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	293	},
		294	.copy = {
		295	.blit = &r100_copy_blit,
		296	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		297	.dma = &r200_copy_dma,
		298	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		299	.copy = &r100_copy_blit,
		300	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		301	},
		302	.surface = {
		303	.set_reg = r100_set_surface_reg,
		304	.clear_reg = r100_clear_surface_reg,
		305	},
		306	.hpd = {
5078	serge	307	.init = &r100_hpd_init,
		308	.fini = &r100_hpd_fini,
		309	.sense = &r100_hpd_sense,
		310	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	311	},
		312	.pm = {
5078	serge	313	.misc = &r100_pm_misc,
		314	.prepare = &r100_pm_prepare,
		315	.finish = &r100_pm_finish,
		316	.init_profile = &r100_pm_init_profile,
		317	.get_dynpm_state = &r100_pm_get_dynpm_state,
		318	.get_engine_clock = &radeon_legacy_get_engine_clock,
		319	.set_engine_clock = &radeon_legacy_set_engine_clock,
		320	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	321	.set_memory_clock = NULL,
		322	.get_pcie_lanes = NULL,
		323	.set_pcie_lanes = NULL,
5078	serge	324	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	325	},
		326	.pflip = {
		327	// .pre_page_flip = &r100_pre_page_flip,
		328	// .page_flip = &r100_page_flip,
		329	},
1963	serge	330	};
		331
5078	serge	332	static struct radeon_asic_ring r300_gfx_ring = {
		333	.ib_execute = &r100_ring_ib_execute,
		334	.emit_fence = &r300_fence_ring_emit,
		335	.emit_semaphore = &r100_semaphore_ring_emit,
		336	.cs_parse = &r300_cs_parse,
		337	.ring_start = &r300_ring_start,
		338	.ring_test = &r100_ring_test,
		339	.ib_test = &r100_ib_test,
		340	.is_lockup = &r100_gpu_is_lockup,
		341	.get_rptr = &r100_gfx_get_rptr,
		342	.get_wptr = &r100_gfx_get_wptr,
		343	.set_wptr = &r100_gfx_set_wptr,
		344	};
		345
6104	serge	346	static struct radeon_asic_ring rv515_gfx_ring = {
		347	.ib_execute = &r100_ring_ib_execute,
		348	.emit_fence = &r300_fence_ring_emit,
		349	.emit_semaphore = &r100_semaphore_ring_emit,
		350	.cs_parse = &r300_cs_parse,
		351	.ring_start = &rv515_ring_start,
		352	.ring_test = &r100_ring_test,
		353	.ib_test = &r100_ib_test,
		354	.is_lockup = &r100_gpu_is_lockup,
		355	.get_rptr = &r100_gfx_get_rptr,
		356	.get_wptr = &r100_gfx_get_wptr,
		357	.set_wptr = &r100_gfx_set_wptr,
		358	};
		359
1963	serge	360	static struct radeon_asic r300_asic = {
		361	.init = &r300_init,
6104	serge	362	.fini = &r300_fini,
1963	serge	363	// .suspend = &r300_suspend,
		364	// .resume = &r300_resume,
		365	// .vga_set_state = &r100_vga_set_state,
		366	.asic_reset = &r300_asic_reset,
5078	serge	367	.mmio_hdp_flush = NULL,
2007	serge	368	.gui_idle = &r100_gui_idle,
2997	Serge	369	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	370	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	371	.gart = {
		372	.tlb_flush = &r100_pci_gart_tlb_flush,
6104	serge	373	.get_page_entry = &r100_pci_gart_get_page_entry,
2997	Serge	374	.set_page = &r100_pci_gart_set_page,
		375	},
		376	.ring = {
5078	serge	377	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	378	},
		379	.irq = {
		380	.set = &r100_irq_set,
		381	.process = &r100_irq_process,
		382	},
		383	.display = {
		384	.bandwidth_update = &r100_bandwidth_update,
		385	.get_vblank_counter = &r100_get_vblank_counter,
		386	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	387	.set_backlight_level = &radeon_legacy_set_backlight_level,
		388	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	389	},
		390	.copy = {
		391	.blit = &r100_copy_blit,
		392	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		393	.dma = &r200_copy_dma,
		394	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		395	.copy = &r100_copy_blit,
		396	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		397	},
		398	.surface = {
		399	.set_reg = r100_set_surface_reg,
		400	.clear_reg = r100_clear_surface_reg,
		401	},
		402	.hpd = {
5078	serge	403	.init = &r100_hpd_init,
		404	.fini = &r100_hpd_fini,
		405	.sense = &r100_hpd_sense,
		406	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	407	},
		408	.pm = {
5078	serge	409	.misc = &r100_pm_misc,
		410	.prepare = &r100_pm_prepare,
		411	.finish = &r100_pm_finish,
		412	.init_profile = &r100_pm_init_profile,
		413	.get_dynpm_state = &r100_pm_get_dynpm_state,
		414	.get_engine_clock = &radeon_legacy_get_engine_clock,
		415	.set_engine_clock = &radeon_legacy_set_engine_clock,
		416	.get_memory_clock = &radeon_legacy_get_memory_clock,
		417	.set_memory_clock = NULL,
		418	.get_pcie_lanes = &rv370_get_pcie_lanes,
		419	.set_pcie_lanes = &rv370_set_pcie_lanes,
		420	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	421	},
		422	.pflip = {
		423	// .pre_page_flip = &r100_pre_page_flip,
		424	// .page_flip = &r100_page_flip,
		425	},
1963	serge	426	};
		427
		428	static struct radeon_asic r300_asic_pcie = {
		429	.init = &r300_init,
6104	serge	430	.fini = &r300_fini,
1963	serge	431	// .suspend = &r300_suspend,
		432	// .resume = &r300_resume,
		433	// .vga_set_state = &r100_vga_set_state,
		434	.asic_reset = &r300_asic_reset,
5078	serge	435	.mmio_hdp_flush = NULL,
2007	serge	436	.gui_idle = &r100_gui_idle,
2997	Serge	437	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	438	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	439	.gart = {
		440	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	441	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	442	.set_page = &rv370_pcie_gart_set_page,
		443	},
		444	.ring = {
5078	serge	445	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	446	},
		447	.irq = {
		448	.set = &r100_irq_set,
		449	.process = &r100_irq_process,
		450	},
		451	.display = {
		452	.bandwidth_update = &r100_bandwidth_update,
		453	.get_vblank_counter = &r100_get_vblank_counter,
		454	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	455	.set_backlight_level = &radeon_legacy_set_backlight_level,
		456	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	457	},
		458	.copy = {
		459	.blit = &r100_copy_blit,
		460	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		461	.dma = &r200_copy_dma,
		462	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		463	.copy = &r100_copy_blit,
		464	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		465	},
		466	.surface = {
		467	.set_reg = r100_set_surface_reg,
		468	.clear_reg = r100_clear_surface_reg,
		469	},
		470	.hpd = {
		471	.init = &r100_hpd_init,
		472	.fini = &r100_hpd_fini,
		473	.sense = &r100_hpd_sense,
		474	.set_polarity = &r100_hpd_set_polarity,
		475	},
		476	.pm = {
5078	serge	477	.misc = &r100_pm_misc,
		478	.prepare = &r100_pm_prepare,
		479	.finish = &r100_pm_finish,
		480	.init_profile = &r100_pm_init_profile,
		481	.get_dynpm_state = &r100_pm_get_dynpm_state,
		482	.get_engine_clock = &radeon_legacy_get_engine_clock,
		483	.set_engine_clock = &radeon_legacy_set_engine_clock,
		484	.get_memory_clock = &radeon_legacy_get_memory_clock,
		485	.set_memory_clock = NULL,
		486	.get_pcie_lanes = &rv370_get_pcie_lanes,
		487	.set_pcie_lanes = &rv370_set_pcie_lanes,
		488	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	489	},
		490	.pflip = {
		491	// .pre_page_flip = &r100_pre_page_flip,
		492	// .page_flip = &r100_page_flip,
		493	},
1963	serge	494	};
		495
		496	static struct radeon_asic r420_asic = {
		497	.init = &r420_init,
6104	serge	498	.fini = &r420_fini,
1963	serge	499	// .suspend = &r420_suspend,
		500	// .resume = &r420_resume,
		501	// .vga_set_state = &r100_vga_set_state,
		502	.asic_reset = &r300_asic_reset,
5078	serge	503	.mmio_hdp_flush = NULL,
2160	serge	504	.gui_idle = &r100_gui_idle,
2997	Serge	505	.mc_wait_for_idle = &r300_mc_wait_for_idle,
6104	serge	506	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	507	.gart = {
		508	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	509	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	510	.set_page = &rv370_pcie_gart_set_page,
		511	},
		512	.ring = {
5078	serge	513	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	514	},
		515	.irq = {
		516	.set = &r100_irq_set,
		517	.process = &r100_irq_process,
		518	},
		519	.display = {
		520	.bandwidth_update = &r100_bandwidth_update,
		521	.get_vblank_counter = &r100_get_vblank_counter,
		522	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	523	.set_backlight_level = &atombios_set_backlight_level,
		524	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	525	},
		526	.copy = {
		527	.blit = &r100_copy_blit,
		528	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		529	.dma = &r200_copy_dma,
		530	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		531	.copy = &r100_copy_blit,
		532	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		533	},
		534	.surface = {
		535	.set_reg = r100_set_surface_reg,
		536	.clear_reg = r100_clear_surface_reg,
		537	},
		538	.hpd = {
5078	serge	539	.init = &r100_hpd_init,
		540	.fini = &r100_hpd_fini,
		541	.sense = &r100_hpd_sense,
		542	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	543	},
		544	.pm = {
5078	serge	545	.misc = &r100_pm_misc,
		546	.prepare = &r100_pm_prepare,
		547	.finish = &r100_pm_finish,
		548	.init_profile = &r420_pm_init_profile,
		549	.get_dynpm_state = &r100_pm_get_dynpm_state,
		550	.get_engine_clock = &radeon_atom_get_engine_clock,
		551	.set_engine_clock = &radeon_atom_set_engine_clock,
		552	.get_memory_clock = &radeon_atom_get_memory_clock,
		553	.set_memory_clock = &radeon_atom_set_memory_clock,
		554	.get_pcie_lanes = &rv370_get_pcie_lanes,
		555	.set_pcie_lanes = &rv370_set_pcie_lanes,
		556	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	557	},
		558	.pflip = {
		559	// .pre_page_flip = &r100_pre_page_flip,
		560	// .page_flip = &r100_page_flip,
		561	},
1963	serge	562	};
		563
		564	static struct radeon_asic rs400_asic = {
		565	.init = &rs400_init,
6104	serge	566	.fini = &rs400_fini,
1963	serge	567	// .suspend = &rs400_suspend,
		568	// .resume = &rs400_resume,
		569	// .vga_set_state = &r100_vga_set_state,
		570	.asic_reset = &r300_asic_reset,
5078	serge	571	.mmio_hdp_flush = NULL,
2160	serge	572	.gui_idle = &r100_gui_idle,
2997	Serge	573	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
6104	serge	574	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	575	.gart = {
		576	.tlb_flush = &rs400_gart_tlb_flush,
6104	serge	577	.get_page_entry = &rs400_gart_get_page_entry,
2997	Serge	578	.set_page = &rs400_gart_set_page,
		579	},
		580	.ring = {
5078	serge	581	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	582	},
		583	.irq = {
		584	.set = &r100_irq_set,
		585	.process = &r100_irq_process,
		586	},
		587	.display = {
		588	.bandwidth_update = &r100_bandwidth_update,
		589	.get_vblank_counter = &r100_get_vblank_counter,
		590	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	591	.set_backlight_level = &radeon_legacy_set_backlight_level,
		592	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	593	},
		594	.copy = {
		595	.blit = &r100_copy_blit,
		596	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		597	.dma = &r200_copy_dma,
		598	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		599	.copy = &r100_copy_blit,
		600	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		601	},
		602	.surface = {
		603	.set_reg = r100_set_surface_reg,
		604	.clear_reg = r100_clear_surface_reg,
		605	},
		606	.hpd = {
5078	serge	607	.init = &r100_hpd_init,
		608	.fini = &r100_hpd_fini,
		609	.sense = &r100_hpd_sense,
		610	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	611	},
		612	.pm = {
5078	serge	613	.misc = &r100_pm_misc,
		614	.prepare = &r100_pm_prepare,
		615	.finish = &r100_pm_finish,
		616	.init_profile = &r100_pm_init_profile,
		617	.get_dynpm_state = &r100_pm_get_dynpm_state,
		618	.get_engine_clock = &radeon_legacy_get_engine_clock,
		619	.set_engine_clock = &radeon_legacy_set_engine_clock,
		620	.get_memory_clock = &radeon_legacy_get_memory_clock,
		621	.set_memory_clock = NULL,
		622	.get_pcie_lanes = NULL,
		623	.set_pcie_lanes = NULL,
		624	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	625	},
		626	.pflip = {
		627	// .pre_page_flip = &r100_pre_page_flip,
		628	// .page_flip = &r100_page_flip,
		629	},
1963	serge	630	};
		631
		632	static struct radeon_asic rs600_asic = {
		633	.init = &rs600_init,
6104	serge	634	.fini = &rs600_fini,
1963	serge	635	// .suspend = &rs600_suspend,
		636	// .resume = &rs600_resume,
		637	// .vga_set_state = &r100_vga_set_state,
		638	.asic_reset = &rs600_asic_reset,
5078	serge	639	.mmio_hdp_flush = NULL,
2160	serge	640	.gui_idle = &r100_gui_idle,
2997	Serge	641	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
6104	serge	642	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	643	.gart = {
		644	.tlb_flush = &rs600_gart_tlb_flush,
6104	serge	645	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	646	.set_page = &rs600_gart_set_page,
		647	},
		648	.ring = {
5078	serge	649	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	650	},
		651	.irq = {
		652	.set = &rs600_irq_set,
		653	.process = &rs600_irq_process,
		654	},
		655	.display = {
		656	.bandwidth_update = &rs600_bandwidth_update,
		657	.get_vblank_counter = &rs600_get_vblank_counter,
		658	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	659	.set_backlight_level = &atombios_set_backlight_level,
		660	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	661	},
		662	.copy = {
		663	.blit = &r100_copy_blit,
		664	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		665	.dma = &r200_copy_dma,
		666	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		667	.copy = &r100_copy_blit,
		668	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		669	},
		670	.surface = {
		671	.set_reg = r100_set_surface_reg,
		672	.clear_reg = r100_clear_surface_reg,
		673	},
		674	.hpd = {
5078	serge	675	.init = &rs600_hpd_init,
		676	.fini = &rs600_hpd_fini,
		677	.sense = &rs600_hpd_sense,
		678	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	679	},
		680	.pm = {
5078	serge	681	.misc = &rs600_pm_misc,
		682	.prepare = &rs600_pm_prepare,
		683	.finish = &rs600_pm_finish,
		684	.init_profile = &r420_pm_init_profile,
		685	.get_dynpm_state = &r100_pm_get_dynpm_state,
		686	.get_engine_clock = &radeon_atom_get_engine_clock,
		687	.set_engine_clock = &radeon_atom_set_engine_clock,
		688	.get_memory_clock = &radeon_atom_get_memory_clock,
		689	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	690	.get_pcie_lanes = NULL,
		691	.set_pcie_lanes = NULL,
5078	serge	692	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	693	},
		694	.pflip = {
		695	// .pre_page_flip = &rs600_pre_page_flip,
		696	// .page_flip = &rs600_page_flip,
		697	},
1963	serge	698	};
		699
		700	static struct radeon_asic rs690_asic = {
		701	.init = &rs690_init,
6104	serge	702	.fini = &rs690_fini,
1963	serge	703	// .suspend = &rs690_suspend,
		704	// .resume = &rs690_resume,
		705	// .vga_set_state = &r100_vga_set_state,
		706	.asic_reset = &rs600_asic_reset,
5078	serge	707	.mmio_hdp_flush = NULL,
2160	serge	708	.gui_idle = &r100_gui_idle,
2997	Serge	709	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
6104	serge	710	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	711	.gart = {
		712	.tlb_flush = &rs400_gart_tlb_flush,
6104	serge	713	.get_page_entry = &rs400_gart_get_page_entry,
2997	Serge	714	.set_page = &rs400_gart_set_page,
		715	},
		716	.ring = {
5078	serge	717	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	718	},
		719	.irq = {
		720	.set = &rs600_irq_set,
		721	.process = &rs600_irq_process,
		722	},
		723	.display = {
		724	.get_vblank_counter = &rs600_get_vblank_counter,
		725	.bandwidth_update = &rs690_bandwidth_update,
		726	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	727	.set_backlight_level = &atombios_set_backlight_level,
		728	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	729	},
		730	.copy = {
		731	.blit = &r100_copy_blit,
		732	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		733	.dma = &r200_copy_dma,
		734	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		735	.copy = &r200_copy_dma,
		736	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		737	},
		738	.surface = {
		739	.set_reg = r100_set_surface_reg,
		740	.clear_reg = r100_clear_surface_reg,
		741	},
		742	.hpd = {
5078	serge	743	.init = &rs600_hpd_init,
		744	.fini = &rs600_hpd_fini,
2997	Serge	745	.sense = &rs600_hpd_sense,
		746	.set_polarity = &rs600_hpd_set_polarity,
		747	},
		748	.pm = {
5078	serge	749	.misc = &rs600_pm_misc,
		750	.prepare = &rs600_pm_prepare,
		751	.finish = &rs600_pm_finish,
		752	.init_profile = &r420_pm_init_profile,
		753	.get_dynpm_state = &r100_pm_get_dynpm_state,
		754	.get_engine_clock = &radeon_atom_get_engine_clock,
		755	.set_engine_clock = &radeon_atom_set_engine_clock,
		756	.get_memory_clock = &radeon_atom_get_memory_clock,
		757	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	758	.get_pcie_lanes = NULL,
		759	.set_pcie_lanes = NULL,
5078	serge	760	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	761	},
		762	.pflip = {
		763	// .pre_page_flip = &rs600_pre_page_flip,
		764	// .page_flip = &rs600_page_flip,
		765	},
1963	serge	766	};
		767
		768	static struct radeon_asic rv515_asic = {
		769	.init = &rv515_init,
6104	serge	770	.fini = &rv515_fini,
1963	serge	771	// .suspend = &rv515_suspend,
		772	// .resume = &rv515_resume,
		773	// .vga_set_state = &r100_vga_set_state,
		774	.asic_reset = &rs600_asic_reset,
5078	serge	775	.mmio_hdp_flush = NULL,
2160	serge	776	.gui_idle = &r100_gui_idle,
2997	Serge	777	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
6104	serge	778	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	779	.gart = {
		780	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	781	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	782	.set_page = &rv370_pcie_gart_set_page,
		783	},
		784	.ring = {
6104	serge	785	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
2997	Serge	786	},
		787	.irq = {
		788	.set = &rs600_irq_set,
		789	.process = &rs600_irq_process,
		790	},
		791	.display = {
		792	.get_vblank_counter = &rs600_get_vblank_counter,
		793	.bandwidth_update = &rv515_bandwidth_update,
		794	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	795	.set_backlight_level = &atombios_set_backlight_level,
		796	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	797	},
		798	.copy = {
		799	.blit = &r100_copy_blit,
		800	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		801	.dma = &r200_copy_dma,
		802	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		803	.copy = &r100_copy_blit,
		804	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		805	},
		806	.surface = {
		807	.set_reg = r100_set_surface_reg,
		808	.clear_reg = r100_clear_surface_reg,
		809	},
		810	.hpd = {
5078	serge	811	.init = &rs600_hpd_init,
		812	.fini = &rs600_hpd_fini,
		813	.sense = &rs600_hpd_sense,
		814	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	815	},
		816	.pm = {
5078	serge	817	.misc = &rs600_pm_misc,
		818	.prepare = &rs600_pm_prepare,
		819	.finish = &rs600_pm_finish,
		820	.init_profile = &r420_pm_init_profile,
		821	.get_dynpm_state = &r100_pm_get_dynpm_state,
		822	.get_engine_clock = &radeon_atom_get_engine_clock,
		823	.set_engine_clock = &radeon_atom_set_engine_clock,
		824	.get_memory_clock = &radeon_atom_get_memory_clock,
		825	.set_memory_clock = &radeon_atom_set_memory_clock,
		826	.get_pcie_lanes = &rv370_get_pcie_lanes,
		827	.set_pcie_lanes = &rv370_set_pcie_lanes,
		828	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	829	},
		830	.pflip = {
		831	// .pre_page_flip = &rs600_pre_page_flip,
		832	// .page_flip = &rs600_page_flip,
		833	},
1963	serge	834	};
		835
		836	static struct radeon_asic r520_asic = {
		837	.init = &r520_init,
6104	serge	838	.fini = &rv515_fini,
1963	serge	839	// .suspend = &rv515_suspend,
		840	// .resume = &r520_resume,
		841	// .vga_set_state = &r100_vga_set_state,
		842	.asic_reset = &rs600_asic_reset,
5078	serge	843	.mmio_hdp_flush = NULL,
2160	serge	844	.gui_idle = &r100_gui_idle,
2997	Serge	845	.mc_wait_for_idle = &r520_mc_wait_for_idle,
6104	serge	846	.get_allowed_info_register = radeon_invalid_get_allowed_info_register,
2997	Serge	847	.gart = {
		848	.tlb_flush = &rv370_pcie_gart_tlb_flush,
6104	serge	849	.get_page_entry = &rv370_pcie_gart_get_page_entry,
2997	Serge	850	.set_page = &rv370_pcie_gart_set_page,
		851	},
		852	.ring = {
6104	serge	853	[RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
2997	Serge	854	},
		855	.irq = {
		856	.set = &rs600_irq_set,
		857	.process = &rs600_irq_process,
		858	},
		859	.display = {
		860	.bandwidth_update = &rv515_bandwidth_update,
		861	.get_vblank_counter = &rs600_get_vblank_counter,
		862	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	863	.set_backlight_level = &atombios_set_backlight_level,
		864	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	865	},
		866	.copy = {
		867	.blit = &r100_copy_blit,
		868	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		869	.dma = &r200_copy_dma,
		870	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		871	.copy = &r100_copy_blit,
		872	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		873	},
		874	.surface = {
		875	.set_reg = r100_set_surface_reg,
		876	.clear_reg = r100_clear_surface_reg,
		877	},
		878	.hpd = {
5078	serge	879	.init = &rs600_hpd_init,
		880	.fini = &rs600_hpd_fini,
		881	.sense = &rs600_hpd_sense,
		882	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	883	},
		884	.pm = {
5078	serge	885	.misc = &rs600_pm_misc,
		886	.prepare = &rs600_pm_prepare,
		887	.finish = &rs600_pm_finish,
		888	.init_profile = &r420_pm_init_profile,
		889	.get_dynpm_state = &r100_pm_get_dynpm_state,
		890	.get_engine_clock = &radeon_atom_get_engine_clock,
		891	.set_engine_clock = &radeon_atom_set_engine_clock,
		892	.get_memory_clock = &radeon_atom_get_memory_clock,
		893	.set_memory_clock = &radeon_atom_set_memory_clock,
		894	.get_pcie_lanes = &rv370_get_pcie_lanes,
		895	.set_pcie_lanes = &rv370_set_pcie_lanes,
		896	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	897	},
		898	.pflip = {
		899	// .pre_page_flip = &rs600_pre_page_flip,
		900	// .page_flip = &rs600_page_flip,
		901	},
1963	serge	902	};
		903
5078	serge	904	static struct radeon_asic_ring r600_gfx_ring = {
		905	.ib_execute = &r600_ring_ib_execute,
		906	.emit_fence = &r600_fence_ring_emit,
		907	.emit_semaphore = &r600_semaphore_ring_emit,
		908	.cs_parse = &r600_cs_parse,
		909	.ring_test = &r600_ring_test,
		910	.ib_test = &r600_ib_test,
		911	.is_lockup = &r600_gfx_is_lockup,
		912	.get_rptr = &r600_gfx_get_rptr,
		913	.get_wptr = &r600_gfx_get_wptr,
		914	.set_wptr = &r600_gfx_set_wptr,
		915	};
		916
		917	static struct radeon_asic_ring r600_dma_ring = {
		918	.ib_execute = &r600_dma_ring_ib_execute,
		919	.emit_fence = &r600_dma_fence_ring_emit,
		920	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		921	.cs_parse = &r600_dma_cs_parse,
		922	.ring_test = &r600_dma_ring_test,
		923	.ib_test = &r600_dma_ib_test,
		924	.is_lockup = &r600_dma_is_lockup,
		925	.get_rptr = &r600_dma_get_rptr,
		926	.get_wptr = &r600_dma_get_wptr,
		927	.set_wptr = &r600_dma_set_wptr,
		928	};
		929
1963	serge	930	static struct radeon_asic r600_asic = {
		931	.init = &r600_init,
6104	serge	932	.fini = &r600_fini,
1963	serge	933	// .suspend = &r600_suspend,
		934	// .resume = &r600_resume,
2997	Serge	935	// .vga_set_state = &r600_vga_set_state,
1963	serge	936	.asic_reset = &r600_asic_reset,
5078	serge	937	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	938	.gui_idle = &r600_gui_idle,
		939	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	940	.get_xclk = &r600_get_xclk,
		941	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	942	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	943	.gart = {
		944	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	945	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	946	.set_page = &rs600_gart_set_page,
		947	},
		948	.ring = {
5078	serge	949	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		950	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	951	},
		952	.irq = {
		953	.set = &r600_irq_set,
		954	.process = &r600_irq_process,
		955	},
		956	.display = {
		957	.bandwidth_update = &rv515_bandwidth_update,
		958	.get_vblank_counter = &rs600_get_vblank_counter,
		959	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	960	.set_backlight_level = &atombios_set_backlight_level,
		961	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	962	},
		963	.copy = {
5078	serge	964	.blit = &r600_copy_cpdma,
2997	Serge	965	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	966	.dma = &r600_copy_dma,
		967	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	968	.copy = &r600_copy_cpdma,
		969	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	970	},
		971	.surface = {
		972	.set_reg = r600_set_surface_reg,
		973	.clear_reg = r600_clear_surface_reg,
		974	},
		975	.hpd = {
5078	serge	976	.init = &r600_hpd_init,
		977	.fini = &r600_hpd_fini,
		978	.sense = &r600_hpd_sense,
		979	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	980	},
		981	.pm = {
5078	serge	982	.misc = &r600_pm_misc,
		983	.prepare = &rs600_pm_prepare,
		984	.finish = &rs600_pm_finish,
		985	.init_profile = &r600_pm_init_profile,
		986	.get_dynpm_state = &r600_pm_get_dynpm_state,
		987	.get_engine_clock = &radeon_atom_get_engine_clock,
		988	.set_engine_clock = &radeon_atom_set_engine_clock,
		989	.get_memory_clock = &radeon_atom_get_memory_clock,
		990	.set_memory_clock = &radeon_atom_set_memory_clock,
		991	.get_pcie_lanes = &r600_get_pcie_lanes,
		992	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	993	.set_clock_gating = NULL,
5078	serge	994	.get_temperature = &rv6xx_get_temp,
2997	Serge	995	},
		996	.pflip = {
		997	// .pre_page_flip = &rs600_pre_page_flip,
		998	// .page_flip = &rs600_page_flip,
		999	},
1963	serge	1000	};
		1001
6104	serge	1002	static struct radeon_asic_ring rv6xx_uvd_ring = {
		1003	.ib_execute = &uvd_v1_0_ib_execute,
		1004	.emit_fence = &uvd_v1_0_fence_emit,
		1005	.emit_semaphore = &uvd_v1_0_semaphore_emit,
		1006	.cs_parse = &radeon_uvd_cs_parse,
		1007	.ring_test = &uvd_v1_0_ring_test,
		1008	.ib_test = &uvd_v1_0_ib_test,
		1009	.is_lockup = &radeon_ring_test_lockup,
		1010	.get_rptr = &uvd_v1_0_get_rptr,
		1011	.get_wptr = &uvd_v1_0_get_wptr,
		1012	.set_wptr = &uvd_v1_0_set_wptr,
		1013	};
		1014
5078	serge	1015	static struct radeon_asic rv6xx_asic = {
		1016	.init = &r600_init,
6104	serge	1017	.fini = &r600_fini,
5078	serge	1018	// .suspend = &r600_suspend,
		1019	// .resume = &r600_resume,
		1020	// .vga_set_state = &r600_vga_set_state,
		1021	.asic_reset = &r600_asic_reset,
		1022	.mmio_hdp_flush = r600_mmio_hdp_flush,
		1023	.gui_idle = &r600_gui_idle,
		1024	.mc_wait_for_idle = &r600_mc_wait_for_idle,
		1025	.get_xclk = &r600_get_xclk,
		1026	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1027	.get_allowed_info_register = r600_get_allowed_info_register,
5078	serge	1028	.gart = {
		1029	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1030	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	1031	.set_page = &rs600_gart_set_page,
		1032	},
		1033	.ring = {
		1034	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1035	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
6104	serge	1036	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
5078	serge	1037	},
		1038	.irq = {
		1039	.set = &r600_irq_set,
		1040	.process = &r600_irq_process,
		1041	},
		1042	.display = {
		1043	.bandwidth_update = &rv515_bandwidth_update,
		1044	.get_vblank_counter = &rs600_get_vblank_counter,
		1045	.wait_for_vblank = &avivo_wait_for_vblank,
		1046	.set_backlight_level = &atombios_set_backlight_level,
		1047	.get_backlight_level = &atombios_get_backlight_level,
		1048	},
		1049	.copy = {
		1050	.blit = &r600_copy_cpdma,
		1051	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1052	.dma = &r600_copy_dma,
		1053	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1054	.copy = &r600_copy_cpdma,
		1055	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1056	},
		1057	.surface = {
		1058	.set_reg = r600_set_surface_reg,
		1059	.clear_reg = r600_clear_surface_reg,
		1060	},
		1061	.hpd = {
		1062	.init = &r600_hpd_init,
		1063	.fini = &r600_hpd_fini,
		1064	.sense = &r600_hpd_sense,
		1065	.set_polarity = &r600_hpd_set_polarity,
		1066	},
		1067	.pm = {
		1068	.misc = &r600_pm_misc,
		1069	.prepare = &rs600_pm_prepare,
		1070	.finish = &rs600_pm_finish,
		1071	.init_profile = &r600_pm_init_profile,
		1072	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1073	.get_engine_clock = &radeon_atom_get_engine_clock,
		1074	.set_engine_clock = &radeon_atom_set_engine_clock,
		1075	.get_memory_clock = &radeon_atom_get_memory_clock,
		1076	.set_memory_clock = &radeon_atom_set_memory_clock,
		1077	.get_pcie_lanes = &r600_get_pcie_lanes,
		1078	.set_pcie_lanes = &r600_set_pcie_lanes,
		1079	.set_clock_gating = NULL,
		1080	.get_temperature = &rv6xx_get_temp,
		1081	.set_uvd_clocks = &r600_set_uvd_clocks,
		1082	},
		1083	.dpm = {
		1084	.init = &rv6xx_dpm_init,
		1085	.setup_asic = &rv6xx_setup_asic,
		1086	.enable = &rv6xx_dpm_enable,
		1087	.late_enable = &r600_dpm_late_enable,
		1088	.disable = &rv6xx_dpm_disable,
		1089	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1090	.set_power_state = &rv6xx_dpm_set_power_state,
		1091	.post_set_power_state = &r600_dpm_post_set_power_state,
		1092	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
		1093	.fini = &rv6xx_dpm_fini,
		1094	.get_sclk = &rv6xx_dpm_get_sclk,
		1095	.get_mclk = &rv6xx_dpm_get_mclk,
		1096	.print_power_state = &rv6xx_dpm_print_power_state,
		1097	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
		1098	.force_performance_level = &rv6xx_dpm_force_performance_level,
6104	serge	1099	.get_current_sclk = &rv6xx_dpm_get_current_sclk,
		1100	.get_current_mclk = &rv6xx_dpm_get_current_mclk,
5078	serge	1101	},
		1102	.pflip = {
		1103	// .pre_page_flip = &rs600_pre_page_flip,
		1104	// .page_flip = &rs600_page_flip,
		1105	},
		1106	};
		1107
1963	serge	1108	static struct radeon_asic rs780_asic = {
		1109	.init = &r600_init,
6104	serge	1110	.fini = &r600_fini,
1963	serge	1111	// .suspend = &r600_suspend,
		1112	// .resume = &r600_resume,
2997	Serge	1113	// .vga_set_state = &r600_vga_set_state,
1963	serge	1114	.asic_reset = &r600_asic_reset,
5078	serge	1115	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1116	.gui_idle = &r600_gui_idle,
		1117	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1118	.get_xclk = &r600_get_xclk,
		1119	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1120	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	1121	.gart = {
		1122	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1123	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1124	.set_page = &rs600_gart_set_page,
		1125	},
		1126	.ring = {
5078	serge	1127	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1128	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
6104	serge	1129	[R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
2997	Serge	1130	},
		1131	.irq = {
		1132	.set = &r600_irq_set,
		1133	.process = &r600_irq_process,
		1134	},
		1135	.display = {
		1136	.bandwidth_update = &rs690_bandwidth_update,
		1137	.get_vblank_counter = &rs600_get_vblank_counter,
		1138	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1139	.set_backlight_level = &atombios_set_backlight_level,
		1140	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1141	},
		1142	.copy = {
5078	serge	1143	.blit = &r600_copy_cpdma,
2997	Serge	1144	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1145	.dma = &r600_copy_dma,
		1146	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	1147	.copy = &r600_copy_cpdma,
		1148	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	1149	},
		1150	.surface = {
		1151	.set_reg = r600_set_surface_reg,
		1152	.clear_reg = r600_clear_surface_reg,
		1153	},
		1154	.hpd = {
5078	serge	1155	.init = &r600_hpd_init,
		1156	.fini = &r600_hpd_fini,
		1157	.sense = &r600_hpd_sense,
		1158	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1159	},
		1160	.pm = {
5078	serge	1161	.misc = &r600_pm_misc,
		1162	.prepare = &rs600_pm_prepare,
		1163	.finish = &rs600_pm_finish,
		1164	.init_profile = &rs780_pm_init_profile,
		1165	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1166	.get_engine_clock = &radeon_atom_get_engine_clock,
		1167	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1168	.get_memory_clock = NULL,
		1169	.set_memory_clock = NULL,
		1170	.get_pcie_lanes = NULL,
		1171	.set_pcie_lanes = NULL,
		1172	.set_clock_gating = NULL,
5078	serge	1173	.get_temperature = &rv6xx_get_temp,
		1174	.set_uvd_clocks = &r600_set_uvd_clocks,
2997	Serge	1175	},
5078	serge	1176	.dpm = {
		1177	.init = &rs780_dpm_init,
		1178	.setup_asic = &rs780_dpm_setup_asic,
		1179	.enable = &rs780_dpm_enable,
		1180	.late_enable = &r600_dpm_late_enable,
		1181	.disable = &rs780_dpm_disable,
		1182	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1183	.set_power_state = &rs780_dpm_set_power_state,
		1184	.post_set_power_state = &r600_dpm_post_set_power_state,
		1185	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
		1186	.fini = &rs780_dpm_fini,
		1187	.get_sclk = &rs780_dpm_get_sclk,
		1188	.get_mclk = &rs780_dpm_get_mclk,
		1189	.print_power_state = &rs780_dpm_print_power_state,
		1190	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
		1191	.force_performance_level = &rs780_dpm_force_performance_level,
6104	serge	1192	.get_current_sclk = &rs780_dpm_get_current_sclk,
		1193	.get_current_mclk = &rs780_dpm_get_current_mclk,
5078	serge	1194	},
2997	Serge	1195	.pflip = {
		1196	// .pre_page_flip = &rs600_pre_page_flip,
		1197	// .page_flip = &rs600_page_flip,
		1198	},
1963	serge	1199	};
		1200
5078	serge	1201	static struct radeon_asic_ring rv770_uvd_ring = {
		1202	.ib_execute = &uvd_v1_0_ib_execute,
		1203	.emit_fence = &uvd_v2_2_fence_emit,
6104	serge	1204	.emit_semaphore = &uvd_v2_2_semaphore_emit,
5078	serge	1205	.cs_parse = &radeon_uvd_cs_parse,
		1206	.ring_test = &uvd_v1_0_ring_test,
		1207	.ib_test = &uvd_v1_0_ib_test,
		1208	.is_lockup = &radeon_ring_test_lockup,
		1209	.get_rptr = &uvd_v1_0_get_rptr,
		1210	.get_wptr = &uvd_v1_0_get_wptr,
		1211	.set_wptr = &uvd_v1_0_set_wptr,
		1212	};
		1213
1963	serge	1214	static struct radeon_asic rv770_asic = {
		1215	.init = &rv770_init,
6104	serge	1216	.fini = &rv770_fini,
1963	serge	1217	// .suspend = &rv770_suspend,
		1218	// .resume = &rv770_resume,
		1219	.asic_reset = &r600_asic_reset,
2997	Serge	1220	// .vga_set_state = &r600_vga_set_state,
5078	serge	1221	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1222	.gui_idle = &r600_gui_idle,
		1223	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1224	.get_xclk = &rv770_get_xclk,
		1225	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1226	.get_allowed_info_register = r600_get_allowed_info_register,
2997	Serge	1227	.gart = {
		1228	.tlb_flush = &r600_pcie_gart_tlb_flush,
6104	serge	1229	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1230	.set_page = &rs600_gart_set_page,
		1231	},
		1232	.ring = {
5078	serge	1233	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1234	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		1235	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1236	},
		1237	.irq = {
		1238	.set = &r600_irq_set,
		1239	.process = &r600_irq_process,
		1240	},
		1241	.display = {
		1242	.bandwidth_update = &rv515_bandwidth_update,
		1243	.get_vblank_counter = &rs600_get_vblank_counter,
		1244	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1245	.set_backlight_level = &atombios_set_backlight_level,
		1246	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1247	},
		1248	.copy = {
5078	serge	1249	.blit = &r600_copy_cpdma,
2997	Serge	1250	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3764	Serge	1251	.dma = &rv770_copy_dma,
3192	Serge	1252	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
3764	Serge	1253	.copy = &rv770_copy_dma,
3192	Serge	1254	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1255	},
		1256	.surface = {
		1257	.set_reg = r600_set_surface_reg,
		1258	.clear_reg = r600_clear_surface_reg,
		1259	},
		1260	.hpd = {
5078	serge	1261	.init = &r600_hpd_init,
		1262	.fini = &r600_hpd_fini,
		1263	.sense = &r600_hpd_sense,
		1264	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1265	},
		1266	.pm = {
5078	serge	1267	.misc = &rv770_pm_misc,
		1268	.prepare = &rs600_pm_prepare,
		1269	.finish = &rs600_pm_finish,
		1270	.init_profile = &r600_pm_init_profile,
		1271	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1272	.get_engine_clock = &radeon_atom_get_engine_clock,
		1273	.set_engine_clock = &radeon_atom_set_engine_clock,
		1274	.get_memory_clock = &radeon_atom_get_memory_clock,
		1275	.set_memory_clock = &radeon_atom_set_memory_clock,
		1276	.get_pcie_lanes = &r600_get_pcie_lanes,
		1277	.set_pcie_lanes = &r600_set_pcie_lanes,
		1278	.set_clock_gating = &radeon_atom_set_clock_gating,
3764	Serge	1279	.set_uvd_clocks = &rv770_set_uvd_clocks,
5078	serge	1280	.get_temperature = &rv770_get_temp,
2997	Serge	1281	},
5078	serge	1282	.dpm = {
		1283	.init = &rv770_dpm_init,
		1284	.setup_asic = &rv770_dpm_setup_asic,
		1285	.enable = &rv770_dpm_enable,
		1286	.late_enable = &rv770_dpm_late_enable,
		1287	.disable = &rv770_dpm_disable,
		1288	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1289	.set_power_state = &rv770_dpm_set_power_state,
		1290	.post_set_power_state = &r600_dpm_post_set_power_state,
		1291	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
		1292	.fini = &rv770_dpm_fini,
		1293	.get_sclk = &rv770_dpm_get_sclk,
		1294	.get_mclk = &rv770_dpm_get_mclk,
		1295	.print_power_state = &rv770_dpm_print_power_state,
		1296	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1297	.force_performance_level = &rv770_dpm_force_performance_level,
		1298	.vblank_too_short = &rv770_dpm_vblank_too_short,
6104	serge	1299	.get_current_sclk = &rv770_dpm_get_current_sclk,
		1300	.get_current_mclk = &rv770_dpm_get_current_mclk,
5078	serge	1301	},
2997	Serge	1302	.pflip = {
		1303	// .pre_page_flip = &rs600_pre_page_flip,
		1304	// .page_flip = &rv770_page_flip,
		1305	},
1963	serge	1306	};
1986	serge	1307
5078	serge	1308	static struct radeon_asic_ring evergreen_gfx_ring = {
		1309	.ib_execute = &evergreen_ring_ib_execute,
		1310	.emit_fence = &r600_fence_ring_emit,
		1311	.emit_semaphore = &r600_semaphore_ring_emit,
		1312	.cs_parse = &evergreen_cs_parse,
		1313	.ring_test = &r600_ring_test,
		1314	.ib_test = &r600_ib_test,
		1315	.is_lockup = &evergreen_gfx_is_lockup,
		1316	.get_rptr = &r600_gfx_get_rptr,
		1317	.get_wptr = &r600_gfx_get_wptr,
		1318	.set_wptr = &r600_gfx_set_wptr,
		1319	};
		1320
		1321	static struct radeon_asic_ring evergreen_dma_ring = {
		1322	.ib_execute = &evergreen_dma_ring_ib_execute,
		1323	.emit_fence = &evergreen_dma_fence_ring_emit,
		1324	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1325	.cs_parse = &evergreen_dma_cs_parse,
		1326	.ring_test = &r600_dma_ring_test,
		1327	.ib_test = &r600_dma_ib_test,
		1328	.is_lockup = &evergreen_dma_is_lockup,
		1329	.get_rptr = &r600_dma_get_rptr,
		1330	.get_wptr = &r600_dma_get_wptr,
		1331	.set_wptr = &r600_dma_set_wptr,
		1332	};
		1333
1963	serge	1334	static struct radeon_asic evergreen_asic = {
		1335	.init = &evergreen_init,
6104	serge	1336	.fini = &evergreen_fini,
1963	serge	1337	// .suspend = &evergreen_suspend,
		1338	// .resume = &evergreen_resume,
		1339	.asic_reset = &evergreen_asic_reset,
2997	Serge	1340	// .vga_set_state = &r600_vga_set_state,
5078	serge	1341	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1342	.gui_idle = &r600_gui_idle,
		1343	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1344	.get_xclk = &rv770_get_xclk,
		1345	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1346	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1347	.gart = {
		1348	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1349	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1350	.set_page = &rs600_gart_set_page,
		1351	},
		1352	.ring = {
5078	serge	1353	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1354	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1355	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1356	},
		1357	.irq = {
		1358	.set = &evergreen_irq_set,
		1359	.process = &evergreen_irq_process,
		1360	},
		1361	.display = {
		1362	.bandwidth_update = &evergreen_bandwidth_update,
		1363	.get_vblank_counter = &evergreen_get_vblank_counter,
		1364	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1365	.set_backlight_level = &atombios_set_backlight_level,
		1366	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1367	},
		1368	.copy = {
5078	serge	1369	.blit = &r600_copy_cpdma,
2997	Serge	1370	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1371	.dma = &evergreen_copy_dma,
		1372	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1373	.copy = &evergreen_copy_dma,
		1374	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1375	},
		1376	.surface = {
		1377	.set_reg = r600_set_surface_reg,
		1378	.clear_reg = r600_clear_surface_reg,
		1379	},
		1380	.hpd = {
5078	serge	1381	.init = &evergreen_hpd_init,
		1382	.fini = &evergreen_hpd_fini,
		1383	.sense = &evergreen_hpd_sense,
		1384	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1385	},
		1386	.pm = {
5078	serge	1387	.misc = &evergreen_pm_misc,
		1388	.prepare = &evergreen_pm_prepare,
		1389	.finish = &evergreen_pm_finish,
		1390	.init_profile = &r600_pm_init_profile,
		1391	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1392	.get_engine_clock = &radeon_atom_get_engine_clock,
		1393	.set_engine_clock = &radeon_atom_set_engine_clock,
		1394	.get_memory_clock = &radeon_atom_get_memory_clock,
		1395	.set_memory_clock = &radeon_atom_set_memory_clock,
		1396	.get_pcie_lanes = &r600_get_pcie_lanes,
		1397	.set_pcie_lanes = &r600_set_pcie_lanes,
		1398	.set_clock_gating = NULL,
3764	Serge	1399	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1400	.get_temperature = &evergreen_get_temp,
2997	Serge	1401	},
5078	serge	1402	.dpm = {
		1403	.init = &cypress_dpm_init,
		1404	.setup_asic = &cypress_dpm_setup_asic,
		1405	.enable = &cypress_dpm_enable,
		1406	.late_enable = &rv770_dpm_late_enable,
		1407	.disable = &cypress_dpm_disable,
		1408	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1409	.set_power_state = &cypress_dpm_set_power_state,
		1410	.post_set_power_state = &r600_dpm_post_set_power_state,
		1411	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1412	.fini = &cypress_dpm_fini,
		1413	.get_sclk = &rv770_dpm_get_sclk,
		1414	.get_mclk = &rv770_dpm_get_mclk,
		1415	.print_power_state = &rv770_dpm_print_power_state,
		1416	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1417	.force_performance_level = &rv770_dpm_force_performance_level,
		1418	.vblank_too_short = &cypress_dpm_vblank_too_short,
6104	serge	1419	.get_current_sclk = &rv770_dpm_get_current_sclk,
		1420	.get_current_mclk = &rv770_dpm_get_current_mclk,
5078	serge	1421	},
2997	Serge	1422	.pflip = {
		1423	},
1986	serge	1424	};
1990	serge	1425
1986	serge	1426	static struct radeon_asic sumo_asic = {
		1427	.init = &evergreen_init,
6104	serge	1428	.fini = &evergreen_fini,
1990	serge	1429	// .suspend = &evergreen_suspend,
		1430	// .resume = &evergreen_resume,
1986	serge	1431	.asic_reset = &evergreen_asic_reset,
2997	Serge	1432	// .vga_set_state = &r600_vga_set_state,
5078	serge	1433	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1434	.gui_idle = &r600_gui_idle,
		1435	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1436	.get_xclk = &r600_get_xclk,
		1437	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1438	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1439	.gart = {
		1440	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1441	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1442	.set_page = &rs600_gart_set_page,
		1443	},
		1444	.ring = {
5078	serge	1445	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1446	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1447	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1448	},
		1449	.irq = {
		1450	.set = &evergreen_irq_set,
		1451	.process = &evergreen_irq_process,
		1452	},
		1453	.display = {
		1454	.bandwidth_update = &evergreen_bandwidth_update,
		1455	.get_vblank_counter = &evergreen_get_vblank_counter,
		1456	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1457	.set_backlight_level = &atombios_set_backlight_level,
		1458	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1459	},
		1460	.copy = {
5078	serge	1461	.blit = &r600_copy_cpdma,
2997	Serge	1462	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1463	.dma = &evergreen_copy_dma,
		1464	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1465	.copy = &evergreen_copy_dma,
		1466	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1467	},
		1468	.surface = {
		1469	.set_reg = r600_set_surface_reg,
		1470	.clear_reg = r600_clear_surface_reg,
		1471	},
		1472	.hpd = {
5078	serge	1473	.init = &evergreen_hpd_init,
		1474	.fini = &evergreen_hpd_fini,
		1475	.sense = &evergreen_hpd_sense,
		1476	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1477	},
		1478	.pm = {
5078	serge	1479	.misc = &evergreen_pm_misc,
		1480	.prepare = &evergreen_pm_prepare,
		1481	.finish = &evergreen_pm_finish,
		1482	.init_profile = &sumo_pm_init_profile,
		1483	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1484	.get_engine_clock = &radeon_atom_get_engine_clock,
		1485	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1486	.get_memory_clock = NULL,
		1487	.set_memory_clock = NULL,
		1488	.get_pcie_lanes = NULL,
		1489	.set_pcie_lanes = NULL,
		1490	.set_clock_gating = NULL,
3764	Serge	1491	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1492	.get_temperature = &sumo_get_temp,
2997	Serge	1493	},
5078	serge	1494	.dpm = {
		1495	.init = &sumo_dpm_init,
		1496	.setup_asic = &sumo_dpm_setup_asic,
		1497	.enable = &sumo_dpm_enable,
		1498	.late_enable = &sumo_dpm_late_enable,
		1499	.disable = &sumo_dpm_disable,
		1500	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
		1501	.set_power_state = &sumo_dpm_set_power_state,
		1502	.post_set_power_state = &sumo_dpm_post_set_power_state,
		1503	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
		1504	.fini = &sumo_dpm_fini,
		1505	.get_sclk = &sumo_dpm_get_sclk,
		1506	.get_mclk = &sumo_dpm_get_mclk,
		1507	.print_power_state = &sumo_dpm_print_power_state,
		1508	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
		1509	.force_performance_level = &sumo_dpm_force_performance_level,
6104	serge	1510	.get_current_sclk = &sumo_dpm_get_current_sclk,
		1511	.get_current_mclk = &sumo_dpm_get_current_mclk,
5078	serge	1512	},
2997	Serge	1513	.pflip = {
		1514	// .pre_page_flip = &evergreen_pre_page_flip,
		1515	// .page_flip = &evergreen_page_flip,
		1516	},
1986	serge	1517	};
		1518
		1519	static struct radeon_asic btc_asic = {
		1520	.init = &evergreen_init,
6104	serge	1521	.fini = &evergreen_fini,
1990	serge	1522	// .suspend = &evergreen_suspend,
		1523	// .resume = &evergreen_resume,
1986	serge	1524	.asic_reset = &evergreen_asic_reset,
2997	Serge	1525	// .vga_set_state = &r600_vga_set_state,
5078	serge	1526	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1527	.gui_idle = &r600_gui_idle,
		1528	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1529	.get_xclk = &rv770_get_xclk,
		1530	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1531	.get_allowed_info_register = evergreen_get_allowed_info_register,
2997	Serge	1532	.gart = {
		1533	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
6104	serge	1534	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1535	.set_page = &rs600_gart_set_page,
		1536	},
		1537	.ring = {
5078	serge	1538	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1539	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1540	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1541	},
		1542	.irq = {
		1543	.set = &evergreen_irq_set,
		1544	.process = &evergreen_irq_process,
		1545	},
		1546	.display = {
		1547	.bandwidth_update = &evergreen_bandwidth_update,
		1548	.get_vblank_counter = &evergreen_get_vblank_counter,
		1549	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1550	.set_backlight_level = &atombios_set_backlight_level,
		1551	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1552	},
		1553	.copy = {
5078	serge	1554	.blit = &r600_copy_cpdma,
2997	Serge	1555	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1556	.dma = &evergreen_copy_dma,
		1557	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1558	.copy = &evergreen_copy_dma,
		1559	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1560	},
		1561	.surface = {
		1562	.set_reg = r600_set_surface_reg,
		1563	.clear_reg = r600_clear_surface_reg,
		1564	},
		1565	.hpd = {
5078	serge	1566	.init = &evergreen_hpd_init,
		1567	.fini = &evergreen_hpd_fini,
		1568	.sense = &evergreen_hpd_sense,
		1569	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1570	},
		1571	.pm = {
5078	serge	1572	.misc = &evergreen_pm_misc,
		1573	.prepare = &evergreen_pm_prepare,
		1574	.finish = &evergreen_pm_finish,
		1575	.init_profile = &btc_pm_init_profile,
		1576	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1577	.get_engine_clock = &radeon_atom_get_engine_clock,
		1578	.set_engine_clock = &radeon_atom_set_engine_clock,
		1579	.get_memory_clock = &radeon_atom_get_memory_clock,
		1580	.set_memory_clock = &radeon_atom_set_memory_clock,
		1581	.get_pcie_lanes = &r600_get_pcie_lanes,
		1582	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1583	.set_clock_gating = NULL,
3764	Serge	1584	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1585	.get_temperature = &evergreen_get_temp,
2997	Serge	1586	},
5078	serge	1587	.dpm = {
		1588	.init = &btc_dpm_init,
		1589	.setup_asic = &btc_dpm_setup_asic,
		1590	.enable = &btc_dpm_enable,
		1591	.late_enable = &rv770_dpm_late_enable,
		1592	.disable = &btc_dpm_disable,
		1593	.pre_set_power_state = &btc_dpm_pre_set_power_state,
		1594	.set_power_state = &btc_dpm_set_power_state,
		1595	.post_set_power_state = &btc_dpm_post_set_power_state,
		1596	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1597	.fini = &btc_dpm_fini,
		1598	.get_sclk = &btc_dpm_get_sclk,
		1599	.get_mclk = &btc_dpm_get_mclk,
		1600	.print_power_state = &rv770_dpm_print_power_state,
		1601	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
		1602	.force_performance_level = &rv770_dpm_force_performance_level,
		1603	.vblank_too_short = &btc_dpm_vblank_too_short,
6104	serge	1604	.get_current_sclk = &btc_dpm_get_current_sclk,
		1605	.get_current_mclk = &btc_dpm_get_current_mclk,
5078	serge	1606	},
2997	Serge	1607	.pflip = {
		1608	// .pre_page_flip = &evergreen_pre_page_flip,
		1609	// .page_flip = &evergreen_page_flip,
		1610	},
1986	serge	1611	};
		1612
5078	serge	1613	static struct radeon_asic_ring cayman_gfx_ring = {
		1614	.ib_execute = &cayman_ring_ib_execute,
		1615	.ib_parse = &evergreen_ib_parse,
		1616	.emit_fence = &cayman_fence_ring_emit,
		1617	.emit_semaphore = &r600_semaphore_ring_emit,
		1618	.cs_parse = &evergreen_cs_parse,
		1619	.ring_test = &r600_ring_test,
		1620	.ib_test = &r600_ib_test,
		1621	.is_lockup = &cayman_gfx_is_lockup,
		1622	.vm_flush = &cayman_vm_flush,
		1623	.get_rptr = &cayman_gfx_get_rptr,
		1624	.get_wptr = &cayman_gfx_get_wptr,
		1625	.set_wptr = &cayman_gfx_set_wptr,
		1626	};
		1627
		1628	static struct radeon_asic_ring cayman_dma_ring = {
		1629	.ib_execute = &cayman_dma_ring_ib_execute,
		1630	.ib_parse = &evergreen_dma_ib_parse,
		1631	.emit_fence = &evergreen_dma_fence_ring_emit,
		1632	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1633	.cs_parse = &evergreen_dma_cs_parse,
		1634	.ring_test = &r600_dma_ring_test,
		1635	.ib_test = &r600_dma_ib_test,
		1636	.is_lockup = &cayman_dma_is_lockup,
		1637	.vm_flush = &cayman_dma_vm_flush,
		1638	.get_rptr = &cayman_dma_get_rptr,
		1639	.get_wptr = &cayman_dma_get_wptr,
		1640	.set_wptr = &cayman_dma_set_wptr
		1641	};
		1642
		1643	static struct radeon_asic_ring cayman_uvd_ring = {
		1644	.ib_execute = &uvd_v1_0_ib_execute,
		1645	.emit_fence = &uvd_v2_2_fence_emit,
		1646	.emit_semaphore = &uvd_v3_1_semaphore_emit,
		1647	.cs_parse = &radeon_uvd_cs_parse,
		1648	.ring_test = &uvd_v1_0_ring_test,
		1649	.ib_test = &uvd_v1_0_ib_test,
		1650	.is_lockup = &radeon_ring_test_lockup,
		1651	.get_rptr = &uvd_v1_0_get_rptr,
		1652	.get_wptr = &uvd_v1_0_get_wptr,
		1653	.set_wptr = &uvd_v1_0_set_wptr,
		1654	};
		1655
1986	serge	1656	static struct radeon_asic cayman_asic = {
		1657	.init = &cayman_init,
6104	serge	1658	.fini = &cayman_fini,
2997	Serge	1659	// .suspend = &cayman_suspend,
		1660	// .resume = &cayman_resume,
1986	serge	1661	.asic_reset = &cayman_asic_reset,
2997	Serge	1662	// .vga_set_state = &r600_vga_set_state,
5078	serge	1663	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1664	.gui_idle = &r600_gui_idle,
		1665	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1666	.get_xclk = &rv770_get_xclk,
		1667	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1668	.get_allowed_info_register = cayman_get_allowed_info_register,
2997	Serge	1669	.gart = {
		1670	.tlb_flush = &cayman_pcie_gart_tlb_flush,
6104	serge	1671	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1672	.set_page = &rs600_gart_set_page,
		1673	},
		1674	.vm = {
		1675	.init = &cayman_vm_init,
		1676	.fini = &cayman_vm_fini,
5078	serge	1677	.copy_pages = &cayman_dma_vm_copy_pages,
		1678	.write_pages = &cayman_dma_vm_write_pages,
		1679	.set_pages = &cayman_dma_vm_set_pages,
		1680	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1681	},
		1682	.ring = {
5078	serge	1683	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1684	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1685	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1686	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1687	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1688	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1689	},
		1690	.irq = {
		1691	.set = &evergreen_irq_set,
		1692	.process = &evergreen_irq_process,
		1693	},
		1694	.display = {
		1695	.bandwidth_update = &evergreen_bandwidth_update,
		1696	.get_vblank_counter = &evergreen_get_vblank_counter,
		1697	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1698	.set_backlight_level = &atombios_set_backlight_level,
		1699	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1700	},
		1701	.copy = {
5078	serge	1702	.blit = &r600_copy_cpdma,
2997	Serge	1703	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1704	.dma = &evergreen_copy_dma,
		1705	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1706	.copy = &evergreen_copy_dma,
		1707	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1708	},
		1709	.surface = {
		1710	.set_reg = r600_set_surface_reg,
		1711	.clear_reg = r600_clear_surface_reg,
		1712	},
		1713	.hpd = {
5078	serge	1714	.init = &evergreen_hpd_init,
		1715	.fini = &evergreen_hpd_fini,
		1716	.sense = &evergreen_hpd_sense,
		1717	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1718	},
		1719	.pm = {
5078	serge	1720	.misc = &evergreen_pm_misc,
		1721	.prepare = &evergreen_pm_prepare,
		1722	.finish = &evergreen_pm_finish,
		1723	.init_profile = &btc_pm_init_profile,
		1724	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1725	.get_engine_clock = &radeon_atom_get_engine_clock,
		1726	.set_engine_clock = &radeon_atom_set_engine_clock,
		1727	.get_memory_clock = &radeon_atom_get_memory_clock,
		1728	.set_memory_clock = &radeon_atom_set_memory_clock,
		1729	.get_pcie_lanes = &r600_get_pcie_lanes,
		1730	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1731	.set_clock_gating = NULL,
3764	Serge	1732	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1733	.get_temperature = &evergreen_get_temp,
2997	Serge	1734	},
5078	serge	1735	.dpm = {
		1736	.init = &ni_dpm_init,
		1737	.setup_asic = &ni_dpm_setup_asic,
		1738	.enable = &ni_dpm_enable,
		1739	.late_enable = &rv770_dpm_late_enable,
		1740	.disable = &ni_dpm_disable,
		1741	.pre_set_power_state = &ni_dpm_pre_set_power_state,
		1742	.set_power_state = &ni_dpm_set_power_state,
		1743	.post_set_power_state = &ni_dpm_post_set_power_state,
		1744	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1745	.fini = &ni_dpm_fini,
		1746	.get_sclk = &ni_dpm_get_sclk,
		1747	.get_mclk = &ni_dpm_get_mclk,
		1748	.print_power_state = &ni_dpm_print_power_state,
		1749	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
		1750	.force_performance_level = &ni_dpm_force_performance_level,
		1751	.vblank_too_short = &ni_dpm_vblank_too_short,
6104	serge	1752	.get_current_sclk = &ni_dpm_get_current_sclk,
		1753	.get_current_mclk = &ni_dpm_get_current_mclk,
5078	serge	1754	},
2997	Serge	1755	.pflip = {
		1756	// .pre_page_flip = &evergreen_pre_page_flip,
		1757	// .page_flip = &evergreen_page_flip,
		1758	},
1963	serge	1759	};
		1760
6104	serge	1761	static struct radeon_asic_ring trinity_vce_ring = {
		1762	.ib_execute = &radeon_vce_ib_execute,
		1763	.emit_fence = &radeon_vce_fence_emit,
		1764	.emit_semaphore = &radeon_vce_semaphore_emit,
		1765	.cs_parse = &radeon_vce_cs_parse,
		1766	.ring_test = &radeon_vce_ring_test,
		1767	.ib_test = &radeon_vce_ib_test,
		1768	.is_lockup = &radeon_ring_test_lockup,
		1769	.get_rptr = &vce_v1_0_get_rptr,
		1770	.get_wptr = &vce_v1_0_get_wptr,
		1771	.set_wptr = &vce_v1_0_set_wptr,
		1772	};
		1773
2997	Serge	1774	static struct radeon_asic trinity_asic = {
		1775	.init = &cayman_init,
6104	serge	1776	.fini = &cayman_fini,
2997	Serge	1777	// .suspend = &cayman_suspend,
		1778	// .resume = &cayman_resume,
		1779	.asic_reset = &cayman_asic_reset,
		1780	// .vga_set_state = &r600_vga_set_state,
5078	serge	1781	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1782	.gui_idle = &r600_gui_idle,
		1783	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1784	.get_xclk = &r600_get_xclk,
		1785	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
6104	serge	1786	.get_allowed_info_register = cayman_get_allowed_info_register,
2997	Serge	1787	.gart = {
		1788	.tlb_flush = &cayman_pcie_gart_tlb_flush,
6104	serge	1789	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1790	.set_page = &rs600_gart_set_page,
		1791	},
		1792	.vm = {
		1793	.init = &cayman_vm_init,
		1794	.fini = &cayman_vm_fini,
5078	serge	1795	.copy_pages = &cayman_dma_vm_copy_pages,
		1796	.write_pages = &cayman_dma_vm_write_pages,
		1797	.set_pages = &cayman_dma_vm_set_pages,
		1798	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1799	},
		1800	.ring = {
5078	serge	1801	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1802	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1803	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1804	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1805	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1806	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
6104	serge	1807	[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		1808	[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
2997	Serge	1809	},
		1810	.irq = {
		1811	.set = &evergreen_irq_set,
		1812	.process = &evergreen_irq_process,
		1813	},
		1814	.display = {
		1815	.bandwidth_update = &dce6_bandwidth_update,
		1816	.get_vblank_counter = &evergreen_get_vblank_counter,
		1817	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1818	.set_backlight_level = &atombios_set_backlight_level,
		1819	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1820	},
		1821	.copy = {
5078	serge	1822	.blit = &r600_copy_cpdma,
2997	Serge	1823	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1824	.dma = &evergreen_copy_dma,
		1825	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1826	.copy = &evergreen_copy_dma,
		1827	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1828	},
		1829	.surface = {
		1830	.set_reg = r600_set_surface_reg,
		1831	.clear_reg = r600_clear_surface_reg,
		1832	},
		1833	.hpd = {
5078	serge	1834	.init = &evergreen_hpd_init,
		1835	.fini = &evergreen_hpd_fini,
		1836	.sense = &evergreen_hpd_sense,
		1837	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1838	},
		1839	.pm = {
5078	serge	1840	.misc = &evergreen_pm_misc,
		1841	.prepare = &evergreen_pm_prepare,
		1842	.finish = &evergreen_pm_finish,
		1843	.init_profile = &sumo_pm_init_profile,
		1844	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1845	.get_engine_clock = &radeon_atom_get_engine_clock,
		1846	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1847	.get_memory_clock = NULL,
		1848	.set_memory_clock = NULL,
		1849	.get_pcie_lanes = NULL,
		1850	.set_pcie_lanes = NULL,
		1851	.set_clock_gating = NULL,
3764	Serge	1852	.set_uvd_clocks = &sumo_set_uvd_clocks,
6104	serge	1853	.set_vce_clocks = &tn_set_vce_clocks,
5078	serge	1854	.get_temperature = &tn_get_temp,
2997	Serge	1855	},
5078	serge	1856	.dpm = {
		1857	.init = &trinity_dpm_init,
		1858	.setup_asic = &trinity_dpm_setup_asic,
		1859	.enable = &trinity_dpm_enable,
		1860	.late_enable = &trinity_dpm_late_enable,
		1861	.disable = &trinity_dpm_disable,
		1862	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
		1863	.set_power_state = &trinity_dpm_set_power_state,
		1864	.post_set_power_state = &trinity_dpm_post_set_power_state,
		1865	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
		1866	.fini = &trinity_dpm_fini,
		1867	.get_sclk = &trinity_dpm_get_sclk,
		1868	.get_mclk = &trinity_dpm_get_mclk,
		1869	.print_power_state = &trinity_dpm_print_power_state,
		1870	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
		1871	.force_performance_level = &trinity_dpm_force_performance_level,
		1872	.enable_bapm = &trinity_dpm_enable_bapm,
6104	serge	1873	.get_current_sclk = &trinity_dpm_get_current_sclk,
		1874	.get_current_mclk = &trinity_dpm_get_current_mclk,
5078	serge	1875	},
2997	Serge	1876	.pflip = {
		1877	// .pre_page_flip = &evergreen_pre_page_flip,
		1878	// .page_flip = &evergreen_page_flip,
		1879	},
		1880	};
		1881
5078	serge	1882	static struct radeon_asic_ring si_gfx_ring = {
		1883	.ib_execute = &si_ring_ib_execute,
		1884	.ib_parse = &si_ib_parse,
		1885	.emit_fence = &si_fence_ring_emit,
		1886	.emit_semaphore = &r600_semaphore_ring_emit,
		1887	.cs_parse = NULL,
		1888	.ring_test = &r600_ring_test,
		1889	.ib_test = &r600_ib_test,
		1890	.is_lockup = &si_gfx_is_lockup,
		1891	.vm_flush = &si_vm_flush,
		1892	.get_rptr = &cayman_gfx_get_rptr,
		1893	.get_wptr = &cayman_gfx_get_wptr,
		1894	.set_wptr = &cayman_gfx_set_wptr,
		1895	};
		1896
		1897	static struct radeon_asic_ring si_dma_ring = {
		1898	.ib_execute = &cayman_dma_ring_ib_execute,
		1899	.ib_parse = &evergreen_dma_ib_parse,
		1900	.emit_fence = &evergreen_dma_fence_ring_emit,
		1901	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1902	.cs_parse = NULL,
		1903	.ring_test = &r600_dma_ring_test,
		1904	.ib_test = &r600_dma_ib_test,
		1905	.is_lockup = &si_dma_is_lockup,
		1906	.vm_flush = &si_dma_vm_flush,
		1907	.get_rptr = &cayman_dma_get_rptr,
		1908	.get_wptr = &cayman_dma_get_wptr,
		1909	.set_wptr = &cayman_dma_set_wptr,
		1910	};
		1911
2997	Serge	1912	static struct radeon_asic si_asic = {
		1913	.init = &si_init,
6104	serge	1914	.fini = &si_fini,
2997	Serge	1915	// .suspend = &si_suspend,
6104	serge	1916	.resume = &si_resume,
2997	Serge	1917	.asic_reset = &si_asic_reset,
		1918	// .vga_set_state = &r600_vga_set_state,
5078	serge	1919	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1920	.gui_idle = &r600_gui_idle,
		1921	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1922	.get_xclk = &si_get_xclk,
		1923	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
6104	serge	1924	.get_allowed_info_register = si_get_allowed_info_register,
2997	Serge	1925	.gart = {
		1926	.tlb_flush = &si_pcie_gart_tlb_flush,
6104	serge	1927	.get_page_entry = &rs600_gart_get_page_entry,
2997	Serge	1928	.set_page = &rs600_gart_set_page,
		1929	},
		1930	.vm = {
		1931	.init = &si_vm_init,
		1932	.fini = &si_vm_fini,
5078	serge	1933	.copy_pages = &si_dma_vm_copy_pages,
		1934	.write_pages = &si_dma_vm_write_pages,
		1935	.set_pages = &si_dma_vm_set_pages,
		1936	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1937	},
		1938	.ring = {
5078	serge	1939	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
		1940	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
		1941	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
		1942	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
		1943	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
		1944	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
6104	serge	1945	[TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
		1946	[TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
2997	Serge	1947	},
		1948	.irq = {
		1949	.set = &si_irq_set,
		1950	.process = &si_irq_process,
		1951	},
		1952	.display = {
		1953	.bandwidth_update = &dce6_bandwidth_update,
		1954	.get_vblank_counter = &evergreen_get_vblank_counter,
		1955	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1956	.set_backlight_level = &atombios_set_backlight_level,
		1957	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	1958	},
		1959	.copy = {
5078	serge	1960	.blit = &r600_copy_cpdma,
2997	Serge	1961	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1962	.dma = &si_copy_dma,
		1963	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1964	.copy = &si_copy_dma,
		1965	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1966	},
		1967	.surface = {
		1968	.set_reg = r600_set_surface_reg,
		1969	.clear_reg = r600_clear_surface_reg,
		1970	},
		1971	.hpd = {
		1972	.init = &evergreen_hpd_init,
		1973	.fini = &evergreen_hpd_fini,
		1974	.sense = &evergreen_hpd_sense,
		1975	.set_polarity = &evergreen_hpd_set_polarity,
		1976	},
		1977	.pm = {
5078	serge	1978	.misc = &evergreen_pm_misc,
		1979	.prepare = &evergreen_pm_prepare,
		1980	.finish = &evergreen_pm_finish,
		1981	.init_profile = &sumo_pm_init_profile,
		1982	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1983	.get_engine_clock = &radeon_atom_get_engine_clock,
		1984	.set_engine_clock = &radeon_atom_set_engine_clock,
		1985	.get_memory_clock = &radeon_atom_get_memory_clock,
		1986	.set_memory_clock = &radeon_atom_set_memory_clock,
		1987	.get_pcie_lanes = &r600_get_pcie_lanes,
		1988	.set_pcie_lanes = &r600_set_pcie_lanes,
		1989	.set_clock_gating = NULL,
		1990	.set_uvd_clocks = &si_set_uvd_clocks,
6104	serge	1991	.set_vce_clocks = &si_set_vce_clocks,
5078	serge	1992	.get_temperature = &si_get_temp,
		1993	},
		1994	.dpm = {
		1995	.init = &si_dpm_init,
		1996	.setup_asic = &si_dpm_setup_asic,
		1997	.enable = &si_dpm_enable,
		1998	.late_enable = &si_dpm_late_enable,
		1999	.disable = &si_dpm_disable,
		2000	.pre_set_power_state = &si_dpm_pre_set_power_state,
		2001	.set_power_state = &si_dpm_set_power_state,
		2002	.post_set_power_state = &si_dpm_post_set_power_state,
		2003	.display_configuration_changed = &si_dpm_display_configuration_changed,
		2004	.fini = &si_dpm_fini,
		2005	.get_sclk = &ni_dpm_get_sclk,
		2006	.get_mclk = &ni_dpm_get_mclk,
		2007	.print_power_state = &ni_dpm_print_power_state,
		2008	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
		2009	.force_performance_level = &si_dpm_force_performance_level,
		2010	.vblank_too_short = &ni_dpm_vblank_too_short,
6104	serge	2011	.fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
		2012	.fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
		2013	.get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
		2014	.set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
		2015	.get_current_sclk = &si_dpm_get_current_sclk,
		2016	.get_current_mclk = &si_dpm_get_current_mclk,
5078	serge	2017	},
		2018	.pflip = {
		2019	// .pre_page_flip = &evergreen_pre_page_flip,
		2020	// .page_flip = &evergreen_page_flip,
		2021	},
		2022	};
		2023
		2024	static struct radeon_asic_ring ci_gfx_ring = {
		2025	.ib_execute = &cik_ring_ib_execute,
		2026	.ib_parse = &cik_ib_parse,
		2027	.emit_fence = &cik_fence_gfx_ring_emit,
		2028	.emit_semaphore = &cik_semaphore_ring_emit,
		2029	.cs_parse = NULL,
		2030	.ring_test = &cik_ring_test,
		2031	.ib_test = &cik_ib_test,
		2032	.is_lockup = &cik_gfx_is_lockup,
		2033	.vm_flush = &cik_vm_flush,
		2034	.get_rptr = &cik_gfx_get_rptr,
		2035	.get_wptr = &cik_gfx_get_wptr,
		2036	.set_wptr = &cik_gfx_set_wptr,
		2037	};
		2038
		2039	static struct radeon_asic_ring ci_cp_ring = {
		2040	.ib_execute = &cik_ring_ib_execute,
		2041	.ib_parse = &cik_ib_parse,
		2042	.emit_fence = &cik_fence_compute_ring_emit,
		2043	.emit_semaphore = &cik_semaphore_ring_emit,
		2044	.cs_parse = NULL,
		2045	.ring_test = &cik_ring_test,
		2046	.ib_test = &cik_ib_test,
		2047	.is_lockup = &cik_gfx_is_lockup,
		2048	.vm_flush = &cik_vm_flush,
		2049	.get_rptr = &cik_compute_get_rptr,
		2050	.get_wptr = &cik_compute_get_wptr,
		2051	.set_wptr = &cik_compute_set_wptr,
		2052	};
		2053
		2054	static struct radeon_asic_ring ci_dma_ring = {
		2055	.ib_execute = &cik_sdma_ring_ib_execute,
		2056	.ib_parse = &cik_ib_parse,
		2057	.emit_fence = &cik_sdma_fence_ring_emit,
		2058	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
		2059	.cs_parse = NULL,
		2060	.ring_test = &cik_sdma_ring_test,
		2061	.ib_test = &cik_sdma_ib_test,
		2062	.is_lockup = &cik_sdma_is_lockup,
		2063	.vm_flush = &cik_dma_vm_flush,
		2064	.get_rptr = &cik_sdma_get_rptr,
		2065	.get_wptr = &cik_sdma_get_wptr,
		2066	.set_wptr = &cik_sdma_set_wptr,
		2067	};
		2068
		2069	static struct radeon_asic_ring ci_vce_ring = {
		2070	.ib_execute = &radeon_vce_ib_execute,
		2071	.emit_fence = &radeon_vce_fence_emit,
		2072	.emit_semaphore = &radeon_vce_semaphore_emit,
		2073	.cs_parse = &radeon_vce_cs_parse,
		2074	.ring_test = &radeon_vce_ring_test,
		2075	.ib_test = &radeon_vce_ib_test,
		2076	.is_lockup = &radeon_ring_test_lockup,
		2077	.get_rptr = &vce_v1_0_get_rptr,
		2078	.get_wptr = &vce_v1_0_get_wptr,
		2079	.set_wptr = &vce_v1_0_set_wptr,
		2080	};
		2081
		2082	static struct radeon_asic ci_asic = {
		2083	.init = &cik_init,
6104	serge	2084	.fini = &cik_fini,
		2085	// .suspend = &cik_suspend,
		2086	// .resume = &cik_resume,
5078	serge	2087	.asic_reset = &cik_asic_reset,
		2088	// .vga_set_state = &r600_vga_set_state,
		2089	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2090	.gui_idle = &r600_gui_idle,
		2091	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2092	.get_xclk = &cik_get_xclk,
		2093	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
6104	serge	2094	.get_allowed_info_register = cik_get_allowed_info_register,
5078	serge	2095	.gart = {
		2096	.tlb_flush = &cik_pcie_gart_tlb_flush,
6104	serge	2097	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	2098	.set_page = &rs600_gart_set_page,
		2099	},
		2100	.vm = {
		2101	.init = &cik_vm_init,
		2102	.fini = &cik_vm_fini,
		2103	.copy_pages = &cik_sdma_vm_copy_pages,
		2104	.write_pages = &cik_sdma_vm_write_pages,
		2105	.set_pages = &cik_sdma_vm_set_pages,
		2106	.pad_ib = &cik_sdma_vm_pad_ib,
		2107	},
		2108	.ring = {
		2109	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2110	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2111	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2112	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2113	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2114	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2115	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2116	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2117	},
		2118	.irq = {
		2119	.set = &cik_irq_set,
		2120	.process = &cik_irq_process,
		2121	},
		2122	.display = {
		2123	.bandwidth_update = &dce8_bandwidth_update,
		2124	.get_vblank_counter = &evergreen_get_vblank_counter,
		2125	.wait_for_vblank = &dce4_wait_for_vblank,
		2126	.set_backlight_level = &atombios_set_backlight_level,
		2127	.get_backlight_level = &atombios_get_backlight_level,
		2128	},
		2129	.copy = {
		2130	.blit = &cik_copy_cpdma,
		2131	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2132	.dma = &cik_copy_dma,
		2133	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2134	.copy = &cik_copy_dma,
		2135	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2136	},
		2137	.surface = {
		2138	.set_reg = r600_set_surface_reg,
		2139	.clear_reg = r600_clear_surface_reg,
		2140	},
		2141	.hpd = {
		2142	.init = &evergreen_hpd_init,
		2143	.fini = &evergreen_hpd_fini,
		2144	.sense = &evergreen_hpd_sense,
		2145	.set_polarity = &evergreen_hpd_set_polarity,
		2146	},
		2147	.pm = {
		2148	.misc = &evergreen_pm_misc,
		2149	.prepare = &evergreen_pm_prepare,
		2150	.finish = &evergreen_pm_finish,
		2151	.init_profile = &sumo_pm_init_profile,
		2152	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2153	.get_engine_clock = &radeon_atom_get_engine_clock,
		2154	.set_engine_clock = &radeon_atom_set_engine_clock,
		2155	.get_memory_clock = &radeon_atom_get_memory_clock,
		2156	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	2157	.get_pcie_lanes = NULL,
		2158	.set_pcie_lanes = NULL,
		2159	.set_clock_gating = NULL,
5078	serge	2160	.set_uvd_clocks = &cik_set_uvd_clocks,
		2161	.set_vce_clocks = &cik_set_vce_clocks,
		2162	.get_temperature = &ci_get_temp,
2997	Serge	2163	},
5078	serge	2164	.dpm = {
		2165	.init = &ci_dpm_init,
		2166	.setup_asic = &ci_dpm_setup_asic,
		2167	.enable = &ci_dpm_enable,
		2168	.late_enable = &ci_dpm_late_enable,
		2169	.disable = &ci_dpm_disable,
		2170	.pre_set_power_state = &ci_dpm_pre_set_power_state,
		2171	.set_power_state = &ci_dpm_set_power_state,
		2172	.post_set_power_state = &ci_dpm_post_set_power_state,
		2173	.display_configuration_changed = &ci_dpm_display_configuration_changed,
		2174	.fini = &ci_dpm_fini,
		2175	.get_sclk = &ci_dpm_get_sclk,
		2176	.get_mclk = &ci_dpm_get_mclk,
		2177	.print_power_state = &ci_dpm_print_power_state,
		2178	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
		2179	.force_performance_level = &ci_dpm_force_performance_level,
		2180	.vblank_too_short = &ci_dpm_vblank_too_short,
		2181	.powergate_uvd = &ci_dpm_powergate_uvd,
6104	serge	2182	.fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
		2183	.fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
		2184	.get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
		2185	.set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
		2186	.get_current_sclk = &ci_dpm_get_current_sclk,
		2187	.get_current_mclk = &ci_dpm_get_current_mclk,
5078	serge	2188	},
2997	Serge	2189	.pflip = {
		2190	// .pre_page_flip = &evergreen_pre_page_flip,
		2191	// .page_flip = &evergreen_page_flip,
		2192	},
		2193	};
		2194
5078	serge	2195	static struct radeon_asic kv_asic = {
		2196	.init = &cik_init,
6104	serge	2197	.fini = &cik_fini,
		2198	// .suspend = &cik_suspend,
		2199	// .resume = &cik_resume,
5078	serge	2200	.asic_reset = &cik_asic_reset,
		2201	// .vga_set_state = &r600_vga_set_state,
		2202	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2203	.gui_idle = &r600_gui_idle,
		2204	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2205	.get_xclk = &cik_get_xclk,
		2206	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
6104	serge	2207	.get_allowed_info_register = cik_get_allowed_info_register,
5078	serge	2208	.gart = {
		2209	.tlb_flush = &cik_pcie_gart_tlb_flush,
6104	serge	2210	.get_page_entry = &rs600_gart_get_page_entry,
5078	serge	2211	.set_page = &rs600_gart_set_page,
		2212	},
		2213	.vm = {
		2214	.init = &cik_vm_init,
		2215	.fini = &cik_vm_fini,
		2216	.copy_pages = &cik_sdma_vm_copy_pages,
		2217	.write_pages = &cik_sdma_vm_write_pages,
		2218	.set_pages = &cik_sdma_vm_set_pages,
		2219	.pad_ib = &cik_sdma_vm_pad_ib,
		2220	},
		2221	.ring = {
		2222	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2223	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2224	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2225	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2226	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2227	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2228	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2229	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2230	},
		2231	.irq = {
		2232	.set = &cik_irq_set,
		2233	.process = &cik_irq_process,
		2234	},
		2235	.display = {
		2236	.bandwidth_update = &dce8_bandwidth_update,
		2237	.get_vblank_counter = &evergreen_get_vblank_counter,
		2238	.wait_for_vblank = &dce4_wait_for_vblank,
		2239	.set_backlight_level = &atombios_set_backlight_level,
		2240	.get_backlight_level = &atombios_get_backlight_level,
		2241	},
		2242	.copy = {
		2243	.blit = &cik_copy_cpdma,
		2244	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2245	.dma = &cik_copy_dma,
		2246	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2247	.copy = &cik_copy_dma,
		2248	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2249	},
		2250	.surface = {
		2251	.set_reg = r600_set_surface_reg,
		2252	.clear_reg = r600_clear_surface_reg,
		2253	},
		2254	.hpd = {
		2255	.init = &evergreen_hpd_init,
		2256	.fini = &evergreen_hpd_fini,
		2257	.sense = &evergreen_hpd_sense,
		2258	.set_polarity = &evergreen_hpd_set_polarity,
		2259	},
		2260	.pm = {
		2261	.misc = &evergreen_pm_misc,
		2262	.prepare = &evergreen_pm_prepare,
		2263	.finish = &evergreen_pm_finish,
		2264	.init_profile = &sumo_pm_init_profile,
		2265	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2266	.get_engine_clock = &radeon_atom_get_engine_clock,
		2267	.set_engine_clock = &radeon_atom_set_engine_clock,
		2268	.get_memory_clock = &radeon_atom_get_memory_clock,
		2269	.set_memory_clock = &radeon_atom_set_memory_clock,
		2270	.get_pcie_lanes = NULL,
		2271	.set_pcie_lanes = NULL,
		2272	.set_clock_gating = NULL,
		2273	.set_uvd_clocks = &cik_set_uvd_clocks,
		2274	.set_vce_clocks = &cik_set_vce_clocks,
		2275	.get_temperature = &kv_get_temp,
		2276	},
		2277	.dpm = {
		2278	.init = &kv_dpm_init,
		2279	.setup_asic = &kv_dpm_setup_asic,
		2280	.enable = &kv_dpm_enable,
		2281	.late_enable = &kv_dpm_late_enable,
		2282	.disable = &kv_dpm_disable,
		2283	.pre_set_power_state = &kv_dpm_pre_set_power_state,
		2284	.set_power_state = &kv_dpm_set_power_state,
		2285	.post_set_power_state = &kv_dpm_post_set_power_state,
		2286	.display_configuration_changed = &kv_dpm_display_configuration_changed,
		2287	.fini = &kv_dpm_fini,
		2288	.get_sclk = &kv_dpm_get_sclk,
		2289	.get_mclk = &kv_dpm_get_mclk,
		2290	.print_power_state = &kv_dpm_print_power_state,
		2291	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
		2292	.force_performance_level = &kv_dpm_force_performance_level,
		2293	.powergate_uvd = &kv_dpm_powergate_uvd,
		2294	.enable_bapm = &kv_dpm_enable_bapm,
6104	serge	2295	.get_current_sclk = &kv_dpm_get_current_sclk,
		2296	.get_current_mclk = &kv_dpm_get_current_mclk,
5078	serge	2297	},
		2298	.pflip = {
		2299	// .pre_page_flip = &evergreen_pre_page_flip,
		2300	// .page_flip = &evergreen_page_flip,
		2301	},
		2302	};
		2303
2997	Serge	2304	/**
		2305	* radeon_asic_init - register asic specific callbacks
		2306	*
		2307	* @rdev: radeon device pointer
		2308	*
		2309	* Registers the appropriate asic specific callbacks for each
		2310	* chip family. Also sets other asics specific info like the number
		2311	* of crtcs and the register aperture accessors (all asics).
		2312	* Returns 0 for success.
		2313	*/
1963	serge	2314	int radeon_asic_init(struct radeon_device *rdev)
		2315	{
		2316	radeon_register_accessor_init(rdev);
1986	serge	2317
		2318	/* set the number of crtcs */
		2319	if (rdev->flags & RADEON_SINGLE_CRTC)
		2320	rdev->num_crtc = 1;
		2321	else
		2322	rdev->num_crtc = 2;
		2323
3764	Serge	2324	rdev->has_uvd = false;
		2325
1963	serge	2326	switch (rdev->family) {
		2327	case CHIP_R100:
		2328	case CHIP_RV100:
		2329	case CHIP_RS100:
		2330	case CHIP_RV200:
		2331	case CHIP_RS200:
		2332	rdev->asic = &r100_asic;
		2333	break;
		2334	case CHIP_R200:
		2335	case CHIP_RV250:
		2336	case CHIP_RS300:
		2337	case CHIP_RV280:
		2338	rdev->asic = &r200_asic;
		2339	break;
		2340	case CHIP_R300:
		2341	case CHIP_R350:
		2342	case CHIP_RV350:
		2343	case CHIP_RV380:
		2344	if (rdev->flags & RADEON_IS_PCIE)
		2345	rdev->asic = &r300_asic_pcie;
		2346	else
		2347	rdev->asic = &r300_asic;
		2348	break;
		2349	case CHIP_R420:
		2350	case CHIP_R423:
		2351	case CHIP_RV410:
		2352	rdev->asic = &r420_asic;
		2353	/* handle macs */
		2354	if (rdev->bios == NULL) {
2997	Serge	2355	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
		2356	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
		2357	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
		2358	rdev->asic->pm.set_memory_clock = NULL;
		2359	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1963	serge	2360	}
		2361	break;
		2362	case CHIP_RS400:
		2363	case CHIP_RS480:
		2364	rdev->asic = &rs400_asic;
		2365	break;
		2366	case CHIP_RS600:
		2367	rdev->asic = &rs600_asic;
		2368	break;
		2369	case CHIP_RS690:
		2370	case CHIP_RS740:
		2371	rdev->asic = &rs690_asic;
		2372	break;
		2373	case CHIP_RV515:
		2374	rdev->asic = &rv515_asic;
		2375	break;
		2376	case CHIP_R520:
		2377	case CHIP_RV530:
		2378	case CHIP_RV560:
		2379	case CHIP_RV570:
		2380	case CHIP_R580:
		2381	rdev->asic = &r520_asic;
		2382	break;
		2383	case CHIP_R600:
5078	serge	2384	rdev->asic = &r600_asic;
		2385	break;
1963	serge	2386	case CHIP_RV610:
		2387	case CHIP_RV630:
		2388	case CHIP_RV620:
		2389	case CHIP_RV635:
		2390	case CHIP_RV670:
5078	serge	2391	rdev->asic = &rv6xx_asic;
6104	serge	2392	rdev->has_uvd = true;
1963	serge	2393	break;
		2394	case CHIP_RS780:
		2395	case CHIP_RS880:
		2396	rdev->asic = &rs780_asic;
5271	serge	2397	/* 760G/780V/880V don't have UVD */
		2398	if ((rdev->pdev->device == 0x9616)\|\|
		2399	(rdev->pdev->device == 0x9611)\|\|
		2400	(rdev->pdev->device == 0x9613)\|\|
		2401	(rdev->pdev->device == 0x9711)\|\|
		2402	(rdev->pdev->device == 0x9713))
		2403	rdev->has_uvd = false;
		2404	else
6104	serge	2405	rdev->has_uvd = true;
1963	serge	2406	break;
		2407	case CHIP_RV770:
		2408	case CHIP_RV730:
		2409	case CHIP_RV710:
		2410	case CHIP_RV740:
		2411	rdev->asic = &rv770_asic;
3764	Serge	2412	rdev->has_uvd = true;
1963	serge	2413	break;
1986	serge	2414	case CHIP_CEDAR:
		2415	case CHIP_REDWOOD:
		2416	case CHIP_JUNIPER:
		2417	case CHIP_CYPRESS:
		2418	case CHIP_HEMLOCK:
		2419	/* set num crtcs */
		2420	if (rdev->family == CHIP_CEDAR)
		2421	rdev->num_crtc = 4;
		2422	else
		2423	rdev->num_crtc = 6;
		2424	rdev->asic = &evergreen_asic;
3764	Serge	2425	rdev->has_uvd = true;
1986	serge	2426	break;
1990	serge	2427	case CHIP_PALM:
		2428	case CHIP_SUMO:
		2429	case CHIP_SUMO2:
		2430	rdev->asic = &sumo_asic;
3764	Serge	2431	rdev->has_uvd = true;
1990	serge	2432	break;
		2433	case CHIP_BARTS:
		2434	case CHIP_TURKS:
		2435	case CHIP_CAICOS:
		2436	/* set num crtcs */
		2437	if (rdev->family == CHIP_CAICOS)
		2438	rdev->num_crtc = 4;
		2439	else
		2440	rdev->num_crtc = 6;
		2441	rdev->asic = &btc_asic;
3764	Serge	2442	rdev->has_uvd = true;
1990	serge	2443	break;
2004	serge	2444	case CHIP_CAYMAN:
		2445	rdev->asic = &cayman_asic;
		2446	/* set num crtcs */
		2447	rdev->num_crtc = 6;
3764	Serge	2448	rdev->has_uvd = true;
2004	serge	2449	break;
2997	Serge	2450	case CHIP_ARUBA:
		2451	rdev->asic = &trinity_asic;
		2452	/* set num crtcs */
		2453	rdev->num_crtc = 4;
3764	Serge	2454	rdev->has_uvd = true;
6104	serge	2455	rdev->cg_flags =
		2456	RADEON_CG_SUPPORT_VCE_MGCG;
2997	Serge	2457	break;
		2458	case CHIP_TAHITI:
		2459	case CHIP_PITCAIRN:
		2460	case CHIP_VERDE:
3764	Serge	2461	case CHIP_OLAND:
		2462	case CHIP_HAINAN:
2997	Serge	2463	rdev->asic = &si_asic;
		2464	/* set num crtcs */
3764	Serge	2465	if (rdev->family == CHIP_HAINAN)
		2466	rdev->num_crtc = 0;
		2467	else if (rdev->family == CHIP_OLAND)
		2468	rdev->num_crtc = 2;
		2469	else
6104	serge	2470	rdev->num_crtc = 6;
3764	Serge	2471	if (rdev->family == CHIP_HAINAN)
		2472	rdev->has_uvd = false;
		2473	else
		2474	rdev->has_uvd = true;
5078	serge	2475	switch (rdev->family) {
		2476	case CHIP_TAHITI:
		2477	rdev->cg_flags =
		2478	RADEON_CG_SUPPORT_GFX_MGCG \|
		2479	RADEON_CG_SUPPORT_GFX_MGLS \|
		2480	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2481	RADEON_CG_SUPPORT_GFX_CGLS \|
		2482	RADEON_CG_SUPPORT_GFX_CGTS \|
		2483	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2484	RADEON_CG_SUPPORT_MC_MGCG \|
		2485	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2486	RADEON_CG_SUPPORT_BIF_LS \|
		2487	RADEON_CG_SUPPORT_VCE_MGCG \|
		2488	RADEON_CG_SUPPORT_UVD_MGCG \|
		2489	RADEON_CG_SUPPORT_HDP_LS \|
		2490	RADEON_CG_SUPPORT_HDP_MGCG;
		2491	rdev->pg_flags = 0;
		2492	break;
		2493	case CHIP_PITCAIRN:
		2494	rdev->cg_flags =
		2495	RADEON_CG_SUPPORT_GFX_MGCG \|
		2496	RADEON_CG_SUPPORT_GFX_MGLS \|
		2497	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2498	RADEON_CG_SUPPORT_GFX_CGLS \|
		2499	RADEON_CG_SUPPORT_GFX_CGTS \|
		2500	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2501	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2502	RADEON_CG_SUPPORT_MC_LS \|
		2503	RADEON_CG_SUPPORT_MC_MGCG \|
		2504	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2505	RADEON_CG_SUPPORT_BIF_LS \|
		2506	RADEON_CG_SUPPORT_VCE_MGCG \|
		2507	RADEON_CG_SUPPORT_UVD_MGCG \|
		2508	RADEON_CG_SUPPORT_HDP_LS \|
		2509	RADEON_CG_SUPPORT_HDP_MGCG;
		2510	rdev->pg_flags = 0;
		2511	break;
		2512	case CHIP_VERDE:
		2513	rdev->cg_flags =
		2514	RADEON_CG_SUPPORT_GFX_MGCG \|
		2515	RADEON_CG_SUPPORT_GFX_MGLS \|
		2516	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2517	RADEON_CG_SUPPORT_GFX_CGLS \|
		2518	RADEON_CG_SUPPORT_GFX_CGTS \|
		2519	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2520	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2521	RADEON_CG_SUPPORT_MC_LS \|
		2522	RADEON_CG_SUPPORT_MC_MGCG \|
		2523	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2524	RADEON_CG_SUPPORT_BIF_LS \|
		2525	RADEON_CG_SUPPORT_VCE_MGCG \|
		2526	RADEON_CG_SUPPORT_UVD_MGCG \|
		2527	RADEON_CG_SUPPORT_HDP_LS \|
		2528	RADEON_CG_SUPPORT_HDP_MGCG;
		2529	rdev->pg_flags = 0 \|
		2530	/RADEON_PG_SUPPORT_GFX_PG \| /
		2531	RADEON_PG_SUPPORT_SDMA;
		2532	break;
		2533	case CHIP_OLAND:
		2534	rdev->cg_flags =
		2535	RADEON_CG_SUPPORT_GFX_MGCG \|
		2536	RADEON_CG_SUPPORT_GFX_MGLS \|
		2537	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2538	RADEON_CG_SUPPORT_GFX_CGLS \|
		2539	RADEON_CG_SUPPORT_GFX_CGTS \|
		2540	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2541	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2542	RADEON_CG_SUPPORT_MC_LS \|
		2543	RADEON_CG_SUPPORT_MC_MGCG \|
		2544	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2545	RADEON_CG_SUPPORT_BIF_LS \|
		2546	RADEON_CG_SUPPORT_UVD_MGCG \|
		2547	RADEON_CG_SUPPORT_HDP_LS \|
		2548	RADEON_CG_SUPPORT_HDP_MGCG;
		2549	rdev->pg_flags = 0;
		2550	break;
		2551	case CHIP_HAINAN:
		2552	rdev->cg_flags =
		2553	RADEON_CG_SUPPORT_GFX_MGCG \|
		2554	RADEON_CG_SUPPORT_GFX_MGLS \|
		2555	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2556	RADEON_CG_SUPPORT_GFX_CGLS \|
		2557	RADEON_CG_SUPPORT_GFX_CGTS \|
		2558	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2559	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2560	RADEON_CG_SUPPORT_MC_LS \|
		2561	RADEON_CG_SUPPORT_MC_MGCG \|
		2562	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2563	RADEON_CG_SUPPORT_BIF_LS \|
		2564	RADEON_CG_SUPPORT_HDP_LS \|
		2565	RADEON_CG_SUPPORT_HDP_MGCG;
		2566	rdev->pg_flags = 0;
		2567	break;
		2568	default:
		2569	rdev->cg_flags = 0;
		2570	rdev->pg_flags = 0;
		2571	break;
		2572	}
2997	Serge	2573	break;
5078	serge	2574	case CHIP_BONAIRE:
		2575	case CHIP_HAWAII:
		2576	rdev->asic = &ci_asic;
		2577	rdev->num_crtc = 6;
		2578	rdev->has_uvd = true;
		2579	if (rdev->family == CHIP_BONAIRE) {
		2580	rdev->cg_flags =
		2581	RADEON_CG_SUPPORT_GFX_MGCG \|
		2582	RADEON_CG_SUPPORT_GFX_MGLS \|
		2583	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2584	RADEON_CG_SUPPORT_GFX_CGLS \|
		2585	RADEON_CG_SUPPORT_GFX_CGTS \|
		2586	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2587	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2588	RADEON_CG_SUPPORT_MC_LS \|
		2589	RADEON_CG_SUPPORT_MC_MGCG \|
		2590	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2591	RADEON_CG_SUPPORT_SDMA_LS \|
		2592	RADEON_CG_SUPPORT_BIF_LS \|
		2593	RADEON_CG_SUPPORT_VCE_MGCG \|
		2594	RADEON_CG_SUPPORT_UVD_MGCG \|
		2595	RADEON_CG_SUPPORT_HDP_LS \|
		2596	RADEON_CG_SUPPORT_HDP_MGCG;
		2597	rdev->pg_flags = 0;
		2598	} else {
		2599	rdev->cg_flags =
		2600	RADEON_CG_SUPPORT_GFX_MGCG \|
		2601	RADEON_CG_SUPPORT_GFX_MGLS \|
		2602	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2603	RADEON_CG_SUPPORT_GFX_CGLS \|
		2604	RADEON_CG_SUPPORT_GFX_CGTS \|
		2605	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2606	RADEON_CG_SUPPORT_MC_LS \|
		2607	RADEON_CG_SUPPORT_MC_MGCG \|
		2608	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2609	RADEON_CG_SUPPORT_SDMA_LS \|
		2610	RADEON_CG_SUPPORT_BIF_LS \|
		2611	RADEON_CG_SUPPORT_VCE_MGCG \|
		2612	RADEON_CG_SUPPORT_UVD_MGCG \|
		2613	RADEON_CG_SUPPORT_HDP_LS \|
		2614	RADEON_CG_SUPPORT_HDP_MGCG;
		2615	rdev->pg_flags = 0;
		2616	}
		2617	break;
		2618	case CHIP_KAVERI:
		2619	case CHIP_KABINI:
		2620	case CHIP_MULLINS:
		2621	rdev->asic = &kv_asic;
		2622	/* set num crtcs */
		2623	if (rdev->family == CHIP_KAVERI) {
		2624	rdev->num_crtc = 4;
		2625	rdev->cg_flags =
		2626	RADEON_CG_SUPPORT_GFX_MGCG \|
		2627	RADEON_CG_SUPPORT_GFX_MGLS \|
		2628	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2629	RADEON_CG_SUPPORT_GFX_CGLS \|
		2630	RADEON_CG_SUPPORT_GFX_CGTS \|
		2631	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2632	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2633	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2634	RADEON_CG_SUPPORT_SDMA_LS \|
		2635	RADEON_CG_SUPPORT_BIF_LS \|
		2636	RADEON_CG_SUPPORT_VCE_MGCG \|
		2637	RADEON_CG_SUPPORT_UVD_MGCG \|
		2638	RADEON_CG_SUPPORT_HDP_LS \|
		2639	RADEON_CG_SUPPORT_HDP_MGCG;
		2640	rdev->pg_flags = 0;
		2641	/*RADEON_PG_SUPPORT_GFX_PG \|
		2642	RADEON_PG_SUPPORT_GFX_SMG \|
		2643	RADEON_PG_SUPPORT_GFX_DMG \|
		2644	RADEON_PG_SUPPORT_UVD \|
		2645	RADEON_PG_SUPPORT_VCE \|
		2646	RADEON_PG_SUPPORT_CP \|
		2647	RADEON_PG_SUPPORT_GDS \|
		2648	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2649	RADEON_PG_SUPPORT_ACP \|
		2650	RADEON_PG_SUPPORT_SAMU;*/
		2651	} else {
		2652	rdev->num_crtc = 2;
		2653	rdev->cg_flags =
		2654	RADEON_CG_SUPPORT_GFX_MGCG \|
		2655	RADEON_CG_SUPPORT_GFX_MGLS \|
		2656	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2657	RADEON_CG_SUPPORT_GFX_CGLS \|
		2658	RADEON_CG_SUPPORT_GFX_CGTS \|
		2659	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2660	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2661	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2662	RADEON_CG_SUPPORT_SDMA_LS \|
		2663	RADEON_CG_SUPPORT_BIF_LS \|
		2664	RADEON_CG_SUPPORT_VCE_MGCG \|
		2665	RADEON_CG_SUPPORT_UVD_MGCG \|
		2666	RADEON_CG_SUPPORT_HDP_LS \|
		2667	RADEON_CG_SUPPORT_HDP_MGCG;
		2668	rdev->pg_flags = 0;
		2669	/*RADEON_PG_SUPPORT_GFX_PG \|
		2670	RADEON_PG_SUPPORT_GFX_SMG \|
		2671	RADEON_PG_SUPPORT_UVD \|
		2672	RADEON_PG_SUPPORT_VCE \|
		2673	RADEON_PG_SUPPORT_CP \|
		2674	RADEON_PG_SUPPORT_GDS \|
		2675	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2676	RADEON_PG_SUPPORT_SAMU;*/
		2677	}
		2678	rdev->has_uvd = true;
		2679	break;
1963	serge	2680	default:
		2681	/* FIXME: not supported yet */
		2682	return -EINVAL;
		2683	}
		2684
		2685	if (rdev->flags & RADEON_IS_IGP) {
2997	Serge	2686	rdev->asic->pm.get_memory_clock = NULL;
		2687	rdev->asic->pm.set_memory_clock = NULL;
1963	serge	2688	}
		2689
		2690	return 0;
		2691	}
		2692

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c @ 6938 – Rev 6104