WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
		33	//#include
		34	//#include
		35	#include "radeon_reg.h"
		36	#include "radeon.h"
		37	#include "radeon_asic.h"
		38	#include "atom.h"
		39
		40	/*
		41	* Registers accessors functions.
		42	*/
2997	Serge	43	/**
		44	* radeon_invalid_rreg - dummy reg read function
		45	*
		46	* @rdev: radeon device pointer
		47	* @reg: offset of register
		48	*
		49	* Dummy register read function. Used for register blocks
		50	* that certain asics don't have (all asics).
		51	* Returns the value in the register.
		52	*/
1963	serge	53	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		54	{
		55	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		56	BUG_ON(1);
		57	return 0;
		58	}
		59
2997	Serge	60	/**
		61	* radeon_invalid_wreg - dummy reg write function
		62	*
		63	* @rdev: radeon device pointer
		64	* @reg: offset of register
		65	* @v: value to write to the register
		66	*
		67	* Dummy register read function. Used for register blocks
		68	* that certain asics don't have (all asics).
		69	*/
1963	serge	70	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		71	{
		72	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		73	reg, v);
		74	BUG_ON(1);
		75	}
		76
2997	Serge	77	/**
		78	* radeon_register_accessor_init - sets up the register accessor callbacks
		79	*
		80	* @rdev: radeon device pointer
		81	*
		82	* Sets up the register accessor callbacks for various register
		83	* apertures. Not all asics have all apertures (all asics).
		84	*/
1963	serge	85	static void radeon_register_accessor_init(struct radeon_device *rdev)
		86	{
		87	rdev->mc_rreg = &radeon_invalid_rreg;
		88	rdev->mc_wreg = &radeon_invalid_wreg;
		89	rdev->pll_rreg = &radeon_invalid_rreg;
		90	rdev->pll_wreg = &radeon_invalid_wreg;
		91	rdev->pciep_rreg = &radeon_invalid_rreg;
		92	rdev->pciep_wreg = &radeon_invalid_wreg;
		93
		94	/* Don't change order as we are overridding accessor. */
		95	if (rdev->family < CHIP_RV515) {
		96	rdev->pcie_reg_mask = 0xff;
		97	} else {
		98	rdev->pcie_reg_mask = 0x7ff;
		99	}
		100	/* FIXME: not sure here */
		101	if (rdev->family <= CHIP_R580) {
		102	rdev->pll_rreg = &r100_pll_rreg;
		103	rdev->pll_wreg = &r100_pll_wreg;
		104	}
		105	if (rdev->family >= CHIP_R420) {
		106	rdev->mc_rreg = &r420_mc_rreg;
		107	rdev->mc_wreg = &r420_mc_wreg;
		108	}
		109	if (rdev->family >= CHIP_RV515) {
		110	rdev->mc_rreg = &rv515_mc_rreg;
		111	rdev->mc_wreg = &rv515_mc_wreg;
		112	}
		113	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		114	rdev->mc_rreg = &rs400_mc_rreg;
		115	rdev->mc_wreg = &rs400_mc_wreg;
		116	}
		117	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		118	rdev->mc_rreg = &rs690_mc_rreg;
		119	rdev->mc_wreg = &rs690_mc_wreg;
		120	}
		121	if (rdev->family == CHIP_RS600) {
		122	rdev->mc_rreg = &rs600_mc_rreg;
		123	rdev->mc_wreg = &rs600_mc_wreg;
		124	}
3764	Serge	125	if (rdev->family == CHIP_RS780 \|\| rdev->family == CHIP_RS880) {
		126	rdev->mc_rreg = &rs780_mc_rreg;
		127	rdev->mc_wreg = &rs780_mc_wreg;
		128	}
5078	serge	129
		130	if (rdev->family >= CHIP_BONAIRE) {
		131	rdev->pciep_rreg = &cik_pciep_rreg;
		132	rdev->pciep_wreg = &cik_pciep_wreg;
		133	} else if (rdev->family >= CHIP_R600) {
1963	serge	134	rdev->pciep_rreg = &r600_pciep_rreg;
		135	rdev->pciep_wreg = &r600_pciep_wreg;
		136	}
		137	}
		138
		139
		140	/* helper to disable agp */
2997	Serge	141	/**
		142	* radeon_agp_disable - AGP disable helper function
		143	*
		144	* @rdev: radeon device pointer
		145	*
		146	* Removes AGP flags and changes the gart callbacks on AGP
		147	* cards when using the internal gart rather than AGP (all asics).
		148	*/
1963	serge	149	void radeon_agp_disable(struct radeon_device *rdev)
		150	{
		151	rdev->flags &= ~RADEON_IS_AGP;
		152	if (rdev->family >= CHIP_R600) {
		153	DRM_INFO("Forcing AGP to PCIE mode\n");
		154	rdev->flags \|= RADEON_IS_PCIE;
		155	} else if (rdev->family >= CHIP_RV515 \|\|
		156	rdev->family == CHIP_RV380 \|\|
		157	rdev->family == CHIP_RV410 \|\|
		158	rdev->family == CHIP_R423) {
		159	DRM_INFO("Forcing AGP to PCIE mode\n");
		160	rdev->flags \|= RADEON_IS_PCIE;
2997	Serge	161	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
		162	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
1963	serge	163	} else {
		164	DRM_INFO("Forcing AGP to PCI mode\n");
		165	rdev->flags \|= RADEON_IS_PCI;
2997	Serge	166	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
		167	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
1963	serge	168	}
		169	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		170	}
		171
		172	/*
		173	* ASIC
		174	*/
5078	serge	175
		176	static struct radeon_asic_ring r100_gfx_ring = {
		177	.ib_execute = &r100_ring_ib_execute,
		178	.emit_fence = &r100_fence_ring_emit,
		179	.emit_semaphore = &r100_semaphore_ring_emit,
		180	.cs_parse = &r100_cs_parse,
		181	.ring_start = &r100_ring_start,
		182	.ring_test = &r100_ring_test,
		183	.ib_test = &r100_ib_test,
		184	.is_lockup = &r100_gpu_is_lockup,
		185	.get_rptr = &r100_gfx_get_rptr,
		186	.get_wptr = &r100_gfx_get_wptr,
		187	.set_wptr = &r100_gfx_set_wptr,
		188	};
		189
1963	serge	190	static struct radeon_asic r100_asic = {
		191	.init = &r100_init,
		192	// .fini = &r100_fini,
		193	// .suspend = &r100_suspend,
		194	// .resume = &r100_resume,
		195	// .vga_set_state = &r100_vga_set_state,
		196	.asic_reset = &r100_asic_reset,
5078	serge	197	.mmio_hdp_flush = NULL,
2997	Serge	198	.gui_idle = &r100_gui_idle,
		199	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		200	.gart = {
		201	.tlb_flush = &r100_pci_gart_tlb_flush,
		202	.set_page = &r100_pci_gart_set_page,
		203	},
		204	.ring = {
5078	serge	205	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	206	},
		207	.irq = {
		208	.set = &r100_irq_set,
		209	.process = &r100_irq_process,
		210	},
		211	.display = {
		212	.bandwidth_update = &r100_bandwidth_update,
		213	.get_vblank_counter = &r100_get_vblank_counter,
		214	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	215	.set_backlight_level = &radeon_legacy_set_backlight_level,
		216	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	217	},
		218	.copy = {
		219	.blit = &r100_copy_blit,
		220	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		221	.dma = NULL,
		222	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2005	serge	223	.copy = &r100_copy_blit,
2997	Serge	224	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		225	},
		226	.surface = {
		227	.set_reg = r100_set_surface_reg,
		228	.clear_reg = r100_clear_surface_reg,
		229	},
		230	.hpd = {
5078	serge	231	.init = &r100_hpd_init,
		232	.fini = &r100_hpd_fini,
		233	.sense = &r100_hpd_sense,
		234	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	235	},
		236	.pm = {
5078	serge	237	.misc = &r100_pm_misc,
		238	.prepare = &r100_pm_prepare,
		239	.finish = &r100_pm_finish,
		240	.init_profile = &r100_pm_init_profile,
		241	.get_dynpm_state = &r100_pm_get_dynpm_state,
		242	.get_engine_clock = &radeon_legacy_get_engine_clock,
		243	.set_engine_clock = &radeon_legacy_set_engine_clock,
		244	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	245	.set_memory_clock = NULL,
		246	.get_pcie_lanes = NULL,
		247	.set_pcie_lanes = NULL,
5078	serge	248	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	249	},
		250	.pflip = {
		251	// .pre_page_flip = &r100_pre_page_flip,
		252	// .page_flip = &r100_page_flip,
		253	},
1963	serge	254	};
		255
		256	static struct radeon_asic r200_asic = {
		257	.init = &r100_init,
		258	// .fini = &r100_fini,
		259	// .suspend = &r100_suspend,
		260	// .resume = &r100_resume,
		261	// .vga_set_state = &r100_vga_set_state,
		262	.asic_reset = &r100_asic_reset,
5078	serge	263	.mmio_hdp_flush = NULL,
2007	serge	264	.gui_idle = &r100_gui_idle,
2997	Serge	265	.mc_wait_for_idle = &r100_mc_wait_for_idle,
		266	.gart = {
		267	.tlb_flush = &r100_pci_gart_tlb_flush,
		268	.set_page = &r100_pci_gart_set_page,
		269	},
		270	.ring = {
5078	serge	271	[RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
2997	Serge	272	},
		273	.irq = {
		274	.set = &r100_irq_set,
		275	.process = &r100_irq_process,
		276	},
		277	.display = {
		278	.bandwidth_update = &r100_bandwidth_update,
		279	.get_vblank_counter = &r100_get_vblank_counter,
		280	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	281	.set_backlight_level = &radeon_legacy_set_backlight_level,
		282	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	283	},
		284	.copy = {
		285	.blit = &r100_copy_blit,
		286	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		287	.dma = &r200_copy_dma,
		288	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		289	.copy = &r100_copy_blit,
		290	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		291	},
		292	.surface = {
		293	.set_reg = r100_set_surface_reg,
		294	.clear_reg = r100_clear_surface_reg,
		295	},
		296	.hpd = {
5078	serge	297	.init = &r100_hpd_init,
		298	.fini = &r100_hpd_fini,
		299	.sense = &r100_hpd_sense,
		300	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	301	},
		302	.pm = {
5078	serge	303	.misc = &r100_pm_misc,
		304	.prepare = &r100_pm_prepare,
		305	.finish = &r100_pm_finish,
		306	.init_profile = &r100_pm_init_profile,
		307	.get_dynpm_state = &r100_pm_get_dynpm_state,
		308	.get_engine_clock = &radeon_legacy_get_engine_clock,
		309	.set_engine_clock = &radeon_legacy_set_engine_clock,
		310	.get_memory_clock = &radeon_legacy_get_memory_clock,
3192	Serge	311	.set_memory_clock = NULL,
		312	.get_pcie_lanes = NULL,
		313	.set_pcie_lanes = NULL,
5078	serge	314	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	315	},
		316	.pflip = {
		317	// .pre_page_flip = &r100_pre_page_flip,
		318	// .page_flip = &r100_page_flip,
		319	},
1963	serge	320	};
		321
5078	serge	322	static struct radeon_asic_ring r300_gfx_ring = {
		323	.ib_execute = &r100_ring_ib_execute,
		324	.emit_fence = &r300_fence_ring_emit,
		325	.emit_semaphore = &r100_semaphore_ring_emit,
		326	.cs_parse = &r300_cs_parse,
		327	.ring_start = &r300_ring_start,
		328	.ring_test = &r100_ring_test,
		329	.ib_test = &r100_ib_test,
		330	.is_lockup = &r100_gpu_is_lockup,
		331	.get_rptr = &r100_gfx_get_rptr,
		332	.get_wptr = &r100_gfx_get_wptr,
		333	.set_wptr = &r100_gfx_set_wptr,
		334	};
		335
1963	serge	336	static struct radeon_asic r300_asic = {
		337	.init = &r300_init,
		338	// .fini = &r300_fini,
		339	// .suspend = &r300_suspend,
		340	// .resume = &r300_resume,
		341	// .vga_set_state = &r100_vga_set_state,
		342	.asic_reset = &r300_asic_reset,
5078	serge	343	.mmio_hdp_flush = NULL,
2007	serge	344	.gui_idle = &r100_gui_idle,
2997	Serge	345	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		346	.gart = {
		347	.tlb_flush = &r100_pci_gart_tlb_flush,
		348	.set_page = &r100_pci_gart_set_page,
		349	},
		350	.ring = {
5078	serge	351	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	352	},
		353	.irq = {
		354	.set = &r100_irq_set,
		355	.process = &r100_irq_process,
		356	},
		357	.display = {
		358	.bandwidth_update = &r100_bandwidth_update,
		359	.get_vblank_counter = &r100_get_vblank_counter,
		360	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	361	.set_backlight_level = &radeon_legacy_set_backlight_level,
		362	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	363	},
		364	.copy = {
		365	.blit = &r100_copy_blit,
		366	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		367	.dma = &r200_copy_dma,
		368	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		369	.copy = &r100_copy_blit,
		370	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		371	},
		372	.surface = {
		373	.set_reg = r100_set_surface_reg,
		374	.clear_reg = r100_clear_surface_reg,
		375	},
		376	.hpd = {
5078	serge	377	.init = &r100_hpd_init,
		378	.fini = &r100_hpd_fini,
		379	.sense = &r100_hpd_sense,
		380	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	381	},
		382	.pm = {
5078	serge	383	.misc = &r100_pm_misc,
		384	.prepare = &r100_pm_prepare,
		385	.finish = &r100_pm_finish,
		386	.init_profile = &r100_pm_init_profile,
		387	.get_dynpm_state = &r100_pm_get_dynpm_state,
		388	.get_engine_clock = &radeon_legacy_get_engine_clock,
		389	.set_engine_clock = &radeon_legacy_set_engine_clock,
		390	.get_memory_clock = &radeon_legacy_get_memory_clock,
		391	.set_memory_clock = NULL,
		392	.get_pcie_lanes = &rv370_get_pcie_lanes,
		393	.set_pcie_lanes = &rv370_set_pcie_lanes,
		394	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	395	},
		396	.pflip = {
		397	// .pre_page_flip = &r100_pre_page_flip,
		398	// .page_flip = &r100_page_flip,
		399	},
1963	serge	400	};
		401
		402	static struct radeon_asic r300_asic_pcie = {
		403	.init = &r300_init,
		404	// .fini = &r300_fini,
		405	// .suspend = &r300_suspend,
		406	// .resume = &r300_resume,
		407	// .vga_set_state = &r100_vga_set_state,
		408	.asic_reset = &r300_asic_reset,
5078	serge	409	.mmio_hdp_flush = NULL,
2007	serge	410	.gui_idle = &r100_gui_idle,
2997	Serge	411	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		412	.gart = {
		413	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		414	.set_page = &rv370_pcie_gart_set_page,
		415	},
		416	.ring = {
5078	serge	417	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	418	},
		419	.irq = {
		420	.set = &r100_irq_set,
		421	.process = &r100_irq_process,
		422	},
		423	.display = {
		424	.bandwidth_update = &r100_bandwidth_update,
		425	.get_vblank_counter = &r100_get_vblank_counter,
		426	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	427	.set_backlight_level = &radeon_legacy_set_backlight_level,
		428	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	429	},
		430	.copy = {
		431	.blit = &r100_copy_blit,
		432	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		433	.dma = &r200_copy_dma,
		434	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		435	.copy = &r100_copy_blit,
		436	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		437	},
		438	.surface = {
		439	.set_reg = r100_set_surface_reg,
		440	.clear_reg = r100_clear_surface_reg,
		441	},
		442	.hpd = {
		443	.init = &r100_hpd_init,
		444	.fini = &r100_hpd_fini,
		445	.sense = &r100_hpd_sense,
		446	.set_polarity = &r100_hpd_set_polarity,
		447	},
		448	.pm = {
5078	serge	449	.misc = &r100_pm_misc,
		450	.prepare = &r100_pm_prepare,
		451	.finish = &r100_pm_finish,
		452	.init_profile = &r100_pm_init_profile,
		453	.get_dynpm_state = &r100_pm_get_dynpm_state,
		454	.get_engine_clock = &radeon_legacy_get_engine_clock,
		455	.set_engine_clock = &radeon_legacy_set_engine_clock,
		456	.get_memory_clock = &radeon_legacy_get_memory_clock,
		457	.set_memory_clock = NULL,
		458	.get_pcie_lanes = &rv370_get_pcie_lanes,
		459	.set_pcie_lanes = &rv370_set_pcie_lanes,
		460	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	461	},
		462	.pflip = {
		463	// .pre_page_flip = &r100_pre_page_flip,
		464	// .page_flip = &r100_page_flip,
		465	},
1963	serge	466	};
		467
		468	static struct radeon_asic r420_asic = {
		469	.init = &r420_init,
		470	// .fini = &r420_fini,
		471	// .suspend = &r420_suspend,
		472	// .resume = &r420_resume,
		473	// .vga_set_state = &r100_vga_set_state,
		474	.asic_reset = &r300_asic_reset,
5078	serge	475	.mmio_hdp_flush = NULL,
2160	serge	476	.gui_idle = &r100_gui_idle,
2997	Serge	477	.mc_wait_for_idle = &r300_mc_wait_for_idle,
		478	.gart = {
		479	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		480	.set_page = &rv370_pcie_gart_set_page,
		481	},
		482	.ring = {
5078	serge	483	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	484	},
		485	.irq = {
		486	.set = &r100_irq_set,
		487	.process = &r100_irq_process,
		488	},
		489	.display = {
		490	.bandwidth_update = &r100_bandwidth_update,
		491	.get_vblank_counter = &r100_get_vblank_counter,
		492	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	493	.set_backlight_level = &atombios_set_backlight_level,
		494	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	495	},
		496	.copy = {
		497	.blit = &r100_copy_blit,
		498	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		499	.dma = &r200_copy_dma,
		500	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		501	.copy = &r100_copy_blit,
		502	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		503	},
		504	.surface = {
		505	.set_reg = r100_set_surface_reg,
		506	.clear_reg = r100_clear_surface_reg,
		507	},
		508	.hpd = {
5078	serge	509	.init = &r100_hpd_init,
		510	.fini = &r100_hpd_fini,
		511	.sense = &r100_hpd_sense,
		512	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	513	},
		514	.pm = {
5078	serge	515	.misc = &r100_pm_misc,
		516	.prepare = &r100_pm_prepare,
		517	.finish = &r100_pm_finish,
		518	.init_profile = &r420_pm_init_profile,
		519	.get_dynpm_state = &r100_pm_get_dynpm_state,
		520	.get_engine_clock = &radeon_atom_get_engine_clock,
		521	.set_engine_clock = &radeon_atom_set_engine_clock,
		522	.get_memory_clock = &radeon_atom_get_memory_clock,
		523	.set_memory_clock = &radeon_atom_set_memory_clock,
		524	.get_pcie_lanes = &rv370_get_pcie_lanes,
		525	.set_pcie_lanes = &rv370_set_pcie_lanes,
		526	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	527	},
		528	.pflip = {
		529	// .pre_page_flip = &r100_pre_page_flip,
		530	// .page_flip = &r100_page_flip,
		531	},
1963	serge	532	};
		533
		534	static struct radeon_asic rs400_asic = {
		535	.init = &rs400_init,
		536	// .fini = &rs400_fini,
		537	// .suspend = &rs400_suspend,
		538	// .resume = &rs400_resume,
		539	// .vga_set_state = &r100_vga_set_state,
		540	.asic_reset = &r300_asic_reset,
5078	serge	541	.mmio_hdp_flush = NULL,
2160	serge	542	.gui_idle = &r100_gui_idle,
2997	Serge	543	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
		544	.gart = {
		545	.tlb_flush = &rs400_gart_tlb_flush,
		546	.set_page = &rs400_gart_set_page,
		547	},
		548	.ring = {
5078	serge	549	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	550	},
		551	.irq = {
		552	.set = &r100_irq_set,
		553	.process = &r100_irq_process,
		554	},
		555	.display = {
		556	.bandwidth_update = &r100_bandwidth_update,
		557	.get_vblank_counter = &r100_get_vblank_counter,
		558	.wait_for_vblank = &r100_wait_for_vblank,
5078	serge	559	.set_backlight_level = &radeon_legacy_set_backlight_level,
		560	.get_backlight_level = &radeon_legacy_get_backlight_level,
2997	Serge	561	},
		562	.copy = {
		563	.blit = &r100_copy_blit,
		564	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		565	.dma = &r200_copy_dma,
		566	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		567	.copy = &r100_copy_blit,
		568	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		569	},
		570	.surface = {
		571	.set_reg = r100_set_surface_reg,
		572	.clear_reg = r100_clear_surface_reg,
		573	},
		574	.hpd = {
5078	serge	575	.init = &r100_hpd_init,
		576	.fini = &r100_hpd_fini,
		577	.sense = &r100_hpd_sense,
		578	.set_polarity = &r100_hpd_set_polarity,
2997	Serge	579	},
		580	.pm = {
5078	serge	581	.misc = &r100_pm_misc,
		582	.prepare = &r100_pm_prepare,
		583	.finish = &r100_pm_finish,
		584	.init_profile = &r100_pm_init_profile,
		585	.get_dynpm_state = &r100_pm_get_dynpm_state,
		586	.get_engine_clock = &radeon_legacy_get_engine_clock,
		587	.set_engine_clock = &radeon_legacy_set_engine_clock,
		588	.get_memory_clock = &radeon_legacy_get_memory_clock,
		589	.set_memory_clock = NULL,
		590	.get_pcie_lanes = NULL,
		591	.set_pcie_lanes = NULL,
		592	.set_clock_gating = &radeon_legacy_set_clock_gating,
2997	Serge	593	},
		594	.pflip = {
		595	// .pre_page_flip = &r100_pre_page_flip,
		596	// .page_flip = &r100_page_flip,
		597	},
1963	serge	598	};
		599
		600	static struct radeon_asic rs600_asic = {
		601	.init = &rs600_init,
		602	// .fini = &rs600_fini,
		603	// .suspend = &rs600_suspend,
		604	// .resume = &rs600_resume,
		605	// .vga_set_state = &r100_vga_set_state,
		606	.asic_reset = &rs600_asic_reset,
5078	serge	607	.mmio_hdp_flush = NULL,
2160	serge	608	.gui_idle = &r100_gui_idle,
2997	Serge	609	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
		610	.gart = {
		611	.tlb_flush = &rs600_gart_tlb_flush,
		612	.set_page = &rs600_gart_set_page,
		613	},
		614	.ring = {
5078	serge	615	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	616	},
		617	.irq = {
		618	.set = &rs600_irq_set,
		619	.process = &rs600_irq_process,
		620	},
		621	.display = {
		622	.bandwidth_update = &rs600_bandwidth_update,
		623	.get_vblank_counter = &rs600_get_vblank_counter,
		624	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	625	.set_backlight_level = &atombios_set_backlight_level,
		626	.get_backlight_level = &atombios_get_backlight_level,
		627	.hdmi_enable = &r600_hdmi_enable,
		628	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	629	},
		630	.copy = {
		631	.blit = &r100_copy_blit,
		632	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		633	.dma = &r200_copy_dma,
		634	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		635	.copy = &r100_copy_blit,
		636	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		637	},
		638	.surface = {
		639	.set_reg = r100_set_surface_reg,
		640	.clear_reg = r100_clear_surface_reg,
		641	},
		642	.hpd = {
5078	serge	643	.init = &rs600_hpd_init,
		644	.fini = &rs600_hpd_fini,
		645	.sense = &rs600_hpd_sense,
		646	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	647	},
		648	.pm = {
5078	serge	649	.misc = &rs600_pm_misc,
		650	.prepare = &rs600_pm_prepare,
		651	.finish = &rs600_pm_finish,
		652	.init_profile = &r420_pm_init_profile,
		653	.get_dynpm_state = &r100_pm_get_dynpm_state,
		654	.get_engine_clock = &radeon_atom_get_engine_clock,
		655	.set_engine_clock = &radeon_atom_set_engine_clock,
		656	.get_memory_clock = &radeon_atom_get_memory_clock,
		657	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	658	.get_pcie_lanes = NULL,
		659	.set_pcie_lanes = NULL,
5078	serge	660	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	661	},
		662	.pflip = {
		663	// .pre_page_flip = &rs600_pre_page_flip,
		664	// .page_flip = &rs600_page_flip,
		665	},
1963	serge	666	};
		667
		668	static struct radeon_asic rs690_asic = {
		669	.init = &rs690_init,
		670	// .fini = &rs690_fini,
		671	// .suspend = &rs690_suspend,
		672	// .resume = &rs690_resume,
		673	// .vga_set_state = &r100_vga_set_state,
		674	.asic_reset = &rs600_asic_reset,
5078	serge	675	.mmio_hdp_flush = NULL,
2160	serge	676	.gui_idle = &r100_gui_idle,
2997	Serge	677	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
		678	.gart = {
		679	.tlb_flush = &rs400_gart_tlb_flush,
		680	.set_page = &rs400_gart_set_page,
		681	},
		682	.ring = {
5078	serge	683	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	684	},
		685	.irq = {
		686	.set = &rs600_irq_set,
		687	.process = &rs600_irq_process,
		688	},
		689	.display = {
		690	.get_vblank_counter = &rs600_get_vblank_counter,
		691	.bandwidth_update = &rs690_bandwidth_update,
		692	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	693	.set_backlight_level = &atombios_set_backlight_level,
		694	.get_backlight_level = &atombios_get_backlight_level,
		695	.hdmi_enable = &r600_hdmi_enable,
		696	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	697	},
		698	.copy = {
		699	.blit = &r100_copy_blit,
		700	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		701	.dma = &r200_copy_dma,
		702	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		703	.copy = &r200_copy_dma,
		704	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		705	},
		706	.surface = {
		707	.set_reg = r100_set_surface_reg,
		708	.clear_reg = r100_clear_surface_reg,
		709	},
		710	.hpd = {
5078	serge	711	.init = &rs600_hpd_init,
		712	.fini = &rs600_hpd_fini,
2997	Serge	713	.sense = &rs600_hpd_sense,
		714	.set_polarity = &rs600_hpd_set_polarity,
		715	},
		716	.pm = {
5078	serge	717	.misc = &rs600_pm_misc,
		718	.prepare = &rs600_pm_prepare,
		719	.finish = &rs600_pm_finish,
		720	.init_profile = &r420_pm_init_profile,
		721	.get_dynpm_state = &r100_pm_get_dynpm_state,
		722	.get_engine_clock = &radeon_atom_get_engine_clock,
		723	.set_engine_clock = &radeon_atom_set_engine_clock,
		724	.get_memory_clock = &radeon_atom_get_memory_clock,
		725	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	726	.get_pcie_lanes = NULL,
		727	.set_pcie_lanes = NULL,
5078	serge	728	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	729	},
		730	.pflip = {
		731	// .pre_page_flip = &rs600_pre_page_flip,
		732	// .page_flip = &rs600_page_flip,
		733	},
1963	serge	734	};
		735
		736	static struct radeon_asic rv515_asic = {
		737	.init = &rv515_init,
		738	// .fini = &rv515_fini,
		739	// .suspend = &rv515_suspend,
		740	// .resume = &rv515_resume,
		741	// .vga_set_state = &r100_vga_set_state,
		742	.asic_reset = &rs600_asic_reset,
5078	serge	743	.mmio_hdp_flush = NULL,
2160	serge	744	.gui_idle = &r100_gui_idle,
2997	Serge	745	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
		746	.gart = {
		747	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		748	.set_page = &rv370_pcie_gart_set_page,
		749	},
		750	.ring = {
5078	serge	751	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	752	},
		753	.irq = {
		754	.set = &rs600_irq_set,
		755	.process = &rs600_irq_process,
		756	},
		757	.display = {
		758	.get_vblank_counter = &rs600_get_vblank_counter,
		759	.bandwidth_update = &rv515_bandwidth_update,
		760	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	761	.set_backlight_level = &atombios_set_backlight_level,
		762	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	763	},
		764	.copy = {
		765	.blit = &r100_copy_blit,
		766	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		767	.dma = &r200_copy_dma,
		768	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		769	.copy = &r100_copy_blit,
		770	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		771	},
		772	.surface = {
		773	.set_reg = r100_set_surface_reg,
		774	.clear_reg = r100_clear_surface_reg,
		775	},
		776	.hpd = {
5078	serge	777	.init = &rs600_hpd_init,
		778	.fini = &rs600_hpd_fini,
		779	.sense = &rs600_hpd_sense,
		780	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	781	},
		782	.pm = {
5078	serge	783	.misc = &rs600_pm_misc,
		784	.prepare = &rs600_pm_prepare,
		785	.finish = &rs600_pm_finish,
		786	.init_profile = &r420_pm_init_profile,
		787	.get_dynpm_state = &r100_pm_get_dynpm_state,
		788	.get_engine_clock = &radeon_atom_get_engine_clock,
		789	.set_engine_clock = &radeon_atom_set_engine_clock,
		790	.get_memory_clock = &radeon_atom_get_memory_clock,
		791	.set_memory_clock = &radeon_atom_set_memory_clock,
		792	.get_pcie_lanes = &rv370_get_pcie_lanes,
		793	.set_pcie_lanes = &rv370_set_pcie_lanes,
		794	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	795	},
		796	.pflip = {
		797	// .pre_page_flip = &rs600_pre_page_flip,
		798	// .page_flip = &rs600_page_flip,
		799	},
1963	serge	800	};
		801
		802	static struct radeon_asic r520_asic = {
		803	.init = &r520_init,
		804	// .fini = &rv515_fini,
		805	// .suspend = &rv515_suspend,
		806	// .resume = &r520_resume,
		807	// .vga_set_state = &r100_vga_set_state,
		808	.asic_reset = &rs600_asic_reset,
5078	serge	809	.mmio_hdp_flush = NULL,
2160	serge	810	.gui_idle = &r100_gui_idle,
2997	Serge	811	.mc_wait_for_idle = &r520_mc_wait_for_idle,
		812	.gart = {
		813	.tlb_flush = &rv370_pcie_gart_tlb_flush,
		814	.set_page = &rv370_pcie_gart_set_page,
		815	},
		816	.ring = {
5078	serge	817	[RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
2997	Serge	818	},
		819	.irq = {
		820	.set = &rs600_irq_set,
		821	.process = &rs600_irq_process,
		822	},
		823	.display = {
		824	.bandwidth_update = &rv515_bandwidth_update,
		825	.get_vblank_counter = &rs600_get_vblank_counter,
		826	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	827	.set_backlight_level = &atombios_set_backlight_level,
		828	.get_backlight_level = &atombios_get_backlight_level,
2997	Serge	829	},
		830	.copy = {
		831	.blit = &r100_copy_blit,
		832	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		833	.dma = &r200_copy_dma,
		834	.dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		835	.copy = &r100_copy_blit,
		836	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		837	},
		838	.surface = {
		839	.set_reg = r100_set_surface_reg,
		840	.clear_reg = r100_clear_surface_reg,
		841	},
		842	.hpd = {
5078	serge	843	.init = &rs600_hpd_init,
		844	.fini = &rs600_hpd_fini,
		845	.sense = &rs600_hpd_sense,
		846	.set_polarity = &rs600_hpd_set_polarity,
2997	Serge	847	},
		848	.pm = {
5078	serge	849	.misc = &rs600_pm_misc,
		850	.prepare = &rs600_pm_prepare,
		851	.finish = &rs600_pm_finish,
		852	.init_profile = &r420_pm_init_profile,
		853	.get_dynpm_state = &r100_pm_get_dynpm_state,
		854	.get_engine_clock = &radeon_atom_get_engine_clock,
		855	.set_engine_clock = &radeon_atom_set_engine_clock,
		856	.get_memory_clock = &radeon_atom_get_memory_clock,
		857	.set_memory_clock = &radeon_atom_set_memory_clock,
		858	.get_pcie_lanes = &rv370_get_pcie_lanes,
		859	.set_pcie_lanes = &rv370_set_pcie_lanes,
		860	.set_clock_gating = &radeon_atom_set_clock_gating,
2997	Serge	861	},
		862	.pflip = {
		863	// .pre_page_flip = &rs600_pre_page_flip,
		864	// .page_flip = &rs600_page_flip,
		865	},
1963	serge	866	};
		867
5078	serge	868	static struct radeon_asic_ring r600_gfx_ring = {
		869	.ib_execute = &r600_ring_ib_execute,
		870	.emit_fence = &r600_fence_ring_emit,
		871	.emit_semaphore = &r600_semaphore_ring_emit,
		872	.cs_parse = &r600_cs_parse,
		873	.ring_test = &r600_ring_test,
		874	.ib_test = &r600_ib_test,
		875	.is_lockup = &r600_gfx_is_lockup,
		876	.get_rptr = &r600_gfx_get_rptr,
		877	.get_wptr = &r600_gfx_get_wptr,
		878	.set_wptr = &r600_gfx_set_wptr,
		879	};
		880
		881	static struct radeon_asic_ring r600_dma_ring = {
		882	.ib_execute = &r600_dma_ring_ib_execute,
		883	.emit_fence = &r600_dma_fence_ring_emit,
		884	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		885	.cs_parse = &r600_dma_cs_parse,
		886	.ring_test = &r600_dma_ring_test,
		887	.ib_test = &r600_dma_ib_test,
		888	.is_lockup = &r600_dma_is_lockup,
		889	.get_rptr = &r600_dma_get_rptr,
		890	.get_wptr = &r600_dma_get_wptr,
		891	.set_wptr = &r600_dma_set_wptr,
		892	};
		893
1963	serge	894	static struct radeon_asic r600_asic = {
		895	.init = &r600_init,
		896	// .fini = &r600_fini,
		897	// .suspend = &r600_suspend,
		898	// .resume = &r600_resume,
2997	Serge	899	// .vga_set_state = &r600_vga_set_state,
1963	serge	900	.asic_reset = &r600_asic_reset,
5078	serge	901	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	902	.gui_idle = &r600_gui_idle,
		903	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	904	.get_xclk = &r600_get_xclk,
		905	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	906	.gart = {
		907	.tlb_flush = &r600_pcie_gart_tlb_flush,
		908	.set_page = &rs600_gart_set_page,
		909	},
		910	.ring = {
5078	serge	911	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		912	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	913	},
		914	.irq = {
		915	.set = &r600_irq_set,
		916	.process = &r600_irq_process,
		917	},
		918	.display = {
		919	.bandwidth_update = &rv515_bandwidth_update,
		920	.get_vblank_counter = &rs600_get_vblank_counter,
		921	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	922	.set_backlight_level = &atombios_set_backlight_level,
		923	.get_backlight_level = &atombios_get_backlight_level,
		924	.hdmi_enable = &r600_hdmi_enable,
		925	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	926	},
		927	.copy = {
5078	serge	928	.blit = &r600_copy_cpdma,
2997	Serge	929	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	930	.dma = &r600_copy_dma,
		931	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	932	.copy = &r600_copy_cpdma,
		933	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	934	},
		935	.surface = {
		936	.set_reg = r600_set_surface_reg,
		937	.clear_reg = r600_clear_surface_reg,
		938	},
		939	.hpd = {
5078	serge	940	.init = &r600_hpd_init,
		941	.fini = &r600_hpd_fini,
		942	.sense = &r600_hpd_sense,
		943	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	944	},
		945	.pm = {
5078	serge	946	.misc = &r600_pm_misc,
		947	.prepare = &rs600_pm_prepare,
		948	.finish = &rs600_pm_finish,
		949	.init_profile = &r600_pm_init_profile,
		950	.get_dynpm_state = &r600_pm_get_dynpm_state,
		951	.get_engine_clock = &radeon_atom_get_engine_clock,
		952	.set_engine_clock = &radeon_atom_set_engine_clock,
		953	.get_memory_clock = &radeon_atom_get_memory_clock,
		954	.set_memory_clock = &radeon_atom_set_memory_clock,
		955	.get_pcie_lanes = &r600_get_pcie_lanes,
		956	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	957	.set_clock_gating = NULL,
5078	serge	958	.get_temperature = &rv6xx_get_temp,
2997	Serge	959	},
		960	.pflip = {
		961	// .pre_page_flip = &rs600_pre_page_flip,
		962	// .page_flip = &rs600_page_flip,
		963	},
1963	serge	964	};
		965
5078	serge	966	static struct radeon_asic rv6xx_asic = {
		967	.init = &r600_init,
		968	// .fini = &r600_fini,
		969	// .suspend = &r600_suspend,
		970	// .resume = &r600_resume,
		971	// .vga_set_state = &r600_vga_set_state,
		972	.asic_reset = &r600_asic_reset,
		973	.mmio_hdp_flush = r600_mmio_hdp_flush,
		974	.gui_idle = &r600_gui_idle,
		975	.mc_wait_for_idle = &r600_mc_wait_for_idle,
		976	.get_xclk = &r600_get_xclk,
		977	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
		978	.gart = {
		979	.tlb_flush = &r600_pcie_gart_tlb_flush,
		980	.set_page = &rs600_gart_set_page,
		981	},
		982	.ring = {
		983	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		984	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		985	},
		986	.irq = {
		987	.set = &r600_irq_set,
		988	.process = &r600_irq_process,
		989	},
		990	.display = {
		991	.bandwidth_update = &rv515_bandwidth_update,
		992	.get_vblank_counter = &rs600_get_vblank_counter,
		993	.wait_for_vblank = &avivo_wait_for_vblank,
		994	.set_backlight_level = &atombios_set_backlight_level,
		995	.get_backlight_level = &atombios_get_backlight_level,
		996	.hdmi_enable = &r600_hdmi_enable,
		997	.hdmi_setmode = &r600_hdmi_setmode,
		998	},
		999	.copy = {
		1000	.blit = &r600_copy_cpdma,
		1001	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1002	.dma = &r600_copy_dma,
		1003	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1004	.copy = &r600_copy_cpdma,
		1005	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		1006	},
		1007	.surface = {
		1008	.set_reg = r600_set_surface_reg,
		1009	.clear_reg = r600_clear_surface_reg,
		1010	},
		1011	.hpd = {
		1012	.init = &r600_hpd_init,
		1013	.fini = &r600_hpd_fini,
		1014	.sense = &r600_hpd_sense,
		1015	.set_polarity = &r600_hpd_set_polarity,
		1016	},
		1017	.pm = {
		1018	.misc = &r600_pm_misc,
		1019	.prepare = &rs600_pm_prepare,
		1020	.finish = &rs600_pm_finish,
		1021	.init_profile = &r600_pm_init_profile,
		1022	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1023	.get_engine_clock = &radeon_atom_get_engine_clock,
		1024	.set_engine_clock = &radeon_atom_set_engine_clock,
		1025	.get_memory_clock = &radeon_atom_get_memory_clock,
		1026	.set_memory_clock = &radeon_atom_set_memory_clock,
		1027	.get_pcie_lanes = &r600_get_pcie_lanes,
		1028	.set_pcie_lanes = &r600_set_pcie_lanes,
		1029	.set_clock_gating = NULL,
		1030	.get_temperature = &rv6xx_get_temp,
		1031	.set_uvd_clocks = &r600_set_uvd_clocks,
		1032	},
		1033	.dpm = {
		1034	.init = &rv6xx_dpm_init,
		1035	.setup_asic = &rv6xx_setup_asic,
		1036	.enable = &rv6xx_dpm_enable,
		1037	.late_enable = &r600_dpm_late_enable,
		1038	.disable = &rv6xx_dpm_disable,
		1039	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1040	.set_power_state = &rv6xx_dpm_set_power_state,
		1041	.post_set_power_state = &r600_dpm_post_set_power_state,
		1042	.display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
		1043	.fini = &rv6xx_dpm_fini,
		1044	.get_sclk = &rv6xx_dpm_get_sclk,
		1045	.get_mclk = &rv6xx_dpm_get_mclk,
		1046	.print_power_state = &rv6xx_dpm_print_power_state,
		1047	.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
		1048	.force_performance_level = &rv6xx_dpm_force_performance_level,
		1049	},
		1050	.pflip = {
		1051	// .pre_page_flip = &rs600_pre_page_flip,
		1052	// .page_flip = &rs600_page_flip,
		1053	},
		1054	};
		1055
1963	serge	1056	static struct radeon_asic rs780_asic = {
		1057	.init = &r600_init,
		1058	// .fini = &r600_fini,
		1059	// .suspend = &r600_suspend,
		1060	// .resume = &r600_resume,
2997	Serge	1061	// .vga_set_state = &r600_vga_set_state,
1963	serge	1062	.asic_reset = &r600_asic_reset,
5078	serge	1063	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1064	.gui_idle = &r600_gui_idle,
		1065	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1066	.get_xclk = &r600_get_xclk,
		1067	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1068	.gart = {
		1069	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1070	.set_page = &rs600_gart_set_page,
		1071	},
		1072	.ring = {
5078	serge	1073	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1074	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
2997	Serge	1075	},
		1076	.irq = {
		1077	.set = &r600_irq_set,
		1078	.process = &r600_irq_process,
		1079	},
		1080	.display = {
		1081	.bandwidth_update = &rs690_bandwidth_update,
		1082	.get_vblank_counter = &rs600_get_vblank_counter,
		1083	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1084	.set_backlight_level = &atombios_set_backlight_level,
		1085	.get_backlight_level = &atombios_get_backlight_level,
		1086	.hdmi_enable = &r600_hdmi_enable,
		1087	.hdmi_setmode = &r600_hdmi_setmode,
2997	Serge	1088	},
		1089	.copy = {
5078	serge	1090	.blit = &r600_copy_cpdma,
2997	Serge	1091	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1092	.dma = &r600_copy_dma,
		1093	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
5078	serge	1094	.copy = &r600_copy_cpdma,
		1095	.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2997	Serge	1096	},
		1097	.surface = {
		1098	.set_reg = r600_set_surface_reg,
		1099	.clear_reg = r600_clear_surface_reg,
		1100	},
		1101	.hpd = {
5078	serge	1102	.init = &r600_hpd_init,
		1103	.fini = &r600_hpd_fini,
		1104	.sense = &r600_hpd_sense,
		1105	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1106	},
		1107	.pm = {
5078	serge	1108	.misc = &r600_pm_misc,
		1109	.prepare = &rs600_pm_prepare,
		1110	.finish = &rs600_pm_finish,
		1111	.init_profile = &rs780_pm_init_profile,
		1112	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1113	.get_engine_clock = &radeon_atom_get_engine_clock,
		1114	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1115	.get_memory_clock = NULL,
		1116	.set_memory_clock = NULL,
		1117	.get_pcie_lanes = NULL,
		1118	.set_pcie_lanes = NULL,
		1119	.set_clock_gating = NULL,
5078	serge	1120	.get_temperature = &rv6xx_get_temp,
		1121	.set_uvd_clocks = &r600_set_uvd_clocks,
2997	Serge	1122	},
5078	serge	1123	.dpm = {
		1124	.init = &rs780_dpm_init,
		1125	.setup_asic = &rs780_dpm_setup_asic,
		1126	.enable = &rs780_dpm_enable,
		1127	.late_enable = &r600_dpm_late_enable,
		1128	.disable = &rs780_dpm_disable,
		1129	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1130	.set_power_state = &rs780_dpm_set_power_state,
		1131	.post_set_power_state = &r600_dpm_post_set_power_state,
		1132	.display_configuration_changed = &rs780_dpm_display_configuration_changed,
		1133	.fini = &rs780_dpm_fini,
		1134	.get_sclk = &rs780_dpm_get_sclk,
		1135	.get_mclk = &rs780_dpm_get_mclk,
		1136	.print_power_state = &rs780_dpm_print_power_state,
		1137	.debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
		1138	.force_performance_level = &rs780_dpm_force_performance_level,
		1139	},
2997	Serge	1140	.pflip = {
		1141	// .pre_page_flip = &rs600_pre_page_flip,
		1142	// .page_flip = &rs600_page_flip,
		1143	},
1963	serge	1144	};
		1145
5078	serge	1146	static struct radeon_asic_ring rv770_uvd_ring = {
		1147	.ib_execute = &uvd_v1_0_ib_execute,
		1148	.emit_fence = &uvd_v2_2_fence_emit,
		1149	.emit_semaphore = &uvd_v1_0_semaphore_emit,
		1150	.cs_parse = &radeon_uvd_cs_parse,
		1151	.ring_test = &uvd_v1_0_ring_test,
		1152	.ib_test = &uvd_v1_0_ib_test,
		1153	.is_lockup = &radeon_ring_test_lockup,
		1154	.get_rptr = &uvd_v1_0_get_rptr,
		1155	.get_wptr = &uvd_v1_0_get_wptr,
		1156	.set_wptr = &uvd_v1_0_set_wptr,
		1157	};
		1158
1963	serge	1159	static struct radeon_asic rv770_asic = {
		1160	.init = &rv770_init,
		1161	// .fini = &rv770_fini,
		1162	// .suspend = &rv770_suspend,
		1163	// .resume = &rv770_resume,
		1164	.asic_reset = &r600_asic_reset,
2997	Serge	1165	// .vga_set_state = &r600_vga_set_state,
5078	serge	1166	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1167	.gui_idle = &r600_gui_idle,
		1168	.mc_wait_for_idle = &r600_mc_wait_for_idle,
3764	Serge	1169	.get_xclk = &rv770_get_xclk,
		1170	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1171	.gart = {
		1172	.tlb_flush = &r600_pcie_gart_tlb_flush,
		1173	.set_page = &rs600_gart_set_page,
		1174	},
		1175	.ring = {
5078	serge	1176	[RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
		1177	[R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
		1178	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1179	},
		1180	.irq = {
		1181	.set = &r600_irq_set,
		1182	.process = &r600_irq_process,
		1183	},
		1184	.display = {
		1185	.bandwidth_update = &rv515_bandwidth_update,
		1186	.get_vblank_counter = &rs600_get_vblank_counter,
		1187	.wait_for_vblank = &avivo_wait_for_vblank,
5078	serge	1188	.set_backlight_level = &atombios_set_backlight_level,
		1189	.get_backlight_level = &atombios_get_backlight_level,
		1190	.hdmi_enable = &r600_hdmi_enable,
		1191	.hdmi_setmode = &dce3_1_hdmi_setmode,
2997	Serge	1192	},
		1193	.copy = {
5078	serge	1194	.blit = &r600_copy_cpdma,
2997	Serge	1195	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3764	Serge	1196	.dma = &rv770_copy_dma,
3192	Serge	1197	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
3764	Serge	1198	.copy = &rv770_copy_dma,
3192	Serge	1199	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1200	},
		1201	.surface = {
		1202	.set_reg = r600_set_surface_reg,
		1203	.clear_reg = r600_clear_surface_reg,
		1204	},
		1205	.hpd = {
5078	serge	1206	.init = &r600_hpd_init,
		1207	.fini = &r600_hpd_fini,
		1208	.sense = &r600_hpd_sense,
		1209	.set_polarity = &r600_hpd_set_polarity,
2997	Serge	1210	},
		1211	.pm = {
5078	serge	1212	.misc = &rv770_pm_misc,
		1213	.prepare = &rs600_pm_prepare,
		1214	.finish = &rs600_pm_finish,
		1215	.init_profile = &r600_pm_init_profile,
		1216	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1217	.get_engine_clock = &radeon_atom_get_engine_clock,
		1218	.set_engine_clock = &radeon_atom_set_engine_clock,
		1219	.get_memory_clock = &radeon_atom_get_memory_clock,
		1220	.set_memory_clock = &radeon_atom_set_memory_clock,
		1221	.get_pcie_lanes = &r600_get_pcie_lanes,
		1222	.set_pcie_lanes = &r600_set_pcie_lanes,
		1223	.set_clock_gating = &radeon_atom_set_clock_gating,
3764	Serge	1224	.set_uvd_clocks = &rv770_set_uvd_clocks,
5078	serge	1225	.get_temperature = &rv770_get_temp,
2997	Serge	1226	},
5078	serge	1227	.dpm = {
		1228	.init = &rv770_dpm_init,
		1229	.setup_asic = &rv770_dpm_setup_asic,
		1230	.enable = &rv770_dpm_enable,
		1231	.late_enable = &rv770_dpm_late_enable,
		1232	.disable = &rv770_dpm_disable,
		1233	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1234	.set_power_state = &rv770_dpm_set_power_state,
		1235	.post_set_power_state = &r600_dpm_post_set_power_state,
		1236	.display_configuration_changed = &rv770_dpm_display_configuration_changed,
		1237	.fini = &rv770_dpm_fini,
		1238	.get_sclk = &rv770_dpm_get_sclk,
		1239	.get_mclk = &rv770_dpm_get_mclk,
		1240	.print_power_state = &rv770_dpm_print_power_state,
		1241	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1242	.force_performance_level = &rv770_dpm_force_performance_level,
		1243	.vblank_too_short = &rv770_dpm_vblank_too_short,
		1244	},
2997	Serge	1245	.pflip = {
		1246	// .pre_page_flip = &rs600_pre_page_flip,
		1247	// .page_flip = &rv770_page_flip,
		1248	},
1963	serge	1249	};
1986	serge	1250
5078	serge	1251	static struct radeon_asic_ring evergreen_gfx_ring = {
		1252	.ib_execute = &evergreen_ring_ib_execute,
		1253	.emit_fence = &r600_fence_ring_emit,
		1254	.emit_semaphore = &r600_semaphore_ring_emit,
		1255	.cs_parse = &evergreen_cs_parse,
		1256	.ring_test = &r600_ring_test,
		1257	.ib_test = &r600_ib_test,
		1258	.is_lockup = &evergreen_gfx_is_lockup,
		1259	.get_rptr = &r600_gfx_get_rptr,
		1260	.get_wptr = &r600_gfx_get_wptr,
		1261	.set_wptr = &r600_gfx_set_wptr,
		1262	};
		1263
		1264	static struct radeon_asic_ring evergreen_dma_ring = {
		1265	.ib_execute = &evergreen_dma_ring_ib_execute,
		1266	.emit_fence = &evergreen_dma_fence_ring_emit,
		1267	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1268	.cs_parse = &evergreen_dma_cs_parse,
		1269	.ring_test = &r600_dma_ring_test,
		1270	.ib_test = &r600_dma_ib_test,
		1271	.is_lockup = &evergreen_dma_is_lockup,
		1272	.get_rptr = &r600_dma_get_rptr,
		1273	.get_wptr = &r600_dma_get_wptr,
		1274	.set_wptr = &r600_dma_set_wptr,
		1275	};
		1276
1963	serge	1277	static struct radeon_asic evergreen_asic = {
		1278	.init = &evergreen_init,
		1279	// .fini = &evergreen_fini,
		1280	// .suspend = &evergreen_suspend,
		1281	// .resume = &evergreen_resume,
		1282	.asic_reset = &evergreen_asic_reset,
2997	Serge	1283	// .vga_set_state = &r600_vga_set_state,
5078	serge	1284	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1285	.gui_idle = &r600_gui_idle,
		1286	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1287	.get_xclk = &rv770_get_xclk,
		1288	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1289	.gart = {
		1290	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1291	.set_page = &rs600_gart_set_page,
		1292	},
		1293	.ring = {
5078	serge	1294	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1295	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1296	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1297	},
		1298	.irq = {
		1299	.set = &evergreen_irq_set,
		1300	.process = &evergreen_irq_process,
		1301	},
		1302	.display = {
		1303	.bandwidth_update = &evergreen_bandwidth_update,
		1304	.get_vblank_counter = &evergreen_get_vblank_counter,
		1305	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1306	.set_backlight_level = &atombios_set_backlight_level,
		1307	.get_backlight_level = &atombios_get_backlight_level,
		1308	.hdmi_enable = &evergreen_hdmi_enable,
		1309	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1310	},
		1311	.copy = {
5078	serge	1312	.blit = &r600_copy_cpdma,
2997	Serge	1313	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1314	.dma = &evergreen_copy_dma,
		1315	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1316	.copy = &evergreen_copy_dma,
		1317	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1318	},
		1319	.surface = {
		1320	.set_reg = r600_set_surface_reg,
		1321	.clear_reg = r600_clear_surface_reg,
		1322	},
		1323	.hpd = {
5078	serge	1324	.init = &evergreen_hpd_init,
		1325	.fini = &evergreen_hpd_fini,
		1326	.sense = &evergreen_hpd_sense,
		1327	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1328	},
		1329	.pm = {
5078	serge	1330	.misc = &evergreen_pm_misc,
		1331	.prepare = &evergreen_pm_prepare,
		1332	.finish = &evergreen_pm_finish,
		1333	.init_profile = &r600_pm_init_profile,
		1334	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1335	.get_engine_clock = &radeon_atom_get_engine_clock,
		1336	.set_engine_clock = &radeon_atom_set_engine_clock,
		1337	.get_memory_clock = &radeon_atom_get_memory_clock,
		1338	.set_memory_clock = &radeon_atom_set_memory_clock,
		1339	.get_pcie_lanes = &r600_get_pcie_lanes,
		1340	.set_pcie_lanes = &r600_set_pcie_lanes,
		1341	.set_clock_gating = NULL,
3764	Serge	1342	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1343	.get_temperature = &evergreen_get_temp,
2997	Serge	1344	},
5078	serge	1345	.dpm = {
		1346	.init = &cypress_dpm_init,
		1347	.setup_asic = &cypress_dpm_setup_asic,
		1348	.enable = &cypress_dpm_enable,
		1349	.late_enable = &rv770_dpm_late_enable,
		1350	.disable = &cypress_dpm_disable,
		1351	.pre_set_power_state = &r600_dpm_pre_set_power_state,
		1352	.set_power_state = &cypress_dpm_set_power_state,
		1353	.post_set_power_state = &r600_dpm_post_set_power_state,
		1354	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1355	.fini = &cypress_dpm_fini,
		1356	.get_sclk = &rv770_dpm_get_sclk,
		1357	.get_mclk = &rv770_dpm_get_mclk,
		1358	.print_power_state = &rv770_dpm_print_power_state,
		1359	.debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
		1360	.force_performance_level = &rv770_dpm_force_performance_level,
		1361	.vblank_too_short = &cypress_dpm_vblank_too_short,
		1362	},
2997	Serge	1363	.pflip = {
		1364	},
1986	serge	1365	};
1990	serge	1366
1986	serge	1367	static struct radeon_asic sumo_asic = {
		1368	.init = &evergreen_init,
1990	serge	1369	// .fini = &evergreen_fini,
		1370	// .suspend = &evergreen_suspend,
		1371	// .resume = &evergreen_resume,
1986	serge	1372	.asic_reset = &evergreen_asic_reset,
2997	Serge	1373	// .vga_set_state = &r600_vga_set_state,
5078	serge	1374	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1375	.gui_idle = &r600_gui_idle,
		1376	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1377	.get_xclk = &r600_get_xclk,
		1378	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1379	.gart = {
		1380	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1381	.set_page = &rs600_gart_set_page,
		1382	},
		1383	.ring = {
5078	serge	1384	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1385	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1386	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1387	},
		1388	.irq = {
		1389	.set = &evergreen_irq_set,
		1390	.process = &evergreen_irq_process,
		1391	},
		1392	.display = {
		1393	.bandwidth_update = &evergreen_bandwidth_update,
		1394	.get_vblank_counter = &evergreen_get_vblank_counter,
		1395	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1396	.set_backlight_level = &atombios_set_backlight_level,
		1397	.get_backlight_level = &atombios_get_backlight_level,
		1398	.hdmi_enable = &evergreen_hdmi_enable,
		1399	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1400	},
		1401	.copy = {
5078	serge	1402	.blit = &r600_copy_cpdma,
2997	Serge	1403	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1404	.dma = &evergreen_copy_dma,
		1405	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1406	.copy = &evergreen_copy_dma,
		1407	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1408	},
		1409	.surface = {
		1410	.set_reg = r600_set_surface_reg,
		1411	.clear_reg = r600_clear_surface_reg,
		1412	},
		1413	.hpd = {
5078	serge	1414	.init = &evergreen_hpd_init,
		1415	.fini = &evergreen_hpd_fini,
		1416	.sense = &evergreen_hpd_sense,
		1417	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1418	},
		1419	.pm = {
5078	serge	1420	.misc = &evergreen_pm_misc,
		1421	.prepare = &evergreen_pm_prepare,
		1422	.finish = &evergreen_pm_finish,
		1423	.init_profile = &sumo_pm_init_profile,
		1424	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1425	.get_engine_clock = &radeon_atom_get_engine_clock,
		1426	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1427	.get_memory_clock = NULL,
		1428	.set_memory_clock = NULL,
		1429	.get_pcie_lanes = NULL,
		1430	.set_pcie_lanes = NULL,
		1431	.set_clock_gating = NULL,
3764	Serge	1432	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1433	.get_temperature = &sumo_get_temp,
2997	Serge	1434	},
5078	serge	1435	.dpm = {
		1436	.init = &sumo_dpm_init,
		1437	.setup_asic = &sumo_dpm_setup_asic,
		1438	.enable = &sumo_dpm_enable,
		1439	.late_enable = &sumo_dpm_late_enable,
		1440	.disable = &sumo_dpm_disable,
		1441	.pre_set_power_state = &sumo_dpm_pre_set_power_state,
		1442	.set_power_state = &sumo_dpm_set_power_state,
		1443	.post_set_power_state = &sumo_dpm_post_set_power_state,
		1444	.display_configuration_changed = &sumo_dpm_display_configuration_changed,
		1445	.fini = &sumo_dpm_fini,
		1446	.get_sclk = &sumo_dpm_get_sclk,
		1447	.get_mclk = &sumo_dpm_get_mclk,
		1448	.print_power_state = &sumo_dpm_print_power_state,
		1449	.debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
		1450	.force_performance_level = &sumo_dpm_force_performance_level,
		1451	},
2997	Serge	1452	.pflip = {
		1453	// .pre_page_flip = &evergreen_pre_page_flip,
		1454	// .page_flip = &evergreen_page_flip,
		1455	},
1986	serge	1456	};
		1457
		1458	static struct radeon_asic btc_asic = {
		1459	.init = &evergreen_init,
1990	serge	1460	// .fini = &evergreen_fini,
		1461	// .suspend = &evergreen_suspend,
		1462	// .resume = &evergreen_resume,
1986	serge	1463	.asic_reset = &evergreen_asic_reset,
2997	Serge	1464	// .vga_set_state = &r600_vga_set_state,
5078	serge	1465	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1466	.gui_idle = &r600_gui_idle,
		1467	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1468	.get_xclk = &rv770_get_xclk,
		1469	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1470	.gart = {
		1471	.tlb_flush = &evergreen_pcie_gart_tlb_flush,
		1472	.set_page = &rs600_gart_set_page,
		1473	},
		1474	.ring = {
5078	serge	1475	[RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
		1476	[R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
		1477	[R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
2997	Serge	1478	},
		1479	.irq = {
		1480	.set = &evergreen_irq_set,
		1481	.process = &evergreen_irq_process,
		1482	},
		1483	.display = {
		1484	.bandwidth_update = &evergreen_bandwidth_update,
		1485	.get_vblank_counter = &evergreen_get_vblank_counter,
		1486	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1487	.set_backlight_level = &atombios_set_backlight_level,
		1488	.get_backlight_level = &atombios_get_backlight_level,
		1489	.hdmi_enable = &evergreen_hdmi_enable,
		1490	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1491	},
		1492	.copy = {
5078	serge	1493	.blit = &r600_copy_cpdma,
2997	Serge	1494	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1495	.dma = &evergreen_copy_dma,
		1496	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1497	.copy = &evergreen_copy_dma,
		1498	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1499	},
		1500	.surface = {
		1501	.set_reg = r600_set_surface_reg,
		1502	.clear_reg = r600_clear_surface_reg,
		1503	},
		1504	.hpd = {
5078	serge	1505	.init = &evergreen_hpd_init,
		1506	.fini = &evergreen_hpd_fini,
		1507	.sense = &evergreen_hpd_sense,
		1508	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1509	},
		1510	.pm = {
5078	serge	1511	.misc = &evergreen_pm_misc,
		1512	.prepare = &evergreen_pm_prepare,
		1513	.finish = &evergreen_pm_finish,
		1514	.init_profile = &btc_pm_init_profile,
		1515	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1516	.get_engine_clock = &radeon_atom_get_engine_clock,
		1517	.set_engine_clock = &radeon_atom_set_engine_clock,
		1518	.get_memory_clock = &radeon_atom_get_memory_clock,
		1519	.set_memory_clock = &radeon_atom_set_memory_clock,
		1520	.get_pcie_lanes = &r600_get_pcie_lanes,
		1521	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1522	.set_clock_gating = NULL,
3764	Serge	1523	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1524	.get_temperature = &evergreen_get_temp,
2997	Serge	1525	},
5078	serge	1526	.dpm = {
		1527	.init = &btc_dpm_init,
		1528	.setup_asic = &btc_dpm_setup_asic,
		1529	.enable = &btc_dpm_enable,
		1530	.late_enable = &rv770_dpm_late_enable,
		1531	.disable = &btc_dpm_disable,
		1532	.pre_set_power_state = &btc_dpm_pre_set_power_state,
		1533	.set_power_state = &btc_dpm_set_power_state,
		1534	.post_set_power_state = &btc_dpm_post_set_power_state,
		1535	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1536	.fini = &btc_dpm_fini,
		1537	.get_sclk = &btc_dpm_get_sclk,
		1538	.get_mclk = &btc_dpm_get_mclk,
		1539	.print_power_state = &rv770_dpm_print_power_state,
		1540	.debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
		1541	.force_performance_level = &rv770_dpm_force_performance_level,
		1542	.vblank_too_short = &btc_dpm_vblank_too_short,
		1543	},
2997	Serge	1544	.pflip = {
		1545	// .pre_page_flip = &evergreen_pre_page_flip,
		1546	// .page_flip = &evergreen_page_flip,
		1547	},
1986	serge	1548	};
		1549
5078	serge	1550	static struct radeon_asic_ring cayman_gfx_ring = {
		1551	.ib_execute = &cayman_ring_ib_execute,
		1552	.ib_parse = &evergreen_ib_parse,
		1553	.emit_fence = &cayman_fence_ring_emit,
		1554	.emit_semaphore = &r600_semaphore_ring_emit,
		1555	.cs_parse = &evergreen_cs_parse,
		1556	.ring_test = &r600_ring_test,
		1557	.ib_test = &r600_ib_test,
		1558	.is_lockup = &cayman_gfx_is_lockup,
		1559	.vm_flush = &cayman_vm_flush,
		1560	.get_rptr = &cayman_gfx_get_rptr,
		1561	.get_wptr = &cayman_gfx_get_wptr,
		1562	.set_wptr = &cayman_gfx_set_wptr,
		1563	};
		1564
		1565	static struct radeon_asic_ring cayman_dma_ring = {
		1566	.ib_execute = &cayman_dma_ring_ib_execute,
		1567	.ib_parse = &evergreen_dma_ib_parse,
		1568	.emit_fence = &evergreen_dma_fence_ring_emit,
		1569	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1570	.cs_parse = &evergreen_dma_cs_parse,
		1571	.ring_test = &r600_dma_ring_test,
		1572	.ib_test = &r600_dma_ib_test,
		1573	.is_lockup = &cayman_dma_is_lockup,
		1574	.vm_flush = &cayman_dma_vm_flush,
		1575	.get_rptr = &cayman_dma_get_rptr,
		1576	.get_wptr = &cayman_dma_get_wptr,
		1577	.set_wptr = &cayman_dma_set_wptr
		1578	};
		1579
		1580	static struct radeon_asic_ring cayman_uvd_ring = {
		1581	.ib_execute = &uvd_v1_0_ib_execute,
		1582	.emit_fence = &uvd_v2_2_fence_emit,
		1583	.emit_semaphore = &uvd_v3_1_semaphore_emit,
		1584	.cs_parse = &radeon_uvd_cs_parse,
		1585	.ring_test = &uvd_v1_0_ring_test,
		1586	.ib_test = &uvd_v1_0_ib_test,
		1587	.is_lockup = &radeon_ring_test_lockup,
		1588	.get_rptr = &uvd_v1_0_get_rptr,
		1589	.get_wptr = &uvd_v1_0_get_wptr,
		1590	.set_wptr = &uvd_v1_0_set_wptr,
		1591	};
		1592
1986	serge	1593	static struct radeon_asic cayman_asic = {
		1594	.init = &cayman_init,
2997	Serge	1595	// .fini = &cayman_fini,
		1596	// .suspend = &cayman_suspend,
		1597	// .resume = &cayman_resume,
1986	serge	1598	.asic_reset = &cayman_asic_reset,
2997	Serge	1599	// .vga_set_state = &r600_vga_set_state,
5078	serge	1600	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1601	.gui_idle = &r600_gui_idle,
		1602	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1603	.get_xclk = &rv770_get_xclk,
		1604	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1605	.gart = {
		1606	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1607	.set_page = &rs600_gart_set_page,
		1608	},
		1609	.vm = {
		1610	.init = &cayman_vm_init,
		1611	.fini = &cayman_vm_fini,
5078	serge	1612	.copy_pages = &cayman_dma_vm_copy_pages,
		1613	.write_pages = &cayman_dma_vm_write_pages,
		1614	.set_pages = &cayman_dma_vm_set_pages,
		1615	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1616	},
		1617	.ring = {
5078	serge	1618	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1619	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1620	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1621	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1622	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1623	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1624	},
		1625	.irq = {
		1626	.set = &evergreen_irq_set,
		1627	.process = &evergreen_irq_process,
		1628	},
		1629	.display = {
		1630	.bandwidth_update = &evergreen_bandwidth_update,
		1631	.get_vblank_counter = &evergreen_get_vblank_counter,
		1632	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1633	.set_backlight_level = &atombios_set_backlight_level,
		1634	.get_backlight_level = &atombios_get_backlight_level,
		1635	.hdmi_enable = &evergreen_hdmi_enable,
		1636	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1637	},
		1638	.copy = {
5078	serge	1639	.blit = &r600_copy_cpdma,
2997	Serge	1640	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1641	.dma = &evergreen_copy_dma,
		1642	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1643	.copy = &evergreen_copy_dma,
		1644	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1645	},
		1646	.surface = {
		1647	.set_reg = r600_set_surface_reg,
		1648	.clear_reg = r600_clear_surface_reg,
		1649	},
		1650	.hpd = {
5078	serge	1651	.init = &evergreen_hpd_init,
		1652	.fini = &evergreen_hpd_fini,
		1653	.sense = &evergreen_hpd_sense,
		1654	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1655	},
		1656	.pm = {
5078	serge	1657	.misc = &evergreen_pm_misc,
		1658	.prepare = &evergreen_pm_prepare,
		1659	.finish = &evergreen_pm_finish,
		1660	.init_profile = &btc_pm_init_profile,
		1661	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1662	.get_engine_clock = &radeon_atom_get_engine_clock,
		1663	.set_engine_clock = &radeon_atom_set_engine_clock,
		1664	.get_memory_clock = &radeon_atom_get_memory_clock,
		1665	.set_memory_clock = &radeon_atom_set_memory_clock,
		1666	.get_pcie_lanes = &r600_get_pcie_lanes,
		1667	.set_pcie_lanes = &r600_set_pcie_lanes,
3120	serge	1668	.set_clock_gating = NULL,
3764	Serge	1669	.set_uvd_clocks = &evergreen_set_uvd_clocks,
5078	serge	1670	.get_temperature = &evergreen_get_temp,
2997	Serge	1671	},
5078	serge	1672	.dpm = {
		1673	.init = &ni_dpm_init,
		1674	.setup_asic = &ni_dpm_setup_asic,
		1675	.enable = &ni_dpm_enable,
		1676	.late_enable = &rv770_dpm_late_enable,
		1677	.disable = &ni_dpm_disable,
		1678	.pre_set_power_state = &ni_dpm_pre_set_power_state,
		1679	.set_power_state = &ni_dpm_set_power_state,
		1680	.post_set_power_state = &ni_dpm_post_set_power_state,
		1681	.display_configuration_changed = &cypress_dpm_display_configuration_changed,
		1682	.fini = &ni_dpm_fini,
		1683	.get_sclk = &ni_dpm_get_sclk,
		1684	.get_mclk = &ni_dpm_get_mclk,
		1685	.print_power_state = &ni_dpm_print_power_state,
		1686	.debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
		1687	.force_performance_level = &ni_dpm_force_performance_level,
		1688	.vblank_too_short = &ni_dpm_vblank_too_short,
		1689	},
2997	Serge	1690	.pflip = {
		1691	// .pre_page_flip = &evergreen_pre_page_flip,
		1692	// .page_flip = &evergreen_page_flip,
		1693	},
1963	serge	1694	};
		1695
2997	Serge	1696	static struct radeon_asic trinity_asic = {
		1697	.init = &cayman_init,
		1698	// .fini = &cayman_fini,
		1699	// .suspend = &cayman_suspend,
		1700	// .resume = &cayman_resume,
		1701	.asic_reset = &cayman_asic_reset,
		1702	// .vga_set_state = &r600_vga_set_state,
5078	serge	1703	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1704	.gui_idle = &r600_gui_idle,
		1705	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1706	.get_xclk = &r600_get_xclk,
		1707	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
2997	Serge	1708	.gart = {
		1709	.tlb_flush = &cayman_pcie_gart_tlb_flush,
		1710	.set_page = &rs600_gart_set_page,
		1711	},
		1712	.vm = {
		1713	.init = &cayman_vm_init,
		1714	.fini = &cayman_vm_fini,
5078	serge	1715	.copy_pages = &cayman_dma_vm_copy_pages,
		1716	.write_pages = &cayman_dma_vm_write_pages,
		1717	.set_pages = &cayman_dma_vm_set_pages,
		1718	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1719	},
		1720	.ring = {
5078	serge	1721	[RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
		1722	[CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
		1723	[CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
		1724	[R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
		1725	[CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
		1726	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1727	},
		1728	.irq = {
		1729	.set = &evergreen_irq_set,
		1730	.process = &evergreen_irq_process,
		1731	},
		1732	.display = {
		1733	.bandwidth_update = &dce6_bandwidth_update,
		1734	.get_vblank_counter = &evergreen_get_vblank_counter,
		1735	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1736	.set_backlight_level = &atombios_set_backlight_level,
		1737	.get_backlight_level = &atombios_get_backlight_level,
		1738	.hdmi_enable = &evergreen_hdmi_enable,
		1739	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1740	},
		1741	.copy = {
5078	serge	1742	.blit = &r600_copy_cpdma,
2997	Serge	1743	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1744	.dma = &evergreen_copy_dma,
		1745	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1746	.copy = &evergreen_copy_dma,
		1747	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1748	},
		1749	.surface = {
		1750	.set_reg = r600_set_surface_reg,
		1751	.clear_reg = r600_clear_surface_reg,
		1752	},
		1753	.hpd = {
5078	serge	1754	.init = &evergreen_hpd_init,
		1755	.fini = &evergreen_hpd_fini,
		1756	.sense = &evergreen_hpd_sense,
		1757	.set_polarity = &evergreen_hpd_set_polarity,
2997	Serge	1758	},
		1759	.pm = {
5078	serge	1760	.misc = &evergreen_pm_misc,
		1761	.prepare = &evergreen_pm_prepare,
		1762	.finish = &evergreen_pm_finish,
		1763	.init_profile = &sumo_pm_init_profile,
		1764	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1765	.get_engine_clock = &radeon_atom_get_engine_clock,
		1766	.set_engine_clock = &radeon_atom_set_engine_clock,
3120	serge	1767	.get_memory_clock = NULL,
		1768	.set_memory_clock = NULL,
		1769	.get_pcie_lanes = NULL,
		1770	.set_pcie_lanes = NULL,
		1771	.set_clock_gating = NULL,
3764	Serge	1772	.set_uvd_clocks = &sumo_set_uvd_clocks,
5078	serge	1773	.get_temperature = &tn_get_temp,
2997	Serge	1774	},
5078	serge	1775	.dpm = {
		1776	.init = &trinity_dpm_init,
		1777	.setup_asic = &trinity_dpm_setup_asic,
		1778	.enable = &trinity_dpm_enable,
		1779	.late_enable = &trinity_dpm_late_enable,
		1780	.disable = &trinity_dpm_disable,
		1781	.pre_set_power_state = &trinity_dpm_pre_set_power_state,
		1782	.set_power_state = &trinity_dpm_set_power_state,
		1783	.post_set_power_state = &trinity_dpm_post_set_power_state,
		1784	.display_configuration_changed = &trinity_dpm_display_configuration_changed,
		1785	.fini = &trinity_dpm_fini,
		1786	.get_sclk = &trinity_dpm_get_sclk,
		1787	.get_mclk = &trinity_dpm_get_mclk,
		1788	.print_power_state = &trinity_dpm_print_power_state,
		1789	.debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
		1790	.force_performance_level = &trinity_dpm_force_performance_level,
		1791	.enable_bapm = &trinity_dpm_enable_bapm,
		1792	},
2997	Serge	1793	.pflip = {
		1794	// .pre_page_flip = &evergreen_pre_page_flip,
		1795	// .page_flip = &evergreen_page_flip,
		1796	},
		1797	};
		1798
5078	serge	1799	static struct radeon_asic_ring si_gfx_ring = {
		1800	.ib_execute = &si_ring_ib_execute,
		1801	.ib_parse = &si_ib_parse,
		1802	.emit_fence = &si_fence_ring_emit,
		1803	.emit_semaphore = &r600_semaphore_ring_emit,
		1804	.cs_parse = NULL,
		1805	.ring_test = &r600_ring_test,
		1806	.ib_test = &r600_ib_test,
		1807	.is_lockup = &si_gfx_is_lockup,
		1808	.vm_flush = &si_vm_flush,
		1809	.get_rptr = &cayman_gfx_get_rptr,
		1810	.get_wptr = &cayman_gfx_get_wptr,
		1811	.set_wptr = &cayman_gfx_set_wptr,
		1812	};
		1813
		1814	static struct radeon_asic_ring si_dma_ring = {
		1815	.ib_execute = &cayman_dma_ring_ib_execute,
		1816	.ib_parse = &evergreen_dma_ib_parse,
		1817	.emit_fence = &evergreen_dma_fence_ring_emit,
		1818	.emit_semaphore = &r600_dma_semaphore_ring_emit,
		1819	.cs_parse = NULL,
		1820	.ring_test = &r600_dma_ring_test,
		1821	.ib_test = &r600_dma_ib_test,
		1822	.is_lockup = &si_dma_is_lockup,
		1823	.vm_flush = &si_dma_vm_flush,
		1824	.get_rptr = &cayman_dma_get_rptr,
		1825	.get_wptr = &cayman_dma_get_wptr,
		1826	.set_wptr = &cayman_dma_set_wptr,
		1827	};
		1828
2997	Serge	1829	static struct radeon_asic si_asic = {
		1830	.init = &si_init,
		1831	// .fini = &si_fini,
		1832	// .suspend = &si_suspend,
		1833	// .resume = &si_resume,
		1834	.asic_reset = &si_asic_reset,
		1835	// .vga_set_state = &r600_vga_set_state,
5078	serge	1836	.mmio_hdp_flush = r600_mmio_hdp_flush,
2997	Serge	1837	.gui_idle = &r600_gui_idle,
		1838	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
3764	Serge	1839	.get_xclk = &si_get_xclk,
		1840	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
2997	Serge	1841	.gart = {
		1842	.tlb_flush = &si_pcie_gart_tlb_flush,
		1843	.set_page = &rs600_gart_set_page,
		1844	},
		1845	.vm = {
		1846	.init = &si_vm_init,
		1847	.fini = &si_vm_fini,
5078	serge	1848	.copy_pages = &si_dma_vm_copy_pages,
		1849	.write_pages = &si_dma_vm_write_pages,
		1850	.set_pages = &si_dma_vm_set_pages,
		1851	.pad_ib = &cayman_dma_vm_pad_ib,
2997	Serge	1852	},
		1853	.ring = {
5078	serge	1854	[RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
		1855	[CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
		1856	[CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
		1857	[R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
		1858	[CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
		1859	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2997	Serge	1860	},
		1861	.irq = {
		1862	.set = &si_irq_set,
		1863	.process = &si_irq_process,
		1864	},
		1865	.display = {
		1866	.bandwidth_update = &dce6_bandwidth_update,
		1867	.get_vblank_counter = &evergreen_get_vblank_counter,
		1868	.wait_for_vblank = &dce4_wait_for_vblank,
5078	serge	1869	.set_backlight_level = &atombios_set_backlight_level,
		1870	.get_backlight_level = &atombios_get_backlight_level,
		1871	.hdmi_enable = &evergreen_hdmi_enable,
		1872	.hdmi_setmode = &evergreen_hdmi_setmode,
2997	Serge	1873	},
		1874	.copy = {
5078	serge	1875	.blit = &r600_copy_cpdma,
2997	Serge	1876	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
3192	Serge	1877	.dma = &si_copy_dma,
		1878	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		1879	.copy = &si_copy_dma,
		1880	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2997	Serge	1881	},
		1882	.surface = {
		1883	.set_reg = r600_set_surface_reg,
		1884	.clear_reg = r600_clear_surface_reg,
		1885	},
		1886	.hpd = {
		1887	.init = &evergreen_hpd_init,
		1888	.fini = &evergreen_hpd_fini,
		1889	.sense = &evergreen_hpd_sense,
		1890	.set_polarity = &evergreen_hpd_set_polarity,
		1891	},
		1892	.pm = {
5078	serge	1893	.misc = &evergreen_pm_misc,
		1894	.prepare = &evergreen_pm_prepare,
		1895	.finish = &evergreen_pm_finish,
		1896	.init_profile = &sumo_pm_init_profile,
		1897	.get_dynpm_state = &r600_pm_get_dynpm_state,
		1898	.get_engine_clock = &radeon_atom_get_engine_clock,
		1899	.set_engine_clock = &radeon_atom_set_engine_clock,
		1900	.get_memory_clock = &radeon_atom_get_memory_clock,
		1901	.set_memory_clock = &radeon_atom_set_memory_clock,
		1902	.get_pcie_lanes = &r600_get_pcie_lanes,
		1903	.set_pcie_lanes = &r600_set_pcie_lanes,
		1904	.set_clock_gating = NULL,
		1905	.set_uvd_clocks = &si_set_uvd_clocks,
		1906	.get_temperature = &si_get_temp,
		1907	},
		1908	.dpm = {
		1909	.init = &si_dpm_init,
		1910	.setup_asic = &si_dpm_setup_asic,
		1911	.enable = &si_dpm_enable,
		1912	.late_enable = &si_dpm_late_enable,
		1913	.disable = &si_dpm_disable,
		1914	.pre_set_power_state = &si_dpm_pre_set_power_state,
		1915	.set_power_state = &si_dpm_set_power_state,
		1916	.post_set_power_state = &si_dpm_post_set_power_state,
		1917	.display_configuration_changed = &si_dpm_display_configuration_changed,
		1918	.fini = &si_dpm_fini,
		1919	.get_sclk = &ni_dpm_get_sclk,
		1920	.get_mclk = &ni_dpm_get_mclk,
		1921	.print_power_state = &ni_dpm_print_power_state,
		1922	.debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
		1923	.force_performance_level = &si_dpm_force_performance_level,
		1924	.vblank_too_short = &ni_dpm_vblank_too_short,
		1925	},
		1926	.pflip = {
		1927	// .pre_page_flip = &evergreen_pre_page_flip,
		1928	// .page_flip = &evergreen_page_flip,
		1929	},
		1930	};
		1931
		1932	static struct radeon_asic_ring ci_gfx_ring = {
		1933	.ib_execute = &cik_ring_ib_execute,
		1934	.ib_parse = &cik_ib_parse,
		1935	.emit_fence = &cik_fence_gfx_ring_emit,
		1936	.emit_semaphore = &cik_semaphore_ring_emit,
		1937	.cs_parse = NULL,
		1938	.ring_test = &cik_ring_test,
		1939	.ib_test = &cik_ib_test,
		1940	.is_lockup = &cik_gfx_is_lockup,
		1941	.vm_flush = &cik_vm_flush,
		1942	.get_rptr = &cik_gfx_get_rptr,
		1943	.get_wptr = &cik_gfx_get_wptr,
		1944	.set_wptr = &cik_gfx_set_wptr,
		1945	};
		1946
		1947	static struct radeon_asic_ring ci_cp_ring = {
		1948	.ib_execute = &cik_ring_ib_execute,
		1949	.ib_parse = &cik_ib_parse,
		1950	.emit_fence = &cik_fence_compute_ring_emit,
		1951	.emit_semaphore = &cik_semaphore_ring_emit,
		1952	.cs_parse = NULL,
		1953	.ring_test = &cik_ring_test,
		1954	.ib_test = &cik_ib_test,
		1955	.is_lockup = &cik_gfx_is_lockup,
		1956	.vm_flush = &cik_vm_flush,
		1957	.get_rptr = &cik_compute_get_rptr,
		1958	.get_wptr = &cik_compute_get_wptr,
		1959	.set_wptr = &cik_compute_set_wptr,
		1960	};
		1961
		1962	static struct radeon_asic_ring ci_dma_ring = {
		1963	.ib_execute = &cik_sdma_ring_ib_execute,
		1964	.ib_parse = &cik_ib_parse,
		1965	.emit_fence = &cik_sdma_fence_ring_emit,
		1966	.emit_semaphore = &cik_sdma_semaphore_ring_emit,
		1967	.cs_parse = NULL,
		1968	.ring_test = &cik_sdma_ring_test,
		1969	.ib_test = &cik_sdma_ib_test,
		1970	.is_lockup = &cik_sdma_is_lockup,
		1971	.vm_flush = &cik_dma_vm_flush,
		1972	.get_rptr = &cik_sdma_get_rptr,
		1973	.get_wptr = &cik_sdma_get_wptr,
		1974	.set_wptr = &cik_sdma_set_wptr,
		1975	};
		1976
		1977	static struct radeon_asic_ring ci_vce_ring = {
		1978	.ib_execute = &radeon_vce_ib_execute,
		1979	.emit_fence = &radeon_vce_fence_emit,
		1980	.emit_semaphore = &radeon_vce_semaphore_emit,
		1981	.cs_parse = &radeon_vce_cs_parse,
		1982	.ring_test = &radeon_vce_ring_test,
		1983	.ib_test = &radeon_vce_ib_test,
		1984	.is_lockup = &radeon_ring_test_lockup,
		1985	.get_rptr = &vce_v1_0_get_rptr,
		1986	.get_wptr = &vce_v1_0_get_wptr,
		1987	.set_wptr = &vce_v1_0_set_wptr,
		1988	};
		1989
		1990	static struct radeon_asic ci_asic = {
		1991	.init = &cik_init,
		1992	// .fini = &si_fini,
		1993	// .suspend = &si_suspend,
		1994	// .resume = &si_resume,
		1995	.asic_reset = &cik_asic_reset,
		1996	// .vga_set_state = &r600_vga_set_state,
		1997	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		1998	.gui_idle = &r600_gui_idle,
		1999	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2000	.get_xclk = &cik_get_xclk,
		2001	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
		2002	.gart = {
		2003	.tlb_flush = &cik_pcie_gart_tlb_flush,
		2004	.set_page = &rs600_gart_set_page,
		2005	},
		2006	.vm = {
		2007	.init = &cik_vm_init,
		2008	.fini = &cik_vm_fini,
		2009	.copy_pages = &cik_sdma_vm_copy_pages,
		2010	.write_pages = &cik_sdma_vm_write_pages,
		2011	.set_pages = &cik_sdma_vm_set_pages,
		2012	.pad_ib = &cik_sdma_vm_pad_ib,
		2013	},
		2014	.ring = {
		2015	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2016	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2017	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2018	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2019	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2020	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2021	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2022	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2023	},
		2024	.irq = {
		2025	.set = &cik_irq_set,
		2026	.process = &cik_irq_process,
		2027	},
		2028	.display = {
		2029	.bandwidth_update = &dce8_bandwidth_update,
		2030	.get_vblank_counter = &evergreen_get_vblank_counter,
		2031	.wait_for_vblank = &dce4_wait_for_vblank,
		2032	.set_backlight_level = &atombios_set_backlight_level,
		2033	.get_backlight_level = &atombios_get_backlight_level,
		2034	.hdmi_enable = &evergreen_hdmi_enable,
		2035	.hdmi_setmode = &evergreen_hdmi_setmode,
		2036	},
		2037	.copy = {
		2038	.blit = &cik_copy_cpdma,
		2039	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2040	.dma = &cik_copy_dma,
		2041	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2042	.copy = &cik_copy_dma,
		2043	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2044	},
		2045	.surface = {
		2046	.set_reg = r600_set_surface_reg,
		2047	.clear_reg = r600_clear_surface_reg,
		2048	},
		2049	.hpd = {
		2050	.init = &evergreen_hpd_init,
		2051	.fini = &evergreen_hpd_fini,
		2052	.sense = &evergreen_hpd_sense,
		2053	.set_polarity = &evergreen_hpd_set_polarity,
		2054	},
		2055	.pm = {
		2056	.misc = &evergreen_pm_misc,
		2057	.prepare = &evergreen_pm_prepare,
		2058	.finish = &evergreen_pm_finish,
		2059	.init_profile = &sumo_pm_init_profile,
		2060	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2061	.get_engine_clock = &radeon_atom_get_engine_clock,
		2062	.set_engine_clock = &radeon_atom_set_engine_clock,
		2063	.get_memory_clock = &radeon_atom_get_memory_clock,
		2064	.set_memory_clock = &radeon_atom_set_memory_clock,
3120	serge	2065	.get_pcie_lanes = NULL,
		2066	.set_pcie_lanes = NULL,
		2067	.set_clock_gating = NULL,
5078	serge	2068	.set_uvd_clocks = &cik_set_uvd_clocks,
		2069	.set_vce_clocks = &cik_set_vce_clocks,
		2070	.get_temperature = &ci_get_temp,
2997	Serge	2071	},
5078	serge	2072	.dpm = {
		2073	.init = &ci_dpm_init,
		2074	.setup_asic = &ci_dpm_setup_asic,
		2075	.enable = &ci_dpm_enable,
		2076	.late_enable = &ci_dpm_late_enable,
		2077	.disable = &ci_dpm_disable,
		2078	.pre_set_power_state = &ci_dpm_pre_set_power_state,
		2079	.set_power_state = &ci_dpm_set_power_state,
		2080	.post_set_power_state = &ci_dpm_post_set_power_state,
		2081	.display_configuration_changed = &ci_dpm_display_configuration_changed,
		2082	.fini = &ci_dpm_fini,
		2083	.get_sclk = &ci_dpm_get_sclk,
		2084	.get_mclk = &ci_dpm_get_mclk,
		2085	.print_power_state = &ci_dpm_print_power_state,
		2086	.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
		2087	.force_performance_level = &ci_dpm_force_performance_level,
		2088	.vblank_too_short = &ci_dpm_vblank_too_short,
		2089	.powergate_uvd = &ci_dpm_powergate_uvd,
		2090	},
2997	Serge	2091	.pflip = {
		2092	// .pre_page_flip = &evergreen_pre_page_flip,
		2093	// .page_flip = &evergreen_page_flip,
		2094	},
		2095	};
		2096
5078	serge	2097	static struct radeon_asic kv_asic = {
		2098	.init = &cik_init,
		2099	// .fini = &si_fini,
		2100	// .suspend = &si_suspend,
		2101	// .resume = &si_resume,
		2102	.asic_reset = &cik_asic_reset,
		2103	// .vga_set_state = &r600_vga_set_state,
		2104	.mmio_hdp_flush = &r600_mmio_hdp_flush,
		2105	.gui_idle = &r600_gui_idle,
		2106	.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
		2107	.get_xclk = &cik_get_xclk,
		2108	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
		2109	.gart = {
		2110	.tlb_flush = &cik_pcie_gart_tlb_flush,
		2111	.set_page = &rs600_gart_set_page,
		2112	},
		2113	.vm = {
		2114	.init = &cik_vm_init,
		2115	.fini = &cik_vm_fini,
		2116	.copy_pages = &cik_sdma_vm_copy_pages,
		2117	.write_pages = &cik_sdma_vm_write_pages,
		2118	.set_pages = &cik_sdma_vm_set_pages,
		2119	.pad_ib = &cik_sdma_vm_pad_ib,
		2120	},
		2121	.ring = {
		2122	[RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
		2123	[CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
		2124	[CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
		2125	[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
		2126	[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
		2127	[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
		2128	[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
		2129	[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
		2130	},
		2131	.irq = {
		2132	.set = &cik_irq_set,
		2133	.process = &cik_irq_process,
		2134	},
		2135	.display = {
		2136	.bandwidth_update = &dce8_bandwidth_update,
		2137	.get_vblank_counter = &evergreen_get_vblank_counter,
		2138	.wait_for_vblank = &dce4_wait_for_vblank,
		2139	.set_backlight_level = &atombios_set_backlight_level,
		2140	.get_backlight_level = &atombios_get_backlight_level,
		2141	.hdmi_enable = &evergreen_hdmi_enable,
		2142	.hdmi_setmode = &evergreen_hdmi_setmode,
		2143	},
		2144	.copy = {
		2145	.blit = &cik_copy_cpdma,
		2146	.blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
		2147	.dma = &cik_copy_dma,
		2148	.dma_ring_index = R600_RING_TYPE_DMA_INDEX,
		2149	.copy = &cik_copy_dma,
		2150	.copy_ring_index = R600_RING_TYPE_DMA_INDEX,
		2151	},
		2152	.surface = {
		2153	.set_reg = r600_set_surface_reg,
		2154	.clear_reg = r600_clear_surface_reg,
		2155	},
		2156	.hpd = {
		2157	.init = &evergreen_hpd_init,
		2158	.fini = &evergreen_hpd_fini,
		2159	.sense = &evergreen_hpd_sense,
		2160	.set_polarity = &evergreen_hpd_set_polarity,
		2161	},
		2162	.pm = {
		2163	.misc = &evergreen_pm_misc,
		2164	.prepare = &evergreen_pm_prepare,
		2165	.finish = &evergreen_pm_finish,
		2166	.init_profile = &sumo_pm_init_profile,
		2167	.get_dynpm_state = &r600_pm_get_dynpm_state,
		2168	.get_engine_clock = &radeon_atom_get_engine_clock,
		2169	.set_engine_clock = &radeon_atom_set_engine_clock,
		2170	.get_memory_clock = &radeon_atom_get_memory_clock,
		2171	.set_memory_clock = &radeon_atom_set_memory_clock,
		2172	.get_pcie_lanes = NULL,
		2173	.set_pcie_lanes = NULL,
		2174	.set_clock_gating = NULL,
		2175	.set_uvd_clocks = &cik_set_uvd_clocks,
		2176	.set_vce_clocks = &cik_set_vce_clocks,
		2177	.get_temperature = &kv_get_temp,
		2178	},
		2179	.dpm = {
		2180	.init = &kv_dpm_init,
		2181	.setup_asic = &kv_dpm_setup_asic,
		2182	.enable = &kv_dpm_enable,
		2183	.late_enable = &kv_dpm_late_enable,
		2184	.disable = &kv_dpm_disable,
		2185	.pre_set_power_state = &kv_dpm_pre_set_power_state,
		2186	.set_power_state = &kv_dpm_set_power_state,
		2187	.post_set_power_state = &kv_dpm_post_set_power_state,
		2188	.display_configuration_changed = &kv_dpm_display_configuration_changed,
		2189	.fini = &kv_dpm_fini,
		2190	.get_sclk = &kv_dpm_get_sclk,
		2191	.get_mclk = &kv_dpm_get_mclk,
		2192	.print_power_state = &kv_dpm_print_power_state,
		2193	.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
		2194	.force_performance_level = &kv_dpm_force_performance_level,
		2195	.powergate_uvd = &kv_dpm_powergate_uvd,
		2196	.enable_bapm = &kv_dpm_enable_bapm,
		2197	},
		2198	.pflip = {
		2199	// .pre_page_flip = &evergreen_pre_page_flip,
		2200	// .page_flip = &evergreen_page_flip,
		2201	},
		2202	};
		2203
2997	Serge	2204	/**
		2205	* radeon_asic_init - register asic specific callbacks
		2206	*
		2207	* @rdev: radeon device pointer
		2208	*
		2209	* Registers the appropriate asic specific callbacks for each
		2210	* chip family. Also sets other asics specific info like the number
		2211	* of crtcs and the register aperture accessors (all asics).
		2212	* Returns 0 for success.
		2213	*/
1963	serge	2214	int radeon_asic_init(struct radeon_device *rdev)
		2215	{
		2216	radeon_register_accessor_init(rdev);
1986	serge	2217
		2218	/* set the number of crtcs */
		2219	if (rdev->flags & RADEON_SINGLE_CRTC)
		2220	rdev->num_crtc = 1;
		2221	else
		2222	rdev->num_crtc = 2;
		2223
3764	Serge	2224	rdev->has_uvd = false;
		2225
1963	serge	2226	switch (rdev->family) {
		2227	case CHIP_R100:
		2228	case CHIP_RV100:
		2229	case CHIP_RS100:
		2230	case CHIP_RV200:
		2231	case CHIP_RS200:
		2232	rdev->asic = &r100_asic;
		2233	break;
		2234	case CHIP_R200:
		2235	case CHIP_RV250:
		2236	case CHIP_RS300:
		2237	case CHIP_RV280:
		2238	rdev->asic = &r200_asic;
		2239	break;
		2240	case CHIP_R300:
		2241	case CHIP_R350:
		2242	case CHIP_RV350:
		2243	case CHIP_RV380:
		2244	if (rdev->flags & RADEON_IS_PCIE)
		2245	rdev->asic = &r300_asic_pcie;
		2246	else
		2247	rdev->asic = &r300_asic;
		2248	break;
		2249	case CHIP_R420:
		2250	case CHIP_R423:
		2251	case CHIP_RV410:
		2252	rdev->asic = &r420_asic;
		2253	/* handle macs */
		2254	if (rdev->bios == NULL) {
2997	Serge	2255	rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
		2256	rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
		2257	rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
		2258	rdev->asic->pm.set_memory_clock = NULL;
		2259	rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1963	serge	2260	}
		2261	break;
		2262	case CHIP_RS400:
		2263	case CHIP_RS480:
		2264	rdev->asic = &rs400_asic;
		2265	break;
		2266	case CHIP_RS600:
		2267	rdev->asic = &rs600_asic;
		2268	break;
		2269	case CHIP_RS690:
		2270	case CHIP_RS740:
		2271	rdev->asic = &rs690_asic;
		2272	break;
		2273	case CHIP_RV515:
		2274	rdev->asic = &rv515_asic;
		2275	break;
		2276	case CHIP_R520:
		2277	case CHIP_RV530:
		2278	case CHIP_RV560:
		2279	case CHIP_RV570:
		2280	case CHIP_R580:
		2281	rdev->asic = &r520_asic;
		2282	break;
		2283	case CHIP_R600:
5078	serge	2284	rdev->asic = &r600_asic;
		2285	break;
1963	serge	2286	case CHIP_RV610:
		2287	case CHIP_RV630:
		2288	case CHIP_RV620:
		2289	case CHIP_RV635:
		2290	case CHIP_RV670:
5078	serge	2291	rdev->asic = &rv6xx_asic;
3764	Serge	2292	rdev->has_uvd = true;
1963	serge	2293	break;
		2294	case CHIP_RS780:
		2295	case CHIP_RS880:
		2296	rdev->asic = &rs780_asic;
5271	serge	2297	/* 760G/780V/880V don't have UVD */
		2298	if ((rdev->pdev->device == 0x9616)\|\|
		2299	(rdev->pdev->device == 0x9611)\|\|
		2300	(rdev->pdev->device == 0x9613)\|\|
		2301	(rdev->pdev->device == 0x9711)\|\|
		2302	(rdev->pdev->device == 0x9713))
		2303	rdev->has_uvd = false;
		2304	else
3764	Serge	2305	rdev->has_uvd = true;
1963	serge	2306	break;
		2307	case CHIP_RV770:
		2308	case CHIP_RV730:
		2309	case CHIP_RV710:
		2310	case CHIP_RV740:
		2311	rdev->asic = &rv770_asic;
3764	Serge	2312	rdev->has_uvd = true;
1963	serge	2313	break;
1986	serge	2314	case CHIP_CEDAR:
		2315	case CHIP_REDWOOD:
		2316	case CHIP_JUNIPER:
		2317	case CHIP_CYPRESS:
		2318	case CHIP_HEMLOCK:
		2319	/* set num crtcs */
		2320	if (rdev->family == CHIP_CEDAR)
		2321	rdev->num_crtc = 4;
		2322	else
		2323	rdev->num_crtc = 6;
		2324	rdev->asic = &evergreen_asic;
3764	Serge	2325	rdev->has_uvd = true;
1986	serge	2326	break;
1990	serge	2327	case CHIP_PALM:
		2328	case CHIP_SUMO:
		2329	case CHIP_SUMO2:
		2330	rdev->asic = &sumo_asic;
3764	Serge	2331	rdev->has_uvd = true;
1990	serge	2332	break;
		2333	case CHIP_BARTS:
		2334	case CHIP_TURKS:
		2335	case CHIP_CAICOS:
		2336	/* set num crtcs */
		2337	if (rdev->family == CHIP_CAICOS)
		2338	rdev->num_crtc = 4;
		2339	else
		2340	rdev->num_crtc = 6;
		2341	rdev->asic = &btc_asic;
3764	Serge	2342	rdev->has_uvd = true;
1990	serge	2343	break;
2004	serge	2344	case CHIP_CAYMAN:
		2345	rdev->asic = &cayman_asic;
		2346	/* set num crtcs */
		2347	rdev->num_crtc = 6;
3764	Serge	2348	rdev->has_uvd = true;
2004	serge	2349	break;
2997	Serge	2350	case CHIP_ARUBA:
		2351	rdev->asic = &trinity_asic;
		2352	/* set num crtcs */
		2353	rdev->num_crtc = 4;
3764	Serge	2354	rdev->has_uvd = true;
2997	Serge	2355	break;
		2356	case CHIP_TAHITI:
		2357	case CHIP_PITCAIRN:
		2358	case CHIP_VERDE:
3764	Serge	2359	case CHIP_OLAND:
		2360	case CHIP_HAINAN:
2997	Serge	2361	rdev->asic = &si_asic;
		2362	/* set num crtcs */
3764	Serge	2363	if (rdev->family == CHIP_HAINAN)
		2364	rdev->num_crtc = 0;
		2365	else if (rdev->family == CHIP_OLAND)
		2366	rdev->num_crtc = 2;
		2367	else
2997	Serge	2368	rdev->num_crtc = 6;
3764	Serge	2369	if (rdev->family == CHIP_HAINAN)
		2370	rdev->has_uvd = false;
		2371	else
		2372	rdev->has_uvd = true;
5078	serge	2373	switch (rdev->family) {
		2374	case CHIP_TAHITI:
		2375	rdev->cg_flags =
		2376	RADEON_CG_SUPPORT_GFX_MGCG \|
		2377	RADEON_CG_SUPPORT_GFX_MGLS \|
		2378	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2379	RADEON_CG_SUPPORT_GFX_CGLS \|
		2380	RADEON_CG_SUPPORT_GFX_CGTS \|
		2381	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2382	RADEON_CG_SUPPORT_MC_MGCG \|
		2383	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2384	RADEON_CG_SUPPORT_BIF_LS \|
		2385	RADEON_CG_SUPPORT_VCE_MGCG \|
		2386	RADEON_CG_SUPPORT_UVD_MGCG \|
		2387	RADEON_CG_SUPPORT_HDP_LS \|
		2388	RADEON_CG_SUPPORT_HDP_MGCG;
		2389	rdev->pg_flags = 0;
		2390	break;
		2391	case CHIP_PITCAIRN:
		2392	rdev->cg_flags =
		2393	RADEON_CG_SUPPORT_GFX_MGCG \|
		2394	RADEON_CG_SUPPORT_GFX_MGLS \|
		2395	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2396	RADEON_CG_SUPPORT_GFX_CGLS \|
		2397	RADEON_CG_SUPPORT_GFX_CGTS \|
		2398	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2399	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2400	RADEON_CG_SUPPORT_MC_LS \|
		2401	RADEON_CG_SUPPORT_MC_MGCG \|
		2402	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2403	RADEON_CG_SUPPORT_BIF_LS \|
		2404	RADEON_CG_SUPPORT_VCE_MGCG \|
		2405	RADEON_CG_SUPPORT_UVD_MGCG \|
		2406	RADEON_CG_SUPPORT_HDP_LS \|
		2407	RADEON_CG_SUPPORT_HDP_MGCG;
		2408	rdev->pg_flags = 0;
		2409	break;
		2410	case CHIP_VERDE:
		2411	rdev->cg_flags =
		2412	RADEON_CG_SUPPORT_GFX_MGCG \|
		2413	RADEON_CG_SUPPORT_GFX_MGLS \|
		2414	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2415	RADEON_CG_SUPPORT_GFX_CGLS \|
		2416	RADEON_CG_SUPPORT_GFX_CGTS \|
		2417	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2418	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2419	RADEON_CG_SUPPORT_MC_LS \|
		2420	RADEON_CG_SUPPORT_MC_MGCG \|
		2421	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2422	RADEON_CG_SUPPORT_BIF_LS \|
		2423	RADEON_CG_SUPPORT_VCE_MGCG \|
		2424	RADEON_CG_SUPPORT_UVD_MGCG \|
		2425	RADEON_CG_SUPPORT_HDP_LS \|
		2426	RADEON_CG_SUPPORT_HDP_MGCG;
		2427	rdev->pg_flags = 0 \|
		2428	/RADEON_PG_SUPPORT_GFX_PG \| /
		2429	RADEON_PG_SUPPORT_SDMA;
		2430	break;
		2431	case CHIP_OLAND:
		2432	rdev->cg_flags =
		2433	RADEON_CG_SUPPORT_GFX_MGCG \|
		2434	RADEON_CG_SUPPORT_GFX_MGLS \|
		2435	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2436	RADEON_CG_SUPPORT_GFX_CGLS \|
		2437	RADEON_CG_SUPPORT_GFX_CGTS \|
		2438	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2439	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2440	RADEON_CG_SUPPORT_MC_LS \|
		2441	RADEON_CG_SUPPORT_MC_MGCG \|
		2442	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2443	RADEON_CG_SUPPORT_BIF_LS \|
		2444	RADEON_CG_SUPPORT_UVD_MGCG \|
		2445	RADEON_CG_SUPPORT_HDP_LS \|
		2446	RADEON_CG_SUPPORT_HDP_MGCG;
		2447	rdev->pg_flags = 0;
		2448	break;
		2449	case CHIP_HAINAN:
		2450	rdev->cg_flags =
		2451	RADEON_CG_SUPPORT_GFX_MGCG \|
		2452	RADEON_CG_SUPPORT_GFX_MGLS \|
		2453	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2454	RADEON_CG_SUPPORT_GFX_CGLS \|
		2455	RADEON_CG_SUPPORT_GFX_CGTS \|
		2456	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2457	RADEON_CG_SUPPORT_GFX_RLC_LS \|
		2458	RADEON_CG_SUPPORT_MC_LS \|
		2459	RADEON_CG_SUPPORT_MC_MGCG \|
		2460	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2461	RADEON_CG_SUPPORT_BIF_LS \|
		2462	RADEON_CG_SUPPORT_HDP_LS \|
		2463	RADEON_CG_SUPPORT_HDP_MGCG;
		2464	rdev->pg_flags = 0;
		2465	break;
		2466	default:
		2467	rdev->cg_flags = 0;
		2468	rdev->pg_flags = 0;
		2469	break;
		2470	}
2997	Serge	2471	break;
5078	serge	2472	case CHIP_BONAIRE:
		2473	case CHIP_HAWAII:
		2474	rdev->asic = &ci_asic;
		2475	rdev->num_crtc = 6;
		2476	rdev->has_uvd = true;
		2477	if (rdev->family == CHIP_BONAIRE) {
		2478	rdev->cg_flags =
		2479	RADEON_CG_SUPPORT_GFX_MGCG \|
		2480	RADEON_CG_SUPPORT_GFX_MGLS \|
		2481	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2482	RADEON_CG_SUPPORT_GFX_CGLS \|
		2483	RADEON_CG_SUPPORT_GFX_CGTS \|
		2484	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2485	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2486	RADEON_CG_SUPPORT_MC_LS \|
		2487	RADEON_CG_SUPPORT_MC_MGCG \|
		2488	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2489	RADEON_CG_SUPPORT_SDMA_LS \|
		2490	RADEON_CG_SUPPORT_BIF_LS \|
		2491	RADEON_CG_SUPPORT_VCE_MGCG \|
		2492	RADEON_CG_SUPPORT_UVD_MGCG \|
		2493	RADEON_CG_SUPPORT_HDP_LS \|
		2494	RADEON_CG_SUPPORT_HDP_MGCG;
		2495	rdev->pg_flags = 0;
		2496	} else {
		2497	rdev->cg_flags =
		2498	RADEON_CG_SUPPORT_GFX_MGCG \|
		2499	RADEON_CG_SUPPORT_GFX_MGLS \|
		2500	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2501	RADEON_CG_SUPPORT_GFX_CGLS \|
		2502	RADEON_CG_SUPPORT_GFX_CGTS \|
		2503	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2504	RADEON_CG_SUPPORT_MC_LS \|
		2505	RADEON_CG_SUPPORT_MC_MGCG \|
		2506	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2507	RADEON_CG_SUPPORT_SDMA_LS \|
		2508	RADEON_CG_SUPPORT_BIF_LS \|
		2509	RADEON_CG_SUPPORT_VCE_MGCG \|
		2510	RADEON_CG_SUPPORT_UVD_MGCG \|
		2511	RADEON_CG_SUPPORT_HDP_LS \|
		2512	RADEON_CG_SUPPORT_HDP_MGCG;
		2513	rdev->pg_flags = 0;
		2514	}
		2515	break;
		2516	case CHIP_KAVERI:
		2517	case CHIP_KABINI:
		2518	case CHIP_MULLINS:
		2519	rdev->asic = &kv_asic;
		2520	/* set num crtcs */
		2521	if (rdev->family == CHIP_KAVERI) {
		2522	rdev->num_crtc = 4;
		2523	rdev->cg_flags =
		2524	RADEON_CG_SUPPORT_GFX_MGCG \|
		2525	RADEON_CG_SUPPORT_GFX_MGLS \|
		2526	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2527	RADEON_CG_SUPPORT_GFX_CGLS \|
		2528	RADEON_CG_SUPPORT_GFX_CGTS \|
		2529	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2530	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2531	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2532	RADEON_CG_SUPPORT_SDMA_LS \|
		2533	RADEON_CG_SUPPORT_BIF_LS \|
		2534	RADEON_CG_SUPPORT_VCE_MGCG \|
		2535	RADEON_CG_SUPPORT_UVD_MGCG \|
		2536	RADEON_CG_SUPPORT_HDP_LS \|
		2537	RADEON_CG_SUPPORT_HDP_MGCG;
		2538	rdev->pg_flags = 0;
		2539	/*RADEON_PG_SUPPORT_GFX_PG \|
		2540	RADEON_PG_SUPPORT_GFX_SMG \|
		2541	RADEON_PG_SUPPORT_GFX_DMG \|
		2542	RADEON_PG_SUPPORT_UVD \|
		2543	RADEON_PG_SUPPORT_VCE \|
		2544	RADEON_PG_SUPPORT_CP \|
		2545	RADEON_PG_SUPPORT_GDS \|
		2546	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2547	RADEON_PG_SUPPORT_ACP \|
		2548	RADEON_PG_SUPPORT_SAMU;*/
		2549	} else {
		2550	rdev->num_crtc = 2;
		2551	rdev->cg_flags =
		2552	RADEON_CG_SUPPORT_GFX_MGCG \|
		2553	RADEON_CG_SUPPORT_GFX_MGLS \|
		2554	/RADEON_CG_SUPPORT_GFX_CGCG \|/
		2555	RADEON_CG_SUPPORT_GFX_CGLS \|
		2556	RADEON_CG_SUPPORT_GFX_CGTS \|
		2557	RADEON_CG_SUPPORT_GFX_CGTS_LS \|
		2558	RADEON_CG_SUPPORT_GFX_CP_LS \|
		2559	RADEON_CG_SUPPORT_SDMA_MGCG \|
		2560	RADEON_CG_SUPPORT_SDMA_LS \|
		2561	RADEON_CG_SUPPORT_BIF_LS \|
		2562	RADEON_CG_SUPPORT_VCE_MGCG \|
		2563	RADEON_CG_SUPPORT_UVD_MGCG \|
		2564	RADEON_CG_SUPPORT_HDP_LS \|
		2565	RADEON_CG_SUPPORT_HDP_MGCG;
		2566	rdev->pg_flags = 0;
		2567	/*RADEON_PG_SUPPORT_GFX_PG \|
		2568	RADEON_PG_SUPPORT_GFX_SMG \|
		2569	RADEON_PG_SUPPORT_UVD \|
		2570	RADEON_PG_SUPPORT_VCE \|
		2571	RADEON_PG_SUPPORT_CP \|
		2572	RADEON_PG_SUPPORT_GDS \|
		2573	RADEON_PG_SUPPORT_RLC_SMU_HS \|
		2574	RADEON_PG_SUPPORT_SAMU;*/
		2575	}
		2576	rdev->has_uvd = true;
		2577	break;
1963	serge	2578	default:
		2579	/* FIXME: not supported yet */
		2580	return -EINVAL;
		2581	}
		2582
		2583	if (rdev->flags & RADEON_IS_IGP) {
2997	Serge	2584	rdev->asic->pm.get_memory_clock = NULL;
		2585	rdev->asic->pm.set_memory_clock = NULL;
1963	serge	2586	}
		2587
		2588	return 0;
		2589	}
		2590

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 5271