Rev 2007 | Rev 2997 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1963 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
| 3 | * Copyright 2008 Red Hat Inc. |
||
| 4 | * Copyright 2009 Jerome Glisse. |
||
| 5 | * |
||
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
| 7 | * copy of this software and associated documentation files (the "Software"), |
||
| 8 | * to deal in the Software without restriction, including without limitation |
||
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
| 11 | * Software is furnished to do so, subject to the following conditions: |
||
| 12 | * |
||
| 13 | * The above copyright notice and this permission notice shall be included in |
||
| 14 | * all copies or substantial portions of the Software. |
||
| 15 | * |
||
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
| 23 | * |
||
| 24 | * Authors: Dave Airlie |
||
| 25 | * Alex Deucher |
||
| 26 | * Jerome Glisse |
||
| 27 | */ |
||
| 28 | |||
| 29 | //#include |
||
| 30 | #include |
||
| 31 | #include |
||
| 32 | #include |
||
| 33 | //#include |
||
| 34 | //#include |
||
| 35 | #include "radeon_reg.h" |
||
| 36 | #include "radeon.h" |
||
| 37 | #include "radeon_asic.h" |
||
| 38 | #include "atom.h" |
||
| 39 | |||
| 40 | /* |
||
| 41 | * Registers accessors functions. |
||
| 42 | */ |
||
| 43 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
||
| 44 | { |
||
| 45 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
||
| 46 | BUG_ON(1); |
||
| 47 | return 0; |
||
| 48 | } |
||
| 49 | |||
| 50 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
| 51 | { |
||
| 52 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
||
| 53 | reg, v); |
||
| 54 | BUG_ON(1); |
||
| 55 | } |
||
| 56 | |||
| 57 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
||
| 58 | { |
||
| 59 | rdev->mc_rreg = &radeon_invalid_rreg; |
||
| 60 | rdev->mc_wreg = &radeon_invalid_wreg; |
||
| 61 | rdev->pll_rreg = &radeon_invalid_rreg; |
||
| 62 | rdev->pll_wreg = &radeon_invalid_wreg; |
||
| 63 | rdev->pciep_rreg = &radeon_invalid_rreg; |
||
| 64 | rdev->pciep_wreg = &radeon_invalid_wreg; |
||
| 65 | |||
| 66 | /* Don't change order as we are overridding accessor. */ |
||
| 67 | if (rdev->family < CHIP_RV515) { |
||
| 68 | rdev->pcie_reg_mask = 0xff; |
||
| 69 | } else { |
||
| 70 | rdev->pcie_reg_mask = 0x7ff; |
||
| 71 | } |
||
| 72 | /* FIXME: not sure here */ |
||
| 73 | if (rdev->family <= CHIP_R580) { |
||
| 74 | rdev->pll_rreg = &r100_pll_rreg; |
||
| 75 | rdev->pll_wreg = &r100_pll_wreg; |
||
| 76 | } |
||
| 77 | if (rdev->family >= CHIP_R420) { |
||
| 78 | rdev->mc_rreg = &r420_mc_rreg; |
||
| 79 | rdev->mc_wreg = &r420_mc_wreg; |
||
| 80 | } |
||
| 81 | if (rdev->family >= CHIP_RV515) { |
||
| 82 | rdev->mc_rreg = &rv515_mc_rreg; |
||
| 83 | rdev->mc_wreg = &rv515_mc_wreg; |
||
| 84 | } |
||
| 85 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
||
| 86 | rdev->mc_rreg = &rs400_mc_rreg; |
||
| 87 | rdev->mc_wreg = &rs400_mc_wreg; |
||
| 88 | } |
||
| 89 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
||
| 90 | rdev->mc_rreg = &rs690_mc_rreg; |
||
| 91 | rdev->mc_wreg = &rs690_mc_wreg; |
||
| 92 | } |
||
| 93 | if (rdev->family == CHIP_RS600) { |
||
| 94 | rdev->mc_rreg = &rs600_mc_rreg; |
||
| 95 | rdev->mc_wreg = &rs600_mc_wreg; |
||
| 96 | } |
||
| 97 | if (rdev->family >= CHIP_R600) { |
||
| 98 | rdev->pciep_rreg = &r600_pciep_rreg; |
||
| 99 | rdev->pciep_wreg = &r600_pciep_wreg; |
||
| 100 | } |
||
| 101 | } |
||
| 102 | |||
| 103 | |||
| 104 | /* helper to disable agp */ |
||
| 105 | void radeon_agp_disable(struct radeon_device *rdev) |
||
| 106 | { |
||
| 107 | rdev->flags &= ~RADEON_IS_AGP; |
||
| 108 | if (rdev->family >= CHIP_R600) { |
||
| 109 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
| 110 | rdev->flags |= RADEON_IS_PCIE; |
||
| 111 | } else if (rdev->family >= CHIP_RV515 || |
||
| 112 | rdev->family == CHIP_RV380 || |
||
| 113 | rdev->family == CHIP_RV410 || |
||
| 114 | rdev->family == CHIP_R423) { |
||
| 115 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
| 116 | rdev->flags |= RADEON_IS_PCIE; |
||
| 117 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
||
| 118 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
||
| 119 | } else { |
||
| 120 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
| 121 | rdev->flags |= RADEON_IS_PCI; |
||
| 122 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
||
| 123 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
||
| 124 | } |
||
| 125 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
| 126 | } |
||
| 127 | |||
| 128 | /* |
||
| 129 | * ASIC |
||
| 130 | */ |
||
| 131 | static struct radeon_asic r100_asic = { |
||
| 132 | .init = &r100_init, |
||
| 133 | // .fini = &r100_fini, |
||
| 134 | // .suspend = &r100_suspend, |
||
| 135 | // .resume = &r100_resume, |
||
| 136 | // .vga_set_state = &r100_vga_set_state, |
||
| 2005 | serge | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
| 1963 | serge | 138 | .asic_reset = &r100_asic_reset, |
| 139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
||
| 140 | .gart_set_page = &r100_pci_gart_set_page, |
||
| 141 | .cp_commit = &r100_cp_commit, |
||
| 142 | .ring_start = &r100_ring_start, |
||
| 143 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 144 | .ring_ib_execute = &r100_ring_ib_execute, |
| 145 | .irq_set = &r100_irq_set, |
||
| 146 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 147 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 148 | .fence_ring_emit = &r100_fence_ring_emit, |
||
| 149 | // .cs_parse = &r100_cs_parse, |
||
| 2005 | serge | 150 | .copy_blit = &r100_copy_blit, |
| 151 | .copy_dma = NULL, |
||
| 152 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 153 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 154 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
| 155 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
| 156 | .set_memory_clock = NULL, |
||
| 157 | .get_pcie_lanes = NULL, |
||
| 158 | .set_pcie_lanes = NULL, |
||
| 159 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
| 160 | .set_surface_reg = r100_set_surface_reg, |
||
| 161 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 162 | .bandwidth_update = &r100_bandwidth_update, |
||
| 163 | .hpd_init = &r100_hpd_init, |
||
| 164 | .hpd_fini = &r100_hpd_fini, |
||
| 165 | .hpd_sense = &r100_hpd_sense, |
||
| 166 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 167 | .ioctl_wait_idle = NULL, |
||
| 2007 | serge | 168 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 169 | }; |
| 170 | |||
| 171 | static struct radeon_asic r200_asic = { |
||
| 172 | .init = &r100_init, |
||
| 173 | // .fini = &r100_fini, |
||
| 174 | // .suspend = &r100_suspend, |
||
| 175 | // .resume = &r100_resume, |
||
| 176 | // .vga_set_state = &r100_vga_set_state, |
||
| 2005 | serge | 177 | .gpu_is_lockup = &r100_gpu_is_lockup, |
| 1963 | serge | 178 | .asic_reset = &r100_asic_reset, |
| 179 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
||
| 180 | .gart_set_page = &r100_pci_gart_set_page, |
||
| 181 | .cp_commit = &r100_cp_commit, |
||
| 182 | .ring_start = &r100_ring_start, |
||
| 183 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 184 | .ring_ib_execute = &r100_ring_ib_execute, |
| 185 | .irq_set = &r100_irq_set, |
||
| 186 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 187 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 188 | .fence_ring_emit = &r100_fence_ring_emit, |
||
| 189 | // .cs_parse = &r100_cs_parse, |
||
| 2005 | serge | 190 | .copy_blit = &r100_copy_blit, |
| 191 | .copy_dma = &r200_copy_dma, |
||
| 192 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 193 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 194 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
| 195 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
| 196 | .set_memory_clock = NULL, |
||
| 197 | .set_pcie_lanes = NULL, |
||
| 198 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
| 199 | .set_surface_reg = r100_set_surface_reg, |
||
| 200 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 201 | .bandwidth_update = &r100_bandwidth_update, |
||
| 202 | .hpd_init = &r100_hpd_init, |
||
| 203 | .hpd_fini = &r100_hpd_fini, |
||
| 204 | .hpd_sense = &r100_hpd_sense, |
||
| 205 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 206 | .ioctl_wait_idle = NULL, |
||
| 2007 | serge | 207 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 208 | }; |
| 209 | |||
| 210 | static struct radeon_asic r300_asic = { |
||
| 211 | .init = &r300_init, |
||
| 212 | // .fini = &r300_fini, |
||
| 213 | // .suspend = &r300_suspend, |
||
| 214 | // .resume = &r300_resume, |
||
| 215 | // .vga_set_state = &r100_vga_set_state, |
||
| 216 | .asic_reset = &r300_asic_reset, |
||
| 217 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
||
| 218 | .gart_set_page = &r100_pci_gart_set_page, |
||
| 219 | .cp_commit = &r100_cp_commit, |
||
| 220 | .ring_start = &r300_ring_start, |
||
| 221 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 222 | .ring_ib_execute = &r100_ring_ib_execute, |
| 223 | .irq_set = &r100_irq_set, |
||
| 224 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 225 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 226 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 227 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 228 | .copy_blit = &r100_copy_blit, |
| 229 | .copy_dma = &r200_copy_dma, |
||
| 230 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 231 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 232 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
| 233 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
| 234 | .set_memory_clock = NULL, |
||
| 235 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
| 236 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
| 237 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
| 238 | .set_surface_reg = r100_set_surface_reg, |
||
| 239 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 240 | .bandwidth_update = &r100_bandwidth_update, |
||
| 241 | .hpd_init = &r100_hpd_init, |
||
| 242 | .hpd_fini = &r100_hpd_fini, |
||
| 243 | .hpd_sense = &r100_hpd_sense, |
||
| 244 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 245 | .ioctl_wait_idle = NULL, |
||
| 2007 | serge | 246 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 247 | }; |
| 248 | |||
| 249 | static struct radeon_asic r300_asic_pcie = { |
||
| 250 | .init = &r300_init, |
||
| 251 | // .fini = &r300_fini, |
||
| 252 | // .suspend = &r300_suspend, |
||
| 253 | // .resume = &r300_resume, |
||
| 254 | // .vga_set_state = &r100_vga_set_state, |
||
| 255 | .asic_reset = &r300_asic_reset, |
||
| 256 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
| 257 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
| 258 | .cp_commit = &r100_cp_commit, |
||
| 259 | .ring_start = &r300_ring_start, |
||
| 260 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 261 | .ring_ib_execute = &r100_ring_ib_execute, |
| 262 | .irq_set = &r100_irq_set, |
||
| 263 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 264 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 265 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 266 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 267 | .copy_blit = &r100_copy_blit, |
| 268 | .copy_dma = &r200_copy_dma, |
||
| 269 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 270 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 271 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
| 272 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
| 273 | .set_memory_clock = NULL, |
||
| 274 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
| 275 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
| 276 | .set_surface_reg = r100_set_surface_reg, |
||
| 277 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 278 | .bandwidth_update = &r100_bandwidth_update, |
||
| 279 | .hpd_init = &r100_hpd_init, |
||
| 280 | .hpd_fini = &r100_hpd_fini, |
||
| 281 | .hpd_sense = &r100_hpd_sense, |
||
| 282 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 283 | .ioctl_wait_idle = NULL, |
||
| 2007 | serge | 284 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 285 | }; |
| 286 | |||
| 287 | static struct radeon_asic r420_asic = { |
||
| 288 | .init = &r420_init, |
||
| 289 | // .fini = &r420_fini, |
||
| 290 | // .suspend = &r420_suspend, |
||
| 291 | // .resume = &r420_resume, |
||
| 292 | // .vga_set_state = &r100_vga_set_state, |
||
| 293 | .asic_reset = &r300_asic_reset, |
||
| 294 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
| 295 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
| 296 | .cp_commit = &r100_cp_commit, |
||
| 297 | .ring_start = &r300_ring_start, |
||
| 298 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 299 | .ring_ib_execute = &r100_ring_ib_execute, |
| 300 | .irq_set = &r100_irq_set, |
||
| 301 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 302 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 303 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 304 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 305 | .copy_blit = &r100_copy_blit, |
| 306 | .copy_dma = &r200_copy_dma, |
||
| 307 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 308 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 309 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 310 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 311 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 312 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
| 313 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
| 314 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
| 315 | .set_surface_reg = r100_set_surface_reg, |
||
| 316 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 317 | .bandwidth_update = &r100_bandwidth_update, |
||
| 318 | .hpd_init = &r100_hpd_init, |
||
| 319 | .hpd_fini = &r100_hpd_fini, |
||
| 320 | .hpd_sense = &r100_hpd_sense, |
||
| 321 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 322 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 323 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 324 | }; |
| 325 | |||
| 326 | static struct radeon_asic rs400_asic = { |
||
| 327 | .init = &rs400_init, |
||
| 328 | // .fini = &rs400_fini, |
||
| 329 | // .suspend = &rs400_suspend, |
||
| 330 | // .resume = &rs400_resume, |
||
| 331 | // .vga_set_state = &r100_vga_set_state, |
||
| 332 | .asic_reset = &r300_asic_reset, |
||
| 333 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
||
| 334 | .gart_set_page = &rs400_gart_set_page, |
||
| 335 | .cp_commit = &r100_cp_commit, |
||
| 336 | .ring_start = &r300_ring_start, |
||
| 337 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 338 | .ring_ib_execute = &r100_ring_ib_execute, |
| 339 | .irq_set = &r100_irq_set, |
||
| 340 | .irq_process = &r100_irq_process, |
||
| 1963 | serge | 341 | // .get_vblank_counter = &r100_get_vblank_counter, |
| 342 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 343 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 344 | .copy_blit = &r100_copy_blit, |
| 345 | .copy_dma = &r200_copy_dma, |
||
| 346 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 347 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
| 348 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
||
| 349 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
||
| 350 | .set_memory_clock = NULL, |
||
| 351 | .get_pcie_lanes = NULL, |
||
| 352 | .set_pcie_lanes = NULL, |
||
| 353 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
||
| 354 | .set_surface_reg = r100_set_surface_reg, |
||
| 355 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 356 | .bandwidth_update = &r100_bandwidth_update, |
||
| 357 | .hpd_init = &r100_hpd_init, |
||
| 358 | .hpd_fini = &r100_hpd_fini, |
||
| 359 | .hpd_sense = &r100_hpd_sense, |
||
| 360 | .hpd_set_polarity = &r100_hpd_set_polarity, |
||
| 361 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 362 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 363 | }; |
| 364 | |||
| 365 | static struct radeon_asic rs600_asic = { |
||
| 366 | .init = &rs600_init, |
||
| 367 | // .fini = &rs600_fini, |
||
| 368 | // .suspend = &rs600_suspend, |
||
| 369 | // .resume = &rs600_resume, |
||
| 370 | // .vga_set_state = &r100_vga_set_state, |
||
| 371 | .asic_reset = &rs600_asic_reset, |
||
| 372 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
||
| 373 | .gart_set_page = &rs600_gart_set_page, |
||
| 374 | .cp_commit = &r100_cp_commit, |
||
| 375 | .ring_start = &r300_ring_start, |
||
| 376 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 377 | .ring_ib_execute = &r100_ring_ib_execute, |
| 378 | .irq_set = &rs600_irq_set, |
||
| 379 | .irq_process = &rs600_irq_process, |
||
| 1963 | serge | 380 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 381 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 382 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 383 | .copy_blit = &r100_copy_blit, |
| 384 | .copy_dma = &r200_copy_dma, |
||
| 385 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 386 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 387 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 388 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 389 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 390 | .get_pcie_lanes = NULL, |
||
| 391 | .set_pcie_lanes = NULL, |
||
| 392 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
| 393 | .set_surface_reg = r100_set_surface_reg, |
||
| 394 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 395 | .bandwidth_update = &rs600_bandwidth_update, |
||
| 396 | .hpd_init = &rs600_hpd_init, |
||
| 397 | .hpd_fini = &rs600_hpd_fini, |
||
| 398 | .hpd_sense = &rs600_hpd_sense, |
||
| 399 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
| 400 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 401 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 402 | }; |
| 403 | |||
| 404 | static struct radeon_asic rs690_asic = { |
||
| 405 | .init = &rs690_init, |
||
| 406 | // .fini = &rs690_fini, |
||
| 407 | // .suspend = &rs690_suspend, |
||
| 408 | // .resume = &rs690_resume, |
||
| 409 | // .vga_set_state = &r100_vga_set_state, |
||
| 410 | .asic_reset = &rs600_asic_reset, |
||
| 411 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
||
| 412 | .gart_set_page = &rs400_gart_set_page, |
||
| 413 | .cp_commit = &r100_cp_commit, |
||
| 414 | .ring_start = &r300_ring_start, |
||
| 415 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 416 | .ring_ib_execute = &r100_ring_ib_execute, |
| 417 | .irq_set = &rs600_irq_set, |
||
| 418 | .irq_process = &rs600_irq_process, |
||
| 1963 | serge | 419 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 420 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 421 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 422 | .copy_blit = &r100_copy_blit, |
| 423 | .copy_dma = &r200_copy_dma, |
||
| 424 | .copy = &r200_copy_dma, |
||
| 1963 | serge | 425 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 426 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 427 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 428 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 429 | .get_pcie_lanes = NULL, |
||
| 430 | .set_pcie_lanes = NULL, |
||
| 431 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
| 432 | .set_surface_reg = r100_set_surface_reg, |
||
| 433 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 434 | .bandwidth_update = &rs690_bandwidth_update, |
||
| 435 | .hpd_init = &rs600_hpd_init, |
||
| 436 | .hpd_fini = &rs600_hpd_fini, |
||
| 437 | .hpd_sense = &rs600_hpd_sense, |
||
| 438 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
| 439 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 440 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 441 | }; |
| 442 | |||
| 443 | static struct radeon_asic rv515_asic = { |
||
| 444 | .init = &rv515_init, |
||
| 445 | // .fini = &rv515_fini, |
||
| 446 | // .suspend = &rv515_suspend, |
||
| 447 | // .resume = &rv515_resume, |
||
| 448 | // .vga_set_state = &r100_vga_set_state, |
||
| 449 | .asic_reset = &rs600_asic_reset, |
||
| 450 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
| 451 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
| 452 | .cp_commit = &r100_cp_commit, |
||
| 453 | .ring_start = &rv515_ring_start, |
||
| 454 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 455 | .ring_ib_execute = &r100_ring_ib_execute, |
| 456 | .irq_set = &rs600_irq_set, |
||
| 457 | .irq_process = &rs600_irq_process, |
||
| 1963 | serge | 458 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 459 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 460 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 461 | .copy_blit = &r100_copy_blit, |
| 462 | .copy_dma = &r200_copy_dma, |
||
| 463 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 464 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 465 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 466 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 467 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 468 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
| 469 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
| 470 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
| 471 | .set_surface_reg = r100_set_surface_reg, |
||
| 472 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 473 | .bandwidth_update = &rv515_bandwidth_update, |
||
| 474 | .hpd_init = &rs600_hpd_init, |
||
| 475 | .hpd_fini = &rs600_hpd_fini, |
||
| 476 | .hpd_sense = &rs600_hpd_sense, |
||
| 477 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
| 478 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 479 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 480 | }; |
| 481 | |||
| 482 | static struct radeon_asic r520_asic = { |
||
| 483 | .init = &r520_init, |
||
| 484 | // .fini = &rv515_fini, |
||
| 485 | // .suspend = &rv515_suspend, |
||
| 486 | // .resume = &r520_resume, |
||
| 487 | // .vga_set_state = &r100_vga_set_state, |
||
| 488 | .asic_reset = &rs600_asic_reset, |
||
| 489 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
||
| 490 | .gart_set_page = &rv370_pcie_gart_set_page, |
||
| 491 | .cp_commit = &r100_cp_commit, |
||
| 492 | .ring_start = &rv515_ring_start, |
||
| 493 | .ring_test = &r100_ring_test, |
||
| 2005 | serge | 494 | .ring_ib_execute = &r100_ring_ib_execute, |
| 495 | .irq_set = &rs600_irq_set, |
||
| 496 | .irq_process = &rs600_irq_process, |
||
| 1963 | serge | 497 | // .get_vblank_counter = &rs600_get_vblank_counter, |
| 498 | .fence_ring_emit = &r300_fence_ring_emit, |
||
| 499 | // .cs_parse = &r300_cs_parse, |
||
| 2005 | serge | 500 | .copy_blit = &r100_copy_blit, |
| 501 | .copy_dma = &r200_copy_dma, |
||
| 502 | .copy = &r100_copy_blit, |
||
| 1963 | serge | 503 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 504 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 505 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 506 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 507 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
||
| 508 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
||
| 509 | .set_clock_gating = &radeon_atom_set_clock_gating, |
||
| 510 | .set_surface_reg = r100_set_surface_reg, |
||
| 511 | .clear_surface_reg = r100_clear_surface_reg, |
||
| 512 | .bandwidth_update = &rv515_bandwidth_update, |
||
| 513 | .hpd_init = &rs600_hpd_init, |
||
| 514 | .hpd_fini = &rs600_hpd_fini, |
||
| 515 | .hpd_sense = &rs600_hpd_sense, |
||
| 516 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
||
| 517 | .ioctl_wait_idle = NULL, |
||
| 2160 | serge | 518 | .gui_idle = &r100_gui_idle, |
| 1963 | serge | 519 | }; |
| 520 | |||
| 521 | static struct radeon_asic r600_asic = { |
||
| 522 | .init = &r600_init, |
||
| 523 | // .fini = &r600_fini, |
||
| 524 | // .suspend = &r600_suspend, |
||
| 525 | // .resume = &r600_resume, |
||
| 526 | .cp_commit = &r600_cp_commit, |
||
| 527 | .vga_set_state = &r600_vga_set_state, |
||
| 528 | .asic_reset = &r600_asic_reset, |
||
| 529 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
| 530 | .gart_set_page = &rs600_gart_set_page, |
||
| 531 | .ring_test = &r600_ring_test, |
||
| 2005 | serge | 532 | .ring_ib_execute = &r600_ring_ib_execute, |
| 2004 | serge | 533 | .irq_set = &r600_irq_set, |
| 534 | .irq_process = &r600_irq_process, |
||
| 1963 | serge | 535 | .fence_ring_emit = &r600_fence_ring_emit, |
| 536 | // .cs_parse = &r600_cs_parse, |
||
| 2005 | serge | 537 | .copy_blit = &r600_copy_blit, |
| 2160 | serge | 538 | .copy_dma = NULL, |
| 2005 | serge | 539 | .copy = &r600_copy_blit, |
| 1963 | serge | 540 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 541 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 542 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 543 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 2005 | serge | 544 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 545 | .set_pcie_lanes = &r600_set_pcie_lanes, |
||
| 1963 | serge | 546 | .set_clock_gating = NULL, |
| 547 | .set_surface_reg = r600_set_surface_reg, |
||
| 548 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 549 | .bandwidth_update = &rv515_bandwidth_update, |
||
| 550 | .hpd_init = &r600_hpd_init, |
||
| 551 | .hpd_fini = &r600_hpd_fini, |
||
| 552 | .hpd_sense = &r600_hpd_sense, |
||
| 553 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
| 554 | // .ioctl_wait_idle = r600_ioctl_wait_idle, |
||
| 555 | }; |
||
| 556 | |||
| 557 | static struct radeon_asic rs780_asic = { |
||
| 558 | .init = &r600_init, |
||
| 559 | // .fini = &r600_fini, |
||
| 560 | // .suspend = &r600_suspend, |
||
| 561 | // .resume = &r600_resume, |
||
| 562 | .cp_commit = &r600_cp_commit, |
||
| 563 | .gpu_is_lockup = &r600_gpu_is_lockup, |
||
| 564 | .vga_set_state = &r600_vga_set_state, |
||
| 565 | .asic_reset = &r600_asic_reset, |
||
| 566 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
| 567 | .gart_set_page = &rs600_gart_set_page, |
||
| 568 | .ring_test = &r600_ring_test, |
||
| 2005 | serge | 569 | .ring_ib_execute = &r600_ring_ib_execute, |
| 2004 | serge | 570 | .irq_set = &r600_irq_set, |
| 571 | .irq_process = &r600_irq_process, |
||
| 1963 | serge | 572 | .fence_ring_emit = &r600_fence_ring_emit, |
| 573 | // .cs_parse = &r600_cs_parse, |
||
| 2005 | serge | 574 | .copy_blit = &r600_copy_blit, |
| 2160 | serge | 575 | .copy_dma = NULL, |
| 2005 | serge | 576 | .copy = &r600_copy_blit, |
| 1963 | serge | 577 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 578 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 579 | .get_memory_clock = NULL, |
||
| 580 | .set_memory_clock = NULL, |
||
| 581 | .get_pcie_lanes = NULL, |
||
| 582 | .set_pcie_lanes = NULL, |
||
| 583 | .set_clock_gating = NULL, |
||
| 584 | .set_surface_reg = r600_set_surface_reg, |
||
| 585 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 586 | .bandwidth_update = &rs690_bandwidth_update, |
||
| 587 | .hpd_init = &r600_hpd_init, |
||
| 588 | .hpd_fini = &r600_hpd_fini, |
||
| 589 | .hpd_sense = &r600_hpd_sense, |
||
| 590 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
| 591 | }; |
||
| 592 | |||
| 593 | static struct radeon_asic rv770_asic = { |
||
| 594 | .init = &rv770_init, |
||
| 595 | // .fini = &rv770_fini, |
||
| 596 | // .suspend = &rv770_suspend, |
||
| 597 | // .resume = &rv770_resume, |
||
| 598 | .cp_commit = &r600_cp_commit, |
||
| 599 | .asic_reset = &r600_asic_reset, |
||
| 600 | .vga_set_state = &r600_vga_set_state, |
||
| 601 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
||
| 602 | .gart_set_page = &rs600_gart_set_page, |
||
| 603 | .ring_test = &r600_ring_test, |
||
| 2004 | serge | 604 | .ring_ib_execute = &r600_ring_ib_execute, |
| 605 | .irq_set = &r600_irq_set, |
||
| 606 | .irq_process = &r600_irq_process, |
||
| 1963 | serge | 607 | .fence_ring_emit = &r600_fence_ring_emit, |
| 608 | // .cs_parse = &r600_cs_parse, |
||
| 2005 | serge | 609 | .copy_blit = &r600_copy_blit, |
| 2160 | serge | 610 | .copy_dma = NULL, |
| 2005 | serge | 611 | .copy = &r600_copy_blit, |
| 1963 | serge | 612 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 613 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 614 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 615 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 2005 | serge | 616 | .get_pcie_lanes = &r600_get_pcie_lanes, |
| 617 | .set_pcie_lanes = &r600_set_pcie_lanes, |
||
| 1963 | serge | 618 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 619 | .set_surface_reg = r600_set_surface_reg, |
||
| 620 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 621 | .bandwidth_update = &rv515_bandwidth_update, |
||
| 622 | .hpd_init = &r600_hpd_init, |
||
| 623 | .hpd_fini = &r600_hpd_fini, |
||
| 624 | .hpd_sense = &r600_hpd_sense, |
||
| 625 | .hpd_set_polarity = &r600_hpd_set_polarity, |
||
| 626 | }; |
||
| 1986 | serge | 627 | |
| 1963 | serge | 628 | static struct radeon_asic evergreen_asic = { |
| 629 | .init = &evergreen_init, |
||
| 630 | // .fini = &evergreen_fini, |
||
| 631 | // .suspend = &evergreen_suspend, |
||
| 632 | // .resume = &evergreen_resume, |
||
| 1986 | serge | 633 | .cp_commit = &r600_cp_commit, |
| 1963 | serge | 634 | .asic_reset = &evergreen_asic_reset, |
| 635 | .vga_set_state = &r600_vga_set_state, |
||
| 1986 | serge | 636 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| 1963 | serge | 637 | .gart_set_page = &rs600_gart_set_page, |
| 1986 | serge | 638 | .ring_test = &r600_ring_test, |
| 2005 | serge | 639 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 640 | .irq_set = &evergreen_irq_set, |
||
| 641 | .irq_process = &evergreen_irq_process, |
||
| 1986 | serge | 642 | .fence_ring_emit = &r600_fence_ring_emit, |
| 2005 | serge | 643 | // .cs_parse = &evergreen_cs_parse, |
| 644 | .copy_blit = &evergreen_copy_blit, |
||
| 2160 | serge | 645 | .copy_dma = NULL, |
| 2005 | serge | 646 | .copy = &evergreen_copy_blit, |
| 1986 | serge | 647 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 648 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 649 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 650 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 651 | .get_pcie_lanes = &r600_get_pcie_lanes, |
||
| 652 | .set_pcie_lanes = &r600_set_pcie_lanes, |
||
| 653 | .set_clock_gating = NULL, |
||
| 654 | .set_surface_reg = r600_set_surface_reg, |
||
| 655 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 656 | .bandwidth_update = &evergreen_bandwidth_update, |
||
| 2005 | serge | 657 | .hpd_init = &evergreen_hpd_init, |
| 658 | .hpd_fini = &evergreen_hpd_fini, |
||
| 659 | .hpd_sense = &evergreen_hpd_sense, |
||
| 660 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
||
| 1986 | serge | 661 | |
| 662 | }; |
||
| 1990 | serge | 663 | |
| 1986 | serge | 664 | static struct radeon_asic sumo_asic = { |
| 665 | .init = &evergreen_init, |
||
| 1990 | serge | 666 | // .fini = &evergreen_fini, |
| 667 | // .suspend = &evergreen_suspend, |
||
| 668 | // .resume = &evergreen_resume, |
||
| 1986 | serge | 669 | .cp_commit = &r600_cp_commit, |
| 670 | .asic_reset = &evergreen_asic_reset, |
||
| 671 | .vga_set_state = &r600_vga_set_state, |
||
| 672 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
| 673 | .gart_set_page = &rs600_gart_set_page, |
||
| 674 | .ring_test = &r600_ring_test, |
||
| 2005 | serge | 675 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 676 | .irq_set = &evergreen_irq_set, |
||
| 677 | .irq_process = &evergreen_irq_process, |
||
| 1986 | serge | 678 | .fence_ring_emit = &r600_fence_ring_emit, |
| 1990 | serge | 679 | // .cs_parse = &r600_cs_parse, |
| 2005 | serge | 680 | .copy_blit = &evergreen_copy_blit, |
| 2160 | serge | 681 | .copy_dma = NULL, |
| 2005 | serge | 682 | .copy = &evergreen_copy_blit, |
| 1986 | serge | 683 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 684 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 685 | .get_memory_clock = NULL, |
||
| 686 | .set_memory_clock = NULL, |
||
| 687 | .get_pcie_lanes = NULL, |
||
| 688 | .set_pcie_lanes = NULL, |
||
| 689 | .set_clock_gating = NULL, |
||
| 690 | .set_surface_reg = r600_set_surface_reg, |
||
| 691 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 692 | .bandwidth_update = &evergreen_bandwidth_update, |
||
| 2005 | serge | 693 | .hpd_init = &evergreen_hpd_init, |
| 694 | .hpd_fini = &evergreen_hpd_fini, |
||
| 695 | .hpd_sense = &evergreen_hpd_sense, |
||
| 696 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
||
| 1986 | serge | 697 | }; |
| 698 | |||
| 699 | static struct radeon_asic btc_asic = { |
||
| 700 | .init = &evergreen_init, |
||
| 1990 | serge | 701 | // .fini = &evergreen_fini, |
| 702 | // .suspend = &evergreen_suspend, |
||
| 703 | // .resume = &evergreen_resume, |
||
| 1986 | serge | 704 | .cp_commit = &r600_cp_commit, |
| 705 | .asic_reset = &evergreen_asic_reset, |
||
| 706 | .vga_set_state = &r600_vga_set_state, |
||
| 707 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
||
| 708 | .gart_set_page = &rs600_gart_set_page, |
||
| 1990 | serge | 709 | .ring_test = &r600_ring_test, |
| 2005 | serge | 710 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 711 | .irq_set = &evergreen_irq_set, |
||
| 712 | .irq_process = &evergreen_irq_process, |
||
| 1963 | serge | 713 | .fence_ring_emit = &r600_fence_ring_emit, |
| 2005 | serge | 714 | // .cs_parse = &evergreen_cs_parse, |
| 715 | .copy_blit = &evergreen_copy_blit, |
||
| 2160 | serge | 716 | .copy_dma = NULL, |
| 2005 | serge | 717 | .copy = &evergreen_copy_blit, |
| 1986 | serge | 718 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 719 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 720 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 721 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 722 | .get_pcie_lanes = NULL, |
||
| 723 | .set_pcie_lanes = NULL, |
||
| 724 | .set_clock_gating = NULL, |
||
| 725 | .set_surface_reg = r600_set_surface_reg, |
||
| 726 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 727 | .bandwidth_update = &evergreen_bandwidth_update, |
||
| 2004 | serge | 728 | .hpd_init = &evergreen_hpd_init, |
| 2005 | serge | 729 | .hpd_fini = &evergreen_hpd_fini, |
| 2004 | serge | 730 | .hpd_sense = &evergreen_hpd_sense, |
| 2005 | serge | 731 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| 1986 | serge | 732 | }; |
| 733 | |||
| 734 | static struct radeon_asic cayman_asic = { |
||
| 735 | .init = &cayman_init, |
||
| 2004 | serge | 736 | // .fini = &evergreen_fini, |
| 737 | // .suspend = &evergreen_suspend, |
||
| 738 | // .resume = &evergreen_resume, |
||
| 1986 | serge | 739 | .cp_commit = &r600_cp_commit, |
| 740 | .asic_reset = &cayman_asic_reset, |
||
| 741 | .vga_set_state = &r600_vga_set_state, |
||
| 742 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
||
| 743 | .gart_set_page = &rs600_gart_set_page, |
||
| 744 | .ring_test = &r600_ring_test, |
||
| 2005 | serge | 745 | .ring_ib_execute = &evergreen_ring_ib_execute, |
| 746 | .irq_set = &evergreen_irq_set, |
||
| 747 | .irq_process = &evergreen_irq_process, |
||
| 1986 | serge | 748 | .fence_ring_emit = &r600_fence_ring_emit, |
| 2005 | serge | 749 | // .cs_parse = &evergreen_cs_parse, |
| 750 | .copy_blit = &evergreen_copy_blit, |
||
| 2160 | serge | 751 | .copy_dma = NULL, |
| 2005 | serge | 752 | .copy = &evergreen_copy_blit, |
| 1963 | serge | 753 | .get_engine_clock = &radeon_atom_get_engine_clock, |
| 754 | .set_engine_clock = &radeon_atom_set_engine_clock, |
||
| 755 | .get_memory_clock = &radeon_atom_get_memory_clock, |
||
| 756 | .set_memory_clock = &radeon_atom_set_memory_clock, |
||
| 2004 | serge | 757 | .get_pcie_lanes = NULL, |
| 1963 | serge | 758 | .set_pcie_lanes = NULL, |
| 759 | .set_clock_gating = NULL, |
||
| 760 | .set_surface_reg = r600_set_surface_reg, |
||
| 761 | .clear_surface_reg = r600_clear_surface_reg, |
||
| 762 | .bandwidth_update = &evergreen_bandwidth_update, |
||
| 2005 | serge | 763 | .hpd_init = &evergreen_hpd_init, |
| 764 | .hpd_fini = &evergreen_hpd_fini, |
||
| 765 | .hpd_sense = &evergreen_hpd_sense, |
||
| 766 | .hpd_set_polarity = &evergreen_hpd_set_polarity, |
||
| 1963 | serge | 767 | }; |
| 768 | |||
| 769 | int radeon_asic_init(struct radeon_device *rdev) |
||
| 770 | { |
||
| 771 | radeon_register_accessor_init(rdev); |
||
| 1986 | serge | 772 | |
| 773 | /* set the number of crtcs */ |
||
| 774 | if (rdev->flags & RADEON_SINGLE_CRTC) |
||
| 775 | rdev->num_crtc = 1; |
||
| 776 | else |
||
| 777 | rdev->num_crtc = 2; |
||
| 778 | |||
| 1963 | serge | 779 | switch (rdev->family) { |
| 780 | case CHIP_R100: |
||
| 781 | case CHIP_RV100: |
||
| 782 | case CHIP_RS100: |
||
| 783 | case CHIP_RV200: |
||
| 784 | case CHIP_RS200: |
||
| 785 | rdev->asic = &r100_asic; |
||
| 786 | break; |
||
| 787 | case CHIP_R200: |
||
| 788 | case CHIP_RV250: |
||
| 789 | case CHIP_RS300: |
||
| 790 | case CHIP_RV280: |
||
| 791 | rdev->asic = &r200_asic; |
||
| 792 | break; |
||
| 793 | case CHIP_R300: |
||
| 794 | case CHIP_R350: |
||
| 795 | case CHIP_RV350: |
||
| 796 | case CHIP_RV380: |
||
| 797 | if (rdev->flags & RADEON_IS_PCIE) |
||
| 798 | rdev->asic = &r300_asic_pcie; |
||
| 799 | else |
||
| 800 | rdev->asic = &r300_asic; |
||
| 801 | break; |
||
| 802 | case CHIP_R420: |
||
| 803 | case CHIP_R423: |
||
| 804 | case CHIP_RV410: |
||
| 805 | rdev->asic = &r420_asic; |
||
| 806 | /* handle macs */ |
||
| 807 | if (rdev->bios == NULL) { |
||
| 808 | rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; |
||
| 809 | rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; |
||
| 810 | rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; |
||
| 811 | rdev->asic->set_memory_clock = NULL; |
||
| 812 | } |
||
| 813 | break; |
||
| 814 | case CHIP_RS400: |
||
| 815 | case CHIP_RS480: |
||
| 816 | rdev->asic = &rs400_asic; |
||
| 817 | break; |
||
| 818 | case CHIP_RS600: |
||
| 819 | rdev->asic = &rs600_asic; |
||
| 820 | break; |
||
| 821 | case CHIP_RS690: |
||
| 822 | case CHIP_RS740: |
||
| 823 | rdev->asic = &rs690_asic; |
||
| 824 | break; |
||
| 825 | case CHIP_RV515: |
||
| 826 | rdev->asic = &rv515_asic; |
||
| 827 | break; |
||
| 828 | case CHIP_R520: |
||
| 829 | case CHIP_RV530: |
||
| 830 | case CHIP_RV560: |
||
| 831 | case CHIP_RV570: |
||
| 832 | case CHIP_R580: |
||
| 833 | rdev->asic = &r520_asic; |
||
| 834 | break; |
||
| 835 | case CHIP_R600: |
||
| 836 | case CHIP_RV610: |
||
| 837 | case CHIP_RV630: |
||
| 838 | case CHIP_RV620: |
||
| 839 | case CHIP_RV635: |
||
| 840 | case CHIP_RV670: |
||
| 841 | rdev->asic = &r600_asic; |
||
| 842 | break; |
||
| 843 | case CHIP_RS780: |
||
| 844 | case CHIP_RS880: |
||
| 845 | rdev->asic = &rs780_asic; |
||
| 846 | break; |
||
| 847 | case CHIP_RV770: |
||
| 848 | case CHIP_RV730: |
||
| 849 | case CHIP_RV710: |
||
| 850 | case CHIP_RV740: |
||
| 851 | rdev->asic = &rv770_asic; |
||
| 852 | break; |
||
| 1986 | serge | 853 | case CHIP_CEDAR: |
| 854 | case CHIP_REDWOOD: |
||
| 855 | case CHIP_JUNIPER: |
||
| 856 | case CHIP_CYPRESS: |
||
| 857 | case CHIP_HEMLOCK: |
||
| 858 | /* set num crtcs */ |
||
| 859 | if (rdev->family == CHIP_CEDAR) |
||
| 860 | rdev->num_crtc = 4; |
||
| 861 | else |
||
| 862 | rdev->num_crtc = 6; |
||
| 863 | rdev->asic = &evergreen_asic; |
||
| 864 | break; |
||
| 1990 | serge | 865 | case CHIP_PALM: |
| 866 | case CHIP_SUMO: |
||
| 867 | case CHIP_SUMO2: |
||
| 868 | rdev->asic = &sumo_asic; |
||
| 869 | break; |
||
| 870 | case CHIP_BARTS: |
||
| 871 | case CHIP_TURKS: |
||
| 872 | case CHIP_CAICOS: |
||
| 873 | /* set num crtcs */ |
||
| 874 | if (rdev->family == CHIP_CAICOS) |
||
| 875 | rdev->num_crtc = 4; |
||
| 876 | else |
||
| 877 | rdev->num_crtc = 6; |
||
| 878 | rdev->asic = &btc_asic; |
||
| 879 | break; |
||
| 2004 | serge | 880 | case CHIP_CAYMAN: |
| 881 | rdev->asic = &cayman_asic; |
||
| 882 | /* set num crtcs */ |
||
| 883 | rdev->num_crtc = 6; |
||
| 884 | break; |
||
| 1963 | serge | 885 | default: |
| 886 | /* FIXME: not supported yet */ |
||
| 887 | return -EINVAL; |
||
| 888 | } |
||
| 889 | |||
| 890 | if (rdev->flags & RADEON_IS_IGP) { |
||
| 891 | rdev->asic->get_memory_clock = NULL; |
||
| 892 | rdev->asic->set_memory_clock = NULL; |
||
| 893 | } |
||
| 894 | |||
| 895 | return 0; |
||
| 896 | } |
||
| 897 |