WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon_asic.c

Rev	Author	Line No.	Line
1963	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28
		29	//#include
		30	#include
		31	#include
		32	#include
		33	//#include
		34	//#include
		35	#include "radeon_reg.h"
		36	#include "radeon.h"
		37	#include "radeon_asic.h"
		38	#include "atom.h"
		39
		40	/*
		41	* Registers accessors functions.
		42	*/
		43	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
		44	{
		45	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
		46	BUG_ON(1);
		47	return 0;
		48	}
		49
		50	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		51	{
		52	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		53	reg, v);
		54	BUG_ON(1);
		55	}
		56
		57	static void radeon_register_accessor_init(struct radeon_device *rdev)
		58	{
		59	rdev->mc_rreg = &radeon_invalid_rreg;
		60	rdev->mc_wreg = &radeon_invalid_wreg;
		61	rdev->pll_rreg = &radeon_invalid_rreg;
		62	rdev->pll_wreg = &radeon_invalid_wreg;
		63	rdev->pciep_rreg = &radeon_invalid_rreg;
		64	rdev->pciep_wreg = &radeon_invalid_wreg;
		65
		66	/* Don't change order as we are overridding accessor. */
		67	if (rdev->family < CHIP_RV515) {
		68	rdev->pcie_reg_mask = 0xff;
		69	} else {
		70	rdev->pcie_reg_mask = 0x7ff;
		71	}
		72	/* FIXME: not sure here */
		73	if (rdev->family <= CHIP_R580) {
		74	rdev->pll_rreg = &r100_pll_rreg;
		75	rdev->pll_wreg = &r100_pll_wreg;
		76	}
		77	if (rdev->family >= CHIP_R420) {
		78	rdev->mc_rreg = &r420_mc_rreg;
		79	rdev->mc_wreg = &r420_mc_wreg;
		80	}
		81	if (rdev->family >= CHIP_RV515) {
		82	rdev->mc_rreg = &rv515_mc_rreg;
		83	rdev->mc_wreg = &rv515_mc_wreg;
		84	}
		85	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
		86	rdev->mc_rreg = &rs400_mc_rreg;
		87	rdev->mc_wreg = &rs400_mc_wreg;
		88	}
		89	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
		90	rdev->mc_rreg = &rs690_mc_rreg;
		91	rdev->mc_wreg = &rs690_mc_wreg;
		92	}
		93	if (rdev->family == CHIP_RS600) {
		94	rdev->mc_rreg = &rs600_mc_rreg;
		95	rdev->mc_wreg = &rs600_mc_wreg;
		96	}
		97	if (rdev->family >= CHIP_R600) {
		98	rdev->pciep_rreg = &r600_pciep_rreg;
		99	rdev->pciep_wreg = &r600_pciep_wreg;
		100	}
		101	}
		102
		103
		104	/* helper to disable agp */
		105	void radeon_agp_disable(struct radeon_device *rdev)
		106	{
		107	rdev->flags &= ~RADEON_IS_AGP;
		108	if (rdev->family >= CHIP_R600) {
		109	DRM_INFO("Forcing AGP to PCIE mode\n");
		110	rdev->flags \|= RADEON_IS_PCIE;
		111	} else if (rdev->family >= CHIP_RV515 \|\|
		112	rdev->family == CHIP_RV380 \|\|
		113	rdev->family == CHIP_RV410 \|\|
		114	rdev->family == CHIP_R423) {
		115	DRM_INFO("Forcing AGP to PCIE mode\n");
		116	rdev->flags \|= RADEON_IS_PCIE;
		117	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		118	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		119	} else {
		120	DRM_INFO("Forcing AGP to PCI mode\n");
		121	rdev->flags \|= RADEON_IS_PCI;
		122	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		123	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
		124	}
		125	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
		126	}
		127
		128	/*
		129	* ASIC
		130	*/
		131	static struct radeon_asic r100_asic = {
		132	.init = &r100_init,
		133	// .fini = &r100_fini,
		134	// .suspend = &r100_suspend,
		135	// .resume = &r100_resume,
		136	// .vga_set_state = &r100_vga_set_state,
2005	serge	137	.gpu_is_lockup = &r100_gpu_is_lockup,
1963	serge	138	.asic_reset = &r100_asic_reset,
		139	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
		140	.gart_set_page = &r100_pci_gart_set_page,
		141	.cp_commit = &r100_cp_commit,
		142	.ring_start = &r100_ring_start,
		143	.ring_test = &r100_ring_test,
2005	serge	144	.ring_ib_execute = &r100_ring_ib_execute,
		145	.irq_set = &r100_irq_set,
		146	.irq_process = &r100_irq_process,
1963	serge	147	// .get_vblank_counter = &r100_get_vblank_counter,
		148	.fence_ring_emit = &r100_fence_ring_emit,
		149	// .cs_parse = &r100_cs_parse,
2005	serge	150	.copy_blit = &r100_copy_blit,
		151	.copy_dma = NULL,
		152	.copy = &r100_copy_blit,
1963	serge	153	.get_engine_clock = &radeon_legacy_get_engine_clock,
		154	.set_engine_clock = &radeon_legacy_set_engine_clock,
		155	.get_memory_clock = &radeon_legacy_get_memory_clock,
		156	.set_memory_clock = NULL,
		157	.get_pcie_lanes = NULL,
		158	.set_pcie_lanes = NULL,
		159	.set_clock_gating = &radeon_legacy_set_clock_gating,
		160	.set_surface_reg = r100_set_surface_reg,
		161	.clear_surface_reg = r100_clear_surface_reg,
		162	.bandwidth_update = &r100_bandwidth_update,
		163	.hpd_init = &r100_hpd_init,
		164	.hpd_fini = &r100_hpd_fini,
		165	.hpd_sense = &r100_hpd_sense,
		166	.hpd_set_polarity = &r100_hpd_set_polarity,
		167	.ioctl_wait_idle = NULL,
2007	serge	168	.gui_idle = &r100_gui_idle,
1963	serge	169	};
		170
		171	static struct radeon_asic r200_asic = {
		172	.init = &r100_init,
		173	// .fini = &r100_fini,
		174	// .suspend = &r100_suspend,
		175	// .resume = &r100_resume,
		176	// .vga_set_state = &r100_vga_set_state,
2005	serge	177	.gpu_is_lockup = &r100_gpu_is_lockup,
1963	serge	178	.asic_reset = &r100_asic_reset,
		179	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
		180	.gart_set_page = &r100_pci_gart_set_page,
		181	.cp_commit = &r100_cp_commit,
		182	.ring_start = &r100_ring_start,
		183	.ring_test = &r100_ring_test,
2005	serge	184	.ring_ib_execute = &r100_ring_ib_execute,
		185	.irq_set = &r100_irq_set,
		186	.irq_process = &r100_irq_process,
1963	serge	187	// .get_vblank_counter = &r100_get_vblank_counter,
		188	.fence_ring_emit = &r100_fence_ring_emit,
		189	// .cs_parse = &r100_cs_parse,
2005	serge	190	.copy_blit = &r100_copy_blit,
		191	.copy_dma = &r200_copy_dma,
		192	.copy = &r100_copy_blit,
1963	serge	193	.get_engine_clock = &radeon_legacy_get_engine_clock,
		194	.set_engine_clock = &radeon_legacy_set_engine_clock,
		195	.get_memory_clock = &radeon_legacy_get_memory_clock,
		196	.set_memory_clock = NULL,
		197	.set_pcie_lanes = NULL,
		198	.set_clock_gating = &radeon_legacy_set_clock_gating,
		199	.set_surface_reg = r100_set_surface_reg,
		200	.clear_surface_reg = r100_clear_surface_reg,
		201	.bandwidth_update = &r100_bandwidth_update,
		202	.hpd_init = &r100_hpd_init,
		203	.hpd_fini = &r100_hpd_fini,
		204	.hpd_sense = &r100_hpd_sense,
		205	.hpd_set_polarity = &r100_hpd_set_polarity,
		206	.ioctl_wait_idle = NULL,
2007	serge	207	.gui_idle = &r100_gui_idle,
1963	serge	208	};
		209
		210	static struct radeon_asic r300_asic = {
		211	.init = &r300_init,
		212	// .fini = &r300_fini,
		213	// .suspend = &r300_suspend,
		214	// .resume = &r300_resume,
		215	// .vga_set_state = &r100_vga_set_state,
		216	.asic_reset = &r300_asic_reset,
		217	.gart_tlb_flush = &r100_pci_gart_tlb_flush,
		218	.gart_set_page = &r100_pci_gart_set_page,
		219	.cp_commit = &r100_cp_commit,
		220	.ring_start = &r300_ring_start,
		221	.ring_test = &r100_ring_test,
2005	serge	222	.ring_ib_execute = &r100_ring_ib_execute,
		223	.irq_set = &r100_irq_set,
		224	.irq_process = &r100_irq_process,
1963	serge	225	// .get_vblank_counter = &r100_get_vblank_counter,
		226	.fence_ring_emit = &r300_fence_ring_emit,
		227	// .cs_parse = &r300_cs_parse,
2005	serge	228	.copy_blit = &r100_copy_blit,
		229	.copy_dma = &r200_copy_dma,
		230	.copy = &r100_copy_blit,
1963	serge	231	.get_engine_clock = &radeon_legacy_get_engine_clock,
		232	.set_engine_clock = &radeon_legacy_set_engine_clock,
		233	.get_memory_clock = &radeon_legacy_get_memory_clock,
		234	.set_memory_clock = NULL,
		235	.get_pcie_lanes = &rv370_get_pcie_lanes,
		236	.set_pcie_lanes = &rv370_set_pcie_lanes,
		237	.set_clock_gating = &radeon_legacy_set_clock_gating,
		238	.set_surface_reg = r100_set_surface_reg,
		239	.clear_surface_reg = r100_clear_surface_reg,
		240	.bandwidth_update = &r100_bandwidth_update,
		241	.hpd_init = &r100_hpd_init,
		242	.hpd_fini = &r100_hpd_fini,
		243	.hpd_sense = &r100_hpd_sense,
		244	.hpd_set_polarity = &r100_hpd_set_polarity,
		245	.ioctl_wait_idle = NULL,
2007	serge	246	.gui_idle = &r100_gui_idle,
1963	serge	247	};
		248
		249	static struct radeon_asic r300_asic_pcie = {
		250	.init = &r300_init,
		251	// .fini = &r300_fini,
		252	// .suspend = &r300_suspend,
		253	// .resume = &r300_resume,
		254	// .vga_set_state = &r100_vga_set_state,
		255	.asic_reset = &r300_asic_reset,
		256	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
		257	.gart_set_page = &rv370_pcie_gart_set_page,
		258	.cp_commit = &r100_cp_commit,
		259	.ring_start = &r300_ring_start,
		260	.ring_test = &r100_ring_test,
2005	serge	261	.ring_ib_execute = &r100_ring_ib_execute,
		262	.irq_set = &r100_irq_set,
		263	.irq_process = &r100_irq_process,
1963	serge	264	// .get_vblank_counter = &r100_get_vblank_counter,
		265	.fence_ring_emit = &r300_fence_ring_emit,
		266	// .cs_parse = &r300_cs_parse,
2005	serge	267	.copy_blit = &r100_copy_blit,
		268	.copy_dma = &r200_copy_dma,
		269	.copy = &r100_copy_blit,
1963	serge	270	.get_engine_clock = &radeon_legacy_get_engine_clock,
		271	.set_engine_clock = &radeon_legacy_set_engine_clock,
		272	.get_memory_clock = &radeon_legacy_get_memory_clock,
		273	.set_memory_clock = NULL,
		274	.set_pcie_lanes = &rv370_set_pcie_lanes,
		275	.set_clock_gating = &radeon_legacy_set_clock_gating,
		276	.set_surface_reg = r100_set_surface_reg,
		277	.clear_surface_reg = r100_clear_surface_reg,
		278	.bandwidth_update = &r100_bandwidth_update,
		279	.hpd_init = &r100_hpd_init,
		280	.hpd_fini = &r100_hpd_fini,
		281	.hpd_sense = &r100_hpd_sense,
		282	.hpd_set_polarity = &r100_hpd_set_polarity,
		283	.ioctl_wait_idle = NULL,
2007	serge	284	.gui_idle = &r100_gui_idle,
1963	serge	285	};
		286
		287	static struct radeon_asic r420_asic = {
		288	.init = &r420_init,
		289	// .fini = &r420_fini,
		290	// .suspend = &r420_suspend,
		291	// .resume = &r420_resume,
		292	// .vga_set_state = &r100_vga_set_state,
		293	.asic_reset = &r300_asic_reset,
		294	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
		295	.gart_set_page = &rv370_pcie_gart_set_page,
		296	.cp_commit = &r100_cp_commit,
		297	.ring_start = &r300_ring_start,
		298	.ring_test = &r100_ring_test,
2005	serge	299	.ring_ib_execute = &r100_ring_ib_execute,
		300	.irq_set = &r100_irq_set,
		301	.irq_process = &r100_irq_process,
1963	serge	302	// .get_vblank_counter = &r100_get_vblank_counter,
		303	.fence_ring_emit = &r300_fence_ring_emit,
		304	// .cs_parse = &r300_cs_parse,
2005	serge	305	.copy_blit = &r100_copy_blit,
		306	.copy_dma = &r200_copy_dma,
		307	.copy = &r100_copy_blit,
1963	serge	308	.get_engine_clock = &radeon_atom_get_engine_clock,
		309	.set_engine_clock = &radeon_atom_set_engine_clock,
		310	.get_memory_clock = &radeon_atom_get_memory_clock,
		311	.set_memory_clock = &radeon_atom_set_memory_clock,
		312	.get_pcie_lanes = &rv370_get_pcie_lanes,
		313	.set_pcie_lanes = &rv370_set_pcie_lanes,
		314	.set_clock_gating = &radeon_atom_set_clock_gating,
		315	.set_surface_reg = r100_set_surface_reg,
		316	.clear_surface_reg = r100_clear_surface_reg,
		317	.bandwidth_update = &r100_bandwidth_update,
		318	.hpd_init = &r100_hpd_init,
		319	.hpd_fini = &r100_hpd_fini,
		320	.hpd_sense = &r100_hpd_sense,
		321	.hpd_set_polarity = &r100_hpd_set_polarity,
		322	.ioctl_wait_idle = NULL,
		323	};
		324
		325	static struct radeon_asic rs400_asic = {
		326	.init = &rs400_init,
		327	// .fini = &rs400_fini,
		328	// .suspend = &rs400_suspend,
		329	// .resume = &rs400_resume,
		330	// .vga_set_state = &r100_vga_set_state,
		331	.asic_reset = &r300_asic_reset,
		332	.gart_tlb_flush = &rs400_gart_tlb_flush,
		333	.gart_set_page = &rs400_gart_set_page,
		334	.cp_commit = &r100_cp_commit,
		335	.ring_start = &r300_ring_start,
		336	.ring_test = &r100_ring_test,
2005	serge	337	.ring_ib_execute = &r100_ring_ib_execute,
		338	.irq_set = &r100_irq_set,
		339	.irq_process = &r100_irq_process,
1963	serge	340	// .get_vblank_counter = &r100_get_vblank_counter,
		341	.fence_ring_emit = &r300_fence_ring_emit,
		342	// .cs_parse = &r300_cs_parse,
2005	serge	343	.copy_blit = &r100_copy_blit,
		344	.copy_dma = &r200_copy_dma,
		345	.copy = &r100_copy_blit,
1963	serge	346	.get_engine_clock = &radeon_legacy_get_engine_clock,
		347	.set_engine_clock = &radeon_legacy_set_engine_clock,
		348	.get_memory_clock = &radeon_legacy_get_memory_clock,
		349	.set_memory_clock = NULL,
		350	.get_pcie_lanes = NULL,
		351	.set_pcie_lanes = NULL,
		352	.set_clock_gating = &radeon_legacy_set_clock_gating,
		353	.set_surface_reg = r100_set_surface_reg,
		354	.clear_surface_reg = r100_clear_surface_reg,
		355	.bandwidth_update = &r100_bandwidth_update,
		356	.hpd_init = &r100_hpd_init,
		357	.hpd_fini = &r100_hpd_fini,
		358	.hpd_sense = &r100_hpd_sense,
		359	.hpd_set_polarity = &r100_hpd_set_polarity,
		360	.ioctl_wait_idle = NULL,
		361	};
		362
		363	static struct radeon_asic rs600_asic = {
		364	.init = &rs600_init,
		365	// .fini = &rs600_fini,
		366	// .suspend = &rs600_suspend,
		367	// .resume = &rs600_resume,
		368	// .vga_set_state = &r100_vga_set_state,
		369	.asic_reset = &rs600_asic_reset,
		370	.gart_tlb_flush = &rs600_gart_tlb_flush,
		371	.gart_set_page = &rs600_gart_set_page,
		372	.cp_commit = &r100_cp_commit,
		373	.ring_start = &r300_ring_start,
		374	.ring_test = &r100_ring_test,
2005	serge	375	.ring_ib_execute = &r100_ring_ib_execute,
		376	.irq_set = &rs600_irq_set,
		377	.irq_process = &rs600_irq_process,
1963	serge	378	// .get_vblank_counter = &rs600_get_vblank_counter,
		379	.fence_ring_emit = &r300_fence_ring_emit,
		380	// .cs_parse = &r300_cs_parse,
2005	serge	381	.copy_blit = &r100_copy_blit,
		382	.copy_dma = &r200_copy_dma,
		383	.copy = &r100_copy_blit,
1963	serge	384	.get_engine_clock = &radeon_atom_get_engine_clock,
		385	.set_engine_clock = &radeon_atom_set_engine_clock,
		386	.get_memory_clock = &radeon_atom_get_memory_clock,
		387	.set_memory_clock = &radeon_atom_set_memory_clock,
		388	.get_pcie_lanes = NULL,
		389	.set_pcie_lanes = NULL,
		390	.set_clock_gating = &radeon_atom_set_clock_gating,
		391	.set_surface_reg = r100_set_surface_reg,
		392	.clear_surface_reg = r100_clear_surface_reg,
		393	.bandwidth_update = &rs600_bandwidth_update,
		394	.hpd_init = &rs600_hpd_init,
		395	.hpd_fini = &rs600_hpd_fini,
		396	.hpd_sense = &rs600_hpd_sense,
		397	.hpd_set_polarity = &rs600_hpd_set_polarity,
		398	.ioctl_wait_idle = NULL,
		399	};
		400
		401	static struct radeon_asic rs690_asic = {
		402	.init = &rs690_init,
		403	// .fini = &rs690_fini,
		404	// .suspend = &rs690_suspend,
		405	// .resume = &rs690_resume,
		406	// .vga_set_state = &r100_vga_set_state,
		407	.asic_reset = &rs600_asic_reset,
		408	.gart_tlb_flush = &rs400_gart_tlb_flush,
		409	.gart_set_page = &rs400_gart_set_page,
		410	.cp_commit = &r100_cp_commit,
		411	.ring_start = &r300_ring_start,
		412	.ring_test = &r100_ring_test,
2005	serge	413	.ring_ib_execute = &r100_ring_ib_execute,
		414	.irq_set = &rs600_irq_set,
		415	.irq_process = &rs600_irq_process,
1963	serge	416	// .get_vblank_counter = &rs600_get_vblank_counter,
		417	.fence_ring_emit = &r300_fence_ring_emit,
		418	// .cs_parse = &r300_cs_parse,
2005	serge	419	.copy_blit = &r100_copy_blit,
		420	.copy_dma = &r200_copy_dma,
		421	.copy = &r200_copy_dma,
1963	serge	422	.get_engine_clock = &radeon_atom_get_engine_clock,
		423	.set_engine_clock = &radeon_atom_set_engine_clock,
		424	.get_memory_clock = &radeon_atom_get_memory_clock,
		425	.set_memory_clock = &radeon_atom_set_memory_clock,
		426	.get_pcie_lanes = NULL,
		427	.set_pcie_lanes = NULL,
		428	.set_clock_gating = &radeon_atom_set_clock_gating,
		429	.set_surface_reg = r100_set_surface_reg,
		430	.clear_surface_reg = r100_clear_surface_reg,
		431	.bandwidth_update = &rs690_bandwidth_update,
		432	.hpd_init = &rs600_hpd_init,
		433	.hpd_fini = &rs600_hpd_fini,
		434	.hpd_sense = &rs600_hpd_sense,
		435	.hpd_set_polarity = &rs600_hpd_set_polarity,
		436	.ioctl_wait_idle = NULL,
		437	};
		438
		439	static struct radeon_asic rv515_asic = {
		440	.init = &rv515_init,
		441	// .fini = &rv515_fini,
		442	// .suspend = &rv515_suspend,
		443	// .resume = &rv515_resume,
		444	// .vga_set_state = &r100_vga_set_state,
		445	.asic_reset = &rs600_asic_reset,
		446	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
		447	.gart_set_page = &rv370_pcie_gart_set_page,
		448	.cp_commit = &r100_cp_commit,
		449	.ring_start = &rv515_ring_start,
		450	.ring_test = &r100_ring_test,
2005	serge	451	.ring_ib_execute = &r100_ring_ib_execute,
		452	.irq_set = &rs600_irq_set,
		453	.irq_process = &rs600_irq_process,
1963	serge	454	// .get_vblank_counter = &rs600_get_vblank_counter,
		455	.fence_ring_emit = &r300_fence_ring_emit,
		456	// .cs_parse = &r300_cs_parse,
2005	serge	457	.copy_blit = &r100_copy_blit,
		458	.copy_dma = &r200_copy_dma,
		459	.copy = &r100_copy_blit,
1963	serge	460	.get_engine_clock = &radeon_atom_get_engine_clock,
		461	.set_engine_clock = &radeon_atom_set_engine_clock,
		462	.get_memory_clock = &radeon_atom_get_memory_clock,
		463	.set_memory_clock = &radeon_atom_set_memory_clock,
		464	.get_pcie_lanes = &rv370_get_pcie_lanes,
		465	.set_pcie_lanes = &rv370_set_pcie_lanes,
		466	.set_clock_gating = &radeon_atom_set_clock_gating,
		467	.set_surface_reg = r100_set_surface_reg,
		468	.clear_surface_reg = r100_clear_surface_reg,
		469	.bandwidth_update = &rv515_bandwidth_update,
		470	.hpd_init = &rs600_hpd_init,
		471	.hpd_fini = &rs600_hpd_fini,
		472	.hpd_sense = &rs600_hpd_sense,
		473	.hpd_set_polarity = &rs600_hpd_set_polarity,
		474	.ioctl_wait_idle = NULL,
		475	};
		476
		477	static struct radeon_asic r520_asic = {
		478	.init = &r520_init,
		479	// .fini = &rv515_fini,
		480	// .suspend = &rv515_suspend,
		481	// .resume = &r520_resume,
		482	// .vga_set_state = &r100_vga_set_state,
		483	.asic_reset = &rs600_asic_reset,
		484	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
		485	.gart_set_page = &rv370_pcie_gart_set_page,
		486	.cp_commit = &r100_cp_commit,
		487	.ring_start = &rv515_ring_start,
		488	.ring_test = &r100_ring_test,
2005	serge	489	.ring_ib_execute = &r100_ring_ib_execute,
		490	.irq_set = &rs600_irq_set,
		491	.irq_process = &rs600_irq_process,
1963	serge	492	// .get_vblank_counter = &rs600_get_vblank_counter,
		493	.fence_ring_emit = &r300_fence_ring_emit,
		494	// .cs_parse = &r300_cs_parse,
2005	serge	495	.copy_blit = &r100_copy_blit,
		496	.copy_dma = &r200_copy_dma,
		497	.copy = &r100_copy_blit,
1963	serge	498	.get_engine_clock = &radeon_atom_get_engine_clock,
		499	.set_engine_clock = &radeon_atom_set_engine_clock,
		500	.get_memory_clock = &radeon_atom_get_memory_clock,
		501	.set_memory_clock = &radeon_atom_set_memory_clock,
		502	.get_pcie_lanes = &rv370_get_pcie_lanes,
		503	.set_pcie_lanes = &rv370_set_pcie_lanes,
		504	.set_clock_gating = &radeon_atom_set_clock_gating,
		505	.set_surface_reg = r100_set_surface_reg,
		506	.clear_surface_reg = r100_clear_surface_reg,
		507	.bandwidth_update = &rv515_bandwidth_update,
		508	.hpd_init = &rs600_hpd_init,
		509	.hpd_fini = &rs600_hpd_fini,
		510	.hpd_sense = &rs600_hpd_sense,
		511	.hpd_set_polarity = &rs600_hpd_set_polarity,
		512	.ioctl_wait_idle = NULL,
		513	};
		514
		515	static struct radeon_asic r600_asic = {
		516	.init = &r600_init,
		517	// .fini = &r600_fini,
		518	// .suspend = &r600_suspend,
		519	// .resume = &r600_resume,
		520	.cp_commit = &r600_cp_commit,
		521	.vga_set_state = &r600_vga_set_state,
		522	.asic_reset = &r600_asic_reset,
		523	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
		524	.gart_set_page = &rs600_gart_set_page,
		525	.ring_test = &r600_ring_test,
2005	serge	526	.ring_ib_execute = &r600_ring_ib_execute,
2004	serge	527	.irq_set = &r600_irq_set,
		528	.irq_process = &r600_irq_process,
1963	serge	529	.fence_ring_emit = &r600_fence_ring_emit,
		530	// .cs_parse = &r600_cs_parse,
2005	serge	531	.copy_blit = &r600_copy_blit,
		532	.copy_dma = &r600_copy_blit,
		533	.copy = &r600_copy_blit,
1963	serge	534	.get_engine_clock = &radeon_atom_get_engine_clock,
		535	.set_engine_clock = &radeon_atom_set_engine_clock,
		536	.get_memory_clock = &radeon_atom_get_memory_clock,
		537	.set_memory_clock = &radeon_atom_set_memory_clock,
2005	serge	538	.get_pcie_lanes = &r600_get_pcie_lanes,
		539	.set_pcie_lanes = &r600_set_pcie_lanes,
1963	serge	540	.set_clock_gating = NULL,
		541	.set_surface_reg = r600_set_surface_reg,
		542	.clear_surface_reg = r600_clear_surface_reg,
		543	.bandwidth_update = &rv515_bandwidth_update,
		544	.hpd_init = &r600_hpd_init,
		545	.hpd_fini = &r600_hpd_fini,
		546	.hpd_sense = &r600_hpd_sense,
		547	.hpd_set_polarity = &r600_hpd_set_polarity,
		548	// .ioctl_wait_idle = r600_ioctl_wait_idle,
		549	};
		550
		551	static struct radeon_asic rs780_asic = {
		552	.init = &r600_init,
		553	// .fini = &r600_fini,
		554	// .suspend = &r600_suspend,
		555	// .resume = &r600_resume,
		556	.cp_commit = &r600_cp_commit,
		557	.gpu_is_lockup = &r600_gpu_is_lockup,
		558	.vga_set_state = &r600_vga_set_state,
		559	.asic_reset = &r600_asic_reset,
		560	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
		561	.gart_set_page = &rs600_gart_set_page,
		562	.ring_test = &r600_ring_test,
2005	serge	563	.ring_ib_execute = &r600_ring_ib_execute,
2004	serge	564	.irq_set = &r600_irq_set,
		565	.irq_process = &r600_irq_process,
1963	serge	566	.fence_ring_emit = &r600_fence_ring_emit,
		567	// .cs_parse = &r600_cs_parse,
2005	serge	568	.copy_blit = &r600_copy_blit,
		569	.copy_dma = &r600_copy_blit,
		570	.copy = &r600_copy_blit,
1963	serge	571	.get_engine_clock = &radeon_atom_get_engine_clock,
		572	.set_engine_clock = &radeon_atom_set_engine_clock,
		573	.get_memory_clock = NULL,
		574	.set_memory_clock = NULL,
		575	.get_pcie_lanes = NULL,
		576	.set_pcie_lanes = NULL,
		577	.set_clock_gating = NULL,
		578	.set_surface_reg = r600_set_surface_reg,
		579	.clear_surface_reg = r600_clear_surface_reg,
		580	.bandwidth_update = &rs690_bandwidth_update,
		581	.hpd_init = &r600_hpd_init,
		582	.hpd_fini = &r600_hpd_fini,
		583	.hpd_sense = &r600_hpd_sense,
		584	.hpd_set_polarity = &r600_hpd_set_polarity,
		585	};
		586
		587	static struct radeon_asic rv770_asic = {
		588	.init = &rv770_init,
		589	// .fini = &rv770_fini,
		590	// .suspend = &rv770_suspend,
		591	// .resume = &rv770_resume,
		592	.cp_commit = &r600_cp_commit,
		593	.asic_reset = &r600_asic_reset,
		594	.vga_set_state = &r600_vga_set_state,
		595	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
		596	.gart_set_page = &rs600_gart_set_page,
		597	.ring_test = &r600_ring_test,
2004	serge	598	.ring_ib_execute = &r600_ring_ib_execute,
		599	.irq_set = &r600_irq_set,
		600	.irq_process = &r600_irq_process,
1963	serge	601	.fence_ring_emit = &r600_fence_ring_emit,
		602	// .cs_parse = &r600_cs_parse,
2005	serge	603	.copy_blit = &r600_copy_blit,
		604	.copy_dma = &r600_copy_blit,
		605	.copy = &r600_copy_blit,
1963	serge	606	.get_engine_clock = &radeon_atom_get_engine_clock,
		607	.set_engine_clock = &radeon_atom_set_engine_clock,
		608	.get_memory_clock = &radeon_atom_get_memory_clock,
		609	.set_memory_clock = &radeon_atom_set_memory_clock,
2005	serge	610	.get_pcie_lanes = &r600_get_pcie_lanes,
		611	.set_pcie_lanes = &r600_set_pcie_lanes,
1963	serge	612	.set_clock_gating = &radeon_atom_set_clock_gating,
		613	.set_surface_reg = r600_set_surface_reg,
		614	.clear_surface_reg = r600_clear_surface_reg,
		615	.bandwidth_update = &rv515_bandwidth_update,
		616	.hpd_init = &r600_hpd_init,
		617	.hpd_fini = &r600_hpd_fini,
		618	.hpd_sense = &r600_hpd_sense,
		619	.hpd_set_polarity = &r600_hpd_set_polarity,
		620	};
1986	serge	621
1963	serge	622	static struct radeon_asic evergreen_asic = {
		623	.init = &evergreen_init,
		624	// .fini = &evergreen_fini,
		625	// .suspend = &evergreen_suspend,
		626	// .resume = &evergreen_resume,
1986	serge	627	.cp_commit = &r600_cp_commit,
1963	serge	628	.asic_reset = &evergreen_asic_reset,
		629	.vga_set_state = &r600_vga_set_state,
1986	serge	630	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1963	serge	631	.gart_set_page = &rs600_gart_set_page,
1986	serge	632	.ring_test = &r600_ring_test,
2005	serge	633	.ring_ib_execute = &evergreen_ring_ib_execute,
		634	.irq_set = &evergreen_irq_set,
		635	.irq_process = &evergreen_irq_process,
1986	serge	636	.fence_ring_emit = &r600_fence_ring_emit,
2005	serge	637	// .cs_parse = &evergreen_cs_parse,
		638	.copy_blit = &evergreen_copy_blit,
		639	.copy_dma = &evergreen_copy_blit,
		640	.copy = &evergreen_copy_blit,
1986	serge	641	.get_engine_clock = &radeon_atom_get_engine_clock,
		642	.set_engine_clock = &radeon_atom_set_engine_clock,
		643	.get_memory_clock = &radeon_atom_get_memory_clock,
		644	.set_memory_clock = &radeon_atom_set_memory_clock,
		645	.get_pcie_lanes = &r600_get_pcie_lanes,
		646	.set_pcie_lanes = &r600_set_pcie_lanes,
		647	.set_clock_gating = NULL,
		648	.set_surface_reg = r600_set_surface_reg,
		649	.clear_surface_reg = r600_clear_surface_reg,
		650	.bandwidth_update = &evergreen_bandwidth_update,
2005	serge	651	.hpd_init = &evergreen_hpd_init,
		652	.hpd_fini = &evergreen_hpd_fini,
		653	.hpd_sense = &evergreen_hpd_sense,
		654	.hpd_set_polarity = &evergreen_hpd_set_polarity,
1986	serge	655
		656	};
1990	serge	657
1986	serge	658	static struct radeon_asic sumo_asic = {
		659	.init = &evergreen_init,
1990	serge	660	// .fini = &evergreen_fini,
		661	// .suspend = &evergreen_suspend,
		662	// .resume = &evergreen_resume,
1986	serge	663	.cp_commit = &r600_cp_commit,
		664	.asic_reset = &evergreen_asic_reset,
		665	.vga_set_state = &r600_vga_set_state,
		666	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
		667	.gart_set_page = &rs600_gart_set_page,
		668	.ring_test = &r600_ring_test,
2005	serge	669	.ring_ib_execute = &evergreen_ring_ib_execute,
		670	.irq_set = &evergreen_irq_set,
		671	.irq_process = &evergreen_irq_process,
1986	serge	672	.fence_ring_emit = &r600_fence_ring_emit,
1990	serge	673	// .cs_parse = &r600_cs_parse,
2005	serge	674	.copy_blit = &evergreen_copy_blit,
		675	.copy_dma = &evergreen_copy_blit,
		676	.copy = &evergreen_copy_blit,
1986	serge	677	.get_engine_clock = &radeon_atom_get_engine_clock,
		678	.set_engine_clock = &radeon_atom_set_engine_clock,
		679	.get_memory_clock = NULL,
		680	.set_memory_clock = NULL,
		681	.get_pcie_lanes = NULL,
		682	.set_pcie_lanes = NULL,
		683	.set_clock_gating = NULL,
		684	.set_surface_reg = r600_set_surface_reg,
		685	.clear_surface_reg = r600_clear_surface_reg,
		686	.bandwidth_update = &evergreen_bandwidth_update,
2005	serge	687	.hpd_init = &evergreen_hpd_init,
		688	.hpd_fini = &evergreen_hpd_fini,
		689	.hpd_sense = &evergreen_hpd_sense,
		690	.hpd_set_polarity = &evergreen_hpd_set_polarity,
1986	serge	691	};
		692
		693	static struct radeon_asic btc_asic = {
		694	.init = &evergreen_init,
1990	serge	695	// .fini = &evergreen_fini,
		696	// .suspend = &evergreen_suspend,
		697	// .resume = &evergreen_resume,
1986	serge	698	.cp_commit = &r600_cp_commit,
		699	.asic_reset = &evergreen_asic_reset,
		700	.vga_set_state = &r600_vga_set_state,
		701	.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
		702	.gart_set_page = &rs600_gart_set_page,
1990	serge	703	.ring_test = &r600_ring_test,
2005	serge	704	.ring_ib_execute = &evergreen_ring_ib_execute,
		705	.irq_set = &evergreen_irq_set,
		706	.irq_process = &evergreen_irq_process,
1963	serge	707	.fence_ring_emit = &r600_fence_ring_emit,
2005	serge	708	// .cs_parse = &evergreen_cs_parse,
		709	.copy_blit = &evergreen_copy_blit,
		710	.copy_dma = &evergreen_copy_blit,
		711	.copy = &evergreen_copy_blit,
1986	serge	712	.get_engine_clock = &radeon_atom_get_engine_clock,
		713	.set_engine_clock = &radeon_atom_set_engine_clock,
		714	.get_memory_clock = &radeon_atom_get_memory_clock,
		715	.set_memory_clock = &radeon_atom_set_memory_clock,
		716	.get_pcie_lanes = NULL,
		717	.set_pcie_lanes = NULL,
		718	.set_clock_gating = NULL,
		719	.set_surface_reg = r600_set_surface_reg,
		720	.clear_surface_reg = r600_clear_surface_reg,
		721	.bandwidth_update = &evergreen_bandwidth_update,
2004	serge	722	.hpd_init = &evergreen_hpd_init,
2005	serge	723	.hpd_fini = &evergreen_hpd_fini,
2004	serge	724	.hpd_sense = &evergreen_hpd_sense,
2005	serge	725	.hpd_set_polarity = &evergreen_hpd_set_polarity,
1986	serge	726	};
		727
		728	static struct radeon_asic cayman_asic = {
		729	.init = &cayman_init,
2004	serge	730	// .fini = &evergreen_fini,
		731	// .suspend = &evergreen_suspend,
		732	// .resume = &evergreen_resume,
1986	serge	733	.cp_commit = &r600_cp_commit,
		734	.asic_reset = &cayman_asic_reset,
		735	.vga_set_state = &r600_vga_set_state,
		736	.gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
		737	.gart_set_page = &rs600_gart_set_page,
		738	.ring_test = &r600_ring_test,
2005	serge	739	.ring_ib_execute = &evergreen_ring_ib_execute,
		740	.irq_set = &evergreen_irq_set,
		741	.irq_process = &evergreen_irq_process,
1986	serge	742	.fence_ring_emit = &r600_fence_ring_emit,
2005	serge	743	// .cs_parse = &evergreen_cs_parse,
		744	.copy_blit = &evergreen_copy_blit,
		745	.copy_dma = &evergreen_copy_blit,
		746	.copy = &evergreen_copy_blit,
1963	serge	747	.get_engine_clock = &radeon_atom_get_engine_clock,
		748	.set_engine_clock = &radeon_atom_set_engine_clock,
		749	.get_memory_clock = &radeon_atom_get_memory_clock,
		750	.set_memory_clock = &radeon_atom_set_memory_clock,
2004	serge	751	.get_pcie_lanes = NULL,
1963	serge	752	.set_pcie_lanes = NULL,
		753	.set_clock_gating = NULL,
		754	.set_surface_reg = r600_set_surface_reg,
		755	.clear_surface_reg = r600_clear_surface_reg,
		756	.bandwidth_update = &evergreen_bandwidth_update,
2005	serge	757	.hpd_init = &evergreen_hpd_init,
		758	.hpd_fini = &evergreen_hpd_fini,
		759	.hpd_sense = &evergreen_hpd_sense,
		760	.hpd_set_polarity = &evergreen_hpd_set_polarity,
1963	serge	761	};
		762
		763	int radeon_asic_init(struct radeon_device *rdev)
		764	{
		765	radeon_register_accessor_init(rdev);
1986	serge	766
		767	/* set the number of crtcs */
		768	if (rdev->flags & RADEON_SINGLE_CRTC)
		769	rdev->num_crtc = 1;
		770	else
		771	rdev->num_crtc = 2;
		772
1963	serge	773	switch (rdev->family) {
		774	case CHIP_R100:
		775	case CHIP_RV100:
		776	case CHIP_RS100:
		777	case CHIP_RV200:
		778	case CHIP_RS200:
		779	rdev->asic = &r100_asic;
		780	break;
		781	case CHIP_R200:
		782	case CHIP_RV250:
		783	case CHIP_RS300:
		784	case CHIP_RV280:
		785	rdev->asic = &r200_asic;
		786	break;
		787	case CHIP_R300:
		788	case CHIP_R350:
		789	case CHIP_RV350:
		790	case CHIP_RV380:
		791	if (rdev->flags & RADEON_IS_PCIE)
		792	rdev->asic = &r300_asic_pcie;
		793	else
		794	rdev->asic = &r300_asic;
		795	break;
		796	case CHIP_R420:
		797	case CHIP_R423:
		798	case CHIP_RV410:
		799	rdev->asic = &r420_asic;
		800	/* handle macs */
		801	if (rdev->bios == NULL) {
		802	rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
		803	rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
		804	rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
		805	rdev->asic->set_memory_clock = NULL;
		806	}
		807	break;
		808	case CHIP_RS400:
		809	case CHIP_RS480:
		810	rdev->asic = &rs400_asic;
		811	break;
		812	case CHIP_RS600:
		813	rdev->asic = &rs600_asic;
		814	break;
		815	case CHIP_RS690:
		816	case CHIP_RS740:
		817	rdev->asic = &rs690_asic;
		818	break;
		819	case CHIP_RV515:
		820	rdev->asic = &rv515_asic;
		821	break;
		822	case CHIP_R520:
		823	case CHIP_RV530:
		824	case CHIP_RV560:
		825	case CHIP_RV570:
		826	case CHIP_R580:
		827	rdev->asic = &r520_asic;
		828	break;
		829	case CHIP_R600:
		830	case CHIP_RV610:
		831	case CHIP_RV630:
		832	case CHIP_RV620:
		833	case CHIP_RV635:
		834	case CHIP_RV670:
		835	rdev->asic = &r600_asic;
		836	break;
		837	case CHIP_RS780:
		838	case CHIP_RS880:
		839	rdev->asic = &rs780_asic;
		840	break;
		841	case CHIP_RV770:
		842	case CHIP_RV730:
		843	case CHIP_RV710:
		844	case CHIP_RV740:
		845	rdev->asic = &rv770_asic;
		846	break;
1986	serge	847	case CHIP_CEDAR:
		848	case CHIP_REDWOOD:
		849	case CHIP_JUNIPER:
		850	case CHIP_CYPRESS:
		851	case CHIP_HEMLOCK:
		852	/* set num crtcs */
		853	if (rdev->family == CHIP_CEDAR)
		854	rdev->num_crtc = 4;
		855	else
		856	rdev->num_crtc = 6;
		857	rdev->asic = &evergreen_asic;
		858	break;
1990	serge	859	case CHIP_PALM:
		860	case CHIP_SUMO:
		861	case CHIP_SUMO2:
		862	rdev->asic = &sumo_asic;
		863	break;
		864	case CHIP_BARTS:
		865	case CHIP_TURKS:
		866	case CHIP_CAICOS:
		867	/* set num crtcs */
		868	if (rdev->family == CHIP_CAICOS)
		869	rdev->num_crtc = 4;
		870	else
		871	rdev->num_crtc = 6;
		872	rdev->asic = &btc_asic;
		873	break;
2004	serge	874	case CHIP_CAYMAN:
		875	rdev->asic = &cayman_asic;
		876	/* set num crtcs */
		877	rdev->num_crtc = 6;
		878	break;
1963	serge	879	default:
		880	/* FIXME: not supported yet */
		881	return -EINVAL;
		882	}
		883
		884	if (rdev->flags & RADEON_IS_IGP) {
		885	rdev->asic->get_memory_clock = NULL;
		886	rdev->asic->set_memory_clock = NULL;
		887	}
		888
		889	return 0;
		890	}
		891

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_asic.c – Rev 2007