WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	/* TODO: Here are things that needs to be done :
		32	* - surface allocator & initializer : (bit like scratch reg) should
		33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		34	* related to surface
		35	* - WB : write back stuff (do it bit like scratch reg things)
		36	* - Vblank : look at Jesse's rework and what we should do
		37	* - r600/r700: gart & cp
		38	* - cs : clean cs ioctl use bitmap & things like that.
		39	* - power management stuff
		40	* - Barrier in gart code
		41	* - Unmappabled vram ?
		42	* - TESTING, TESTING, TESTING
		43	*/
		44
1221	serge	45	/* Initialization path:
		46	* We expect that acceleration initialization might fail for various
		47	* reasons even thought we work hard to make it works on most
		48	* configurations. In order to still have a working userspace in such
		49	* situation the init path must succeed up to the memory controller
		50	* initialization point. Failure before this point are considered as
		51	* fatal error. Here is the init callchain :
		52	* radeon_device_init perform common structure, mutex initialization
		53	* asic_init setup the GPU memory layout and perform all
		54	* one time initialization (failure in this
		55	* function are considered fatal)
		56	* asic_startup setup the GPU acceleration, in order to
		57	* follow guideline the first thing this
		58	* function should do is setting the GPU
		59	* memory controller (only MC setup failure
		60	* are considered as fatal)
		61	*/
		62
5271	serge	63	#include
2997	Serge	64	#include
1321	serge	65	#include
		66	#include
5078	serge	67	#include
6661	serge	68	#include
5271	serge	69	#include
1221	serge	70
1321	serge	71	#include
		72	#include
		73	#include
6661	serge	74	#include
5078	serge	75	#include
5346	serge	76	#include
1221	serge	77
5271	serge	78	#include
		79
2004	serge	80	#include
5271	serge	81	#include
1117	serge	82
1179	serge	83	#include "radeon_family.h"
1117	serge	84	#include "radeon_mode.h"
		85	#include "radeon_reg.h"
		86
		87	#include
		88
1179	serge	89	/*
		90	* Modules parameters.
		91	*/
		92	extern int radeon_no_wb;
1123	serge	93	extern int radeon_modeset;
1117	serge	94	extern int radeon_dynclks;
1123	serge	95	extern int radeon_r4xx_atom;
1128	serge	96	extern int radeon_agpmode;
		97	extern int radeon_vram_limit;
1117	serge	98	extern int radeon_gart_size;
1128	serge	99	extern int radeon_benchmarking;
1179	serge	100	extern int radeon_testing;
1123	serge	101	extern int radeon_connector_table;
1179	serge	102	extern int radeon_tv;
1403	serge	103	extern int radeon_audio;
1963	serge	104	extern int radeon_disp_priority;
		105	extern int radeon_hw_i2c;
		106	extern int radeon_pcie_gen2;
2997	Serge	107	extern int radeon_msi;
		108	extern int radeon_lockup_timeout;
3764	Serge	109	extern int radeon_fastfb;
5078	serge	110	extern int radeon_dpm;
		111	extern int radeon_aspm;
		112	extern int radeon_runtime_pm;
		113	extern int radeon_hard_reset;
		114	extern int radeon_vm_size;
		115	extern int radeon_vm_block_size;
		116	extern int radeon_deep_color;
		117	extern int radeon_use_pflipirq;
		118	extern int radeon_bapm;
5179	serge	119	extern int radeon_backlight;
6104	serge	120	extern int radeon_auxch;
		121	extern int radeon_mst;
2997	Serge	122
1117	serge	123	/*
		124	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		125	* symbol;
		126	*/
6104	serge	127	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
		128	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
7146	serge	129	#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
1428	serge	130	/* RADEON_IB_POOL_SIZE must be a power of 2 */
6104	serge	131	#define RADEON_IB_POOL_SIZE 16
		132	#define RADEON_DEBUGFS_MAX_COMPONENTS 32
		133	#define RADEONFB_CONN_LIMIT 4
		134	#define RADEON_BIOS_NUM_SCRATCH 8
1117	serge	135
2997	Serge	136	/* internal ring indices */
		137	/* r1xx+ has gfx CP ring */
6104	serge	138	#define RADEON_RING_TYPE_GFX_INDEX 0
2997	Serge	139
		140	/* cayman has 2 compute CP rings */
6104	serge	141	#define CAYMAN_RING_TYPE_CP1_INDEX 1
		142	#define CAYMAN_RING_TYPE_CP2_INDEX 2
2997	Serge	143
3192	Serge	144	/* R600+ has an async dma ring */
		145	#define R600_RING_TYPE_DMA_INDEX 3
		146	/* cayman add a second async dma ring */
		147	#define CAYMAN_RING_TYPE_DMA1_INDEX 4
		148
3764	Serge	149	/* R600+ */
6104	serge	150	#define R600_RING_TYPE_UVD_INDEX 5
3764	Serge	151
5078	serge	152	/* TN+ */
		153	#define TN_RING_TYPE_VCE1_INDEX 6
		154	#define TN_RING_TYPE_VCE2_INDEX 7
		155
		156	/* max number of rings */
		157	#define RADEON_NUM_RINGS 8
		158
		159	/* number of hw syncs before falling back on blocking */
		160	#define RADEON_NUM_SYNCS 4
		161
2997	Serge	162	/* hardcode those limit for now */
		163	#define RADEON_VA_IB_OFFSET (1 << 20)
6104	serge	164	#define RADEON_VA_RESERVED_SIZE (8 << 20)
		165	#define RADEON_IB_VM_MAX_SIZE (64 << 10)
2997	Serge	166
5078	serge	167	/* hard reset data */
		168	#define RADEON_ASIC_RESET_DATA 0x39d5e86b
		169
3192	Serge	170	/* reset flags */
		171	#define RADEON_RESET_GFX (1 << 0)
		172	#define RADEON_RESET_COMPUTE (1 << 1)
		173	#define RADEON_RESET_DMA (1 << 2)
3764	Serge	174	#define RADEON_RESET_CP (1 << 3)
		175	#define RADEON_RESET_GRBM (1 << 4)
		176	#define RADEON_RESET_DMA1 (1 << 5)
		177	#define RADEON_RESET_RLC (1 << 6)
		178	#define RADEON_RESET_SEM (1 << 7)
		179	#define RADEON_RESET_IH (1 << 8)
		180	#define RADEON_RESET_VMC (1 << 9)
		181	#define RADEON_RESET_MC (1 << 10)
		182	#define RADEON_RESET_DISPLAY (1 << 11)
3192	Serge	183
5078	serge	184	/* CG block flags */
		185	#define RADEON_CG_BLOCK_GFX (1 << 0)
		186	#define RADEON_CG_BLOCK_MC (1 << 1)
		187	#define RADEON_CG_BLOCK_SDMA (1 << 2)
		188	#define RADEON_CG_BLOCK_UVD (1 << 3)
		189	#define RADEON_CG_BLOCK_VCE (1 << 4)
		190	#define RADEON_CG_BLOCK_HDP (1 << 5)
		191	#define RADEON_CG_BLOCK_BIF (1 << 6)
		192
		193	/* CG flags */
		194	#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
		195	#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
		196	#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
		197	#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
		198	#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
		199	#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
		200	#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
		201	#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
		202	#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
		203	#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
		204	#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
		205	#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
		206	#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
		207	#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
		208	#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
		209	#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
		210	#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
		211
		212	/* PG flags */
		213	#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
		214	#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
		215	#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
		216	#define RADEON_PG_SUPPORT_UVD (1 << 3)
		217	#define RADEON_PG_SUPPORT_VCE (1 << 4)
		218	#define RADEON_PG_SUPPORT_CP (1 << 5)
		219	#define RADEON_PG_SUPPORT_GDS (1 << 6)
		220	#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
		221	#define RADEON_PG_SUPPORT_SDMA (1 << 8)
		222	#define RADEON_PG_SUPPORT_ACP (1 << 9)
		223	#define RADEON_PG_SUPPORT_SAMU (1 << 10)
		224
		225	/* max cursor sizes (in pixels) */
		226	#define CURSOR_WIDTH 64
		227	#define CURSOR_HEIGHT 64
		228
		229	#define CIK_CURSOR_WIDTH 128
		230	#define CIK_CURSOR_HEIGHT 128
		231
1117	serge	232	/*
		233	* Errata workarounds.
		234	*/
		235	enum radeon_pll_errata {
6104	serge	236	CHIP_ERRATA_R300_CG = 0x00000001,
		237	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		238	CHIP_ERRATA_PLL_DELAY = 0x00000004
1117	serge	239	};
		240
		241
		242	struct radeon_device;
		243
		244
		245	/*
		246	* BIOS.
		247	*/
		248	bool radeon_get_bios(struct radeon_device *rdev);
		249
		250	/*
1179	serge	251	* Dummy page
		252	*/
		253	struct radeon_dummy_page {
6104	serge	254	uint64_t entry;
1179	serge	255	struct page *page;
		256	dma_addr_t addr;
		257	};
		258	int radeon_dummy_page_init(struct radeon_device *rdev);
		259	void radeon_dummy_page_fini(struct radeon_device *rdev);
		260
		261
		262	/*
1117	serge	263	* Clocks
		264	*/
		265	struct radeon_clock {
		266	struct radeon_pll p1pll;
		267	struct radeon_pll p2pll;
1430	serge	268	struct radeon_pll dcpll;
1117	serge	269	struct radeon_pll spll;
		270	struct radeon_pll mpll;
		271	/* 10 Khz units */
		272	uint32_t default_mclk;
		273	uint32_t default_sclk;
1430	serge	274	uint32_t default_dispclk;
5078	serge	275	uint32_t current_dispclk;
1430	serge	276	uint32_t dp_extclk;
1963	serge	277	uint32_t max_pixel_clock;
6321	serge	278	uint32_t vco_freq;
1117	serge	279	};
		280
1268	serge	281	/*
		282	* Power management
		283	*/
		284	int radeon_pm_init(struct radeon_device *rdev);
5078	serge	285	int radeon_pm_late_init(struct radeon_device *rdev);
1963	serge	286	void radeon_pm_fini(struct radeon_device *rdev);
1430	serge	287	void radeon_pm_compute_clocks(struct radeon_device *rdev);
1963	serge	288	void radeon_pm_suspend(struct radeon_device *rdev);
		289	void radeon_pm_resume(struct radeon_device *rdev);
1430	serge	290	void radeon_combios_get_power_modes(struct radeon_device *rdev);
		291	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
3764	Serge	292	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		293	u8 clock_type,
		294	u32 clock,
		295	bool strobe_mode,
		296	struct atom_clock_dividers *dividers);
5078	serge	297	int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
		298	u32 clock,
		299	bool strobe_mode,
		300	struct atom_mpll_param *mpll_param);
1963	serge	301	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
5078	serge	302	int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
		303	u16 voltage_level, u8 voltage_type,
		304	u32 gpio_value, u32 gpio_mask);
		305	void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
		306	u32 eng_clock, u32 mem_clock);
		307	int radeon_atom_get_voltage_step(struct radeon_device *rdev,
		308	u8 voltage_type, u16 *voltage_step);
		309	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		310	u16 voltage_id, u16 *voltage);
		311	int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
		312	u16 *voltage,
		313	u16 leakage_idx);
		314	int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
		315	u16 *leakage_id);
		316	int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
		317	u16 vddc, u16 vddci,
		318	u16 virtual_voltage_id,
		319	u16 vbios_voltage_id);
		320	int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
		321	u16 virtual_voltage_id,
		322	u16 *voltage);
		323	int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
		324	u8 voltage_type,
		325	u16 nominal_voltage,
		326	u16 *true_voltage);
		327	int radeon_atom_get_min_voltage(struct radeon_device *rdev,
		328	u8 voltage_type, u16 *min_voltage);
		329	int radeon_atom_get_max_voltage(struct radeon_device *rdev,
		330	u8 voltage_type, u16 *max_voltage);
		331	int radeon_atom_get_voltage_table(struct radeon_device *rdev,
		332	u8 voltage_type, u8 voltage_mode,
		333	struct atom_voltage_table *voltage_table);
		334	bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
		335	u8 voltage_type, u8 voltage_mode);
		336	int radeon_atom_get_svi2_info(struct radeon_device *rdev,
		337	u8 voltage_type,
		338	u8 svd_gpio_id, u8 svc_gpio_id);
		339	void radeon_atom_update_memory_dll(struct radeon_device *rdev,
		340	u32 mem_clock);
		341	void radeon_atom_set_ac_timing(struct radeon_device *rdev,
		342	u32 mem_clock);
		343	int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
		344	u8 module_index,
		345	struct atom_mc_reg_table *reg_table);
		346	int radeon_atom_get_memory_info(struct radeon_device *rdev,
		347	u8 module_index, struct atom_memory_info *mem_info);
		348	int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
		349	bool gddr5, u8 module_index,
		350	struct atom_memory_clock_range_table *mclk_range_table);
		351	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		352	u16 voltage_id, u16 *voltage);
1963	serge	353	void rs690_pm_info(struct radeon_device *rdev);
2997	Serge	354	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
		355	unsigned bankh, unsigned mtaspect,
		356	unsigned *tile_split);
1179	serge	357
1117	serge	358	/*
		359	* Fences.
		360	*/
		361	struct radeon_fence_driver {
5271	serge	362	struct radeon_device *rdev;
1117	serge	363	uint32_t scratch_reg;
2997	Serge	364	uint64_t gpu_addr;
		365	volatile uint32_t *cpu_addr;
		366	/* sync_seq is protected by ring emission lock */
		367	uint64_t sync_seq[RADEON_NUM_RINGS];
		368	atomic64_t last_seq;
5271	serge	369	bool initialized, delayed_irq;
		370	struct delayed_work lockup_work;
1117	serge	371	};
		372
		373	struct radeon_fence {
5271	serge	374	struct fence base;
		375
6104	serge	376	struct radeon_device *rdev;
		377	uint64_t seq;
2997	Serge	378	/* RB, DMA, etc. */
6104	serge	379	unsigned ring;
5271	serge	380	bool is_vm_update;
		381
		382	wait_queue_t fence_wake;
1117	serge	383	};
		384
2997	Serge	385	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
1117	serge	386	int radeon_fence_driver_init(struct radeon_device *rdev);
		387	void radeon_fence_driver_fini(struct radeon_device *rdev);
5271	serge	388	void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
2997	Serge	389	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);
		390	void radeon_fence_process(struct radeon_device *rdev, int ring);
1117	serge	391	bool radeon_fence_signaled(struct radeon_fence *fence);
7146	serge	392	long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
1117	serge	393	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
5078	serge	394	int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
		395	int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
2997	Serge	396	int radeon_fence_wait_any(struct radeon_device *rdev,
		397	struct radeon_fence **fences,
		398	bool intr);
1117	serge	399	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		400	void radeon_fence_unref(struct radeon_fence **fence);
2997	Serge	401	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
		402	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
		403	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
		404	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,
		405	struct radeon_fence *b)
		406	{
		407	if (!a) {
		408	return b;
		409	}
1117	serge	410
2997	Serge	411	if (!b) {
		412	return a;
		413	}
		414
		415	BUG_ON(a->ring != b->ring);
		416
		417	if (a->seq > b->seq) {
		418	return a;
		419	} else {
		420	return b;
		421	}
		422	}
		423
		424	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
		425	struct radeon_fence *b)
		426	{
		427	if (!a) {
		428	return false;
		429	}
		430
		431	if (!b) {
		432	return true;
		433	}
		434
		435	BUG_ON(a->ring != b->ring);
		436
		437	return a->seq < b->seq;
		438	}
		439
1179	serge	440	/*
		441	* Tiling registers
		442	*/
		443	struct radeon_surface_reg {
1321	serge	444	struct radeon_bo *bo;
1179	serge	445	};
1117	serge	446
1179	serge	447	#define RADEON_GEM_MAX_SURFACES 8
		448
1117	serge	449	/*
1321	serge	450	* TTM.
1117	serge	451	*/
1321	serge	452	struct radeon_mman {
		453	struct ttm_bo_global_ref bo_global_ref;
3764	Serge	454	struct drm_global_reference mem_global_ref;
1403	serge	455	struct ttm_bo_device bdev;
1321	serge	456	bool mem_global_referenced;
1403	serge	457	bool initialized;
5078	serge	458
		459	#if defined(CONFIG_DEBUG_FS)
		460	struct dentry *vram;
		461	struct dentry *gtt;
		462	#endif
1321	serge	463	};
1117	serge	464
5271	serge	465	struct radeon_bo_list {
		466	struct radeon_bo *robj;
		467	struct ttm_validate_buffer tv;
		468	uint64_t gpu_offset;
		469	unsigned prefered_domains;
		470	unsigned allowed_domains;
		471	uint32_t tiling_flags;
		472	};
		473
2997	Serge	474	/* bo virtual address in a specific vm */
		475	struct radeon_bo_va {
		476	/* protected by bo being reserved */
		477	struct list_head bo_list;
		478	uint32_t flags;
5271	serge	479	struct radeon_fence *last_pt_update;
2997	Serge	480	unsigned ref_count;
		481
		482	/* protected by vm mutex */
5078	serge	483	struct interval_tree_node it;
		484	struct list_head vm_status;
2997	Serge	485
		486	/* constant after initialization */
		487	struct radeon_vm *vm;
		488	struct radeon_bo *bo;
		489	};
		490
1321	serge	491	struct radeon_bo {
		492	/* Protected by gem.mutex */
		493	struct list_head list;
		494	/* Protected by tbo.reserved */
5078	serge	495	u32 initial_domain;
5271	serge	496	struct ttm_place placements[4];
6104	serge	497	struct ttm_placement placement;
		498	struct ttm_buffer_object tbo;
1321	serge	499	struct ttm_bo_kmap_obj kmap;
5078	serge	500	u32 flags;
6104	serge	501	unsigned pin_count;
		502	void *kptr;
		503	u32 tiling_flags;
		504	u32 pitch;
		505	int surface_reg;
2997	Serge	506	/* list of all virtual address to which this bo
		507	* is associated to
		508	*/
		509	struct list_head va;
1321	serge	510	/* Constant after initialization */
		511	struct radeon_device *rdev;
1963	serge	512	struct drm_gem_object gem_base;
3120	serge	513
5078	serge	514	pid_t pid;
5271	serge	515
		516	struct radeon_mn *mn;
6104	serge	517	struct list_head mn_list;
1321	serge	518	};
1963	serge	519	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
1321	serge	520
3764	Serge	521	int radeon_gem_debugfs_init(struct radeon_device *rdev);
		522
2997	Serge	523	/* sub-allocation manager, it has to be protected by another lock.
		524	* By conception this is an helper for other part of the driver
		525	* like the indirect buffer or semaphore, which both have their
		526	* locking.
		527	*
		528	* Principe is simple, we keep a list of sub allocation in offset
		529	* order (first entry has offset == 0, last entry has the highest
		530	* offset).
		531	*
		532	* When allocating new object we first check if there is room at
		533	* the end total_size - (last_object_offset + last_object_size) >=
		534	* alloc_size. If so we allocate new object there.
		535	*
		536	* When there is not enough room at the end, we start waiting for
		537	* each sub object until we reach object_offset+object_size >=
		538	* alloc_size, this object then become the sub object we return.
		539	*
		540	* Alignment can't be bigger than page size.
		541	*
		542	* Hole are not considered for allocation to keep things simple.
		543	* Assumption is that there won't be hole (all object on same
		544	* alignment).
		545	*/
		546	struct radeon_sa_manager {
		547	wait_queue_head_t wq;
		548	struct radeon_bo *bo;
		549	struct list_head *hole;
		550	struct list_head flist[RADEON_NUM_RINGS];
		551	struct list_head olist;
		552	unsigned size;
		553	uint64_t gpu_addr;
		554	void *cpu_ptr;
		555	uint32_t domain;
5078	serge	556	uint32_t align;
2997	Serge	557	};
		558
		559	struct radeon_sa_bo;
		560
		561	/* sub-allocation buffer */
		562	struct radeon_sa_bo {
		563	struct list_head olist;
		564	struct list_head flist;
		565	struct radeon_sa_manager *manager;
		566	unsigned soffset;
		567	unsigned eoffset;
		568	struct radeon_fence *fence;
		569	};
		570
1123	serge	571	/*
		572	* GEM objects.
		573	*/
		574	struct radeon_gem {
1630	serge	575	struct mutex mutex;
1123	serge	576	struct list_head objects;
		577	};
1117	serge	578
1126	serge	579	int radeon_gem_init(struct radeon_device *rdev);
		580	void radeon_gem_fini(struct radeon_device *rdev);
5078	serge	581	int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
6104	serge	582	int alignment, int initial_domain,
5078	serge	583	u32 flags, bool kernel,
6104	serge	584	struct drm_gem_object **obj);
1117	serge	585
2004	serge	586	int radeon_mode_dumb_create(struct drm_file *file_priv,
		587	struct drm_device *dev,
		588	struct drm_mode_create_dumb *args);
		589	int radeon_mode_dumb_mmap(struct drm_file *filp,
		590	struct drm_device *dev,
		591	uint32_t handle, uint64_t *offset_p);
1117	serge	592
		593	/*
2997	Serge	594	* Semaphores.
1117	serge	595	*/
2997	Serge	596	struct radeon_semaphore {
6104	serge	597	struct radeon_sa_bo *sa_bo;
		598	signed waiters;
		599	uint64_t gpu_addr;
1117	serge	600	};
		601
2997	Serge	602	int radeon_semaphore_create(struct radeon_device *rdev,
		603	struct radeon_semaphore **semaphore);
5078	serge	604	bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
2997	Serge	605	struct radeon_semaphore *semaphore);
5078	serge	606	bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
2997	Serge	607	struct radeon_semaphore *semaphore);
		608	void radeon_semaphore_free(struct radeon_device *rdev,
		609	struct radeon_semaphore **semaphore,
		610	struct radeon_fence *fence);
1117	serge	611
2997	Serge	612	/*
5271	serge	613	* Synchronization
		614	*/
		615	struct radeon_sync {
		616	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
		617	struct radeon_fence *sync_to[RADEON_NUM_RINGS];
		618	struct radeon_fence *last_vm_update;
		619	};
		620
		621	void radeon_sync_create(struct radeon_sync *sync);
		622	void radeon_sync_fence(struct radeon_sync *sync,
6104	serge	623	struct radeon_fence *fence);
5271	serge	624	int radeon_sync_resv(struct radeon_device *rdev,
		625	struct radeon_sync *sync,
		626	struct reservation_object *resv,
		627	bool shared);
		628	int radeon_sync_rings(struct radeon_device *rdev,
		629	struct radeon_sync *sync,
6104	serge	630	int waiting_ring);
5271	serge	631	void radeon_sync_free(struct radeon_device rdev, struct radeon_sync sync,
6104	serge	632	struct radeon_fence *fence);
5271	serge	633
		634	/*
2997	Serge	635	* GART structures, functions & helpers
		636	*/
		637	struct radeon_mc;
1117	serge	638
1268	serge	639	#define RADEON_GPU_PAGE_SIZE 4096
1430	serge	640	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
2997	Serge	641	#define RADEON_GPU_PAGE_SHIFT 12
		642	#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
1268	serge	643
5078	serge	644	#define RADEON_GART_PAGE_DUMMY 0
		645	#define RADEON_GART_PAGE_VALID (1 << 0)
		646	#define RADEON_GART_PAGE_READ (1 << 1)
		647	#define RADEON_GART_PAGE_WRITE (1 << 2)
		648	#define RADEON_GART_PAGE_SNOOP (1 << 3)
		649
1117	serge	650	struct radeon_gart {
6104	serge	651	dma_addr_t table_addr;
2997	Serge	652	struct radeon_bo *robj;
		653	void *ptr;
6104	serge	654	unsigned num_gpu_pages;
		655	unsigned num_cpu_pages;
		656	unsigned table_size;
		657	struct page **pages;
		658	uint64_t *pages_entry;
		659	bool ready;
1117	serge	660	};
		661
		662	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		663	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		664	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		665	void radeon_gart_table_vram_free(struct radeon_device *rdev);
2997	Serge	666	int radeon_gart_table_vram_pin(struct radeon_device *rdev);
		667	void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
1117	serge	668	int radeon_gart_init(struct radeon_device *rdev);
		669	void radeon_gart_fini(struct radeon_device *rdev);
		670	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		671	int pages);
1120	serge	672	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
5078	serge	673	int pages, struct page **pagelist,
		674	dma_addr_t *dma_addr, uint32_t flags);
1117	serge	675
		676
		677	/*
		678	* GPU MC structures, functions & helpers
		679	*/
		680	struct radeon_mc {
6104	serge	681	resource_size_t aper_size;
		682	resource_size_t aper_base;
		683	resource_size_t agp_base;
1179	serge	684	/* for some chips with <= 32MB we need to lie
		685	* about vram size near mc fb location */
		686	u64 mc_vram_size;
1430	serge	687	u64 visible_vram_size;
1179	serge	688	u64 gtt_size;
		689	u64 gtt_start;
		690	u64 gtt_end;
		691	u64 vram_start;
		692	u64 vram_end;
6104	serge	693	unsigned vram_width;
1179	serge	694	u64 real_vram_size;
6104	serge	695	int vram_mtrr;
		696	bool vram_is_ddr;
		697	bool igp_sideport_enabled;
1963	serge	698	u64 gtt_base_align;
3764	Serge	699	u64 mc_mask;
1117	serge	700	};
		701
1403	serge	702	bool radeon_combios_sideport_present(struct radeon_device *rdev);
		703	bool radeon_atombios_sideport_present(struct radeon_device *rdev);
1117	serge	704
		705	/*
		706	* GPU scratch registers structures, functions & helpers
		707	*/
		708	struct radeon_scratch {
6104	serge	709	unsigned num_reg;
1963	serge	710	uint32_t reg_base;
6104	serge	711	bool free[32];
		712	uint32_t reg[32];
1117	serge	713	};
		714
		715	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		716	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		717
5078	serge	718	/*
		719	* GPU doorbell structures, functions & helpers
		720	*/
		721	#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
1117	serge	722
5078	serge	723	struct radeon_doorbell {
		724	/* doorbell mmio */
6104	serge	725	resource_size_t base;
		726	resource_size_t size;
5078	serge	727	u32 __iomem *ptr;
		728	u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
6104	serge	729	DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
5078	serge	730	};
		731
		732	int radeon_doorbell_get(struct radeon_device rdev, u32 page);
		733	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
5271	serge	734	void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
		735	phys_addr_t *aperture_base,
		736	size_t *aperture_size,
		737	size_t *start_offset);
5078	serge	738
1117	serge	739	/*
		740	* IRQS.
		741	*/
1963	serge	742	struct r500_irq_stat_regs {
		743	u32 disp_int;
2997	Serge	744	u32 hdmi0_status;
1963	serge	745	};
		746
		747	struct r600_irq_stat_regs {
		748	u32 disp_int;
		749	u32 disp_int_cont;
		750	u32 disp_int_cont2;
		751	u32 d1grph_int;
		752	u32 d2grph_int;
2997	Serge	753	u32 hdmi0_status;
		754	u32 hdmi1_status;
1963	serge	755	};
		756
		757	struct evergreen_irq_stat_regs {
		758	u32 disp_int;
		759	u32 disp_int_cont;
		760	u32 disp_int_cont2;
		761	u32 disp_int_cont3;
		762	u32 disp_int_cont4;
		763	u32 disp_int_cont5;
		764	u32 d1grph_int;
		765	u32 d2grph_int;
		766	u32 d3grph_int;
		767	u32 d4grph_int;
		768	u32 d5grph_int;
		769	u32 d6grph_int;
2997	Serge	770	u32 afmt_status1;
		771	u32 afmt_status2;
		772	u32 afmt_status3;
		773	u32 afmt_status4;
		774	u32 afmt_status5;
		775	u32 afmt_status6;
1963	serge	776	};
		777
5078	serge	778	struct cik_irq_stat_regs {
		779	u32 disp_int;
		780	u32 disp_int_cont;
		781	u32 disp_int_cont2;
		782	u32 disp_int_cont3;
		783	u32 disp_int_cont4;
		784	u32 disp_int_cont5;
		785	u32 disp_int_cont6;
		786	u32 d1grph_int;
		787	u32 d2grph_int;
		788	u32 d3grph_int;
		789	u32 d4grph_int;
		790	u32 d5grph_int;
		791	u32 d6grph_int;
		792	};
		793
1963	serge	794	union radeon_irq_stat_regs {
		795	struct r500_irq_stat_regs r500;
		796	struct r600_irq_stat_regs r600;
		797	struct evergreen_irq_stat_regs evergreen;
5078	serge	798	struct cik_irq_stat_regs cik;
1963	serge	799	};
		800
1117	serge	801	struct radeon_irq {
6104	serge	802	bool installed;
2997	Serge	803	spinlock_t lock;
		804	atomic_t ring_int[RADEON_NUM_RINGS];
		805	bool crtc_vblank_int[RADEON_MAX_CRTCS];
		806	atomic_t pflip[RADEON_MAX_CRTCS];
6104	serge	807	wait_queue_head_t vblank_queue;
2997	Serge	808	bool hpd[RADEON_MAX_HPD_PINS];
		809	bool afmt[RADEON_MAX_AFMT_BLOCKS];
6104	serge	810	union radeon_irq_stat_regs stat_regs;
5078	serge	811	bool dpm_thermal;
1117	serge	812	};
		813
		814	int radeon_irq_kms_init(struct radeon_device *rdev);
		815	void radeon_irq_kms_fini(struct radeon_device *rdev);
2997	Serge	816	void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
5271	serge	817	bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
2997	Serge	818	void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
2004	serge	819	void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
		820	void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
2997	Serge	821	void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
		822	void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
		823	void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
		824	void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
1117	serge	825
		826	/*
2997	Serge	827	* CP & rings.
1117	serge	828	*/
2997	Serge	829
1117	serge	830	struct radeon_ib {
2997	Serge	831	struct radeon_sa_bo *sa_bo;
6104	serge	832	uint32_t length_dw;
		833	uint64_t gpu_addr;
		834	uint32_t *ptr;
2997	Serge	835	int ring;
6104	serge	836	struct radeon_fence *fence;
2997	Serge	837	struct radeon_vm *vm;
6104	serge	838	bool is_const_ib;
5271	serge	839	struct radeon_sync sync;
1117	serge	840	};
		841
2997	Serge	842	struct radeon_ring {
1321	serge	843	struct radeon_bo *ring_obj;
1117	serge	844	volatile uint32_t *ring;
2997	Serge	845	unsigned rptr_offs;
		846	unsigned rptr_save_reg;
		847	u64 next_rptr_gpu_addr;
		848	volatile u32 *next_rptr_cpu_addr;
5078	serge	849	unsigned wptr;
		850	unsigned wptr_old;
		851	unsigned ring_size;
		852	unsigned ring_free_dw;
		853	int count_dw;
		854	atomic_t last_rptr;
		855	atomic64_t last_activity;
		856	uint64_t gpu_addr;
		857	uint32_t align_mask;
		858	uint32_t ptr_mask;
		859	bool ready;
2997	Serge	860	u32 nop;
		861	u32 idx;
3764	Serge	862	u64 last_semaphore_signal_addr;
		863	u64 last_semaphore_wait_addr;
5078	serge	864	/* for CIK queues */
		865	u32 me;
		866	u32 pipe;
		867	u32 queue;
		868	struct radeon_bo *mqd_obj;
		869	u32 doorbell_index;
		870	unsigned wptr_offs;
1117	serge	871	};
		872
5078	serge	873	struct radeon_mec {
		874	struct radeon_bo *hpd_eop_obj;
		875	u64 hpd_eop_gpu_addr;
		876	u32 num_pipe;
		877	u32 num_mec;
		878	u32 num_queue;
		879	};
		880
1321	serge	881	/*
2997	Serge	882	* VM
		883	*/
		884
		885	/* maximum number of VMIDs */
		886	#define RADEON_NUM_VM 16
		887
		888	/* number of entries in page table */
5078	serge	889	#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
2997	Serge	890
5078	serge	891	/* PTBs (Page Table Blocks) need to be aligned to 32K */
		892	#define RADEON_VM_PTB_ALIGN_SIZE 32768
		893	#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
		894	#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
		895
		896	#define R600_PTE_VALID (1 << 0)
		897	#define R600_PTE_SYSTEM (1 << 1)
		898	#define R600_PTE_SNOOPED (1 << 2)
		899	#define R600_PTE_READABLE (1 << 5)
		900	#define R600_PTE_WRITEABLE (1 << 6)
		901
		902	/* PTE (Page Table Entry) fragment field for different page sizes */
		903	#define R600_PTE_FRAG_4KB (0 << 7)
		904	#define R600_PTE_FRAG_64KB (4 << 7)
		905	#define R600_PTE_FRAG_256KB (6 << 7)
		906
		907	/* flags needed to be set so we can copy directly from the GART table */
		908	#define R600_PTE_GART_MASK ( R600_PTE_READABLE \| R600_PTE_WRITEABLE \| \
		909	R600_PTE_SYSTEM \| R600_PTE_VALID )
		910
		911	struct radeon_vm_pt {
		912	struct radeon_bo *bo;
		913	uint64_t addr;
		914	};
		915
5271	serge	916	struct radeon_vm_id {
		917	unsigned id;
		918	uint64_t pd_gpu_addr;
		919	/* last flushed PD/PT update */
		920	struct radeon_fence *flushed_updates;
		921	/* last use of vmid */
		922	struct radeon_fence *last_id_use;
		923	};
		924
2997	Serge	925	struct radeon_vm {
5271	serge	926	struct mutex mutex;
		927
6104	serge	928	struct rb_root va;
2997	Serge	929
5271	serge	930	/* protecting invalidated and freed */
		931	spinlock_t status_lock;
		932
5078	serge	933	/* BOs moved, but not yet updated in the PT */
6104	serge	934	struct list_head invalidated;
5078	serge	935
		936	/* BOs freed, but not yet updated in the PT */
6104	serge	937	struct list_head freed;
5078	serge	938
6104	serge	939	/* BOs cleared in the PT */
		940	struct list_head cleared;
		941
2997	Serge	942	/* contains the page directory */
6104	serge	943	struct radeon_bo *page_directory;
		944	unsigned max_pde_used;
2997	Serge	945
		946	/* array of page tables, one for each page directory entry */
6104	serge	947	struct radeon_vm_pt *page_tables;
2997	Serge	948
6104	serge	949	struct radeon_bo_va *ib_bo_va;
5078	serge	950
5271	serge	951	/* for id and flush management per ring */
		952	struct radeon_vm_id ids[RADEON_NUM_RINGS];
2997	Serge	953	};
		954
		955	struct radeon_vm_manager {
		956	struct radeon_fence *active[RADEON_NUM_VM];
		957	uint32_t max_pfn;
		958	/* number of VMIDs */
		959	unsigned nvm;
		960	/* vram base address for page table entry */
		961	u64 vram_base_offset;
		962	/* is vm enabled? */
		963	bool enabled;
5078	serge	964	/* for hw to save the PD addr on suspend/resume */
		965	uint32_t saved_table_addr[RADEON_NUM_VM];
2997	Serge	966	};
		967
		968	/*
		969	* file private structure
		970	*/
		971	struct radeon_fpriv {
		972	struct radeon_vm vm;
		973	};
		974
		975	/*
1321	serge	976	* R6xx+ IH ring
		977	*/
		978	struct r600_ih {
		979	struct radeon_bo *ring_obj;
		980	volatile uint32_t *ring;
6104	serge	981	unsigned rptr;
		982	unsigned ring_size;
		983	uint64_t gpu_addr;
		984	uint32_t ptr_mask;
2997	Serge	985	atomic_t lock;
6104	serge	986	bool enabled;
1321	serge	987	};
		988
2997	Serge	989	/*
5078	serge	990	* RLC stuff
2997	Serge	991	*/
5078	serge	992	#include "clearstate_defs.h"
		993
		994	struct radeon_rlc {
2997	Serge	995	/* for power gating */
		996	struct radeon_bo *save_restore_obj;
		997	uint64_t save_restore_gpu_addr;
5078	serge	998	volatile uint32_t *sr_ptr;
		999	const u32 *reg_list;
		1000	u32 reg_list_size;
2997	Serge	1001	/* for clear state */
		1002	struct radeon_bo *clear_state_obj;
		1003	uint64_t clear_state_gpu_addr;
5078	serge	1004	volatile uint32_t *cs_ptr;
		1005	const struct cs_section_def *cs_data;
		1006	u32 clear_state_size;
		1007	/* for cp tables */
		1008	struct radeon_bo *cp_table_obj;
		1009	uint64_t cp_table_gpu_addr;
		1010	volatile uint32_t *cp_table_ptr;
		1011	u32 cp_table_size;
2997	Serge	1012	};
		1013
		1014	int radeon_ib_get(struct radeon_device *rdev, int ring,
		1015	struct radeon_ib ib, struct radeon_vm vm,
		1016	unsigned size);
		1017	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib);
		1018	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
5078	serge	1019	struct radeon_ib *const_ib, bool hdp_flush);
1117	serge	1020	int radeon_ib_pool_init(struct radeon_device *rdev);
		1021	void radeon_ib_pool_fini(struct radeon_device *rdev);
2997	Serge	1022	int radeon_ib_ring_tests(struct radeon_device *rdev);
1117	serge	1023	/* Ring access between begin & end cannot sleep */
2997	Serge	1024	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
		1025	struct radeon_ring *ring);
		1026	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring cp);
		1027	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		1028	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
5078	serge	1029	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring cp,
		1030	bool hdp_flush);
		1031	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring cp,
		1032	bool hdp_flush);
2997	Serge	1033	void radeon_ring_undo(struct radeon_ring *ring);
		1034	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring cp);
		1035	int radeon_ring_test(struct radeon_device rdev, struct radeon_ring cp);
5078	serge	1036	void radeon_ring_lockup_update(struct radeon_device *rdev,
		1037	struct radeon_ring *ring);
2997	Serge	1038	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring);
		1039	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
		1040	uint32_t **data);
		1041	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
		1042	unsigned size, uint32_t *data);
		1043	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring cp, unsigned ring_size,
5078	serge	1044	unsigned rptr_offs, u32 nop);
2997	Serge	1045	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring cp);
1117	serge	1046
		1047
3192	Serge	1048	/* r600 async dma */
		1049	void r600_dma_stop(struct radeon_device *rdev);
		1050	int r600_dma_resume(struct radeon_device *rdev);
		1051	void r600_dma_fini(struct radeon_device *rdev);
		1052
		1053	void cayman_dma_stop(struct radeon_device *rdev);
		1054	int cayman_dma_resume(struct radeon_device *rdev);
		1055	void cayman_dma_fini(struct radeon_device *rdev);
		1056
1117	serge	1057	/*
		1058	* CS.
		1059	*/
		1060	struct radeon_cs_chunk {
		1061	uint32_t length_dw;
		1062	uint32_t *kdata;
6104	serge	1063	void __user *user_ptr;
1117	serge	1064	};
		1065
		1066	struct radeon_cs_parser {
1430	serge	1067	struct device *dev;
1117	serge	1068	struct radeon_device *rdev;
2004	serge	1069	struct drm_file *filp;
1117	serge	1070	/* chunks */
		1071	unsigned nchunks;
		1072	struct radeon_cs_chunk *chunks;
		1073	uint64_t *chunks_array;
		1074	/* IB */
		1075	unsigned idx;
		1076	/* relocations */
		1077	unsigned nrelocs;
5271	serge	1078	struct radeon_bo_list *relocs;
		1079	struct radeon_bo_list *vm_bos;
1120	serge	1080	struct list_head validated;
3192	Serge	1081	unsigned dma_reloc_idx;
1117	serge	1082	/* indices of various chunks */
5271	serge	1083	struct radeon_cs_chunk *chunk_ib;
		1084	struct radeon_cs_chunk *chunk_relocs;
		1085	struct radeon_cs_chunk *chunk_flags;
		1086	struct radeon_cs_chunk *chunk_const_ib;
2997	Serge	1087	struct radeon_ib ib;
		1088	struct radeon_ib const_ib;
1117	serge	1089	void *track;
1179	serge	1090	unsigned family;
6104	serge	1091	int parser_error;
2997	Serge	1092	u32 cs_flags;
		1093	u32 ring;
		1094	s32 priority;
5078	serge	1095	struct ww_acquire_ctx ticket;
1117	serge	1096	};
		1097
5078	serge	1098	static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
		1099	{
5271	serge	1100	struct radeon_cs_chunk *ibc = p->chunk_ib;
1221	serge	1101
5078	serge	1102	if (ibc->kdata)
		1103	return ibc->kdata[idx];
		1104	return p->ib.ptr[idx];
		1105	}
		1106
		1107
1117	serge	1108	struct radeon_cs_packet {
		1109	unsigned idx;
		1110	unsigned type;
		1111	unsigned reg;
		1112	unsigned opcode;
		1113	int count;
		1114	unsigned one_reg_wr;
		1115	};
		1116
		1117	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		1118	struct radeon_cs_packet *pkt,
		1119	unsigned idx, unsigned reg);
		1120	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		1121	struct radeon_cs_packet *pkt);
		1122
		1123
		1124	/*
		1125	* AGP
		1126	*/
		1127	int radeon_agp_init(struct radeon_device *rdev);
1321	serge	1128	void radeon_agp_resume(struct radeon_device *rdev);
1963	serge	1129	void radeon_agp_suspend(struct radeon_device *rdev);
1117	serge	1130	void radeon_agp_fini(struct radeon_device *rdev);
		1131
		1132
		1133	/*
		1134	* Writeback
		1135	*/
		1136	struct radeon_wb {
1321	serge	1137	struct radeon_bo *wb_obj;
1117	serge	1138	volatile uint32_t *wb;
		1139	uint64_t gpu_addr;
1963	serge	1140	bool enabled;
		1141	bool use_event;
1117	serge	1142	};
		1143
1963	serge	1144	#define RADEON_WB_SCRATCH_OFFSET 0
2997	Serge	1145	#define RADEON_WB_RING0_NEXT_RPTR 256
1963	serge	1146	#define RADEON_WB_CP_RPTR_OFFSET 1024
		1147	#define RADEON_WB_CP1_RPTR_OFFSET 1280
		1148	#define RADEON_WB_CP2_RPTR_OFFSET 1536
3192	Serge	1149	#define R600_WB_DMA_RPTR_OFFSET 1792
1963	serge	1150	#define R600_WB_IH_WPTR_OFFSET 2048
3192	Serge	1151	#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1963	serge	1152	#define R600_WB_EVENT_OFFSET 3072
5078	serge	1153	#define CIK_WB_CP1_WPTR_OFFSET 3328
		1154	#define CIK_WB_CP2_WPTR_OFFSET 3584
5179	serge	1155	#define R600_WB_DMA_RING_TEST_OFFSET 3588
		1156	#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1963	serge	1157
1179	serge	1158	/**
		1159	* struct radeon_pm - power management datas
		1160	* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
		1161	* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
		1162	* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
		1163	* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
		1164	* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
		1165	* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
		1166	* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
		1167	* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
		1168	* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1963	serge	1169	* @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1179	serge	1170	* @needed_bandwidth: current bandwidth needs
		1171	*
		1172	* It keeps track of various data needed to take powermanagement decision.
1963	serge	1173	* Bandwidth need is used to determine minimun clock of the GPU and memory.
1179	serge	1174	* Equation between gpu/memory clock and available bandwidth is hw dependent
		1175	* (type of memory, bus size, efficiency, ...)
		1176	*/
1963	serge	1177
		1178	enum radeon_pm_method {
		1179	PM_METHOD_PROFILE,
		1180	PM_METHOD_DYNPM,
5078	serge	1181	PM_METHOD_DPM,
1430	serge	1182	};
1963	serge	1183
		1184	enum radeon_dynpm_state {
		1185	DYNPM_STATE_DISABLED,
		1186	DYNPM_STATE_MINIMUM,
		1187	DYNPM_STATE_PAUSED,
		1188	DYNPM_STATE_ACTIVE,
		1189	DYNPM_STATE_SUSPENDED,
1430	serge	1190	};
1963	serge	1191	enum radeon_dynpm_action {
		1192	DYNPM_ACTION_NONE,
		1193	DYNPM_ACTION_MINIMUM,
		1194	DYNPM_ACTION_DOWNCLOCK,
		1195	DYNPM_ACTION_UPCLOCK,
		1196	DYNPM_ACTION_DEFAULT
		1197	};
1430	serge	1198
		1199	enum radeon_voltage_type {
		1200	VOLTAGE_NONE = 0,
		1201	VOLTAGE_GPIO,
		1202	VOLTAGE_VDDC,
		1203	VOLTAGE_SW
		1204	};
		1205
		1206	enum radeon_pm_state_type {
5078	serge	1207	/* not used for dpm */
1430	serge	1208	POWER_STATE_TYPE_DEFAULT,
		1209	POWER_STATE_TYPE_POWERSAVE,
5078	serge	1210	/* user selectable states */
1430	serge	1211	POWER_STATE_TYPE_BATTERY,
		1212	POWER_STATE_TYPE_BALANCED,
		1213	POWER_STATE_TYPE_PERFORMANCE,
5078	serge	1214	/* internal states */
		1215	POWER_STATE_TYPE_INTERNAL_UVD,
		1216	POWER_STATE_TYPE_INTERNAL_UVD_SD,
		1217	POWER_STATE_TYPE_INTERNAL_UVD_HD,
		1218	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
		1219	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
		1220	POWER_STATE_TYPE_INTERNAL_BOOT,
		1221	POWER_STATE_TYPE_INTERNAL_THERMAL,
		1222	POWER_STATE_TYPE_INTERNAL_ACPI,
		1223	POWER_STATE_TYPE_INTERNAL_ULV,
		1224	POWER_STATE_TYPE_INTERNAL_3DPERF,
1430	serge	1225	};
		1226
1963	serge	1227	enum radeon_pm_profile_type {
		1228	PM_PROFILE_DEFAULT,
		1229	PM_PROFILE_AUTO,
		1230	PM_PROFILE_LOW,
		1231	PM_PROFILE_MID,
		1232	PM_PROFILE_HIGH,
1430	serge	1233	};
		1234
1963	serge	1235	#define PM_PROFILE_DEFAULT_IDX 0
		1236	#define PM_PROFILE_LOW_SH_IDX 1
		1237	#define PM_PROFILE_MID_SH_IDX 2
		1238	#define PM_PROFILE_HIGH_SH_IDX 3
		1239	#define PM_PROFILE_LOW_MH_IDX 4
		1240	#define PM_PROFILE_MID_MH_IDX 5
		1241	#define PM_PROFILE_HIGH_MH_IDX 6
		1242	#define PM_PROFILE_MAX 7
		1243
		1244	struct radeon_pm_profile {
		1245	int dpms_off_ps_idx;
		1246	int dpms_on_ps_idx;
		1247	int dpms_off_cm_idx;
		1248	int dpms_on_cm_idx;
		1249	};
		1250
		1251	enum radeon_int_thermal_type {
		1252	THERMAL_TYPE_NONE,
5078	serge	1253	THERMAL_TYPE_EXTERNAL,
		1254	THERMAL_TYPE_EXTERNAL_GPIO,
1963	serge	1255	THERMAL_TYPE_RV6XX,
		1256	THERMAL_TYPE_RV770,
5078	serge	1257	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1963	serge	1258	THERMAL_TYPE_EVERGREEN,
		1259	THERMAL_TYPE_SUMO,
		1260	THERMAL_TYPE_NI,
2997	Serge	1261	THERMAL_TYPE_SI,
5078	serge	1262	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
		1263	THERMAL_TYPE_CI,
		1264	THERMAL_TYPE_KV,
1963	serge	1265	};
		1266
1430	serge	1267	struct radeon_voltage {
		1268	enum radeon_voltage_type type;
		1269	/* gpio voltage */
		1270	struct radeon_gpio_rec gpio;
		1271	u32 delay; /* delay in usec from voltage drop to sclk change */
		1272	bool active_high; /* voltage drop is active when bit is high */
		1273	/* VDDC voltage */
		1274	u8 vddc_id; /* index into vddc voltage table */
		1275	u8 vddci_id; /* index into vddci voltage table */
		1276	bool vddci_enabled;
		1277	/* r6xx+ sw */
1963	serge	1278	u16 voltage;
		1279	/* evergreen+ vddci */
		1280	u16 vddci;
1430	serge	1281	};
		1282
1963	serge	1283	/* clock mode flags */
		1284	#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1430	serge	1285
		1286	struct radeon_pm_clock_info {
		1287	/* memory clock */
		1288	u32 mclk;
		1289	/* engine clock */
		1290	u32 sclk;
		1291	/* voltage info */
		1292	struct radeon_voltage voltage;
1963	serge	1293	/* standardized clock flags */
1430	serge	1294	u32 flags;
		1295	};
		1296
1963	serge	1297	/* state flags */
		1298	#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
		1299
1430	serge	1300	struct radeon_power_state {
		1301	enum radeon_pm_state_type type;
2997	Serge	1302	struct radeon_pm_clock_info *clock_info;
1430	serge	1303	/* number of valid clock modes in this power state */
		1304	int num_clock_modes;
		1305	struct radeon_pm_clock_info *default_clock_mode;
1963	serge	1306	/* standardized state flags */
		1307	u32 flags;
		1308	u32 misc; /* vbios specific flags */
		1309	u32 misc2; /* vbios specific flags */
		1310	int pcie_lanes; /* pcie lanes */
1430	serge	1311	};
		1312
		1313	/*
		1314	* Some modes are overclocked by very low value, accept them
		1315	*/
		1316	#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
		1317
5078	serge	1318	enum radeon_dpm_auto_throttle_src {
		1319	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
		1320	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
		1321	};
		1322
		1323	enum radeon_dpm_event_src {
		1324	RADEON_DPM_EVENT_SRC_ANALOG = 0,
		1325	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
		1326	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
		1327	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
		1328	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		1329	};
		1330
		1331	#define RADEON_MAX_VCE_LEVELS 6
		1332
		1333	enum radeon_vce_level {
		1334	RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
		1335	RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
		1336	RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
		1337	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
		1338	RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
		1339	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
		1340	};
		1341
		1342	struct radeon_ps {
		1343	u32 caps; /* vbios flags */
		1344	u32 class; /* vbios flags */
		1345	u32 class2; /* vbios flags */
		1346	/* UVD clocks */
		1347	u32 vclk;
		1348	u32 dclk;
		1349	/* VCE clocks */
		1350	u32 evclk;
		1351	u32 ecclk;
		1352	bool vce_active;
		1353	enum radeon_vce_level vce_level;
		1354	/* asic priv */
		1355	void *ps_priv;
		1356	};
		1357
		1358	struct radeon_dpm_thermal {
		1359	/* thermal interrupt work */
		1360	struct work_struct work;
		1361	/* low temperature threshold */
		1362	int min_temp;
		1363	/* high temperature threshold */
		1364	int max_temp;
		1365	/* was interrupt low to high or high to low */
		1366	bool high_to_low;
		1367	};
		1368
		1369	enum radeon_clk_action
		1370	{
		1371	RADEON_SCLK_UP = 1,
		1372	RADEON_SCLK_DOWN
		1373	};
		1374
		1375	struct radeon_blacklist_clocks
		1376	{
		1377	u32 sclk;
		1378	u32 mclk;
		1379	enum radeon_clk_action action;
		1380	};
		1381
		1382	struct radeon_clock_and_voltage_limits {
		1383	u32 sclk;
		1384	u32 mclk;
		1385	u16 vddc;
		1386	u16 vddci;
		1387	};
		1388
		1389	struct radeon_clock_array {
		1390	u32 count;
		1391	u32 *values;
		1392	};
		1393
		1394	struct radeon_clock_voltage_dependency_entry {
		1395	u32 clk;
		1396	u16 v;
		1397	};
		1398
		1399	struct radeon_clock_voltage_dependency_table {
		1400	u32 count;
		1401	struct radeon_clock_voltage_dependency_entry *entries;
		1402	};
		1403
		1404	union radeon_cac_leakage_entry {
		1405	struct {
		1406	u16 vddc;
		1407	u32 leakage;
		1408	};
		1409	struct {
		1410	u16 vddc1;
		1411	u16 vddc2;
		1412	u16 vddc3;
		1413	};
		1414	};
		1415
		1416	struct radeon_cac_leakage_table {
		1417	u32 count;
		1418	union radeon_cac_leakage_entry *entries;
		1419	};
		1420
		1421	struct radeon_phase_shedding_limits_entry {
		1422	u16 voltage;
		1423	u32 sclk;
		1424	u32 mclk;
		1425	};
		1426
		1427	struct radeon_phase_shedding_limits_table {
		1428	u32 count;
		1429	struct radeon_phase_shedding_limits_entry *entries;
		1430	};
		1431
		1432	struct radeon_uvd_clock_voltage_dependency_entry {
		1433	u32 vclk;
		1434	u32 dclk;
		1435	u16 v;
		1436	};
		1437
		1438	struct radeon_uvd_clock_voltage_dependency_table {
		1439	u8 count;
		1440	struct radeon_uvd_clock_voltage_dependency_entry *entries;
		1441	};
		1442
		1443	struct radeon_vce_clock_voltage_dependency_entry {
		1444	u32 ecclk;
		1445	u32 evclk;
		1446	u16 v;
		1447	};
		1448
		1449	struct radeon_vce_clock_voltage_dependency_table {
		1450	u8 count;
		1451	struct radeon_vce_clock_voltage_dependency_entry *entries;
		1452	};
		1453
		1454	struct radeon_ppm_table {
		1455	u8 ppm_design;
		1456	u16 cpu_core_number;
		1457	u32 platform_tdp;
		1458	u32 small_ac_platform_tdp;
		1459	u32 platform_tdc;
		1460	u32 small_ac_platform_tdc;
		1461	u32 apu_tdp;
		1462	u32 dgpu_tdp;
		1463	u32 dgpu_ulv_power;
		1464	u32 tj_max;
		1465	};
		1466
		1467	struct radeon_cac_tdp_table {
		1468	u16 tdp;
		1469	u16 configurable_tdp;
		1470	u16 tdc;
		1471	u16 battery_power_limit;
		1472	u16 small_power_limit;
		1473	u16 low_cac_leakage;
		1474	u16 high_cac_leakage;
		1475	u16 maximum_power_delivery_limit;
		1476	};
		1477
		1478	struct radeon_dpm_dynamic_state {
		1479	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
		1480	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
		1481	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
		1482	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
		1483	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
		1484	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
		1485	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
		1486	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
		1487	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
		1488	struct radeon_clock_array valid_sclk_values;
		1489	struct radeon_clock_array valid_mclk_values;
		1490	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
		1491	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
		1492	u32 mclk_sclk_ratio;
		1493	u32 sclk_mclk_delta;
		1494	u16 vddc_vddci_delta;
		1495	u16 min_vddc_for_pcie_gen2;
		1496	struct radeon_cac_leakage_table cac_leakage_table;
		1497	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
		1498	struct radeon_ppm_table *ppm_table;
		1499	struct radeon_cac_tdp_table *cac_tdp_table;
		1500	};
		1501
		1502	struct radeon_dpm_fan {
		1503	u16 t_min;
		1504	u16 t_med;
		1505	u16 t_high;
		1506	u16 pwm_min;
		1507	u16 pwm_med;
		1508	u16 pwm_high;
		1509	u8 t_hyst;
		1510	u32 cycle_delay;
		1511	u16 t_max;
5271	serge	1512	u8 control_mode;
		1513	u16 default_max_fan_pwm;
		1514	u16 default_fan_output_sensitivity;
		1515	u16 fan_output_sensitivity;
5078	serge	1516	bool ucode_fan_control;
		1517	};
		1518
		1519	enum radeon_pcie_gen {
		1520	RADEON_PCIE_GEN1 = 0,
		1521	RADEON_PCIE_GEN2 = 1,
		1522	RADEON_PCIE_GEN3 = 2,
		1523	RADEON_PCIE_GEN_INVALID = 0xffff
		1524	};
		1525
		1526	enum radeon_dpm_forced_level {
		1527	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
		1528	RADEON_DPM_FORCED_LEVEL_LOW = 1,
		1529	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
		1530	};
		1531
		1532	struct radeon_vce_state {
		1533	/* vce clocks */
		1534	u32 evclk;
		1535	u32 ecclk;
		1536	/* gpu clocks */
		1537	u32 sclk;
		1538	u32 mclk;
		1539	u8 clk_idx;
		1540	u8 pstate;
		1541	};
		1542
		1543	struct radeon_dpm {
		1544	struct radeon_ps *ps;
		1545	/* number of valid power states */
		1546	int num_ps;
		1547	/* current power state that is active */
		1548	struct radeon_ps *current_ps;
		1549	/* requested power state */
		1550	struct radeon_ps *requested_ps;
		1551	/* boot up power state */
		1552	struct radeon_ps *boot_ps;
		1553	/* default uvd power state */
		1554	struct radeon_ps *uvd_ps;
		1555	/* vce requirements */
		1556	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
		1557	enum radeon_vce_level vce_level;
		1558	enum radeon_pm_state_type state;
		1559	enum radeon_pm_state_type user_state;
		1560	u32 platform_caps;
		1561	u32 voltage_response_time;
		1562	u32 backbias_response_time;
		1563	void *priv;
		1564	u32 new_active_crtcs;
		1565	int new_active_crtc_count;
		1566	u32 current_active_crtcs;
		1567	int current_active_crtc_count;
6104	serge	1568	bool single_display;
5078	serge	1569	struct radeon_dpm_dynamic_state dyn_state;
		1570	struct radeon_dpm_fan fan;
		1571	u32 tdp_limit;
		1572	u32 near_tdp_limit;
		1573	u32 near_tdp_limit_adjusted;
		1574	u32 sq_ramping_threshold;
		1575	u32 cac_leakage;
		1576	u16 tdp_od_limit;
		1577	u32 tdp_adjustment;
		1578	u16 load_line_slope;
		1579	bool power_control;
		1580	bool ac_power;
		1581	/* special states active */
		1582	bool thermal_active;
		1583	bool uvd_active;
		1584	bool vce_active;
		1585	/* thermal handling */
		1586	struct radeon_dpm_thermal thermal;
		1587	/* forced levels */
		1588	enum radeon_dpm_forced_level forced_level;
		1589	/* track UVD streams */
		1590	unsigned sd;
		1591	unsigned hd;
		1592	};
		1593
		1594	void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
		1595	void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
		1596
1179	serge	1597	struct radeon_pm {
1630	serge	1598	struct mutex mutex;
2997	Serge	1599	/* write locked while reprogramming mclk */
		1600	struct rw_semaphore mclk_lock;
1963	serge	1601	u32 active_crtcs;
		1602	int active_crtc_count;
1430	serge	1603	int req_vblank;
1963	serge	1604	bool vblank_sync;
1179	serge	1605	fixed20_12 max_bandwidth;
		1606	fixed20_12 igp_sideport_mclk;
		1607	fixed20_12 igp_system_mclk;
		1608	fixed20_12 igp_ht_link_clk;
		1609	fixed20_12 igp_ht_link_width;
		1610	fixed20_12 k8_bandwidth;
		1611	fixed20_12 sideport_bandwidth;
		1612	fixed20_12 ht_bandwidth;
		1613	fixed20_12 core_bandwidth;
		1614	fixed20_12 sclk;
1963	serge	1615	fixed20_12 mclk;
1179	serge	1616	fixed20_12 needed_bandwidth;
1963	serge	1617	struct radeon_power_state *power_state;
1430	serge	1618	/* number of valid power states */
		1619	int num_power_states;
1963	serge	1620	int current_power_state_index;
		1621	int current_clock_mode_index;
		1622	int requested_power_state_index;
		1623	int requested_clock_mode_index;
		1624	int default_power_state_index;
		1625	u32 current_sclk;
		1626	u32 current_mclk;
		1627	u16 current_vddc;
		1628	u16 current_vddci;
		1629	u32 default_sclk;
		1630	u32 default_mclk;
		1631	u16 default_vddc;
		1632	u16 default_vddci;
		1633	struct radeon_i2c_chan *i2c_bus;
		1634	/* selected pm method */
		1635	enum radeon_pm_method pm_method;
		1636	/* dynpm power management */
5078	serge	1637	struct delayed_work dynpm_idle_work;
1963	serge	1638	enum radeon_dynpm_state dynpm_state;
		1639	enum radeon_dynpm_action dynpm_planned_action;
		1640	unsigned long dynpm_action_timeout;
		1641	bool dynpm_can_upclock;
		1642	bool dynpm_can_downclock;
		1643	/* profile-based power management */
		1644	enum radeon_pm_profile_type profile;
		1645	int profile_index;
		1646	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
		1647	/* internal thermal controller on rv6xx+ */
		1648	enum radeon_int_thermal_type int_thermal_type;
		1649	struct device *int_hwmon_dev;
5271	serge	1650	/* fan control parameters */
		1651	bool no_fan;
		1652	u8 fan_pulses_per_revolution;
		1653	u8 fan_min_rpm;
		1654	u8 fan_max_rpm;
5078	serge	1655	/* dpm */
		1656	bool dpm_enabled;
6104	serge	1657	bool sysfs_initialized;
5078	serge	1658	struct radeon_dpm dpm;
1179	serge	1659	};
1117	serge	1660
2997	Serge	1661	int radeon_pm_get_type_index(struct radeon_device *rdev,
		1662	enum radeon_pm_state_type ps_type,
		1663	int instance);
3764	Serge	1664	/*
		1665	* UVD
		1666	*/
		1667	#define RADEON_MAX_UVD_HANDLES 10
		1668	#define RADEON_UVD_STACK_SIZE (1024*1024)
		1669	#define RADEON_UVD_HEAP_SIZE (1024*1024)
2997	Serge	1670
3764	Serge	1671	struct radeon_uvd {
		1672	struct radeon_bo *vcpu_bo;
		1673	void *cpu_addr;
		1674	uint64_t gpu_addr;
		1675	atomic_t handles[RADEON_MAX_UVD_HANDLES];
		1676	struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
5078	serge	1677	unsigned img_size[RADEON_MAX_UVD_HANDLES];
3764	Serge	1678	struct delayed_work idle_work;
		1679	};
		1680
		1681	int radeon_uvd_init(struct radeon_device *rdev);
		1682	void radeon_uvd_fini(struct radeon_device *rdev);
		1683	int radeon_uvd_suspend(struct radeon_device *rdev);
		1684	int radeon_uvd_resume(struct radeon_device *rdev);
		1685	int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
		1686	uint32_t handle, struct radeon_fence **fence);
		1687	int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
		1688	uint32_t handle, struct radeon_fence **fence);
5271	serge	1689	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
		1690	uint32_t allowed_domains);
3764	Serge	1691	void radeon_uvd_free_handles(struct radeon_device *rdev,
		1692	struct drm_file *filp);
		1693	int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
		1694	void radeon_uvd_note_usage(struct radeon_device *rdev);
		1695	int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
		1696	unsigned vclk, unsigned dclk,
		1697	unsigned vco_min, unsigned vco_max,
		1698	unsigned fb_factor, unsigned fb_mask,
		1699	unsigned pd_min, unsigned pd_max,
		1700	unsigned pd_even,
		1701	unsigned *optimal_fb_div,
		1702	unsigned *optimal_vclk_div,
		1703	unsigned *optimal_dclk_div);
		1704	int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
		1705	unsigned cg_upll_func_cntl);
		1706
5078	serge	1707	/*
		1708	* VCE
		1709	*/
		1710	#define RADEON_MAX_VCE_HANDLES 16
		1711
		1712	struct radeon_vce {
		1713	struct radeon_bo *vcpu_bo;
		1714	uint64_t gpu_addr;
		1715	unsigned fw_version;
		1716	unsigned fb_version;
		1717	atomic_t handles[RADEON_MAX_VCE_HANDLES];
		1718	struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
		1719	unsigned img_size[RADEON_MAX_VCE_HANDLES];
		1720	struct delayed_work idle_work;
6104	serge	1721	uint32_t keyselect;
5078	serge	1722	};
		1723
		1724	int radeon_vce_init(struct radeon_device *rdev);
		1725	void radeon_vce_fini(struct radeon_device *rdev);
		1726	int radeon_vce_suspend(struct radeon_device *rdev);
		1727	int radeon_vce_resume(struct radeon_device *rdev);
		1728	int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
		1729	uint32_t handle, struct radeon_fence **fence);
		1730	int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
		1731	uint32_t handle, struct radeon_fence **fence);
		1732	void radeon_vce_free_handles(struct radeon_device rdev, struct drm_file filp);
		1733	void radeon_vce_note_usage(struct radeon_device *rdev);
		1734	int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
		1735	int radeon_vce_cs_parse(struct radeon_cs_parser *p);
		1736	bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
		1737	struct radeon_ring *ring,
		1738	struct radeon_semaphore *semaphore,
		1739	bool emit_wait);
		1740	void radeon_vce_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
		1741	void radeon_vce_fence_emit(struct radeon_device *rdev,
		1742	struct radeon_fence *fence);
		1743	int radeon_vce_ring_test(struct radeon_device rdev, struct radeon_ring ring);
		1744	int radeon_vce_ib_test(struct radeon_device rdev, struct radeon_ring ring);
		1745
		1746	struct r600_audio_pin {
2997	Serge	1747	int channels;
		1748	int rate;
		1749	int bits_per_sample;
		1750	u8 status_bits;
		1751	u8 category_code;
5078	serge	1752	u32 offset;
		1753	bool connected;
		1754	u32 id;
2997	Serge	1755	};
5078	serge	1756
		1757	struct r600_audio {
		1758	bool enabled;
		1759	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
		1760	int num_pins;
6104	serge	1761	struct radeon_audio_funcs *hdmi_funcs;
		1762	struct radeon_audio_funcs *dp_funcs;
		1763	struct radeon_audio_basic_funcs *funcs;
5078	serge	1764	};
		1765
1117	serge	1766	/*
5078	serge	1767	* Benchmarking
		1768	*/
		1769	void radeon_benchmark(struct radeon_device *rdev, int test_number);
		1770
		1771
		1772	/*
		1773	* Testing
		1774	*/
		1775	void radeon_test_moves(struct radeon_device *rdev);
		1776	void radeon_test_ring_sync(struct radeon_device *rdev,
		1777	struct radeon_ring *cpA,
		1778	struct radeon_ring *cpB);
		1779	void radeon_test_syncing(struct radeon_device *rdev);
		1780
5271	serge	1781	/*
		1782	* MMU Notifier
		1783	*/
6104	serge	1784	#if defined(CONFIG_MMU_NOTIFIER)
5271	serge	1785	int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
		1786	void radeon_mn_unregister(struct radeon_bo *bo);
6104	serge	1787	#else
		1788	static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
		1789	{
		1790	return -ENODEV;
		1791	}
		1792	static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
		1793	#endif
5078	serge	1794
		1795	/*
		1796	* Debugfs
		1797	*/
		1798	struct radeon_debugfs {
		1799	struct drm_info_list *files;
		1800	unsigned num_files;
		1801	};
		1802
		1803	int radeon_debugfs_add_files(struct radeon_device *rdev,
		1804	struct drm_info_list *files,
		1805	unsigned nfiles);
		1806	int radeon_debugfs_fence_init(struct radeon_device *rdev);
		1807
		1808	/*
		1809	* ASIC ring specific functions.
		1810	*/
		1811	struct radeon_asic_ring {
		1812	/* ring read/write ptr handling */
		1813	u32 (get_rptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1814	u32 (get_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1815	void (set_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1816
		1817	/* validating and patching of IBs */
		1818	int (ib_parse)(struct radeon_device rdev, struct radeon_ib *ib);
		1819	int (cs_parse)(struct radeon_cs_parser p);
		1820
		1821	/* command emmit functions */
		1822	void (ib_execute)(struct radeon_device rdev, struct radeon_ib *ib);
		1823	void (emit_fence)(struct radeon_device rdev, struct radeon_fence *fence);
		1824	void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);
		1825	bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,
		1826	struct radeon_semaphore *semaphore, bool emit_wait);
5271	serge	1827	void (vm_flush)(struct radeon_device rdev, struct radeon_ring *ring,
		1828	unsigned vm_id, uint64_t pd_addr);
5078	serge	1829
		1830	/* testing functions */
		1831	int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1832	int (ib_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1833	bool (is_lockup)(struct radeon_device rdev, struct radeon_ring *cp);
		1834
		1835	/* deprecated */
		1836	void (ring_start)(struct radeon_device rdev, struct radeon_ring *cp);
		1837	};
		1838
		1839	/*
1117	serge	1840	* ASIC specific functions.
		1841	*/
		1842	struct radeon_asic {
		1843	int (init)(struct radeon_device rdev);
1179	serge	1844	void (fini)(struct radeon_device rdev);
		1845	int (resume)(struct radeon_device rdev);
		1846	int (suspend)(struct radeon_device rdev);
		1847	void (vga_set_state)(struct radeon_device rdev, bool state);
1963	serge	1848	int (asic_reset)(struct radeon_device rdev);
5078	serge	1849	/* Flush the HDP cache via MMIO */
		1850	void (mmio_hdp_flush)(struct radeon_device rdev);
2997	Serge	1851	/* check if 3D engine is idle */
		1852	bool (gui_idle)(struct radeon_device rdev);
		1853	/* wait for mc_idle */
		1854	int (mc_wait_for_idle)(struct radeon_device rdev);
3764	Serge	1855	/* get the reference clock */
		1856	u32 (get_xclk)(struct radeon_device rdev);
		1857	/* get the gpu clock counter */
		1858	uint64_t (get_gpu_clock_counter)(struct radeon_device rdev);
6104	serge	1859	/* get register for info ioctl */
		1860	int (get_allowed_info_register)(struct radeon_device rdev, u32 reg, u32 *val);
2997	Serge	1861	/* gart */
		1862	struct {
		1863	void (tlb_flush)(struct radeon_device rdev);
6104	serge	1864	uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
5078	serge	1865	void (set_page)(struct radeon_device rdev, unsigned i,
6104	serge	1866	uint64_t entry);
2997	Serge	1867	} gart;
		1868	struct {
		1869	int (init)(struct radeon_device rdev);
		1870	void (fini)(struct radeon_device rdev);
5078	serge	1871	void (copy_pages)(struct radeon_device rdev,
		1872	struct radeon_ib *ib,
		1873	uint64_t pe, uint64_t src,
		1874	unsigned count);
		1875	void (write_pages)(struct radeon_device rdev,
		1876	struct radeon_ib *ib,
		1877	uint64_t pe,
		1878	uint64_t addr, unsigned count,
		1879	uint32_t incr, uint32_t flags);
		1880	void (set_pages)(struct radeon_device rdev,
6104	serge	1881	struct radeon_ib *ib,
		1882	uint64_t pe,
		1883	uint64_t addr, unsigned count,
		1884	uint32_t incr, uint32_t flags);
5078	serge	1885	void (pad_ib)(struct radeon_ib ib);
2997	Serge	1886	} vm;
		1887	/* ring specific callbacks */
6938	serge	1888	const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
2997	Serge	1889	/* irqs */
		1890	struct {
		1891	int (set)(struct radeon_device rdev);
		1892	int (process)(struct radeon_device rdev);
		1893	} irq;
		1894	/* displays */
		1895	struct {
		1896	/* display watermarks */
		1897	void (bandwidth_update)(struct radeon_device rdev);
		1898	/* get frame count */
6104	serge	1899	u32 (get_vblank_counter)(struct radeon_device rdev, int crtc);
2997	Serge	1900	/* wait for vblank */
		1901	void (wait_for_vblank)(struct radeon_device rdev, int crtc);
		1902	/* set backlight level */
		1903	void (set_backlight_level)(struct radeon_encoder radeon_encoder, u8 level);
		1904	/* get backlight level */
		1905	u8 (get_backlight_level)(struct radeon_encoder radeon_encoder);
3764	Serge	1906	/* audio callbacks */
		1907	void (hdmi_enable)(struct drm_encoder encoder, bool enable);
		1908	void (hdmi_setmode)(struct drm_encoder encoder, struct drm_display_mode *mode);
2997	Serge	1909	} display;
		1910	/* copy functions for bo handling */
		1911	struct {
5271	serge	1912	struct radeon_fence (blit)(struct radeon_device *rdev,
6104	serge	1913	uint64_t src_offset,
		1914	uint64_t dst_offset,
		1915	unsigned num_gpu_pages,
5271	serge	1916	struct reservation_object *resv);
2997	Serge	1917	u32 blit_ring_index;
5271	serge	1918	struct radeon_fence (dma)(struct radeon_device *rdev,
6104	serge	1919	uint64_t src_offset,
		1920	uint64_t dst_offset,
		1921	unsigned num_gpu_pages,
5271	serge	1922	struct reservation_object *resv);
2997	Serge	1923	u32 dma_ring_index;
		1924	/* method used for bo copy */
5271	serge	1925	struct radeon_fence (copy)(struct radeon_device *rdev,
6104	serge	1926	uint64_t src_offset,
		1927	uint64_t dst_offset,
		1928	unsigned num_gpu_pages,
5271	serge	1929	struct reservation_object *resv);
2997	Serge	1930	/* ring used for bo copies */
		1931	u32 copy_ring_index;
		1932	} copy;
		1933	/* surfaces */
		1934	struct {
		1935	int (set_reg)(struct radeon_device rdev, int reg,
		1936	uint32_t tiling_flags, uint32_t pitch,
		1937	uint32_t offset, uint32_t obj_size);
		1938	void (clear_reg)(struct radeon_device rdev, int reg);
		1939	} surface;
		1940	/* hotplug detect */
		1941	struct {
		1942	void (init)(struct radeon_device rdev);
		1943	void (fini)(struct radeon_device rdev);
		1944	bool (sense)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1945	void (set_polarity)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1946	} hpd;
5078	serge	1947	/* static power management */
2997	Serge	1948	struct {
		1949	void (misc)(struct radeon_device rdev);
		1950	void (prepare)(struct radeon_device rdev);
		1951	void (finish)(struct radeon_device rdev);
		1952	void (init_profile)(struct radeon_device rdev);
		1953	void (get_dynpm_state)(struct radeon_device rdev);
6104	serge	1954	uint32_t (get_engine_clock)(struct radeon_device rdev);
		1955	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
		1956	uint32_t (get_memory_clock)(struct radeon_device rdev);
		1957	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
		1958	int (get_pcie_lanes)(struct radeon_device rdev);
		1959	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		1960	void (set_clock_gating)(struct radeon_device rdev, int enable);
3764	Serge	1961	int (set_uvd_clocks)(struct radeon_device rdev, u32 vclk, u32 dclk);
5078	serge	1962	int (set_vce_clocks)(struct radeon_device rdev, u32 evclk, u32 ecclk);
		1963	int (get_temperature)(struct radeon_device rdev);
2997	Serge	1964	} pm;
5078	serge	1965	/* dynamic power management */
		1966	struct {
		1967	int (init)(struct radeon_device rdev);
		1968	void (setup_asic)(struct radeon_device rdev);
		1969	int (enable)(struct radeon_device rdev);
		1970	int (late_enable)(struct radeon_device rdev);
		1971	void (disable)(struct radeon_device rdev);
		1972	int (pre_set_power_state)(struct radeon_device rdev);
		1973	int (set_power_state)(struct radeon_device rdev);
		1974	void (post_set_power_state)(struct radeon_device rdev);
		1975	void (display_configuration_changed)(struct radeon_device rdev);
		1976	void (fini)(struct radeon_device rdev);
		1977	u32 (get_sclk)(struct radeon_device rdev, bool low);
		1978	u32 (get_mclk)(struct radeon_device rdev, bool low);
		1979	void (print_power_state)(struct radeon_device rdev, struct radeon_ps *ps);
		1980	void (debugfs_print_current_performance_level)(struct radeon_device rdev, struct seq_file *m);
		1981	int (force_performance_level)(struct radeon_device rdev, enum radeon_dpm_forced_level level);
		1982	bool (vblank_too_short)(struct radeon_device rdev);
		1983	void (powergate_uvd)(struct radeon_device rdev, bool gate);
		1984	void (enable_bapm)(struct radeon_device rdev, bool enable);
6104	serge	1985	void (fan_ctrl_set_mode)(struct radeon_device rdev, u32 mode);
		1986	u32 (fan_ctrl_get_mode)(struct radeon_device rdev);
		1987	int (set_fan_speed_percent)(struct radeon_device rdev, u32 speed);
		1988	int (get_fan_speed_percent)(struct radeon_device rdev, u32 *speed);
		1989	u32 (get_current_sclk)(struct radeon_device rdev);
		1990	u32 (get_current_mclk)(struct radeon_device rdev);
5078	serge	1991	} dpm;
1963	serge	1992	/* pageflipping */
2997	Serge	1993	struct {
5078	serge	1994	void (page_flip)(struct radeon_device rdev, int crtc, u64 crtc_base);
		1995	bool (page_flip_pending)(struct radeon_device rdev, int crtc);
2997	Serge	1996	} pflip;
1117	serge	1997	};
		1998
1179	serge	1999	/*
		2000	* Asic structures
		2001	*/
		2002	struct r100_asic {
6104	serge	2003	const unsigned *reg_safe_bm;
		2004	unsigned reg_safe_bm_size;
		2005	u32 hdp_cntl;
1179	serge	2006	};
		2007
		2008	struct r300_asic {
6104	serge	2009	const unsigned *reg_safe_bm;
		2010	unsigned reg_safe_bm_size;
		2011	u32 resync_scratch;
		2012	u32 hdp_cntl;
1179	serge	2013	};
		2014
		2015	struct r600_asic {
6104	serge	2016	unsigned max_pipes;
		2017	unsigned max_tile_pipes;
		2018	unsigned max_simds;
		2019	unsigned max_backends;
		2020	unsigned max_gprs;
		2021	unsigned max_threads;
		2022	unsigned max_stack_entries;
		2023	unsigned max_hw_contexts;
		2024	unsigned max_gs_threads;
		2025	unsigned sx_max_export_size;
		2026	unsigned sx_max_export_pos_size;
		2027	unsigned sx_max_export_smx_size;
		2028	unsigned sq_num_cf_insts;
		2029	unsigned tiling_nbanks;
		2030	unsigned tiling_npipes;
		2031	unsigned tiling_group_size;
1963	serge	2032	unsigned tile_config;
2160	serge	2033	unsigned backend_map;
5078	serge	2034	unsigned active_simds;
1179	serge	2035	};
		2036
		2037	struct rv770_asic {
6104	serge	2038	unsigned max_pipes;
		2039	unsigned max_tile_pipes;
		2040	unsigned max_simds;
		2041	unsigned max_backends;
		2042	unsigned max_gprs;
		2043	unsigned max_threads;
		2044	unsigned max_stack_entries;
		2045	unsigned max_hw_contexts;
		2046	unsigned max_gs_threads;
		2047	unsigned sx_max_export_size;
		2048	unsigned sx_max_export_pos_size;
		2049	unsigned sx_max_export_smx_size;
		2050	unsigned sq_num_cf_insts;
		2051	unsigned sx_num_of_sets;
		2052	unsigned sc_prim_fifo_size;
		2053	unsigned sc_hiz_tile_fifo_size;
		2054	unsigned sc_earlyz_tile_fifo_fize;
		2055	unsigned tiling_nbanks;
		2056	unsigned tiling_npipes;
		2057	unsigned tiling_group_size;
1963	serge	2058	unsigned tile_config;
2160	serge	2059	unsigned backend_map;
5078	serge	2060	unsigned active_simds;
1179	serge	2061	};
		2062
1963	serge	2063	struct evergreen_asic {
		2064	unsigned num_ses;
		2065	unsigned max_pipes;
		2066	unsigned max_tile_pipes;
		2067	unsigned max_simds;
		2068	unsigned max_backends;
		2069	unsigned max_gprs;
		2070	unsigned max_threads;
		2071	unsigned max_stack_entries;
		2072	unsigned max_hw_contexts;
		2073	unsigned max_gs_threads;
		2074	unsigned sx_max_export_size;
		2075	unsigned sx_max_export_pos_size;
		2076	unsigned sx_max_export_smx_size;
		2077	unsigned sq_num_cf_insts;
		2078	unsigned sx_num_of_sets;
		2079	unsigned sc_prim_fifo_size;
		2080	unsigned sc_hiz_tile_fifo_size;
		2081	unsigned sc_earlyz_tile_fifo_size;
		2082	unsigned tiling_nbanks;
		2083	unsigned tiling_npipes;
		2084	unsigned tiling_group_size;
		2085	unsigned tile_config;
2160	serge	2086	unsigned backend_map;
5078	serge	2087	unsigned active_simds;
1963	serge	2088	};
		2089
		2090	struct cayman_asic {
		2091	unsigned max_shader_engines;
		2092	unsigned max_pipes_per_simd;
		2093	unsigned max_tile_pipes;
		2094	unsigned max_simds_per_se;
		2095	unsigned max_backends_per_se;
		2096	unsigned max_texture_channel_caches;
		2097	unsigned max_gprs;
		2098	unsigned max_threads;
		2099	unsigned max_gs_threads;
		2100	unsigned max_stack_entries;
		2101	unsigned sx_num_of_sets;
		2102	unsigned sx_max_export_size;
		2103	unsigned sx_max_export_pos_size;
		2104	unsigned sx_max_export_smx_size;
		2105	unsigned max_hw_contexts;
		2106	unsigned sq_num_cf_insts;
		2107	unsigned sc_prim_fifo_size;
		2108	unsigned sc_hiz_tile_fifo_size;
		2109	unsigned sc_earlyz_tile_fifo_size;
		2110
		2111	unsigned num_shader_engines;
		2112	unsigned num_shader_pipes_per_simd;
		2113	unsigned num_tile_pipes;
		2114	unsigned num_simds_per_se;
		2115	unsigned num_backends_per_se;
		2116	unsigned backend_disable_mask_per_asic;
		2117	unsigned backend_map;
		2118	unsigned num_texture_channel_caches;
		2119	unsigned mem_max_burst_length_bytes;
		2120	unsigned mem_row_size_in_kb;
		2121	unsigned shader_engine_tile_size;
		2122	unsigned num_gpus;
		2123	unsigned multi_gpu_tile_size;
		2124
		2125	unsigned tile_config;
5078	serge	2126	unsigned active_simds;
1963	serge	2127	};
		2128
2997	Serge	2129	struct si_asic {
		2130	unsigned max_shader_engines;
		2131	unsigned max_tile_pipes;
		2132	unsigned max_cu_per_sh;
		2133	unsigned max_sh_per_se;
		2134	unsigned max_backends_per_se;
		2135	unsigned max_texture_channel_caches;
		2136	unsigned max_gprs;
		2137	unsigned max_gs_threads;
		2138	unsigned max_hw_contexts;
		2139	unsigned sc_prim_fifo_size_frontend;
		2140	unsigned sc_prim_fifo_size_backend;
		2141	unsigned sc_hiz_tile_fifo_size;
		2142	unsigned sc_earlyz_tile_fifo_size;
		2143
		2144	unsigned num_tile_pipes;
5078	serge	2145	unsigned backend_enable_mask;
2997	Serge	2146	unsigned backend_disable_mask_per_asic;
		2147	unsigned backend_map;
		2148	unsigned num_texture_channel_caches;
		2149	unsigned mem_max_burst_length_bytes;
		2150	unsigned mem_row_size_in_kb;
		2151	unsigned shader_engine_tile_size;
		2152	unsigned num_gpus;
		2153	unsigned multi_gpu_tile_size;
		2154
		2155	unsigned tile_config;
3764	Serge	2156	uint32_t tile_mode_array[32];
5078	serge	2157	uint32_t active_cus;
2997	Serge	2158	};
		2159
5078	serge	2160	struct cik_asic {
		2161	unsigned max_shader_engines;
		2162	unsigned max_tile_pipes;
		2163	unsigned max_cu_per_sh;
		2164	unsigned max_sh_per_se;
		2165	unsigned max_backends_per_se;
		2166	unsigned max_texture_channel_caches;
		2167	unsigned max_gprs;
		2168	unsigned max_gs_threads;
		2169	unsigned max_hw_contexts;
		2170	unsigned sc_prim_fifo_size_frontend;
		2171	unsigned sc_prim_fifo_size_backend;
		2172	unsigned sc_hiz_tile_fifo_size;
		2173	unsigned sc_earlyz_tile_fifo_size;
		2174
		2175	unsigned num_tile_pipes;
		2176	unsigned backend_enable_mask;
		2177	unsigned backend_disable_mask_per_asic;
		2178	unsigned backend_map;
		2179	unsigned num_texture_channel_caches;
		2180	unsigned mem_max_burst_length_bytes;
		2181	unsigned mem_row_size_in_kb;
		2182	unsigned shader_engine_tile_size;
		2183	unsigned num_gpus;
		2184	unsigned multi_gpu_tile_size;
		2185
		2186	unsigned tile_config;
		2187	uint32_t tile_mode_array[32];
		2188	uint32_t macrotile_mode_array[16];
		2189	uint32_t active_cus;
		2190	};
		2191
1117	serge	2192	union radeon_asic_config {
		2193	struct r300_asic r300;
1179	serge	2194	struct r100_asic r100;
		2195	struct r600_asic r600;
		2196	struct rv770_asic rv770;
1963	serge	2197	struct evergreen_asic evergreen;
		2198	struct cayman_asic cayman;
2997	Serge	2199	struct si_asic si;
5078	serge	2200	struct cik_asic cik;
1117	serge	2201	};
		2202
		2203	/*
1963	serge	2204	* asic initizalization from radeon_asic.c
		2205	*/
		2206	void radeon_agp_disable(struct radeon_device *rdev);
		2207	int radeon_asic_init(struct radeon_device *rdev);
1179	serge	2208
		2209
		2210
2997	Serge	2211	/* VRAM scratch page for HDP bug, default vram page */
		2212	struct r600_vram_scratch {
1963	serge	2213	struct radeon_bo *robj;
		2214	volatile uint32_t *ptr;
2997	Serge	2215	u64 gpu_addr;
1963	serge	2216	};
1179	serge	2217
5078	serge	2218	/*
		2219	* ACPI
		2220	*/
		2221	struct radeon_atif_notification_cfg {
		2222	bool enabled;
		2223	int command_code;
		2224	};
2997	Serge	2225
5078	serge	2226	struct radeon_atif_notifications {
		2227	bool display_switch;
		2228	bool expansion_mode_change;
		2229	bool thermal_state;
		2230	bool forced_power_state;
		2231	bool system_power_state;
		2232	bool display_conf_change;
		2233	bool px_gfx_switch;
		2234	bool brightness_change;
		2235	bool dgpu_display_event;
		2236	};
		2237
		2238	struct radeon_atif_functions {
		2239	bool system_params;
		2240	bool sbios_requests;
		2241	bool select_active_disp;
		2242	bool lid_state;
		2243	bool get_tv_standard;
		2244	bool set_tv_standard;
		2245	bool get_panel_expansion_mode;
		2246	bool set_panel_expansion_mode;
		2247	bool temperature_change;
		2248	bool graphics_device_types;
		2249	};
		2250
		2251	struct radeon_atif {
		2252	struct radeon_atif_notifications notifications;
		2253	struct radeon_atif_functions functions;
		2254	struct radeon_atif_notification_cfg notification_cfg;
		2255	struct radeon_encoder *encoder_for_bl;
		2256	};
		2257
		2258	struct radeon_atcs_functions {
		2259	bool get_ext_state;
		2260	bool pcie_perf_req;
		2261	bool pcie_dev_rdy;
		2262	bool pcie_bus_width;
		2263	};
		2264
		2265	struct radeon_atcs {
		2266	struct radeon_atcs_functions functions;
		2267	};
		2268
1117	serge	2269	/*
		2270	* Core structure, functions and helpers.
		2271	*/
		2272	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		2273	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		2274
		2275	struct radeon_device {
6104	serge	2276	struct device *dev;
		2277	struct drm_device *ddev;
		2278	struct pci_dev *pdev;
2997	Serge	2279	struct rw_semaphore exclusive_lock;
6104	serge	2280	/* ASIC */
		2281	union radeon_asic_config config;
		2282	enum radeon_family family;
		2283	unsigned long flags;
		2284	int usec_timeout;
		2285	enum radeon_pll_errata pll_errata;
		2286	int num_gb_pipes;
		2287	int num_z_pipes;
		2288	int disp_priority;
		2289	/* BIOS */
		2290	uint8_t *bios;
		2291	bool is_atom_bios;
		2292	uint16_t bios_header_start;
		2293	struct radeon_bo *stollen_vga_memory;
		2294	/* Register mmio */
1963	serge	2295	resource_size_t rmmio_base;
		2296	resource_size_t rmmio_size;
3192	Serge	2297	/* protects concurrent MM_INDEX/DATA based register access */
		2298	spinlock_t mmio_idx_lock;
5078	serge	2299	/* protects concurrent SMC based register access */
		2300	spinlock_t smc_idx_lock;
		2301	/* protects concurrent PLL register access */
		2302	spinlock_t pll_idx_lock;
		2303	/* protects concurrent MC register access */
		2304	spinlock_t mc_idx_lock;
		2305	/* protects concurrent PCIE register access */
		2306	spinlock_t pcie_idx_lock;
		2307	/* protects concurrent PCIE_PORT register access */
		2308	spinlock_t pciep_idx_lock;
		2309	/* protects concurrent PIF register access */
		2310	spinlock_t pif_idx_lock;
		2311	/* protects concurrent CG register access */
		2312	spinlock_t cg_idx_lock;
		2313	/* protects concurrent UVD register access */
		2314	spinlock_t uvd_idx_lock;
		2315	/* protects concurrent RCU register access */
		2316	spinlock_t rcu_idx_lock;
		2317	/* protects concurrent DIDT register access */
		2318	spinlock_t didt_idx_lock;
		2319	/* protects concurrent ENDPOINT (audio) register access */
		2320	spinlock_t end_idx_lock;
2997	Serge	2321	void __iomem *rmmio;
6104	serge	2322	radeon_rreg_t mc_rreg;
		2323	radeon_wreg_t mc_wreg;
		2324	radeon_rreg_t pll_rreg;
		2325	radeon_wreg_t pll_wreg;
1179	serge	2326	uint32_t pcie_reg_mask;
6104	serge	2327	radeon_rreg_t pciep_rreg;
		2328	radeon_wreg_t pciep_wreg;
1963	serge	2329	/* io port */
		2330	void __iomem *rio_mem;
		2331	resource_size_t rio_mem_size;
6104	serge	2332	struct radeon_clock clock;
		2333	struct radeon_mc mc;
		2334	struct radeon_gart gart;
1117	serge	2335	struct radeon_mode_info mode_info;
6104	serge	2336	struct radeon_scratch scratch;
5078	serge	2337	struct radeon_doorbell doorbell;
6104	serge	2338	struct radeon_mman mman;
2997	Serge	2339	struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
		2340	wait_queue_head_t fence_queue;
5271	serge	2341	unsigned fence_context;
2997	Serge	2342	struct mutex ring_lock;
		2343	struct radeon_ring ring[RADEON_NUM_RINGS];
		2344	bool ib_pool_ready;
		2345	struct radeon_sa_manager ring_tmp_bo;
6104	serge	2346	struct radeon_irq irq;
		2347	struct radeon_asic *asic;
		2348	struct radeon_gem gem;
1179	serge	2349	struct radeon_pm pm;
3764	Serge	2350	struct radeon_uvd uvd;
5078	serge	2351	struct radeon_vce vce;
1179	serge	2352	uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
6104	serge	2353	struct radeon_wb wb;
1179	serge	2354	struct radeon_dummy_page dummy_page;
6104	serge	2355	bool shutdown;
		2356	bool suspend;
1179	serge	2357	bool need_dma32;
		2358	bool accel_working;
3764	Serge	2359	bool fastfb_working; /* IGP feature*/
5271	serge	2360	bool needs_reset, in_reset;
1179	serge	2361	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
		2362	const struct firmware me_fw; / all family ME firmware */
		2363	const struct firmware pfp_fw; / r6/700 PFP firmware */
1403	serge	2364	const struct firmware rlc_fw; / r6/700 RLC firmware */
1963	serge	2365	const struct firmware mc_fw; / NI MC firmware */
2997	Serge	2366	const struct firmware ce_fw; / SI CE firmware */
5078	serge	2367	const struct firmware mec_fw; / CIK MEC firmware */
		2368	const struct firmware mec2_fw; / KV MEC2 firmware */
		2369	const struct firmware sdma_fw; / CIK SDMA firmware */
		2370	const struct firmware smc_fw; / SMC firmware */
3764	Serge	2371	const struct firmware uvd_fw; / UVD firmware */
5078	serge	2372	const struct firmware vce_fw; / VCE firmware */
		2373	bool new_fw;
2997	Serge	2374	struct r600_vram_scratch vram_scratch;
1268	serge	2375	int msi_enabled; /* msi enabled */
2004	serge	2376	struct r600_ih ih; /* r6/700 interrupt ring */
5078	serge	2377	struct radeon_rlc rlc;
		2378	struct radeon_mec mec;
6321	serge	2379	struct delayed_work hotplug_work;
		2380	struct work_struct dp_work;
5078	serge	2381	struct work_struct audio_work;
1430	serge	2382	int num_crtc; /* number of crtcs */
1630	serge	2383	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3764	Serge	2384	bool has_uvd;
5078	serge	2385	struct r600_audio audio; /* audio stuff */
6938	serge	2386	struct notifier_block acpi_nb;
2997	Serge	2387	/* only one userspace can use Hyperz features or CMASK at a time */
5078	serge	2388	struct drm_file *hyperz_filp;
		2389	struct drm_file *cmask_filp;
1963	serge	2390	/* i2c buses */
		2391	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2997	Serge	2392	/* debugfs */
5078	serge	2393	struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2997	Serge	2394	unsigned debugfs_count;
		2395	/* virtual memory */
		2396	struct radeon_vm_manager vm_manager;
		2397	struct mutex gpu_clock_mutex;
5078	serge	2398	/* memory stats */
		2399	atomic64_t vram_usage;
		2400	atomic64_t gtt_usage;
		2401	atomic64_t num_bytes_moved;
6104	serge	2402	atomic_t gpu_reset_counter;
2997	Serge	2403	/* ACPI interface */
5078	serge	2404	struct radeon_atif atif;
		2405	struct radeon_atcs atcs;
		2406	/* srbm instance registers */
		2407	struct mutex srbm_mutex;
5271	serge	2408	/* GRBM index mutex. Protects concurrents access to GRBM index */
		2409	struct mutex grbm_idx_mutex;
5078	serge	2410	/* clock, powergating flags */
		2411	u32 cg_flags;
		2412	u32 pg_flags;
		2413
		2414	// struct dev_pm_domain vga_pm_domain;
		2415	bool have_disp_power_ref;
		2416	u32 px_quirk_flags;
		2417
		2418	/* tracking pinned memory */
		2419	u64 vram_pin_size;
		2420	u64 gart_pin_size;
5271	serge	2421	struct mutex mn_lock;
1117	serge	2422	};
		2423
5078	serge	2424	bool radeon_is_px(struct drm_device *dev);
1117	serge	2425	int radeon_device_init(struct radeon_device *rdev,
		2426	struct drm_device *ddev,
		2427	struct pci_dev *pdev,
		2428	uint32_t flags);
		2429	void radeon_device_fini(struct radeon_device *rdev);
		2430	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		2431
5078	serge	2432	#define RADEON_MIN_MMIO_SIZE 0x10000
		2433
6104	serge	2434	uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
		2435	void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
5078	serge	2436	static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		2437	bool always_indirect)
		2438	{
		2439	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
		2440	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2441	return readl(((void __iomem *)rdev->rmmio) + reg);
6104	serge	2442	else
		2443	return r100_mm_rreg_slow(rdev, reg);
5078	serge	2444	}
		2445	static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		2446	bool always_indirect)
		2447	{
		2448	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2449	writel(v, ((void __iomem *)rdev->rmmio) + reg);
6104	serge	2450	else
		2451	r100_mm_wreg_slow(rdev, reg, v);
5078	serge	2452	}
		2453
2997	Serge	2454	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
		2455	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2456
5078	serge	2457	u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
		2458	void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
		2459
1321	serge	2460	/*
		2461	* Cast helper
		2462	*/
5271	serge	2463	extern const struct fence_ops radeon_fence_ops;
1117	serge	2464
5271	serge	2465	static inline struct radeon_fence to_radeon_fence(struct fence f)
		2466	{
		2467	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
		2468
		2469	if (__f->base.ops == &radeon_fence_ops)
		2470	return __f;
		2471
		2472	return NULL;
		2473	}
		2474
1117	serge	2475	/*
		2476	* Registers read & write functions.
		2477	*/
2997	Serge	2478	#define RREG8(reg) readb((rdev->rmmio) + (reg))
		2479	#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
		2480	#define RREG16(reg) readw((rdev->rmmio) + (reg))
		2481	#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
3192	Serge	2482	#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
		2483	#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
		2484	#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
		2485	#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
		2486	#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1117	serge	2487	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2488	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2489	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		2490	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		2491	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		2492	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179	serge	2493	#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
		2494	#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
3764	Serge	2495	#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
		2496	#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
5078	serge	2497	#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
		2498	#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
		2499	#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
		2500	#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
		2501	#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
		2502	#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
		2503	#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
		2504	#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
		2505	#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
		2506	#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
		2507	#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
		2508	#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
		2509	#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
		2510	#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
1117	serge	2511	#define WREG32_P(reg, val, mask) \
		2512	do { \
		2513	uint32_t tmp_ = RREG32(reg); \
		2514	tmp_ &= (mask); \
		2515	tmp_ \|= ((val) & ~(mask)); \
		2516	WREG32(reg, tmp_); \
		2517	} while (0)
3764	Serge	2518	#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
5078	serge	2519	#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1117	serge	2520	#define WREG32_PLL_P(reg, val, mask) \
		2521	do { \
		2522	uint32_t tmp_ = RREG32_PLL(reg); \
		2523	tmp_ &= (mask); \
		2524	tmp_ \|= ((val) & ~(mask)); \
		2525	WREG32_PLL(reg, tmp_); \
		2526	} while (0)
6104	serge	2527	#define WREG32_SMC_P(reg, val, mask) \
		2528	do { \
		2529	uint32_t tmp_ = RREG32_SMC(reg); \
		2530	tmp_ &= (mask); \
		2531	tmp_ \|= ((val) & ~(mask)); \
		2532	WREG32_SMC(reg, tmp_); \
		2533	} while (0)
5078	serge	2534	#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1963	serge	2535	#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
		2536	#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1117	serge	2537
5078	serge	2538	#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
		2539	#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
		2540
1179	serge	2541	/*
6104	serge	2542	* Indirect registers accessors.
		2543	* They used to be inlined, but this increases code size by ~65 kbytes.
		2544	* Since each performs a pair of MMIO ops
		2545	* within a spin_lock_irqsave/spin_unlock_irqrestore region,
		2546	* the cost of call+ret is almost negligible. MMIO and locking
		2547	* costs several dozens of cycles each at best, call+ret is ~5 cycles.
1179	serge	2548	*/
6104	serge	2549	uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
		2550	void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
		2551	u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
		2552	void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2553	u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
		2554	void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2555	u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
		2556	void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2557	u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
		2558	void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2559	u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
		2560	void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2561	u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
		2562	void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2563	u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
		2564	void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2565
1179	serge	2566	void r100_pll_errata_after_index(struct radeon_device *rdev);
		2567
		2568
1117	serge	2569	/*
		2570	* ASICs helpers.
		2571	*/
1179	serge	2572	#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) \|\| \
		2573	(rdev->pdev->device == 0x5969))
1117	serge	2574	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
6104	serge	2575	(rdev->family == CHIP_RV200) \|\| \
		2576	(rdev->family == CHIP_RS100) \|\| \
		2577	(rdev->family == CHIP_RS200) \|\| \
		2578	(rdev->family == CHIP_RV250) \|\| \
		2579	(rdev->family == CHIP_RV280) \|\| \
		2580	(rdev->family == CHIP_RS300))
		2581	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		2582	(rdev->family == CHIP_RV350) \|\| \
		2583	(rdev->family == CHIP_R350) \|\| \
		2584	(rdev->family == CHIP_RV380) \|\| \
		2585	(rdev->family == CHIP_R420) \|\| \
		2586	(rdev->family == CHIP_R423) \|\| \
		2587	(rdev->family == CHIP_RV410) \|\| \
		2588	(rdev->family == CHIP_RS400) \|\| \
		2589	(rdev->family == CHIP_RS480))
1963	serge	2590	#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \
		2591	(rdev->ddev->pdev->device == 0x9443) \|\| \
		2592	(rdev->ddev->pdev->device == 0x944B) \|\| \
		2593	(rdev->ddev->pdev->device == 0x9506) \|\| \
		2594	(rdev->ddev->pdev->device == 0x9509) \|\| \
		2595	(rdev->ddev->pdev->device == 0x950F) \|\| \
		2596	(rdev->ddev->pdev->device == 0x689C) \|\| \
		2597	(rdev->ddev->pdev->device == 0x689D))
1117	serge	2598	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1963	serge	2599	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
		2600	(rdev->family == CHIP_RS690) \|\| \
		2601	(rdev->family == CHIP_RS740) \|\| \
		2602	(rdev->family >= CHIP_R600))
1117	serge	2603	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		2604	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1430	serge	2605	#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1963	serge	2606	#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
		2607	(rdev->flags & RADEON_IS_IGP))
		2608	#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2997	Serge	2609	#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
		2610	#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
		2611	(rdev->flags & RADEON_IS_IGP))
3764	Serge	2612	#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
		2613	#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
5078	serge	2614	#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
		2615	#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
		2616	#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
		2617	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
		2618	(rdev->family == CHIP_MULLINS))
1117	serge	2619
5078	serge	2620	#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \
		2621	(rdev->ddev->pdev->device == 0x6850) \|\| \
		2622	(rdev->ddev->pdev->device == 0x6858) \|\| \
		2623	(rdev->ddev->pdev->device == 0x6859) \|\| \
		2624	(rdev->ddev->pdev->device == 0x6840) \|\| \
		2625	(rdev->ddev->pdev->device == 0x6841) \|\| \
		2626	(rdev->ddev->pdev->device == 0x6842) \|\| \
		2627	(rdev->ddev->pdev->device == 0x6843))
		2628
1117	serge	2629	/*
		2630	* BIOS helpers.
		2631	*/
		2632	#define RBIOS8(i) (rdev->bios[i])
		2633	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		2634	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		2635
		2636	int radeon_combios_init(struct radeon_device *rdev);
		2637	void radeon_combios_fini(struct radeon_device *rdev);
		2638	int radeon_atombios_init(struct radeon_device *rdev);
		2639	void radeon_atombios_fini(struct radeon_device *rdev);
		2640
		2641
		2642	/*
		2643	* RING helpers.
		2644	*/
5271	serge	2645
		2646	/**
		2647	* radeon_ring_write - write a value to the ring
		2648	*
		2649	* @ring: radeon_ring structure holding ring information
		2650	* @v: dword (dw) value to write
		2651	*
		2652	* Write a value to the requested ring buffer (all asics).
		2653	*/
2997	Serge	2654	static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1117	serge	2655	{
5271	serge	2656	if (ring->count_dw <= 0)
		2657	DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
		2658
2997	Serge	2659	ring->ring[ring->wptr++] = v;
		2660	ring->wptr &= ring->ptr_mask;
		2661	ring->count_dw--;
		2662	ring->ring_free_dw--;
		2663	}
1117	serge	2664
		2665	/*
		2666	* ASICs macro.
		2667	*/
		2668	#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179	serge	2669	#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
		2670	#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
		2671	#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
5078	serge	2672	#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
1179	serge	2673	#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1963	serge	2674	#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2997	Serge	2675	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
6104	serge	2676	#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
		2677	#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2997	Serge	2678	#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
		2679	#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
5078	serge	2680	#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
		2681	#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2682	#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2683	#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
		2684	#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
		2685	#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
		2686	#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
		2687	#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
		2688	#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
		2689	#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
5271	serge	2690	#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
5078	serge	2691	#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
		2692	#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
		2693	#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2997	Serge	2694	#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
		2695	#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
		2696	#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
		2697	#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
		2698	#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
3764	Serge	2699	#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
		2700	#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
5078	serge	2701	#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
		2702	#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
5271	serge	2703	#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
		2704	#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
		2705	#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2997	Serge	2706	#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
		2707	#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
		2708	#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
		2709	#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
		2710	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
		2711	#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
		2712	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
		2713	#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
		2714	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
		2715	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
3764	Serge	2716	#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
5078	serge	2717	#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
		2718	#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2997	Serge	2719	#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
		2720	#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
		2721	#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
		2722	#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
		2723	#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
		2724	#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
		2725	#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1963	serge	2726	#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2997	Serge	2727	#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
		2728	#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
		2729	#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
		2730	#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
		2731	#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
		2732	#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
5078	serge	2733	#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2997	Serge	2734	#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
		2735	#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
3764	Serge	2736	#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
		2737	#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
6104	serge	2738	#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
5078	serge	2739	#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
		2740	#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
		2741	#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
		2742	#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
		2743	#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
		2744	#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
		2745	#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
		2746	#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
		2747	#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
		2748	#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
		2749	#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
		2750	#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
		2751	#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
		2752	#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
		2753	#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
		2754	#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
		2755	#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
		2756	#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
6104	serge	2757	#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
		2758	#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
1117	serge	2759
1179	serge	2760	/* Common functions */
1403	serge	2761	/* AGP */
1963	serge	2762	extern int radeon_gpu_reset(struct radeon_device *rdev);
5078	serge	2763	extern void radeon_pci_config_reset(struct radeon_device *rdev);
3764	Serge	2764	extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1403	serge	2765	extern void radeon_agp_disable(struct radeon_device *rdev);
1179	serge	2766	extern int radeon_modeset_init(struct radeon_device *rdev);
		2767	extern void radeon_modeset_fini(struct radeon_device *rdev);
		2768	extern bool radeon_card_posted(struct radeon_device *rdev);
1963	serge	2769	extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
		2770	extern void radeon_update_display_priority(struct radeon_device *rdev);
1321	serge	2771	extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1179	serge	2772	extern void radeon_scratch_init(struct radeon_device *rdev);
1963	serge	2773	extern void radeon_wb_fini(struct radeon_device *rdev);
		2774	extern int radeon_wb_init(struct radeon_device *rdev);
		2775	extern void radeon_wb_disable(struct radeon_device *rdev);
1179	serge	2776	extern void radeon_surface_init(struct radeon_device *rdev);
		2777	extern int radeon_cs_parser_init(struct radeon_cs_parser p, void data);
1221	serge	2778	extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
		2779	extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1321	serge	2780	extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1403	serge	2781	extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
5271	serge	2782	extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
		2783	uint32_t flags);
		2784	extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
		2785	extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
1430	serge	2786	extern void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base);
		2787	extern void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc);
5078	serge	2788	extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
		2789	extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
1963	serge	2790	extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
3764	Serge	2791	extern void radeon_program_register_sequence(struct radeon_device *rdev,
		2792	const u32 *registers,
		2793	const u32 array_size);
1117	serge	2794
1963	serge	2795	/*
2997	Serge	2796	* vm
		2797	*/
		2798	int radeon_vm_manager_init(struct radeon_device *rdev);
		2799	void radeon_vm_manager_fini(struct radeon_device *rdev);
5078	serge	2800	int radeon_vm_init(struct radeon_device rdev, struct radeon_vm vm);
2997	Serge	2801	void radeon_vm_fini(struct radeon_device rdev, struct radeon_vm vm);
5271	serge	2802	struct radeon_bo_list radeon_vm_get_bos(struct radeon_device rdev,
5078	serge	2803	struct radeon_vm *vm,
		2804	struct list_head *head);
2997	Serge	2805	struct radeon_fence radeon_vm_grab_id(struct radeon_device rdev,
		2806	struct radeon_vm *vm, int ring);
5078	serge	2807	void radeon_vm_flush(struct radeon_device *rdev,
		2808	struct radeon_vm *vm,
5271	serge	2809	int ring, struct radeon_fence *fence);
2997	Serge	2810	void radeon_vm_fence(struct radeon_device *rdev,
		2811	struct radeon_vm *vm,
		2812	struct radeon_fence *fence);
		2813	uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
5078	serge	2814	int radeon_vm_update_page_directory(struct radeon_device *rdev,
		2815	struct radeon_vm *vm);
		2816	int radeon_vm_clear_freed(struct radeon_device *rdev,
		2817	struct radeon_vm *vm);
		2818	int radeon_vm_clear_invalids(struct radeon_device *rdev,
		2819	struct radeon_vm *vm);
		2820	int radeon_vm_bo_update(struct radeon_device *rdev,
		2821	struct radeon_bo_va *bo_va,
		2822	struct ttm_mem_reg *mem);
2997	Serge	2823	void radeon_vm_bo_invalidate(struct radeon_device *rdev,
		2824	struct radeon_bo *bo);
		2825	struct radeon_bo_va radeon_vm_bo_find(struct radeon_vm vm,
		2826	struct radeon_bo *bo);
		2827	struct radeon_bo_va radeon_vm_bo_add(struct radeon_device rdev,
		2828	struct radeon_vm *vm,
		2829	struct radeon_bo *bo);
		2830	int radeon_vm_bo_set_addr(struct radeon_device *rdev,
		2831	struct radeon_bo_va *bo_va,
		2832	uint64_t offset,
		2833	uint32_t flags);
5078	serge	2834	void radeon_vm_bo_rmv(struct radeon_device *rdev,
6104	serge	2835	struct radeon_bo_va *bo_va);
2997	Serge	2836
		2837	/* audio */
		2838	void r600_audio_update_hdmi(struct work_struct *work);
5078	serge	2839	struct r600_audio_pin r600_audio_get_pin(struct radeon_device rdev);
		2840	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev);
		2841	void r600_audio_enable(struct radeon_device *rdev,
		2842	struct r600_audio_pin *pin,
5271	serge	2843	u8 enable_mask);
5078	serge	2844	void dce6_audio_enable(struct radeon_device *rdev,
		2845	struct r600_audio_pin *pin,
5271	serge	2846	u8 enable_mask);
2997	Serge	2847
		2848	/*
		2849	* R600 vram scratch functions
		2850	*/
		2851	int r600_vram_scratch_init(struct radeon_device *rdev);
		2852	void r600_vram_scratch_fini(struct radeon_device *rdev);
		2853
		2854	/*
		2855	* r600 cs checking helper
		2856	*/
		2857	unsigned r600_mip_minify(unsigned size, unsigned level);
		2858	bool r600_fmt_is_valid_color(u32 format);
		2859	bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
		2860	int r600_fmt_get_blocksize(u32 format);
		2861	int r600_fmt_get_nblocksx(u32 format, u32 w);
		2862	int r600_fmt_get_nblocksy(u32 format, u32 h);
		2863
		2864	/*
1963	serge	2865	* r600 functions used by radeon_encoder.c
		2866	*/
2997	Serge	2867	struct radeon_hdmi_acr {
		2868	u32 clock;
		2869
		2870	int n_32khz;
		2871	int cts_32khz;
		2872
		2873	int n_44_1khz;
		2874	int cts_44_1khz;
		2875
		2876	int n_48khz;
		2877	int cts_48khz;
		2878
		2879	};
		2880
		2881	extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
		2882
		2883	extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
		2884	u32 tiling_pipe_num,
		2885	u32 max_rb_num,
		2886	u32 total_max_rb_num,
		2887	u32 enabled_rb_mask);
1179	serge	2888
2997	Serge	2889	/*
		2890	* evergreen functions used by radeon_encoder.c
		2891	*/
		2892
1963	serge	2893	extern int ni_init_microcode(struct radeon_device *rdev);
		2894	extern int ni_mc_load_microcode(struct radeon_device *rdev);
1221	serge	2895
1963	serge	2896	/* radeon_acpi.c */
		2897	#if defined(CONFIG_ACPI)
		2898	extern int radeon_acpi_init(struct radeon_device *rdev);
2997	Serge	2899	extern void radeon_acpi_fini(struct radeon_device *rdev);
5078	serge	2900	extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
		2901	extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
		2902	u8 perf_req, bool advertise);
		2903	extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
1963	serge	2904	#else
		2905	static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2997	Serge	2906	static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1963	serge	2907	#endif
1179	serge	2908
5078	serge	2909	int radeon_cs_packet_parse(struct radeon_cs_parser *p,
		2910	struct radeon_cs_packet *pkt,
		2911	unsigned idx);
		2912	bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
		2913	void radeon_cs_dump_packet(struct radeon_cs_parser *p,
		2914	struct radeon_cs_packet *pkt);
		2915	int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
5271	serge	2916	struct radeon_bo_list **cs_reloc,
5078	serge	2917	int nomm);
		2918	int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
		2919	uint32_t *vline_start_end,
		2920	uint32_t *vline_status);
		2921
1321	serge	2922	#include "radeon_object.h"
1179	serge	2923
5271	serge	2924	#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
6104	serge	2925	#define PCI_VENDOR_ID_ATI 0x1002
1117	serge	2926
		2927	resource_size_t
		2928	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		2929	resource_size_t
		2930	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		2931
3764	Serge	2932	#endif

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(root)/drivers/video/drm/radeon/radeon.h – Rev 7146