WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	/* TODO: Here are things that needs to be done :
		32	* - surface allocator & initializer : (bit like scratch reg) should
		33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		34	* related to surface
		35	* - WB : write back stuff (do it bit like scratch reg things)
		36	* - Vblank : look at Jesse's rework and what we should do
		37	* - r600/r700: gart & cp
		38	* - cs : clean cs ioctl use bitmap & things like that.
		39	* - power management stuff
		40	* - Barrier in gart code
		41	* - Unmappabled vram ?
		42	* - TESTING, TESTING, TESTING
		43	*/
		44
1221	serge	45	/* Initialization path:
		46	* We expect that acceleration initialization might fail for various
		47	* reasons even thought we work hard to make it works on most
		48	* configurations. In order to still have a working userspace in such
		49	* situation the init path must succeed up to the memory controller
		50	* initialization point. Failure before this point are considered as
		51	* fatal error. Here is the init callchain :
		52	* radeon_device_init perform common structure, mutex initialization
		53	* asic_init setup the GPU memory layout and perform all
		54	* one time initialization (failure in this
		55	* function are considered fatal)
		56	* asic_startup setup the GPU acceleration, in order to
		57	* follow guideline the first thing this
		58	* function should do is setting the GPU
		59	* memory controller (only MC setup failure
		60	* are considered as fatal)
		61	*/
		62
5271	serge	63	#include
2997	Serge	64	#include
1321	serge	65	#include
		66	#include
5078	serge	67	#include
2997	Serge	68	#include
5271	serge	69	#include
1221	serge	70
1321	serge	71	#include
		72	#include
		73	#include
5078	serge	74	//#include
		75	#include
5346	serge	76	#include
1221	serge	77
5271	serge	78	#include
		79
2004	serge	80	#include
5271	serge	81	#include
1117	serge	82
1179	serge	83	#include "radeon_family.h"
1117	serge	84	#include "radeon_mode.h"
		85	#include "radeon_reg.h"
		86
		87	#include
		88
1179	serge	89	/*
		90	* Modules parameters.
		91	*/
		92	extern int radeon_no_wb;
1123	serge	93	extern int radeon_modeset;
1117	serge	94	extern int radeon_dynclks;
1123	serge	95	extern int radeon_r4xx_atom;
1128	serge	96	extern int radeon_agpmode;
		97	extern int radeon_vram_limit;
1117	serge	98	extern int radeon_gart_size;
1128	serge	99	extern int radeon_benchmarking;
1179	serge	100	extern int radeon_testing;
1123	serge	101	extern int radeon_connector_table;
1179	serge	102	extern int radeon_tv;
1403	serge	103	extern int radeon_audio;
1963	serge	104	extern int radeon_disp_priority;
		105	extern int radeon_hw_i2c;
		106	extern int radeon_pcie_gen2;
2997	Serge	107	extern int radeon_msi;
		108	extern int radeon_lockup_timeout;
3764	Serge	109	extern int radeon_fastfb;
5078	serge	110	extern int radeon_dpm;
		111	extern int radeon_aspm;
		112	extern int radeon_runtime_pm;
		113	extern int radeon_hard_reset;
		114	extern int radeon_vm_size;
		115	extern int radeon_vm_block_size;
		116	extern int radeon_deep_color;
		117	extern int radeon_use_pflipirq;
		118	extern int radeon_bapm;
5179	serge	119	extern int radeon_backlight;
6104	serge	120	extern int radeon_auxch;
		121	extern int radeon_mst;
2997	Serge	122
		123
1963	serge	124	static inline u32 ioread32(const volatile void __iomem *addr)
		125	{
		126	return in32((u32)addr);
		127	}
		128
3764	Serge	129	//static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
		130	//{
		131	// out32((u32)addr, b);
		132	//}
1963	serge	133
		134
1117	serge	135	/*
		136	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		137	* symbol;
		138	*/
6104	serge	139	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
		140	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
1428	serge	141	/* RADEON_IB_POOL_SIZE must be a power of 2 */
6104	serge	142	#define RADEON_IB_POOL_SIZE 16
		143	#define RADEON_DEBUGFS_MAX_COMPONENTS 32
		144	#define RADEONFB_CONN_LIMIT 4
		145	#define RADEON_BIOS_NUM_SCRATCH 8
1117	serge	146
2997	Serge	147	/* internal ring indices */
		148	/* r1xx+ has gfx CP ring */
6104	serge	149	#define RADEON_RING_TYPE_GFX_INDEX 0
2997	Serge	150
		151	/* cayman has 2 compute CP rings */
6104	serge	152	#define CAYMAN_RING_TYPE_CP1_INDEX 1
		153	#define CAYMAN_RING_TYPE_CP2_INDEX 2
2997	Serge	154
3192	Serge	155	/* R600+ has an async dma ring */
		156	#define R600_RING_TYPE_DMA_INDEX 3
		157	/* cayman add a second async dma ring */
		158	#define CAYMAN_RING_TYPE_DMA1_INDEX 4
		159
3764	Serge	160	/* R600+ */
6104	serge	161	#define R600_RING_TYPE_UVD_INDEX 5
3764	Serge	162
5078	serge	163	/* TN+ */
		164	#define TN_RING_TYPE_VCE1_INDEX 6
		165	#define TN_RING_TYPE_VCE2_INDEX 7
		166
		167	/* max number of rings */
		168	#define RADEON_NUM_RINGS 8
		169
		170	/* number of hw syncs before falling back on blocking */
		171	#define RADEON_NUM_SYNCS 4
		172
2997	Serge	173	/* hardcode those limit for now */
		174	#define RADEON_VA_IB_OFFSET (1 << 20)
6104	serge	175	#define RADEON_VA_RESERVED_SIZE (8 << 20)
		176	#define RADEON_IB_VM_MAX_SIZE (64 << 10)
2997	Serge	177
5078	serge	178	/* hard reset data */
		179	#define RADEON_ASIC_RESET_DATA 0x39d5e86b
		180
3192	Serge	181	/* reset flags */
		182	#define RADEON_RESET_GFX (1 << 0)
		183	#define RADEON_RESET_COMPUTE (1 << 1)
		184	#define RADEON_RESET_DMA (1 << 2)
3764	Serge	185	#define RADEON_RESET_CP (1 << 3)
		186	#define RADEON_RESET_GRBM (1 << 4)
		187	#define RADEON_RESET_DMA1 (1 << 5)
		188	#define RADEON_RESET_RLC (1 << 6)
		189	#define RADEON_RESET_SEM (1 << 7)
		190	#define RADEON_RESET_IH (1 << 8)
		191	#define RADEON_RESET_VMC (1 << 9)
		192	#define RADEON_RESET_MC (1 << 10)
		193	#define RADEON_RESET_DISPLAY (1 << 11)
3192	Serge	194
5078	serge	195	/* CG block flags */
		196	#define RADEON_CG_BLOCK_GFX (1 << 0)
		197	#define RADEON_CG_BLOCK_MC (1 << 1)
		198	#define RADEON_CG_BLOCK_SDMA (1 << 2)
		199	#define RADEON_CG_BLOCK_UVD (1 << 3)
		200	#define RADEON_CG_BLOCK_VCE (1 << 4)
		201	#define RADEON_CG_BLOCK_HDP (1 << 5)
		202	#define RADEON_CG_BLOCK_BIF (1 << 6)
		203
		204	/* CG flags */
		205	#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
		206	#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
		207	#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
		208	#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
		209	#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
		210	#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
		211	#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
		212	#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
		213	#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
		214	#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
		215	#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
		216	#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
		217	#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
		218	#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
		219	#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
		220	#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
		221	#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
		222
		223	/* PG flags */
		224	#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
		225	#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
		226	#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
		227	#define RADEON_PG_SUPPORT_UVD (1 << 3)
		228	#define RADEON_PG_SUPPORT_VCE (1 << 4)
		229	#define RADEON_PG_SUPPORT_CP (1 << 5)
		230	#define RADEON_PG_SUPPORT_GDS (1 << 6)
		231	#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
		232	#define RADEON_PG_SUPPORT_SDMA (1 << 8)
		233	#define RADEON_PG_SUPPORT_ACP (1 << 9)
		234	#define RADEON_PG_SUPPORT_SAMU (1 << 10)
		235
		236	/* max cursor sizes (in pixels) */
		237	#define CURSOR_WIDTH 64
		238	#define CURSOR_HEIGHT 64
		239
		240	#define CIK_CURSOR_WIDTH 128
		241	#define CIK_CURSOR_HEIGHT 128
		242
1117	serge	243	/*
		244	* Errata workarounds.
		245	*/
		246	enum radeon_pll_errata {
6104	serge	247	CHIP_ERRATA_R300_CG = 0x00000001,
		248	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		249	CHIP_ERRATA_PLL_DELAY = 0x00000004
1117	serge	250	};
		251
		252
		253	struct radeon_device;
		254
		255
		256	/*
		257	* BIOS.
		258	*/
		259	bool radeon_get_bios(struct radeon_device *rdev);
		260
		261	/*
1179	serge	262	* Dummy page
		263	*/
		264	struct radeon_dummy_page {
6104	serge	265	uint64_t entry;
1179	serge	266	struct page *page;
		267	dma_addr_t addr;
		268	};
		269	int radeon_dummy_page_init(struct radeon_device *rdev);
		270	void radeon_dummy_page_fini(struct radeon_device *rdev);
		271
		272
		273	/*
1117	serge	274	* Clocks
		275	*/
		276	struct radeon_clock {
		277	struct radeon_pll p1pll;
		278	struct radeon_pll p2pll;
1430	serge	279	struct radeon_pll dcpll;
1117	serge	280	struct radeon_pll spll;
		281	struct radeon_pll mpll;
		282	/* 10 Khz units */
		283	uint32_t default_mclk;
		284	uint32_t default_sclk;
1430	serge	285	uint32_t default_dispclk;
5078	serge	286	uint32_t current_dispclk;
1430	serge	287	uint32_t dp_extclk;
1963	serge	288	uint32_t max_pixel_clock;
1117	serge	289	};
		290
1268	serge	291	/*
		292	* Power management
		293	*/
		294	int radeon_pm_init(struct radeon_device *rdev);
5078	serge	295	int radeon_pm_late_init(struct radeon_device *rdev);
1963	serge	296	void radeon_pm_fini(struct radeon_device *rdev);
1430	serge	297	void radeon_pm_compute_clocks(struct radeon_device *rdev);
1963	serge	298	void radeon_pm_suspend(struct radeon_device *rdev);
		299	void radeon_pm_resume(struct radeon_device *rdev);
1430	serge	300	void radeon_combios_get_power_modes(struct radeon_device *rdev);
		301	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
3764	Serge	302	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		303	u8 clock_type,
		304	u32 clock,
		305	bool strobe_mode,
		306	struct atom_clock_dividers *dividers);
5078	serge	307	int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
		308	u32 clock,
		309	bool strobe_mode,
		310	struct atom_mpll_param *mpll_param);
1963	serge	311	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
5078	serge	312	int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
		313	u16 voltage_level, u8 voltage_type,
		314	u32 gpio_value, u32 gpio_mask);
		315	void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
		316	u32 eng_clock, u32 mem_clock);
		317	int radeon_atom_get_voltage_step(struct radeon_device *rdev,
		318	u8 voltage_type, u16 *voltage_step);
		319	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		320	u16 voltage_id, u16 *voltage);
		321	int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
		322	u16 *voltage,
		323	u16 leakage_idx);
		324	int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
		325	u16 *leakage_id);
		326	int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
		327	u16 vddc, u16 vddci,
		328	u16 virtual_voltage_id,
		329	u16 vbios_voltage_id);
		330	int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
		331	u16 virtual_voltage_id,
		332	u16 *voltage);
		333	int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
		334	u8 voltage_type,
		335	u16 nominal_voltage,
		336	u16 *true_voltage);
		337	int radeon_atom_get_min_voltage(struct radeon_device *rdev,
		338	u8 voltage_type, u16 *min_voltage);
		339	int radeon_atom_get_max_voltage(struct radeon_device *rdev,
		340	u8 voltage_type, u16 *max_voltage);
		341	int radeon_atom_get_voltage_table(struct radeon_device *rdev,
		342	u8 voltage_type, u8 voltage_mode,
		343	struct atom_voltage_table *voltage_table);
		344	bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
		345	u8 voltage_type, u8 voltage_mode);
		346	int radeon_atom_get_svi2_info(struct radeon_device *rdev,
		347	u8 voltage_type,
		348	u8 svd_gpio_id, u8 svc_gpio_id);
		349	void radeon_atom_update_memory_dll(struct radeon_device *rdev,
		350	u32 mem_clock);
		351	void radeon_atom_set_ac_timing(struct radeon_device *rdev,
		352	u32 mem_clock);
		353	int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
		354	u8 module_index,
		355	struct atom_mc_reg_table *reg_table);
		356	int radeon_atom_get_memory_info(struct radeon_device *rdev,
		357	u8 module_index, struct atom_memory_info *mem_info);
		358	int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
		359	bool gddr5, u8 module_index,
		360	struct atom_memory_clock_range_table *mclk_range_table);
		361	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		362	u16 voltage_id, u16 *voltage);
1963	serge	363	void rs690_pm_info(struct radeon_device *rdev);
2997	Serge	364	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
		365	unsigned bankh, unsigned mtaspect,
		366	unsigned *tile_split);
1179	serge	367
1117	serge	368	/*
		369	* Fences.
		370	*/
		371	struct radeon_fence_driver {
5271	serge	372	struct radeon_device *rdev;
1117	serge	373	uint32_t scratch_reg;
2997	Serge	374	uint64_t gpu_addr;
		375	volatile uint32_t *cpu_addr;
		376	/* sync_seq is protected by ring emission lock */
		377	uint64_t sync_seq[RADEON_NUM_RINGS];
		378	atomic64_t last_seq;
5271	serge	379	bool initialized, delayed_irq;
		380	struct delayed_work lockup_work;
1117	serge	381	};
		382
		383	struct radeon_fence {
5271	serge	384	struct fence base;
		385
6104	serge	386	struct radeon_device *rdev;
		387	uint64_t seq;
2997	Serge	388	/* RB, DMA, etc. */
6104	serge	389	unsigned ring;
5271	serge	390	bool is_vm_update;
		391
		392	wait_queue_t fence_wake;
1117	serge	393	};
		394
2997	Serge	395	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
1117	serge	396	int radeon_fence_driver_init(struct radeon_device *rdev);
		397	void radeon_fence_driver_fini(struct radeon_device *rdev);
5271	serge	398	void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
2997	Serge	399	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);
		400	void radeon_fence_process(struct radeon_device *rdev, int ring);
1117	serge	401	bool radeon_fence_signaled(struct radeon_fence *fence);
		402	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
5078	serge	403	int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
		404	int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
2997	Serge	405	int radeon_fence_wait_any(struct radeon_device *rdev,
		406	struct radeon_fence **fences,
		407	bool intr);
1117	serge	408	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		409	void radeon_fence_unref(struct radeon_fence **fence);
2997	Serge	410	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
		411	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
		412	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
		413	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,
		414	struct radeon_fence *b)
		415	{
		416	if (!a) {
		417	return b;
		418	}
1117	serge	419
2997	Serge	420	if (!b) {
		421	return a;
		422	}
		423
		424	BUG_ON(a->ring != b->ring);
		425
		426	if (a->seq > b->seq) {
		427	return a;
		428	} else {
		429	return b;
		430	}
		431	}
		432
		433	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
		434	struct radeon_fence *b)
		435	{
		436	if (!a) {
		437	return false;
		438	}
		439
		440	if (!b) {
		441	return true;
		442	}
		443
		444	BUG_ON(a->ring != b->ring);
		445
		446	return a->seq < b->seq;
		447	}
		448
1179	serge	449	/*
		450	* Tiling registers
		451	*/
		452	struct radeon_surface_reg {
1321	serge	453	struct radeon_bo *bo;
1179	serge	454	};
1117	serge	455
1179	serge	456	#define RADEON_GEM_MAX_SURFACES 8
		457
1117	serge	458	/*
1321	serge	459	* TTM.
1117	serge	460	*/
1321	serge	461	struct radeon_mman {
		462	struct ttm_bo_global_ref bo_global_ref;
3764	Serge	463	struct drm_global_reference mem_global_ref;
1403	serge	464	struct ttm_bo_device bdev;
1321	serge	465	bool mem_global_referenced;
1403	serge	466	bool initialized;
5078	serge	467
		468	#if defined(CONFIG_DEBUG_FS)
		469	struct dentry *vram;
		470	struct dentry *gtt;
		471	#endif
1321	serge	472	};
1117	serge	473
5271	serge	474	struct radeon_bo_list {
		475	struct radeon_bo *robj;
		476	struct ttm_validate_buffer tv;
		477	uint64_t gpu_offset;
		478	unsigned prefered_domains;
		479	unsigned allowed_domains;
		480	uint32_t tiling_flags;
		481	};
		482
2997	Serge	483	/* bo virtual address in a specific vm */
		484	struct radeon_bo_va {
		485	/* protected by bo being reserved */
		486	struct list_head bo_list;
		487	uint32_t flags;
5078	serge	488	uint64_t addr;
5271	serge	489	struct radeon_fence *last_pt_update;
2997	Serge	490	unsigned ref_count;
		491
		492	/* protected by vm mutex */
5078	serge	493	struct interval_tree_node it;
		494	struct list_head vm_status;
2997	Serge	495
		496	/* constant after initialization */
		497	struct radeon_vm *vm;
		498	struct radeon_bo *bo;
		499	};
		500
1321	serge	501	struct radeon_bo {
		502	/* Protected by gem.mutex */
		503	struct list_head list;
		504	/* Protected by tbo.reserved */
5078	serge	505	u32 initial_domain;
5271	serge	506	struct ttm_place placements[4];
6104	serge	507	struct ttm_placement placement;
		508	struct ttm_buffer_object tbo;
1321	serge	509	struct ttm_bo_kmap_obj kmap;
5078	serge	510	u32 flags;
6104	serge	511	unsigned pin_count;
		512	void *kptr;
		513	u32 tiling_flags;
		514	u32 pitch;
		515	int surface_reg;
2997	Serge	516	/* list of all virtual address to which this bo
		517	* is associated to
		518	*/
		519	struct list_head va;
1321	serge	520	/* Constant after initialization */
		521	struct radeon_device *rdev;
1963	serge	522	struct drm_gem_object gem_base;
3120	serge	523
5078	serge	524	pid_t pid;
5271	serge	525
		526	struct radeon_mn *mn;
6104	serge	527	struct list_head mn_list;
1321	serge	528	};
1963	serge	529	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
1321	serge	530
3764	Serge	531	int radeon_gem_debugfs_init(struct radeon_device *rdev);
		532
2997	Serge	533	/* sub-allocation manager, it has to be protected by another lock.
		534	* By conception this is an helper for other part of the driver
		535	* like the indirect buffer or semaphore, which both have their
		536	* locking.
		537	*
		538	* Principe is simple, we keep a list of sub allocation in offset
		539	* order (first entry has offset == 0, last entry has the highest
		540	* offset).
		541	*
		542	* When allocating new object we first check if there is room at
		543	* the end total_size - (last_object_offset + last_object_size) >=
		544	* alloc_size. If so we allocate new object there.
		545	*
		546	* When there is not enough room at the end, we start waiting for
		547	* each sub object until we reach object_offset+object_size >=
		548	* alloc_size, this object then become the sub object we return.
		549	*
		550	* Alignment can't be bigger than page size.
		551	*
		552	* Hole are not considered for allocation to keep things simple.
		553	* Assumption is that there won't be hole (all object on same
		554	* alignment).
		555	*/
		556	struct radeon_sa_manager {
		557	wait_queue_head_t wq;
		558	struct radeon_bo *bo;
		559	struct list_head *hole;
		560	struct list_head flist[RADEON_NUM_RINGS];
		561	struct list_head olist;
		562	unsigned size;
		563	uint64_t gpu_addr;
		564	void *cpu_ptr;
		565	uint32_t domain;
5078	serge	566	uint32_t align;
2997	Serge	567	};
		568
		569	struct radeon_sa_bo;
		570
		571	/* sub-allocation buffer */
		572	struct radeon_sa_bo {
		573	struct list_head olist;
		574	struct list_head flist;
		575	struct radeon_sa_manager *manager;
		576	unsigned soffset;
		577	unsigned eoffset;
		578	struct radeon_fence *fence;
		579	};
		580
1123	serge	581	/*
		582	* GEM objects.
		583	*/
		584	struct radeon_gem {
1630	serge	585	struct mutex mutex;
1123	serge	586	struct list_head objects;
		587	};
1117	serge	588
1126	serge	589	int radeon_gem_init(struct radeon_device *rdev);
		590	void radeon_gem_fini(struct radeon_device *rdev);
5078	serge	591	int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
6104	serge	592	int alignment, int initial_domain,
5078	serge	593	u32 flags, bool kernel,
6104	serge	594	struct drm_gem_object **obj);
1117	serge	595
2004	serge	596	int radeon_mode_dumb_create(struct drm_file *file_priv,
		597	struct drm_device *dev,
		598	struct drm_mode_create_dumb *args);
		599	int radeon_mode_dumb_mmap(struct drm_file *filp,
		600	struct drm_device *dev,
		601	uint32_t handle, uint64_t *offset_p);
1117	serge	602
		603	/*
2997	Serge	604	* Semaphores.
1117	serge	605	*/
2997	Serge	606	struct radeon_semaphore {
6104	serge	607	struct radeon_sa_bo *sa_bo;
		608	signed waiters;
		609	uint64_t gpu_addr;
1117	serge	610	};
		611
2997	Serge	612	int radeon_semaphore_create(struct radeon_device *rdev,
		613	struct radeon_semaphore **semaphore);
5078	serge	614	bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
2997	Serge	615	struct radeon_semaphore *semaphore);
5078	serge	616	bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
2997	Serge	617	struct radeon_semaphore *semaphore);
		618	void radeon_semaphore_free(struct radeon_device *rdev,
		619	struct radeon_semaphore **semaphore,
		620	struct radeon_fence *fence);
1117	serge	621
2997	Serge	622	/*
5271	serge	623	* Synchronization
		624	*/
		625	struct radeon_sync {
		626	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
		627	struct radeon_fence *sync_to[RADEON_NUM_RINGS];
		628	struct radeon_fence *last_vm_update;
		629	};
		630
		631	void radeon_sync_create(struct radeon_sync *sync);
		632	void radeon_sync_fence(struct radeon_sync *sync,
6104	serge	633	struct radeon_fence *fence);
5271	serge	634	int radeon_sync_resv(struct radeon_device *rdev,
		635	struct radeon_sync *sync,
		636	struct reservation_object *resv,
		637	bool shared);
		638	int radeon_sync_rings(struct radeon_device *rdev,
		639	struct radeon_sync *sync,
6104	serge	640	int waiting_ring);
5271	serge	641	void radeon_sync_free(struct radeon_device rdev, struct radeon_sync sync,
6104	serge	642	struct radeon_fence *fence);
5271	serge	643
		644	/*
2997	Serge	645	* GART structures, functions & helpers
		646	*/
		647	struct radeon_mc;
1117	serge	648
1268	serge	649	#define RADEON_GPU_PAGE_SIZE 4096
1430	serge	650	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
2997	Serge	651	#define RADEON_GPU_PAGE_SHIFT 12
		652	#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
1268	serge	653
5078	serge	654	#define RADEON_GART_PAGE_DUMMY 0
		655	#define RADEON_GART_PAGE_VALID (1 << 0)
		656	#define RADEON_GART_PAGE_READ (1 << 1)
		657	#define RADEON_GART_PAGE_WRITE (1 << 2)
		658	#define RADEON_GART_PAGE_SNOOP (1 << 3)
		659
1117	serge	660	struct radeon_gart {
6104	serge	661	dma_addr_t table_addr;
2997	Serge	662	struct radeon_bo *robj;
		663	void *ptr;
6104	serge	664	unsigned num_gpu_pages;
		665	unsigned num_cpu_pages;
		666	unsigned table_size;
		667	struct page **pages;
		668	uint64_t *pages_entry;
		669	bool ready;
1117	serge	670	};
		671
		672	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		673	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		674	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		675	void radeon_gart_table_vram_free(struct radeon_device *rdev);
2997	Serge	676	int radeon_gart_table_vram_pin(struct radeon_device *rdev);
		677	void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
1117	serge	678	int radeon_gart_init(struct radeon_device *rdev);
		679	void radeon_gart_fini(struct radeon_device *rdev);
		680	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		681	int pages);
1120	serge	682	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
5078	serge	683	int pages, struct page **pagelist,
		684	dma_addr_t *dma_addr, uint32_t flags);
1117	serge	685
		686
		687	/*
		688	* GPU MC structures, functions & helpers
		689	*/
		690	struct radeon_mc {
6104	serge	691	resource_size_t aper_size;
		692	resource_size_t aper_base;
		693	resource_size_t agp_base;
1179	serge	694	/* for some chips with <= 32MB we need to lie
		695	* about vram size near mc fb location */
		696	u64 mc_vram_size;
1430	serge	697	u64 visible_vram_size;
1179	serge	698	u64 gtt_size;
		699	u64 gtt_start;
		700	u64 gtt_end;
		701	u64 vram_start;
		702	u64 vram_end;
6104	serge	703	unsigned vram_width;
1179	serge	704	u64 real_vram_size;
6104	serge	705	int vram_mtrr;
		706	bool vram_is_ddr;
		707	bool igp_sideport_enabled;
1963	serge	708	u64 gtt_base_align;
3764	Serge	709	u64 mc_mask;
1117	serge	710	};
		711
1403	serge	712	bool radeon_combios_sideport_present(struct radeon_device *rdev);
		713	bool radeon_atombios_sideport_present(struct radeon_device *rdev);
1117	serge	714
		715	/*
		716	* GPU scratch registers structures, functions & helpers
		717	*/
		718	struct radeon_scratch {
6104	serge	719	unsigned num_reg;
1963	serge	720	uint32_t reg_base;
6104	serge	721	bool free[32];
		722	uint32_t reg[32];
1117	serge	723	};
		724
		725	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		726	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		727
5078	serge	728	/*
		729	* GPU doorbell structures, functions & helpers
		730	*/
		731	#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
1117	serge	732
5078	serge	733	struct radeon_doorbell {
		734	/* doorbell mmio */
6104	serge	735	resource_size_t base;
		736	resource_size_t size;
5078	serge	737	u32 __iomem *ptr;
		738	u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
6104	serge	739	DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
5078	serge	740	};
		741
		742	int radeon_doorbell_get(struct radeon_device rdev, u32 page);
		743	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
5271	serge	744	void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
		745	phys_addr_t *aperture_base,
		746	size_t *aperture_size,
		747	size_t *start_offset);
5078	serge	748
1117	serge	749	/*
		750	* IRQS.
		751	*/
1963	serge	752	struct r500_irq_stat_regs {
		753	u32 disp_int;
2997	Serge	754	u32 hdmi0_status;
1963	serge	755	};
		756
		757	struct r600_irq_stat_regs {
		758	u32 disp_int;
		759	u32 disp_int_cont;
		760	u32 disp_int_cont2;
		761	u32 d1grph_int;
		762	u32 d2grph_int;
2997	Serge	763	u32 hdmi0_status;
		764	u32 hdmi1_status;
1963	serge	765	};
		766
		767	struct evergreen_irq_stat_regs {
		768	u32 disp_int;
		769	u32 disp_int_cont;
		770	u32 disp_int_cont2;
		771	u32 disp_int_cont3;
		772	u32 disp_int_cont4;
		773	u32 disp_int_cont5;
		774	u32 d1grph_int;
		775	u32 d2grph_int;
		776	u32 d3grph_int;
		777	u32 d4grph_int;
		778	u32 d5grph_int;
		779	u32 d6grph_int;
2997	Serge	780	u32 afmt_status1;
		781	u32 afmt_status2;
		782	u32 afmt_status3;
		783	u32 afmt_status4;
		784	u32 afmt_status5;
		785	u32 afmt_status6;
1963	serge	786	};
		787
5078	serge	788	struct cik_irq_stat_regs {
		789	u32 disp_int;
		790	u32 disp_int_cont;
		791	u32 disp_int_cont2;
		792	u32 disp_int_cont3;
		793	u32 disp_int_cont4;
		794	u32 disp_int_cont5;
		795	u32 disp_int_cont6;
		796	u32 d1grph_int;
		797	u32 d2grph_int;
		798	u32 d3grph_int;
		799	u32 d4grph_int;
		800	u32 d5grph_int;
		801	u32 d6grph_int;
		802	};
		803
1963	serge	804	union radeon_irq_stat_regs {
		805	struct r500_irq_stat_regs r500;
		806	struct r600_irq_stat_regs r600;
		807	struct evergreen_irq_stat_regs evergreen;
5078	serge	808	struct cik_irq_stat_regs cik;
1963	serge	809	};
		810
1117	serge	811	struct radeon_irq {
6104	serge	812	bool installed;
2997	Serge	813	spinlock_t lock;
		814	atomic_t ring_int[RADEON_NUM_RINGS];
		815	bool crtc_vblank_int[RADEON_MAX_CRTCS];
		816	atomic_t pflip[RADEON_MAX_CRTCS];
6104	serge	817	wait_queue_head_t vblank_queue;
2997	Serge	818	bool hpd[RADEON_MAX_HPD_PINS];
		819	bool afmt[RADEON_MAX_AFMT_BLOCKS];
6104	serge	820	union radeon_irq_stat_regs stat_regs;
5078	serge	821	bool dpm_thermal;
1117	serge	822	};
		823
		824	int radeon_irq_kms_init(struct radeon_device *rdev);
		825	void radeon_irq_kms_fini(struct radeon_device *rdev);
2997	Serge	826	void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
5271	serge	827	bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
2997	Serge	828	void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
2004	serge	829	void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
		830	void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
2997	Serge	831	void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
		832	void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
		833	void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
		834	void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
1117	serge	835
		836	/*
2997	Serge	837	* CP & rings.
1117	serge	838	*/
2997	Serge	839
1117	serge	840	struct radeon_ib {
2997	Serge	841	struct radeon_sa_bo *sa_bo;
6104	serge	842	uint32_t length_dw;
		843	uint64_t gpu_addr;
		844	uint32_t *ptr;
2997	Serge	845	int ring;
6104	serge	846	struct radeon_fence *fence;
2997	Serge	847	struct radeon_vm *vm;
6104	serge	848	bool is_const_ib;
5271	serge	849	struct radeon_sync sync;
1117	serge	850	};
		851
2997	Serge	852	struct radeon_ring {
1321	serge	853	struct radeon_bo *ring_obj;
1117	serge	854	volatile uint32_t *ring;
2997	Serge	855	unsigned rptr_offs;
		856	unsigned rptr_save_reg;
		857	u64 next_rptr_gpu_addr;
		858	volatile u32 *next_rptr_cpu_addr;
5078	serge	859	unsigned wptr;
		860	unsigned wptr_old;
		861	unsigned ring_size;
		862	unsigned ring_free_dw;
		863	int count_dw;
		864	atomic_t last_rptr;
		865	atomic64_t last_activity;
		866	uint64_t gpu_addr;
		867	uint32_t align_mask;
		868	uint32_t ptr_mask;
		869	bool ready;
2997	Serge	870	u32 nop;
		871	u32 idx;
3764	Serge	872	u64 last_semaphore_signal_addr;
		873	u64 last_semaphore_wait_addr;
5078	serge	874	/* for CIK queues */
		875	u32 me;
		876	u32 pipe;
		877	u32 queue;
		878	struct radeon_bo *mqd_obj;
		879	u32 doorbell_index;
		880	unsigned wptr_offs;
1117	serge	881	};
		882
5078	serge	883	struct radeon_mec {
		884	struct radeon_bo *hpd_eop_obj;
		885	u64 hpd_eop_gpu_addr;
		886	u32 num_pipe;
		887	u32 num_mec;
		888	u32 num_queue;
		889	};
		890
1321	serge	891	/*
2997	Serge	892	* VM
		893	*/
		894
		895	/* maximum number of VMIDs */
		896	#define RADEON_NUM_VM 16
		897
		898	/* number of entries in page table */
5078	serge	899	#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
2997	Serge	900
5078	serge	901	/* PTBs (Page Table Blocks) need to be aligned to 32K */
		902	#define RADEON_VM_PTB_ALIGN_SIZE 32768
		903	#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
		904	#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
		905
		906	#define R600_PTE_VALID (1 << 0)
		907	#define R600_PTE_SYSTEM (1 << 1)
		908	#define R600_PTE_SNOOPED (1 << 2)
		909	#define R600_PTE_READABLE (1 << 5)
		910	#define R600_PTE_WRITEABLE (1 << 6)
		911
		912	/* PTE (Page Table Entry) fragment field for different page sizes */
		913	#define R600_PTE_FRAG_4KB (0 << 7)
		914	#define R600_PTE_FRAG_64KB (4 << 7)
		915	#define R600_PTE_FRAG_256KB (6 << 7)
		916
		917	/* flags needed to be set so we can copy directly from the GART table */
		918	#define R600_PTE_GART_MASK ( R600_PTE_READABLE \| R600_PTE_WRITEABLE \| \
		919	R600_PTE_SYSTEM \| R600_PTE_VALID )
		920
		921	struct radeon_vm_pt {
		922	struct radeon_bo *bo;
		923	uint64_t addr;
		924	};
		925
5271	serge	926	struct radeon_vm_id {
		927	unsigned id;
		928	uint64_t pd_gpu_addr;
		929	/* last flushed PD/PT update */
		930	struct radeon_fence *flushed_updates;
		931	/* last use of vmid */
		932	struct radeon_fence *last_id_use;
		933	};
		934
2997	Serge	935	struct radeon_vm {
5271	serge	936	struct mutex mutex;
		937
6104	serge	938	struct rb_root va;
2997	Serge	939
5271	serge	940	/* protecting invalidated and freed */
		941	spinlock_t status_lock;
		942
5078	serge	943	/* BOs moved, but not yet updated in the PT */
6104	serge	944	struct list_head invalidated;
5078	serge	945
		946	/* BOs freed, but not yet updated in the PT */
6104	serge	947	struct list_head freed;
5078	serge	948
6104	serge	949	/* BOs cleared in the PT */
		950	struct list_head cleared;
		951
2997	Serge	952	/* contains the page directory */
6104	serge	953	struct radeon_bo *page_directory;
		954	unsigned max_pde_used;
2997	Serge	955
		956	/* array of page tables, one for each page directory entry */
6104	serge	957	struct radeon_vm_pt *page_tables;
2997	Serge	958
6104	serge	959	struct radeon_bo_va *ib_bo_va;
5078	serge	960
5271	serge	961	/* for id and flush management per ring */
		962	struct radeon_vm_id ids[RADEON_NUM_RINGS];
2997	Serge	963	};
		964
		965	struct radeon_vm_manager {
		966	struct radeon_fence *active[RADEON_NUM_VM];
		967	uint32_t max_pfn;
		968	/* number of VMIDs */
		969	unsigned nvm;
		970	/* vram base address for page table entry */
		971	u64 vram_base_offset;
		972	/* is vm enabled? */
		973	bool enabled;
5078	serge	974	/* for hw to save the PD addr on suspend/resume */
		975	uint32_t saved_table_addr[RADEON_NUM_VM];
2997	Serge	976	};
		977
		978	/*
		979	* file private structure
		980	*/
		981	struct radeon_fpriv {
		982	struct radeon_vm vm;
		983	};
		984
		985	/*
1321	serge	986	* R6xx+ IH ring
		987	*/
		988	struct r600_ih {
		989	struct radeon_bo *ring_obj;
		990	volatile uint32_t *ring;
6104	serge	991	unsigned rptr;
		992	unsigned ring_size;
		993	uint64_t gpu_addr;
		994	uint32_t ptr_mask;
2997	Serge	995	atomic_t lock;
6104	serge	996	bool enabled;
1321	serge	997	};
		998
2997	Serge	999	/*
5078	serge	1000	* RLC stuff
2997	Serge	1001	*/
5078	serge	1002	#include "clearstate_defs.h"
		1003
		1004	struct radeon_rlc {
2997	Serge	1005	/* for power gating */
		1006	struct radeon_bo *save_restore_obj;
		1007	uint64_t save_restore_gpu_addr;
5078	serge	1008	volatile uint32_t *sr_ptr;
		1009	const u32 *reg_list;
		1010	u32 reg_list_size;
2997	Serge	1011	/* for clear state */
		1012	struct radeon_bo *clear_state_obj;
		1013	uint64_t clear_state_gpu_addr;
5078	serge	1014	volatile uint32_t *cs_ptr;
		1015	const struct cs_section_def *cs_data;
		1016	u32 clear_state_size;
		1017	/* for cp tables */
		1018	struct radeon_bo *cp_table_obj;
		1019	uint64_t cp_table_gpu_addr;
		1020	volatile uint32_t *cp_table_ptr;
		1021	u32 cp_table_size;
2997	Serge	1022	};
		1023
		1024	int radeon_ib_get(struct radeon_device *rdev, int ring,
		1025	struct radeon_ib ib, struct radeon_vm vm,
		1026	unsigned size);
		1027	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib);
		1028	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
5078	serge	1029	struct radeon_ib *const_ib, bool hdp_flush);
1117	serge	1030	int radeon_ib_pool_init(struct radeon_device *rdev);
		1031	void radeon_ib_pool_fini(struct radeon_device *rdev);
2997	Serge	1032	int radeon_ib_ring_tests(struct radeon_device *rdev);
1117	serge	1033	/* Ring access between begin & end cannot sleep */
2997	Serge	1034	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
		1035	struct radeon_ring *ring);
		1036	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring cp);
		1037	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		1038	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
5078	serge	1039	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring cp,
		1040	bool hdp_flush);
		1041	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring cp,
		1042	bool hdp_flush);
2997	Serge	1043	void radeon_ring_undo(struct radeon_ring *ring);
		1044	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring cp);
		1045	int radeon_ring_test(struct radeon_device rdev, struct radeon_ring cp);
5078	serge	1046	void radeon_ring_lockup_update(struct radeon_device *rdev,
		1047	struct radeon_ring *ring);
2997	Serge	1048	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring);
		1049	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
		1050	uint32_t **data);
		1051	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
		1052	unsigned size, uint32_t *data);
		1053	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring cp, unsigned ring_size,
5078	serge	1054	unsigned rptr_offs, u32 nop);
2997	Serge	1055	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring cp);
1117	serge	1056
		1057
3192	Serge	1058	/* r600 async dma */
		1059	void r600_dma_stop(struct radeon_device *rdev);
		1060	int r600_dma_resume(struct radeon_device *rdev);
		1061	void r600_dma_fini(struct radeon_device *rdev);
		1062
		1063	void cayman_dma_stop(struct radeon_device *rdev);
		1064	int cayman_dma_resume(struct radeon_device *rdev);
		1065	void cayman_dma_fini(struct radeon_device *rdev);
		1066
1117	serge	1067	/*
		1068	* CS.
		1069	*/
		1070	struct radeon_cs_chunk {
		1071	uint32_t length_dw;
		1072	uint32_t *kdata;
6104	serge	1073	void __user *user_ptr;
1117	serge	1074	};
		1075
		1076	struct radeon_cs_parser {
1430	serge	1077	struct device *dev;
1117	serge	1078	struct radeon_device *rdev;
2004	serge	1079	struct drm_file *filp;
1117	serge	1080	/* chunks */
		1081	unsigned nchunks;
		1082	struct radeon_cs_chunk *chunks;
		1083	uint64_t *chunks_array;
		1084	/* IB */
		1085	unsigned idx;
		1086	/* relocations */
		1087	unsigned nrelocs;
5271	serge	1088	struct radeon_bo_list *relocs;
		1089	struct radeon_bo_list *vm_bos;
1120	serge	1090	struct list_head validated;
3192	Serge	1091	unsigned dma_reloc_idx;
1117	serge	1092	/* indices of various chunks */
5271	serge	1093	struct radeon_cs_chunk *chunk_ib;
		1094	struct radeon_cs_chunk *chunk_relocs;
		1095	struct radeon_cs_chunk *chunk_flags;
		1096	struct radeon_cs_chunk *chunk_const_ib;
2997	Serge	1097	struct radeon_ib ib;
		1098	struct radeon_ib const_ib;
1117	serge	1099	void *track;
1179	serge	1100	unsigned family;
6104	serge	1101	int parser_error;
2997	Serge	1102	u32 cs_flags;
		1103	u32 ring;
		1104	s32 priority;
5078	serge	1105	struct ww_acquire_ctx ticket;
1117	serge	1106	};
		1107
5078	serge	1108	static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
		1109	{
5271	serge	1110	struct radeon_cs_chunk *ibc = p->chunk_ib;
1221	serge	1111
5078	serge	1112	if (ibc->kdata)
		1113	return ibc->kdata[idx];
		1114	return p->ib.ptr[idx];
		1115	}
		1116
		1117
1117	serge	1118	struct radeon_cs_packet {
		1119	unsigned idx;
		1120	unsigned type;
		1121	unsigned reg;
		1122	unsigned opcode;
		1123	int count;
		1124	unsigned one_reg_wr;
		1125	};
		1126
		1127	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		1128	struct radeon_cs_packet *pkt,
		1129	unsigned idx, unsigned reg);
		1130	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		1131	struct radeon_cs_packet *pkt);
		1132
		1133
		1134	/*
		1135	* AGP
		1136	*/
		1137	int radeon_agp_init(struct radeon_device *rdev);
1321	serge	1138	void radeon_agp_resume(struct radeon_device *rdev);
1963	serge	1139	void radeon_agp_suspend(struct radeon_device *rdev);
1117	serge	1140	void radeon_agp_fini(struct radeon_device *rdev);
		1141
		1142
		1143	/*
		1144	* Writeback
		1145	*/
		1146	struct radeon_wb {
1321	serge	1147	struct radeon_bo *wb_obj;
1117	serge	1148	volatile uint32_t *wb;
		1149	uint64_t gpu_addr;
1963	serge	1150	bool enabled;
		1151	bool use_event;
1117	serge	1152	};
		1153
1963	serge	1154	#define RADEON_WB_SCRATCH_OFFSET 0
2997	Serge	1155	#define RADEON_WB_RING0_NEXT_RPTR 256
1963	serge	1156	#define RADEON_WB_CP_RPTR_OFFSET 1024
		1157	#define RADEON_WB_CP1_RPTR_OFFSET 1280
		1158	#define RADEON_WB_CP2_RPTR_OFFSET 1536
3192	Serge	1159	#define R600_WB_DMA_RPTR_OFFSET 1792
1963	serge	1160	#define R600_WB_IH_WPTR_OFFSET 2048
3192	Serge	1161	#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1963	serge	1162	#define R600_WB_EVENT_OFFSET 3072
5078	serge	1163	#define CIK_WB_CP1_WPTR_OFFSET 3328
		1164	#define CIK_WB_CP2_WPTR_OFFSET 3584
5179	serge	1165	#define R600_WB_DMA_RING_TEST_OFFSET 3588
		1166	#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1963	serge	1167
1179	serge	1168	/**
		1169	* struct radeon_pm - power management datas
		1170	* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
		1171	* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
		1172	* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
		1173	* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
		1174	* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
		1175	* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
		1176	* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
		1177	* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
		1178	* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1963	serge	1179	* @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1179	serge	1180	* @needed_bandwidth: current bandwidth needs
		1181	*
		1182	* It keeps track of various data needed to take powermanagement decision.
1963	serge	1183	* Bandwidth need is used to determine minimun clock of the GPU and memory.
1179	serge	1184	* Equation between gpu/memory clock and available bandwidth is hw dependent
		1185	* (type of memory, bus size, efficiency, ...)
		1186	*/
1963	serge	1187
		1188	enum radeon_pm_method {
		1189	PM_METHOD_PROFILE,
		1190	PM_METHOD_DYNPM,
5078	serge	1191	PM_METHOD_DPM,
1430	serge	1192	};
1963	serge	1193
		1194	enum radeon_dynpm_state {
		1195	DYNPM_STATE_DISABLED,
		1196	DYNPM_STATE_MINIMUM,
		1197	DYNPM_STATE_PAUSED,
		1198	DYNPM_STATE_ACTIVE,
		1199	DYNPM_STATE_SUSPENDED,
1430	serge	1200	};
1963	serge	1201	enum radeon_dynpm_action {
		1202	DYNPM_ACTION_NONE,
		1203	DYNPM_ACTION_MINIMUM,
		1204	DYNPM_ACTION_DOWNCLOCK,
		1205	DYNPM_ACTION_UPCLOCK,
		1206	DYNPM_ACTION_DEFAULT
		1207	};
1430	serge	1208
		1209	enum radeon_voltage_type {
		1210	VOLTAGE_NONE = 0,
		1211	VOLTAGE_GPIO,
		1212	VOLTAGE_VDDC,
		1213	VOLTAGE_SW
		1214	};
		1215
		1216	enum radeon_pm_state_type {
5078	serge	1217	/* not used for dpm */
1430	serge	1218	POWER_STATE_TYPE_DEFAULT,
		1219	POWER_STATE_TYPE_POWERSAVE,
5078	serge	1220	/* user selectable states */
1430	serge	1221	POWER_STATE_TYPE_BATTERY,
		1222	POWER_STATE_TYPE_BALANCED,
		1223	POWER_STATE_TYPE_PERFORMANCE,
5078	serge	1224	/* internal states */
		1225	POWER_STATE_TYPE_INTERNAL_UVD,
		1226	POWER_STATE_TYPE_INTERNAL_UVD_SD,
		1227	POWER_STATE_TYPE_INTERNAL_UVD_HD,
		1228	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
		1229	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
		1230	POWER_STATE_TYPE_INTERNAL_BOOT,
		1231	POWER_STATE_TYPE_INTERNAL_THERMAL,
		1232	POWER_STATE_TYPE_INTERNAL_ACPI,
		1233	POWER_STATE_TYPE_INTERNAL_ULV,
		1234	POWER_STATE_TYPE_INTERNAL_3DPERF,
1430	serge	1235	};
		1236
1963	serge	1237	enum radeon_pm_profile_type {
		1238	PM_PROFILE_DEFAULT,
		1239	PM_PROFILE_AUTO,
		1240	PM_PROFILE_LOW,
		1241	PM_PROFILE_MID,
		1242	PM_PROFILE_HIGH,
1430	serge	1243	};
		1244
1963	serge	1245	#define PM_PROFILE_DEFAULT_IDX 0
		1246	#define PM_PROFILE_LOW_SH_IDX 1
		1247	#define PM_PROFILE_MID_SH_IDX 2
		1248	#define PM_PROFILE_HIGH_SH_IDX 3
		1249	#define PM_PROFILE_LOW_MH_IDX 4
		1250	#define PM_PROFILE_MID_MH_IDX 5
		1251	#define PM_PROFILE_HIGH_MH_IDX 6
		1252	#define PM_PROFILE_MAX 7
		1253
		1254	struct radeon_pm_profile {
		1255	int dpms_off_ps_idx;
		1256	int dpms_on_ps_idx;
		1257	int dpms_off_cm_idx;
		1258	int dpms_on_cm_idx;
		1259	};
		1260
		1261	enum radeon_int_thermal_type {
		1262	THERMAL_TYPE_NONE,
5078	serge	1263	THERMAL_TYPE_EXTERNAL,
		1264	THERMAL_TYPE_EXTERNAL_GPIO,
1963	serge	1265	THERMAL_TYPE_RV6XX,
		1266	THERMAL_TYPE_RV770,
5078	serge	1267	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1963	serge	1268	THERMAL_TYPE_EVERGREEN,
		1269	THERMAL_TYPE_SUMO,
		1270	THERMAL_TYPE_NI,
2997	Serge	1271	THERMAL_TYPE_SI,
5078	serge	1272	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
		1273	THERMAL_TYPE_CI,
		1274	THERMAL_TYPE_KV,
1963	serge	1275	};
		1276
1430	serge	1277	struct radeon_voltage {
		1278	enum radeon_voltage_type type;
		1279	/* gpio voltage */
		1280	struct radeon_gpio_rec gpio;
		1281	u32 delay; /* delay in usec from voltage drop to sclk change */
		1282	bool active_high; /* voltage drop is active when bit is high */
		1283	/* VDDC voltage */
		1284	u8 vddc_id; /* index into vddc voltage table */
		1285	u8 vddci_id; /* index into vddci voltage table */
		1286	bool vddci_enabled;
		1287	/* r6xx+ sw */
1963	serge	1288	u16 voltage;
		1289	/* evergreen+ vddci */
		1290	u16 vddci;
1430	serge	1291	};
		1292
1963	serge	1293	/* clock mode flags */
		1294	#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1430	serge	1295
		1296	struct radeon_pm_clock_info {
		1297	/* memory clock */
		1298	u32 mclk;
		1299	/* engine clock */
		1300	u32 sclk;
		1301	/* voltage info */
		1302	struct radeon_voltage voltage;
1963	serge	1303	/* standardized clock flags */
1430	serge	1304	u32 flags;
		1305	};
		1306
1963	serge	1307	/* state flags */
		1308	#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
		1309
1430	serge	1310	struct radeon_power_state {
		1311	enum radeon_pm_state_type type;
2997	Serge	1312	struct radeon_pm_clock_info *clock_info;
1430	serge	1313	/* number of valid clock modes in this power state */
		1314	int num_clock_modes;
		1315	struct radeon_pm_clock_info *default_clock_mode;
1963	serge	1316	/* standardized state flags */
		1317	u32 flags;
		1318	u32 misc; /* vbios specific flags */
		1319	u32 misc2; /* vbios specific flags */
		1320	int pcie_lanes; /* pcie lanes */
1430	serge	1321	};
		1322
		1323	/*
		1324	* Some modes are overclocked by very low value, accept them
		1325	*/
		1326	#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
		1327
5078	serge	1328	enum radeon_dpm_auto_throttle_src {
		1329	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
		1330	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
		1331	};
		1332
		1333	enum radeon_dpm_event_src {
		1334	RADEON_DPM_EVENT_SRC_ANALOG = 0,
		1335	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
		1336	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
		1337	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
		1338	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		1339	};
		1340
		1341	#define RADEON_MAX_VCE_LEVELS 6
		1342
		1343	enum radeon_vce_level {
		1344	RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
		1345	RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
		1346	RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
		1347	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
		1348	RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
		1349	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
		1350	};
		1351
		1352	struct radeon_ps {
		1353	u32 caps; /* vbios flags */
		1354	u32 class; /* vbios flags */
		1355	u32 class2; /* vbios flags */
		1356	/* UVD clocks */
		1357	u32 vclk;
		1358	u32 dclk;
		1359	/* VCE clocks */
		1360	u32 evclk;
		1361	u32 ecclk;
		1362	bool vce_active;
		1363	enum radeon_vce_level vce_level;
		1364	/* asic priv */
		1365	void *ps_priv;
		1366	};
		1367
		1368	struct radeon_dpm_thermal {
		1369	/* thermal interrupt work */
		1370	struct work_struct work;
		1371	/* low temperature threshold */
		1372	int min_temp;
		1373	/* high temperature threshold */
		1374	int max_temp;
		1375	/* was interrupt low to high or high to low */
		1376	bool high_to_low;
		1377	};
		1378
		1379	enum radeon_clk_action
		1380	{
		1381	RADEON_SCLK_UP = 1,
		1382	RADEON_SCLK_DOWN
		1383	};
		1384
		1385	struct radeon_blacklist_clocks
		1386	{
		1387	u32 sclk;
		1388	u32 mclk;
		1389	enum radeon_clk_action action;
		1390	};
		1391
		1392	struct radeon_clock_and_voltage_limits {
		1393	u32 sclk;
		1394	u32 mclk;
		1395	u16 vddc;
		1396	u16 vddci;
		1397	};
		1398
		1399	struct radeon_clock_array {
		1400	u32 count;
		1401	u32 *values;
		1402	};
		1403
		1404	struct radeon_clock_voltage_dependency_entry {
		1405	u32 clk;
		1406	u16 v;
		1407	};
		1408
		1409	struct radeon_clock_voltage_dependency_table {
		1410	u32 count;
		1411	struct radeon_clock_voltage_dependency_entry *entries;
		1412	};
		1413
		1414	union radeon_cac_leakage_entry {
		1415	struct {
		1416	u16 vddc;
		1417	u32 leakage;
		1418	};
		1419	struct {
		1420	u16 vddc1;
		1421	u16 vddc2;
		1422	u16 vddc3;
		1423	};
		1424	};
		1425
		1426	struct radeon_cac_leakage_table {
		1427	u32 count;
		1428	union radeon_cac_leakage_entry *entries;
		1429	};
		1430
		1431	struct radeon_phase_shedding_limits_entry {
		1432	u16 voltage;
		1433	u32 sclk;
		1434	u32 mclk;
		1435	};
		1436
		1437	struct radeon_phase_shedding_limits_table {
		1438	u32 count;
		1439	struct radeon_phase_shedding_limits_entry *entries;
		1440	};
		1441
		1442	struct radeon_uvd_clock_voltage_dependency_entry {
		1443	u32 vclk;
		1444	u32 dclk;
		1445	u16 v;
		1446	};
		1447
		1448	struct radeon_uvd_clock_voltage_dependency_table {
		1449	u8 count;
		1450	struct radeon_uvd_clock_voltage_dependency_entry *entries;
		1451	};
		1452
		1453	struct radeon_vce_clock_voltage_dependency_entry {
		1454	u32 ecclk;
		1455	u32 evclk;
		1456	u16 v;
		1457	};
		1458
		1459	struct radeon_vce_clock_voltage_dependency_table {
		1460	u8 count;
		1461	struct radeon_vce_clock_voltage_dependency_entry *entries;
		1462	};
		1463
		1464	struct radeon_ppm_table {
		1465	u8 ppm_design;
		1466	u16 cpu_core_number;
		1467	u32 platform_tdp;
		1468	u32 small_ac_platform_tdp;
		1469	u32 platform_tdc;
		1470	u32 small_ac_platform_tdc;
		1471	u32 apu_tdp;
		1472	u32 dgpu_tdp;
		1473	u32 dgpu_ulv_power;
		1474	u32 tj_max;
		1475	};
		1476
		1477	struct radeon_cac_tdp_table {
		1478	u16 tdp;
		1479	u16 configurable_tdp;
		1480	u16 tdc;
		1481	u16 battery_power_limit;
		1482	u16 small_power_limit;
		1483	u16 low_cac_leakage;
		1484	u16 high_cac_leakage;
		1485	u16 maximum_power_delivery_limit;
		1486	};
		1487
		1488	struct radeon_dpm_dynamic_state {
		1489	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
		1490	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
		1491	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
		1492	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
		1493	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
		1494	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
		1495	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
		1496	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
		1497	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
		1498	struct radeon_clock_array valid_sclk_values;
		1499	struct radeon_clock_array valid_mclk_values;
		1500	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
		1501	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
		1502	u32 mclk_sclk_ratio;
		1503	u32 sclk_mclk_delta;
		1504	u16 vddc_vddci_delta;
		1505	u16 min_vddc_for_pcie_gen2;
		1506	struct radeon_cac_leakage_table cac_leakage_table;
		1507	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
		1508	struct radeon_ppm_table *ppm_table;
		1509	struct radeon_cac_tdp_table *cac_tdp_table;
		1510	};
		1511
		1512	struct radeon_dpm_fan {
		1513	u16 t_min;
		1514	u16 t_med;
		1515	u16 t_high;
		1516	u16 pwm_min;
		1517	u16 pwm_med;
		1518	u16 pwm_high;
		1519	u8 t_hyst;
		1520	u32 cycle_delay;
		1521	u16 t_max;
5271	serge	1522	u8 control_mode;
		1523	u16 default_max_fan_pwm;
		1524	u16 default_fan_output_sensitivity;
		1525	u16 fan_output_sensitivity;
5078	serge	1526	bool ucode_fan_control;
		1527	};
		1528
		1529	enum radeon_pcie_gen {
		1530	RADEON_PCIE_GEN1 = 0,
		1531	RADEON_PCIE_GEN2 = 1,
		1532	RADEON_PCIE_GEN3 = 2,
		1533	RADEON_PCIE_GEN_INVALID = 0xffff
		1534	};
		1535
		1536	enum radeon_dpm_forced_level {
		1537	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
		1538	RADEON_DPM_FORCED_LEVEL_LOW = 1,
		1539	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
		1540	};
		1541
		1542	struct radeon_vce_state {
		1543	/* vce clocks */
		1544	u32 evclk;
		1545	u32 ecclk;
		1546	/* gpu clocks */
		1547	u32 sclk;
		1548	u32 mclk;
		1549	u8 clk_idx;
		1550	u8 pstate;
		1551	};
		1552
		1553	struct radeon_dpm {
		1554	struct radeon_ps *ps;
		1555	/* number of valid power states */
		1556	int num_ps;
		1557	/* current power state that is active */
		1558	struct radeon_ps *current_ps;
		1559	/* requested power state */
		1560	struct radeon_ps *requested_ps;
		1561	/* boot up power state */
		1562	struct radeon_ps *boot_ps;
		1563	/* default uvd power state */
		1564	struct radeon_ps *uvd_ps;
		1565	/* vce requirements */
		1566	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
		1567	enum radeon_vce_level vce_level;
		1568	enum radeon_pm_state_type state;
		1569	enum radeon_pm_state_type user_state;
		1570	u32 platform_caps;
		1571	u32 voltage_response_time;
		1572	u32 backbias_response_time;
		1573	void *priv;
		1574	u32 new_active_crtcs;
		1575	int new_active_crtc_count;
		1576	u32 current_active_crtcs;
		1577	int current_active_crtc_count;
6104	serge	1578	bool single_display;
5078	serge	1579	struct radeon_dpm_dynamic_state dyn_state;
		1580	struct radeon_dpm_fan fan;
		1581	u32 tdp_limit;
		1582	u32 near_tdp_limit;
		1583	u32 near_tdp_limit_adjusted;
		1584	u32 sq_ramping_threshold;
		1585	u32 cac_leakage;
		1586	u16 tdp_od_limit;
		1587	u32 tdp_adjustment;
		1588	u16 load_line_slope;
		1589	bool power_control;
		1590	bool ac_power;
		1591	/* special states active */
		1592	bool thermal_active;
		1593	bool uvd_active;
		1594	bool vce_active;
		1595	/* thermal handling */
		1596	struct radeon_dpm_thermal thermal;
		1597	/* forced levels */
		1598	enum radeon_dpm_forced_level forced_level;
		1599	/* track UVD streams */
		1600	unsigned sd;
		1601	unsigned hd;
		1602	};
		1603
		1604	void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
		1605	void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
		1606
1179	serge	1607	struct radeon_pm {
1630	serge	1608	struct mutex mutex;
2997	Serge	1609	/* write locked while reprogramming mclk */
		1610	struct rw_semaphore mclk_lock;
1963	serge	1611	u32 active_crtcs;
		1612	int active_crtc_count;
1430	serge	1613	int req_vblank;
1963	serge	1614	bool vblank_sync;
1179	serge	1615	fixed20_12 max_bandwidth;
		1616	fixed20_12 igp_sideport_mclk;
		1617	fixed20_12 igp_system_mclk;
		1618	fixed20_12 igp_ht_link_clk;
		1619	fixed20_12 igp_ht_link_width;
		1620	fixed20_12 k8_bandwidth;
		1621	fixed20_12 sideport_bandwidth;
		1622	fixed20_12 ht_bandwidth;
		1623	fixed20_12 core_bandwidth;
		1624	fixed20_12 sclk;
1963	serge	1625	fixed20_12 mclk;
1179	serge	1626	fixed20_12 needed_bandwidth;
1963	serge	1627	struct radeon_power_state *power_state;
1430	serge	1628	/* number of valid power states */
		1629	int num_power_states;
1963	serge	1630	int current_power_state_index;
		1631	int current_clock_mode_index;
		1632	int requested_power_state_index;
		1633	int requested_clock_mode_index;
		1634	int default_power_state_index;
		1635	u32 current_sclk;
		1636	u32 current_mclk;
		1637	u16 current_vddc;
		1638	u16 current_vddci;
		1639	u32 default_sclk;
		1640	u32 default_mclk;
		1641	u16 default_vddc;
		1642	u16 default_vddci;
		1643	struct radeon_i2c_chan *i2c_bus;
		1644	/* selected pm method */
		1645	enum radeon_pm_method pm_method;
		1646	/* dynpm power management */
5078	serge	1647	struct delayed_work dynpm_idle_work;
1963	serge	1648	enum radeon_dynpm_state dynpm_state;
		1649	enum radeon_dynpm_action dynpm_planned_action;
		1650	unsigned long dynpm_action_timeout;
		1651	bool dynpm_can_upclock;
		1652	bool dynpm_can_downclock;
		1653	/* profile-based power management */
		1654	enum radeon_pm_profile_type profile;
		1655	int profile_index;
		1656	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
		1657	/* internal thermal controller on rv6xx+ */
		1658	enum radeon_int_thermal_type int_thermal_type;
		1659	struct device *int_hwmon_dev;
5271	serge	1660	/* fan control parameters */
		1661	bool no_fan;
		1662	u8 fan_pulses_per_revolution;
		1663	u8 fan_min_rpm;
		1664	u8 fan_max_rpm;
5078	serge	1665	/* dpm */
		1666	bool dpm_enabled;
6104	serge	1667	bool sysfs_initialized;
5078	serge	1668	struct radeon_dpm dpm;
1179	serge	1669	};
1117	serge	1670
2997	Serge	1671	int radeon_pm_get_type_index(struct radeon_device *rdev,
		1672	enum radeon_pm_state_type ps_type,
		1673	int instance);
3764	Serge	1674	/*
		1675	* UVD
		1676	*/
		1677	#define RADEON_MAX_UVD_HANDLES 10
		1678	#define RADEON_UVD_STACK_SIZE (1024*1024)
		1679	#define RADEON_UVD_HEAP_SIZE (1024*1024)
2997	Serge	1680
3764	Serge	1681	struct radeon_uvd {
		1682	struct radeon_bo *vcpu_bo;
		1683	void *cpu_addr;
		1684	uint64_t gpu_addr;
		1685	atomic_t handles[RADEON_MAX_UVD_HANDLES];
		1686	struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
5078	serge	1687	unsigned img_size[RADEON_MAX_UVD_HANDLES];
3764	Serge	1688	struct delayed_work idle_work;
		1689	};
		1690
		1691	int radeon_uvd_init(struct radeon_device *rdev);
		1692	void radeon_uvd_fini(struct radeon_device *rdev);
		1693	int radeon_uvd_suspend(struct radeon_device *rdev);
		1694	int radeon_uvd_resume(struct radeon_device *rdev);
		1695	int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
		1696	uint32_t handle, struct radeon_fence **fence);
		1697	int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
		1698	uint32_t handle, struct radeon_fence **fence);
5271	serge	1699	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
		1700	uint32_t allowed_domains);
3764	Serge	1701	void radeon_uvd_free_handles(struct radeon_device *rdev,
		1702	struct drm_file *filp);
		1703	int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
		1704	void radeon_uvd_note_usage(struct radeon_device *rdev);
		1705	int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
		1706	unsigned vclk, unsigned dclk,
		1707	unsigned vco_min, unsigned vco_max,
		1708	unsigned fb_factor, unsigned fb_mask,
		1709	unsigned pd_min, unsigned pd_max,
		1710	unsigned pd_even,
		1711	unsigned *optimal_fb_div,
		1712	unsigned *optimal_vclk_div,
		1713	unsigned *optimal_dclk_div);
		1714	int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
		1715	unsigned cg_upll_func_cntl);
		1716
5078	serge	1717	/*
		1718	* VCE
		1719	*/
		1720	#define RADEON_MAX_VCE_HANDLES 16
		1721
		1722	struct radeon_vce {
		1723	struct radeon_bo *vcpu_bo;
		1724	uint64_t gpu_addr;
		1725	unsigned fw_version;
		1726	unsigned fb_version;
		1727	atomic_t handles[RADEON_MAX_VCE_HANDLES];
		1728	struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
		1729	unsigned img_size[RADEON_MAX_VCE_HANDLES];
		1730	struct delayed_work idle_work;
6104	serge	1731	uint32_t keyselect;
5078	serge	1732	};
		1733
		1734	int radeon_vce_init(struct radeon_device *rdev);
		1735	void radeon_vce_fini(struct radeon_device *rdev);
		1736	int radeon_vce_suspend(struct radeon_device *rdev);
		1737	int radeon_vce_resume(struct radeon_device *rdev);
		1738	int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
		1739	uint32_t handle, struct radeon_fence **fence);
		1740	int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
		1741	uint32_t handle, struct radeon_fence **fence);
		1742	void radeon_vce_free_handles(struct radeon_device rdev, struct drm_file filp);
		1743	void radeon_vce_note_usage(struct radeon_device *rdev);
		1744	int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
		1745	int radeon_vce_cs_parse(struct radeon_cs_parser *p);
		1746	bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
		1747	struct radeon_ring *ring,
		1748	struct radeon_semaphore *semaphore,
		1749	bool emit_wait);
		1750	void radeon_vce_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
		1751	void radeon_vce_fence_emit(struct radeon_device *rdev,
		1752	struct radeon_fence *fence);
		1753	int radeon_vce_ring_test(struct radeon_device rdev, struct radeon_ring ring);
		1754	int radeon_vce_ib_test(struct radeon_device rdev, struct radeon_ring ring);
		1755
		1756	struct r600_audio_pin {
2997	Serge	1757	int channels;
		1758	int rate;
		1759	int bits_per_sample;
		1760	u8 status_bits;
		1761	u8 category_code;
5078	serge	1762	u32 offset;
		1763	bool connected;
		1764	u32 id;
2997	Serge	1765	};
5078	serge	1766
		1767	struct r600_audio {
		1768	bool enabled;
		1769	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
		1770	int num_pins;
6104	serge	1771	struct radeon_audio_funcs *hdmi_funcs;
		1772	struct radeon_audio_funcs *dp_funcs;
		1773	struct radeon_audio_basic_funcs *funcs;
5078	serge	1774	};
		1775
1117	serge	1776	/*
5078	serge	1777	* Benchmarking
		1778	*/
		1779	void radeon_benchmark(struct radeon_device *rdev, int test_number);
		1780
		1781
		1782	/*
		1783	* Testing
		1784	*/
		1785	void radeon_test_moves(struct radeon_device *rdev);
		1786	void radeon_test_ring_sync(struct radeon_device *rdev,
		1787	struct radeon_ring *cpA,
		1788	struct radeon_ring *cpB);
		1789	void radeon_test_syncing(struct radeon_device *rdev);
		1790
5271	serge	1791	/*
		1792	* MMU Notifier
		1793	*/
6104	serge	1794	#if defined(CONFIG_MMU_NOTIFIER)
5271	serge	1795	int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
		1796	void radeon_mn_unregister(struct radeon_bo *bo);
6104	serge	1797	#else
		1798	static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
		1799	{
		1800	return -ENODEV;
		1801	}
		1802	static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
		1803	#endif
5078	serge	1804
		1805	/*
		1806	* Debugfs
		1807	*/
		1808	struct radeon_debugfs {
		1809	struct drm_info_list *files;
		1810	unsigned num_files;
		1811	};
		1812
		1813	int radeon_debugfs_add_files(struct radeon_device *rdev,
		1814	struct drm_info_list *files,
		1815	unsigned nfiles);
		1816	int radeon_debugfs_fence_init(struct radeon_device *rdev);
		1817
		1818	/*
		1819	* ASIC ring specific functions.
		1820	*/
		1821	struct radeon_asic_ring {
		1822	/* ring read/write ptr handling */
		1823	u32 (get_rptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1824	u32 (get_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1825	void (set_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1826
		1827	/* validating and patching of IBs */
		1828	int (ib_parse)(struct radeon_device rdev, struct radeon_ib *ib);
		1829	int (cs_parse)(struct radeon_cs_parser p);
		1830
		1831	/* command emmit functions */
		1832	void (ib_execute)(struct radeon_device rdev, struct radeon_ib *ib);
		1833	void (emit_fence)(struct radeon_device rdev, struct radeon_fence *fence);
		1834	void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);
		1835	bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,
		1836	struct radeon_semaphore *semaphore, bool emit_wait);
5271	serge	1837	void (vm_flush)(struct radeon_device rdev, struct radeon_ring *ring,
		1838	unsigned vm_id, uint64_t pd_addr);
5078	serge	1839
		1840	/* testing functions */
		1841	int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1842	int (ib_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1843	bool (is_lockup)(struct radeon_device rdev, struct radeon_ring *cp);
		1844
		1845	/* deprecated */
		1846	void (ring_start)(struct radeon_device rdev, struct radeon_ring *cp);
		1847	};
		1848
		1849	/*
1117	serge	1850	* ASIC specific functions.
		1851	*/
		1852	struct radeon_asic {
		1853	int (init)(struct radeon_device rdev);
1179	serge	1854	void (fini)(struct radeon_device rdev);
		1855	int (resume)(struct radeon_device rdev);
		1856	int (suspend)(struct radeon_device rdev);
		1857	void (vga_set_state)(struct radeon_device rdev, bool state);
1963	serge	1858	int (asic_reset)(struct radeon_device rdev);
5078	serge	1859	/* Flush the HDP cache via MMIO */
		1860	void (mmio_hdp_flush)(struct radeon_device rdev);
2997	Serge	1861	/* check if 3D engine is idle */
		1862	bool (gui_idle)(struct radeon_device rdev);
		1863	/* wait for mc_idle */
		1864	int (mc_wait_for_idle)(struct radeon_device rdev);
3764	Serge	1865	/* get the reference clock */
		1866	u32 (get_xclk)(struct radeon_device rdev);
		1867	/* get the gpu clock counter */
		1868	uint64_t (get_gpu_clock_counter)(struct radeon_device rdev);
6104	serge	1869	/* get register for info ioctl */
		1870	int (get_allowed_info_register)(struct radeon_device rdev, u32 reg, u32 *val);
2997	Serge	1871	/* gart */
		1872	struct {
		1873	void (tlb_flush)(struct radeon_device rdev);
6104	serge	1874	uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
5078	serge	1875	void (set_page)(struct radeon_device rdev, unsigned i,
6104	serge	1876	uint64_t entry);
2997	Serge	1877	} gart;
		1878	struct {
		1879	int (init)(struct radeon_device rdev);
		1880	void (fini)(struct radeon_device rdev);
5078	serge	1881	void (copy_pages)(struct radeon_device rdev,
		1882	struct radeon_ib *ib,
		1883	uint64_t pe, uint64_t src,
		1884	unsigned count);
		1885	void (write_pages)(struct radeon_device rdev,
		1886	struct radeon_ib *ib,
		1887	uint64_t pe,
		1888	uint64_t addr, unsigned count,
		1889	uint32_t incr, uint32_t flags);
		1890	void (set_pages)(struct radeon_device rdev,
6104	serge	1891	struct radeon_ib *ib,
		1892	uint64_t pe,
		1893	uint64_t addr, unsigned count,
		1894	uint32_t incr, uint32_t flags);
5078	serge	1895	void (pad_ib)(struct radeon_ib ib);
2997	Serge	1896	} vm;
		1897	/* ring specific callbacks */
5078	serge	1898	struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
2997	Serge	1899	/* irqs */
		1900	struct {
		1901	int (set)(struct radeon_device rdev);
		1902	int (process)(struct radeon_device rdev);
		1903	} irq;
		1904	/* displays */
		1905	struct {
		1906	/* display watermarks */
		1907	void (bandwidth_update)(struct radeon_device rdev);
		1908	/* get frame count */
6104	serge	1909	u32 (get_vblank_counter)(struct radeon_device rdev, int crtc);
2997	Serge	1910	/* wait for vblank */
		1911	void (wait_for_vblank)(struct radeon_device rdev, int crtc);
		1912	/* set backlight level */
		1913	void (set_backlight_level)(struct radeon_encoder radeon_encoder, u8 level);
		1914	/* get backlight level */
		1915	u8 (get_backlight_level)(struct radeon_encoder radeon_encoder);
3764	Serge	1916	/* audio callbacks */
		1917	void (hdmi_enable)(struct drm_encoder encoder, bool enable);
		1918	void (hdmi_setmode)(struct drm_encoder encoder, struct drm_display_mode *mode);
2997	Serge	1919	} display;
		1920	/* copy functions for bo handling */
		1921	struct {
5271	serge	1922	struct radeon_fence (blit)(struct radeon_device *rdev,
6104	serge	1923	uint64_t src_offset,
		1924	uint64_t dst_offset,
		1925	unsigned num_gpu_pages,
5271	serge	1926	struct reservation_object *resv);
2997	Serge	1927	u32 blit_ring_index;
5271	serge	1928	struct radeon_fence (dma)(struct radeon_device *rdev,
6104	serge	1929	uint64_t src_offset,
		1930	uint64_t dst_offset,
		1931	unsigned num_gpu_pages,
5271	serge	1932	struct reservation_object *resv);
2997	Serge	1933	u32 dma_ring_index;
		1934	/* method used for bo copy */
5271	serge	1935	struct radeon_fence (copy)(struct radeon_device *rdev,
6104	serge	1936	uint64_t src_offset,
		1937	uint64_t dst_offset,
		1938	unsigned num_gpu_pages,
5271	serge	1939	struct reservation_object *resv);
2997	Serge	1940	/* ring used for bo copies */
		1941	u32 copy_ring_index;
		1942	} copy;
		1943	/* surfaces */
		1944	struct {
		1945	int (set_reg)(struct radeon_device rdev, int reg,
		1946	uint32_t tiling_flags, uint32_t pitch,
		1947	uint32_t offset, uint32_t obj_size);
		1948	void (clear_reg)(struct radeon_device rdev, int reg);
		1949	} surface;
		1950	/* hotplug detect */
		1951	struct {
		1952	void (init)(struct radeon_device rdev);
		1953	void (fini)(struct radeon_device rdev);
		1954	bool (sense)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1955	void (set_polarity)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1956	} hpd;
5078	serge	1957	/* static power management */
2997	Serge	1958	struct {
		1959	void (misc)(struct radeon_device rdev);
		1960	void (prepare)(struct radeon_device rdev);
		1961	void (finish)(struct radeon_device rdev);
		1962	void (init_profile)(struct radeon_device rdev);
		1963	void (get_dynpm_state)(struct radeon_device rdev);
6104	serge	1964	uint32_t (get_engine_clock)(struct radeon_device rdev);
		1965	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
		1966	uint32_t (get_memory_clock)(struct radeon_device rdev);
		1967	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
		1968	int (get_pcie_lanes)(struct radeon_device rdev);
		1969	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		1970	void (set_clock_gating)(struct radeon_device rdev, int enable);
3764	Serge	1971	int (set_uvd_clocks)(struct radeon_device rdev, u32 vclk, u32 dclk);
5078	serge	1972	int (set_vce_clocks)(struct radeon_device rdev, u32 evclk, u32 ecclk);
		1973	int (get_temperature)(struct radeon_device rdev);
2997	Serge	1974	} pm;
5078	serge	1975	/* dynamic power management */
		1976	struct {
		1977	int (init)(struct radeon_device rdev);
		1978	void (setup_asic)(struct radeon_device rdev);
		1979	int (enable)(struct radeon_device rdev);
		1980	int (late_enable)(struct radeon_device rdev);
		1981	void (disable)(struct radeon_device rdev);
		1982	int (pre_set_power_state)(struct radeon_device rdev);
		1983	int (set_power_state)(struct radeon_device rdev);
		1984	void (post_set_power_state)(struct radeon_device rdev);
		1985	void (display_configuration_changed)(struct radeon_device rdev);
		1986	void (fini)(struct radeon_device rdev);
		1987	u32 (get_sclk)(struct radeon_device rdev, bool low);
		1988	u32 (get_mclk)(struct radeon_device rdev, bool low);
		1989	void (print_power_state)(struct radeon_device rdev, struct radeon_ps *ps);
		1990	void (debugfs_print_current_performance_level)(struct radeon_device rdev, struct seq_file *m);
		1991	int (force_performance_level)(struct radeon_device rdev, enum radeon_dpm_forced_level level);
		1992	bool (vblank_too_short)(struct radeon_device rdev);
		1993	void (powergate_uvd)(struct radeon_device rdev, bool gate);
		1994	void (enable_bapm)(struct radeon_device rdev, bool enable);
6104	serge	1995	void (fan_ctrl_set_mode)(struct radeon_device rdev, u32 mode);
		1996	u32 (fan_ctrl_get_mode)(struct radeon_device rdev);
		1997	int (set_fan_speed_percent)(struct radeon_device rdev, u32 speed);
		1998	int (get_fan_speed_percent)(struct radeon_device rdev, u32 *speed);
		1999	u32 (get_current_sclk)(struct radeon_device rdev);
		2000	u32 (get_current_mclk)(struct radeon_device rdev);
5078	serge	2001	} dpm;
1963	serge	2002	/* pageflipping */
2997	Serge	2003	struct {
5078	serge	2004	void (page_flip)(struct radeon_device rdev, int crtc, u64 crtc_base);
		2005	bool (page_flip_pending)(struct radeon_device rdev, int crtc);
2997	Serge	2006	} pflip;
1117	serge	2007	};
		2008
1179	serge	2009	/*
		2010	* Asic structures
		2011	*/
		2012	struct r100_asic {
6104	serge	2013	const unsigned *reg_safe_bm;
		2014	unsigned reg_safe_bm_size;
		2015	u32 hdp_cntl;
1179	serge	2016	};
		2017
		2018	struct r300_asic {
6104	serge	2019	const unsigned *reg_safe_bm;
		2020	unsigned reg_safe_bm_size;
		2021	u32 resync_scratch;
		2022	u32 hdp_cntl;
1179	serge	2023	};
		2024
		2025	struct r600_asic {
6104	serge	2026	unsigned max_pipes;
		2027	unsigned max_tile_pipes;
		2028	unsigned max_simds;
		2029	unsigned max_backends;
		2030	unsigned max_gprs;
		2031	unsigned max_threads;
		2032	unsigned max_stack_entries;
		2033	unsigned max_hw_contexts;
		2034	unsigned max_gs_threads;
		2035	unsigned sx_max_export_size;
		2036	unsigned sx_max_export_pos_size;
		2037	unsigned sx_max_export_smx_size;
		2038	unsigned sq_num_cf_insts;
		2039	unsigned tiling_nbanks;
		2040	unsigned tiling_npipes;
		2041	unsigned tiling_group_size;
1963	serge	2042	unsigned tile_config;
2160	serge	2043	unsigned backend_map;
5078	serge	2044	unsigned active_simds;
1179	serge	2045	};
		2046
		2047	struct rv770_asic {
6104	serge	2048	unsigned max_pipes;
		2049	unsigned max_tile_pipes;
		2050	unsigned max_simds;
		2051	unsigned max_backends;
		2052	unsigned max_gprs;
		2053	unsigned max_threads;
		2054	unsigned max_stack_entries;
		2055	unsigned max_hw_contexts;
		2056	unsigned max_gs_threads;
		2057	unsigned sx_max_export_size;
		2058	unsigned sx_max_export_pos_size;
		2059	unsigned sx_max_export_smx_size;
		2060	unsigned sq_num_cf_insts;
		2061	unsigned sx_num_of_sets;
		2062	unsigned sc_prim_fifo_size;
		2063	unsigned sc_hiz_tile_fifo_size;
		2064	unsigned sc_earlyz_tile_fifo_fize;
		2065	unsigned tiling_nbanks;
		2066	unsigned tiling_npipes;
		2067	unsigned tiling_group_size;
1963	serge	2068	unsigned tile_config;
2160	serge	2069	unsigned backend_map;
5078	serge	2070	unsigned active_simds;
1179	serge	2071	};
		2072
1963	serge	2073	struct evergreen_asic {
		2074	unsigned num_ses;
		2075	unsigned max_pipes;
		2076	unsigned max_tile_pipes;
		2077	unsigned max_simds;
		2078	unsigned max_backends;
		2079	unsigned max_gprs;
		2080	unsigned max_threads;
		2081	unsigned max_stack_entries;
		2082	unsigned max_hw_contexts;
		2083	unsigned max_gs_threads;
		2084	unsigned sx_max_export_size;
		2085	unsigned sx_max_export_pos_size;
		2086	unsigned sx_max_export_smx_size;
		2087	unsigned sq_num_cf_insts;
		2088	unsigned sx_num_of_sets;
		2089	unsigned sc_prim_fifo_size;
		2090	unsigned sc_hiz_tile_fifo_size;
		2091	unsigned sc_earlyz_tile_fifo_size;
		2092	unsigned tiling_nbanks;
		2093	unsigned tiling_npipes;
		2094	unsigned tiling_group_size;
		2095	unsigned tile_config;
2160	serge	2096	unsigned backend_map;
5078	serge	2097	unsigned active_simds;
1963	serge	2098	};
		2099
		2100	struct cayman_asic {
		2101	unsigned max_shader_engines;
		2102	unsigned max_pipes_per_simd;
		2103	unsigned max_tile_pipes;
		2104	unsigned max_simds_per_se;
		2105	unsigned max_backends_per_se;
		2106	unsigned max_texture_channel_caches;
		2107	unsigned max_gprs;
		2108	unsigned max_threads;
		2109	unsigned max_gs_threads;
		2110	unsigned max_stack_entries;
		2111	unsigned sx_num_of_sets;
		2112	unsigned sx_max_export_size;
		2113	unsigned sx_max_export_pos_size;
		2114	unsigned sx_max_export_smx_size;
		2115	unsigned max_hw_contexts;
		2116	unsigned sq_num_cf_insts;
		2117	unsigned sc_prim_fifo_size;
		2118	unsigned sc_hiz_tile_fifo_size;
		2119	unsigned sc_earlyz_tile_fifo_size;
		2120
		2121	unsigned num_shader_engines;
		2122	unsigned num_shader_pipes_per_simd;
		2123	unsigned num_tile_pipes;
		2124	unsigned num_simds_per_se;
		2125	unsigned num_backends_per_se;
		2126	unsigned backend_disable_mask_per_asic;
		2127	unsigned backend_map;
		2128	unsigned num_texture_channel_caches;
		2129	unsigned mem_max_burst_length_bytes;
		2130	unsigned mem_row_size_in_kb;
		2131	unsigned shader_engine_tile_size;
		2132	unsigned num_gpus;
		2133	unsigned multi_gpu_tile_size;
		2134
		2135	unsigned tile_config;
5078	serge	2136	unsigned active_simds;
1963	serge	2137	};
		2138
2997	Serge	2139	struct si_asic {
		2140	unsigned max_shader_engines;
		2141	unsigned max_tile_pipes;
		2142	unsigned max_cu_per_sh;
		2143	unsigned max_sh_per_se;
		2144	unsigned max_backends_per_se;
		2145	unsigned max_texture_channel_caches;
		2146	unsigned max_gprs;
		2147	unsigned max_gs_threads;
		2148	unsigned max_hw_contexts;
		2149	unsigned sc_prim_fifo_size_frontend;
		2150	unsigned sc_prim_fifo_size_backend;
		2151	unsigned sc_hiz_tile_fifo_size;
		2152	unsigned sc_earlyz_tile_fifo_size;
		2153
		2154	unsigned num_tile_pipes;
5078	serge	2155	unsigned backend_enable_mask;
2997	Serge	2156	unsigned backend_disable_mask_per_asic;
		2157	unsigned backend_map;
		2158	unsigned num_texture_channel_caches;
		2159	unsigned mem_max_burst_length_bytes;
		2160	unsigned mem_row_size_in_kb;
		2161	unsigned shader_engine_tile_size;
		2162	unsigned num_gpus;
		2163	unsigned multi_gpu_tile_size;
		2164
		2165	unsigned tile_config;
3764	Serge	2166	uint32_t tile_mode_array[32];
5078	serge	2167	uint32_t active_cus;
2997	Serge	2168	};
		2169
5078	serge	2170	struct cik_asic {
		2171	unsigned max_shader_engines;
		2172	unsigned max_tile_pipes;
		2173	unsigned max_cu_per_sh;
		2174	unsigned max_sh_per_se;
		2175	unsigned max_backends_per_se;
		2176	unsigned max_texture_channel_caches;
		2177	unsigned max_gprs;
		2178	unsigned max_gs_threads;
		2179	unsigned max_hw_contexts;
		2180	unsigned sc_prim_fifo_size_frontend;
		2181	unsigned sc_prim_fifo_size_backend;
		2182	unsigned sc_hiz_tile_fifo_size;
		2183	unsigned sc_earlyz_tile_fifo_size;
		2184
		2185	unsigned num_tile_pipes;
		2186	unsigned backend_enable_mask;
		2187	unsigned backend_disable_mask_per_asic;
		2188	unsigned backend_map;
		2189	unsigned num_texture_channel_caches;
		2190	unsigned mem_max_burst_length_bytes;
		2191	unsigned mem_row_size_in_kb;
		2192	unsigned shader_engine_tile_size;
		2193	unsigned num_gpus;
		2194	unsigned multi_gpu_tile_size;
		2195
		2196	unsigned tile_config;
		2197	uint32_t tile_mode_array[32];
		2198	uint32_t macrotile_mode_array[16];
		2199	uint32_t active_cus;
		2200	};
		2201
1117	serge	2202	union radeon_asic_config {
		2203	struct r300_asic r300;
1179	serge	2204	struct r100_asic r100;
		2205	struct r600_asic r600;
		2206	struct rv770_asic rv770;
1963	serge	2207	struct evergreen_asic evergreen;
		2208	struct cayman_asic cayman;
2997	Serge	2209	struct si_asic si;
5078	serge	2210	struct cik_asic cik;
1117	serge	2211	};
		2212
		2213	/*
1963	serge	2214	* asic initizalization from radeon_asic.c
		2215	*/
		2216	void radeon_agp_disable(struct radeon_device *rdev);
		2217	int radeon_asic_init(struct radeon_device *rdev);
1179	serge	2218
		2219
		2220
2997	Serge	2221	/* VRAM scratch page for HDP bug, default vram page */
		2222	struct r600_vram_scratch {
1963	serge	2223	struct radeon_bo *robj;
		2224	volatile uint32_t *ptr;
2997	Serge	2225	u64 gpu_addr;
1963	serge	2226	};
1179	serge	2227
5078	serge	2228	/*
		2229	* ACPI
		2230	*/
		2231	struct radeon_atif_notification_cfg {
		2232	bool enabled;
		2233	int command_code;
		2234	};
2997	Serge	2235
5078	serge	2236	struct radeon_atif_notifications {
		2237	bool display_switch;
		2238	bool expansion_mode_change;
		2239	bool thermal_state;
		2240	bool forced_power_state;
		2241	bool system_power_state;
		2242	bool display_conf_change;
		2243	bool px_gfx_switch;
		2244	bool brightness_change;
		2245	bool dgpu_display_event;
		2246	};
		2247
		2248	struct radeon_atif_functions {
		2249	bool system_params;
		2250	bool sbios_requests;
		2251	bool select_active_disp;
		2252	bool lid_state;
		2253	bool get_tv_standard;
		2254	bool set_tv_standard;
		2255	bool get_panel_expansion_mode;
		2256	bool set_panel_expansion_mode;
		2257	bool temperature_change;
		2258	bool graphics_device_types;
		2259	};
		2260
		2261	struct radeon_atif {
		2262	struct radeon_atif_notifications notifications;
		2263	struct radeon_atif_functions functions;
		2264	struct radeon_atif_notification_cfg notification_cfg;
		2265	struct radeon_encoder *encoder_for_bl;
		2266	};
		2267
		2268	struct radeon_atcs_functions {
		2269	bool get_ext_state;
		2270	bool pcie_perf_req;
		2271	bool pcie_dev_rdy;
		2272	bool pcie_bus_width;
		2273	};
		2274
		2275	struct radeon_atcs {
		2276	struct radeon_atcs_functions functions;
		2277	};
		2278
1117	serge	2279	/*
		2280	* Core structure, functions and helpers.
		2281	*/
		2282	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		2283	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		2284
		2285	struct radeon_device {
6104	serge	2286	struct device *dev;
		2287	struct drm_device *ddev;
		2288	struct pci_dev *pdev;
2997	Serge	2289	struct rw_semaphore exclusive_lock;
6104	serge	2290	/* ASIC */
		2291	union radeon_asic_config config;
		2292	enum radeon_family family;
		2293	unsigned long flags;
		2294	int usec_timeout;
		2295	enum radeon_pll_errata pll_errata;
		2296	int num_gb_pipes;
		2297	int num_z_pipes;
		2298	int disp_priority;
		2299	/* BIOS */
		2300	uint8_t *bios;
		2301	bool is_atom_bios;
		2302	uint16_t bios_header_start;
		2303	struct radeon_bo *stollen_vga_memory;
		2304	/* Register mmio */
1963	serge	2305	resource_size_t rmmio_base;
		2306	resource_size_t rmmio_size;
3192	Serge	2307	/* protects concurrent MM_INDEX/DATA based register access */
		2308	spinlock_t mmio_idx_lock;
5078	serge	2309	/* protects concurrent SMC based register access */
		2310	spinlock_t smc_idx_lock;
		2311	/* protects concurrent PLL register access */
		2312	spinlock_t pll_idx_lock;
		2313	/* protects concurrent MC register access */
		2314	spinlock_t mc_idx_lock;
		2315	/* protects concurrent PCIE register access */
		2316	spinlock_t pcie_idx_lock;
		2317	/* protects concurrent PCIE_PORT register access */
		2318	spinlock_t pciep_idx_lock;
		2319	/* protects concurrent PIF register access */
		2320	spinlock_t pif_idx_lock;
		2321	/* protects concurrent CG register access */
		2322	spinlock_t cg_idx_lock;
		2323	/* protects concurrent UVD register access */
		2324	spinlock_t uvd_idx_lock;
		2325	/* protects concurrent RCU register access */
		2326	spinlock_t rcu_idx_lock;
		2327	/* protects concurrent DIDT register access */
		2328	spinlock_t didt_idx_lock;
		2329	/* protects concurrent ENDPOINT (audio) register access */
		2330	spinlock_t end_idx_lock;
2997	Serge	2331	void __iomem *rmmio;
6104	serge	2332	radeon_rreg_t mc_rreg;
		2333	radeon_wreg_t mc_wreg;
		2334	radeon_rreg_t pll_rreg;
		2335	radeon_wreg_t pll_wreg;
1179	serge	2336	uint32_t pcie_reg_mask;
6104	serge	2337	radeon_rreg_t pciep_rreg;
		2338	radeon_wreg_t pciep_wreg;
1963	serge	2339	/* io port */
		2340	void __iomem *rio_mem;
		2341	resource_size_t rio_mem_size;
6104	serge	2342	struct radeon_clock clock;
		2343	struct radeon_mc mc;
		2344	struct radeon_gart gart;
1117	serge	2345	struct radeon_mode_info mode_info;
6104	serge	2346	struct radeon_scratch scratch;
5078	serge	2347	struct radeon_doorbell doorbell;
6104	serge	2348	struct radeon_mman mman;
2997	Serge	2349	struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
		2350	wait_queue_head_t fence_queue;
5271	serge	2351	unsigned fence_context;
2997	Serge	2352	struct mutex ring_lock;
		2353	struct radeon_ring ring[RADEON_NUM_RINGS];
		2354	bool ib_pool_ready;
		2355	struct radeon_sa_manager ring_tmp_bo;
6104	serge	2356	struct radeon_irq irq;
		2357	struct radeon_asic *asic;
		2358	struct radeon_gem gem;
1179	serge	2359	struct radeon_pm pm;
3764	Serge	2360	struct radeon_uvd uvd;
5078	serge	2361	struct radeon_vce vce;
1179	serge	2362	uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
6104	serge	2363	struct radeon_wb wb;
1179	serge	2364	struct radeon_dummy_page dummy_page;
6104	serge	2365	bool shutdown;
		2366	bool suspend;
1179	serge	2367	bool need_dma32;
		2368	bool accel_working;
3764	Serge	2369	bool fastfb_working; /* IGP feature*/
5271	serge	2370	bool needs_reset, in_reset;
1179	serge	2371	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
		2372	const struct firmware me_fw; / all family ME firmware */
		2373	const struct firmware pfp_fw; / r6/700 PFP firmware */
1403	serge	2374	const struct firmware rlc_fw; / r6/700 RLC firmware */
1963	serge	2375	const struct firmware mc_fw; / NI MC firmware */
2997	Serge	2376	const struct firmware ce_fw; / SI CE firmware */
5078	serge	2377	const struct firmware mec_fw; / CIK MEC firmware */
		2378	const struct firmware mec2_fw; / KV MEC2 firmware */
		2379	const struct firmware sdma_fw; / CIK SDMA firmware */
		2380	const struct firmware smc_fw; / SMC firmware */
3764	Serge	2381	const struct firmware uvd_fw; / UVD firmware */
5078	serge	2382	const struct firmware vce_fw; / VCE firmware */
		2383	bool new_fw;
2997	Serge	2384	struct r600_vram_scratch vram_scratch;
1268	serge	2385	int msi_enabled; /* msi enabled */
2004	serge	2386	struct r600_ih ih; /* r6/700 interrupt ring */
5078	serge	2387	struct radeon_rlc rlc;
		2388	struct radeon_mec mec;
		2389	struct work_struct hotplug_work;
		2390	struct work_struct audio_work;
1430	serge	2391	int num_crtc; /* number of crtcs */
1630	serge	2392	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3764	Serge	2393	bool has_uvd;
5078	serge	2394	struct r600_audio audio; /* audio stuff */
2997	Serge	2395	/* only one userspace can use Hyperz features or CMASK at a time */
5078	serge	2396	struct drm_file *hyperz_filp;
		2397	struct drm_file *cmask_filp;
1963	serge	2398	/* i2c buses */
		2399	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2997	Serge	2400	/* debugfs */
5078	serge	2401	struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2997	Serge	2402	unsigned debugfs_count;
		2403	/* virtual memory */
		2404	struct radeon_vm_manager vm_manager;
		2405	struct mutex gpu_clock_mutex;
5078	serge	2406	/* memory stats */
		2407	atomic64_t vram_usage;
		2408	atomic64_t gtt_usage;
		2409	atomic64_t num_bytes_moved;
6104	serge	2410	atomic_t gpu_reset_counter;
2997	Serge	2411	/* ACPI interface */
5078	serge	2412	struct radeon_atif atif;
		2413	struct radeon_atcs atcs;
		2414	/* srbm instance registers */
		2415	struct mutex srbm_mutex;
5271	serge	2416	/* GRBM index mutex. Protects concurrents access to GRBM index */
		2417	struct mutex grbm_idx_mutex;
5078	serge	2418	/* clock, powergating flags */
		2419	u32 cg_flags;
		2420	u32 pg_flags;
		2421
		2422	// struct dev_pm_domain vga_pm_domain;
		2423	bool have_disp_power_ref;
		2424	u32 px_quirk_flags;
		2425
		2426	/* tracking pinned memory */
		2427	u64 vram_pin_size;
		2428	u64 gart_pin_size;
5271	serge	2429	struct mutex mn_lock;
1117	serge	2430	};
		2431
5078	serge	2432	bool radeon_is_px(struct drm_device *dev);
1117	serge	2433	int radeon_device_init(struct radeon_device *rdev,
		2434	struct drm_device *ddev,
		2435	struct pci_dev *pdev,
		2436	uint32_t flags);
		2437	void radeon_device_fini(struct radeon_device *rdev);
		2438	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		2439
5078	serge	2440	#define RADEON_MIN_MMIO_SIZE 0x10000
		2441
6104	serge	2442	uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
		2443	void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
5078	serge	2444	static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		2445	bool always_indirect)
		2446	{
		2447	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
		2448	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2449	return readl(((void __iomem *)rdev->rmmio) + reg);
6104	serge	2450	else
		2451	return r100_mm_rreg_slow(rdev, reg);
5078	serge	2452	}
		2453	static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		2454	bool always_indirect)
		2455	{
		2456	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2457	writel(v, ((void __iomem *)rdev->rmmio) + reg);
6104	serge	2458	else
		2459	r100_mm_wreg_slow(rdev, reg, v);
5078	serge	2460	}
		2461
2997	Serge	2462	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
		2463	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2464
5078	serge	2465	u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
		2466	void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
		2467
1321	serge	2468	/*
		2469	* Cast helper
		2470	*/
5271	serge	2471	extern const struct fence_ops radeon_fence_ops;
1117	serge	2472
5271	serge	2473	static inline struct radeon_fence to_radeon_fence(struct fence f)
		2474	{
		2475	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
		2476
		2477	if (__f->base.ops == &radeon_fence_ops)
		2478	return __f;
		2479
		2480	return NULL;
		2481	}
		2482
1117	serge	2483	/*
		2484	* Registers read & write functions.
		2485	*/
2997	Serge	2486	#define RREG8(reg) readb((rdev->rmmio) + (reg))
		2487	#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
		2488	#define RREG16(reg) readw((rdev->rmmio) + (reg))
		2489	#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
3192	Serge	2490	#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
		2491	#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
		2492	#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
		2493	#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
		2494	#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1117	serge	2495	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2496	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2497	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		2498	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		2499	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		2500	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179	serge	2501	#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
		2502	#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
3764	Serge	2503	#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
		2504	#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
5078	serge	2505	#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
		2506	#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
		2507	#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
		2508	#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
		2509	#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
		2510	#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
		2511	#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
		2512	#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
		2513	#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
		2514	#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
		2515	#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
		2516	#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
		2517	#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
		2518	#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
1117	serge	2519	#define WREG32_P(reg, val, mask) \
		2520	do { \
		2521	uint32_t tmp_ = RREG32(reg); \
		2522	tmp_ &= (mask); \
		2523	tmp_ \|= ((val) & ~(mask)); \
		2524	WREG32(reg, tmp_); \
		2525	} while (0)
3764	Serge	2526	#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
5078	serge	2527	#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1117	serge	2528	#define WREG32_PLL_P(reg, val, mask) \
		2529	do { \
		2530	uint32_t tmp_ = RREG32_PLL(reg); \
		2531	tmp_ &= (mask); \
		2532	tmp_ \|= ((val) & ~(mask)); \
		2533	WREG32_PLL(reg, tmp_); \
		2534	} while (0)
6104	serge	2535	#define WREG32_SMC_P(reg, val, mask) \
		2536	do { \
		2537	uint32_t tmp_ = RREG32_SMC(reg); \
		2538	tmp_ &= (mask); \
		2539	tmp_ \|= ((val) & ~(mask)); \
		2540	WREG32_SMC(reg, tmp_); \
		2541	} while (0)
5078	serge	2542	#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1963	serge	2543	#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
		2544	#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1117	serge	2545
5078	serge	2546	#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
		2547	#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
		2548
1179	serge	2549	/*
6104	serge	2550	* Indirect registers accessors.
		2551	* They used to be inlined, but this increases code size by ~65 kbytes.
		2552	* Since each performs a pair of MMIO ops
		2553	* within a spin_lock_irqsave/spin_unlock_irqrestore region,
		2554	* the cost of call+ret is almost negligible. MMIO and locking
		2555	* costs several dozens of cycles each at best, call+ret is ~5 cycles.
1179	serge	2556	*/
6104	serge	2557	uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
		2558	void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
		2559	u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
		2560	void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2561	u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
		2562	void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2563	u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
		2564	void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2565	u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
		2566	void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2567	u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
		2568	void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2569	u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
		2570	void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
		2571	u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
		2572	void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2573
1179	serge	2574	void r100_pll_errata_after_index(struct radeon_device *rdev);
		2575
		2576
1117	serge	2577	/*
		2578	* ASICs helpers.
		2579	*/
1179	serge	2580	#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) \|\| \
		2581	(rdev->pdev->device == 0x5969))
1117	serge	2582	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
6104	serge	2583	(rdev->family == CHIP_RV200) \|\| \
		2584	(rdev->family == CHIP_RS100) \|\| \
		2585	(rdev->family == CHIP_RS200) \|\| \
		2586	(rdev->family == CHIP_RV250) \|\| \
		2587	(rdev->family == CHIP_RV280) \|\| \
		2588	(rdev->family == CHIP_RS300))
		2589	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		2590	(rdev->family == CHIP_RV350) \|\| \
		2591	(rdev->family == CHIP_R350) \|\| \
		2592	(rdev->family == CHIP_RV380) \|\| \
		2593	(rdev->family == CHIP_R420) \|\| \
		2594	(rdev->family == CHIP_R423) \|\| \
		2595	(rdev->family == CHIP_RV410) \|\| \
		2596	(rdev->family == CHIP_RS400) \|\| \
		2597	(rdev->family == CHIP_RS480))
1963	serge	2598	#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \
		2599	(rdev->ddev->pdev->device == 0x9443) \|\| \
		2600	(rdev->ddev->pdev->device == 0x944B) \|\| \
		2601	(rdev->ddev->pdev->device == 0x9506) \|\| \
		2602	(rdev->ddev->pdev->device == 0x9509) \|\| \
		2603	(rdev->ddev->pdev->device == 0x950F) \|\| \
		2604	(rdev->ddev->pdev->device == 0x689C) \|\| \
		2605	(rdev->ddev->pdev->device == 0x689D))
1117	serge	2606	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1963	serge	2607	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
		2608	(rdev->family == CHIP_RS690) \|\| \
		2609	(rdev->family == CHIP_RS740) \|\| \
		2610	(rdev->family >= CHIP_R600))
1117	serge	2611	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		2612	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1430	serge	2613	#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1963	serge	2614	#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
		2615	(rdev->flags & RADEON_IS_IGP))
		2616	#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2997	Serge	2617	#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
		2618	#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
		2619	(rdev->flags & RADEON_IS_IGP))
3764	Serge	2620	#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
		2621	#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
5078	serge	2622	#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
		2623	#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
		2624	#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
		2625	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
		2626	(rdev->family == CHIP_MULLINS))
1117	serge	2627
5078	serge	2628	#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \
		2629	(rdev->ddev->pdev->device == 0x6850) \|\| \
		2630	(rdev->ddev->pdev->device == 0x6858) \|\| \
		2631	(rdev->ddev->pdev->device == 0x6859) \|\| \
		2632	(rdev->ddev->pdev->device == 0x6840) \|\| \
		2633	(rdev->ddev->pdev->device == 0x6841) \|\| \
		2634	(rdev->ddev->pdev->device == 0x6842) \|\| \
		2635	(rdev->ddev->pdev->device == 0x6843))
		2636
1117	serge	2637	/*
		2638	* BIOS helpers.
		2639	*/
		2640	#define RBIOS8(i) (rdev->bios[i])
		2641	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		2642	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		2643
		2644	int radeon_combios_init(struct radeon_device *rdev);
		2645	void radeon_combios_fini(struct radeon_device *rdev);
		2646	int radeon_atombios_init(struct radeon_device *rdev);
		2647	void radeon_atombios_fini(struct radeon_device *rdev);
		2648
		2649
		2650	/*
		2651	* RING helpers.
		2652	*/
5271	serge	2653
		2654	/**
		2655	* radeon_ring_write - write a value to the ring
		2656	*
		2657	* @ring: radeon_ring structure holding ring information
		2658	* @v: dword (dw) value to write
		2659	*
		2660	* Write a value to the requested ring buffer (all asics).
		2661	*/
2997	Serge	2662	static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1117	serge	2663	{
5271	serge	2664	if (ring->count_dw <= 0)
		2665	DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
		2666
2997	Serge	2667	ring->ring[ring->wptr++] = v;
		2668	ring->wptr &= ring->ptr_mask;
		2669	ring->count_dw--;
		2670	ring->ring_free_dw--;
		2671	}
1117	serge	2672
		2673	/*
		2674	* ASICs macro.
		2675	*/
		2676	#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179	serge	2677	#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
		2678	#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
		2679	#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
5078	serge	2680	#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
1179	serge	2681	#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1963	serge	2682	#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2997	Serge	2683	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
6104	serge	2684	#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
		2685	#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2997	Serge	2686	#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
		2687	#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
5078	serge	2688	#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
		2689	#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2690	#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2691	#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
		2692	#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
		2693	#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
		2694	#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
		2695	#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
		2696	#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
		2697	#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
5271	serge	2698	#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
5078	serge	2699	#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
		2700	#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
		2701	#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2997	Serge	2702	#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
		2703	#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
		2704	#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
		2705	#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
		2706	#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
3764	Serge	2707	#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
		2708	#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
5078	serge	2709	#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
		2710	#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
5271	serge	2711	#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
		2712	#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
		2713	#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2997	Serge	2714	#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
		2715	#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
		2716	#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
		2717	#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
		2718	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
		2719	#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
		2720	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
		2721	#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
		2722	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
		2723	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
3764	Serge	2724	#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
5078	serge	2725	#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
		2726	#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2997	Serge	2727	#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
		2728	#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
		2729	#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
		2730	#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
		2731	#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
		2732	#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
		2733	#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1963	serge	2734	#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2997	Serge	2735	#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
		2736	#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
		2737	#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
		2738	#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
		2739	#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
		2740	#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
5078	serge	2741	#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2997	Serge	2742	#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
		2743	#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
3764	Serge	2744	#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
		2745	#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
6104	serge	2746	#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
5078	serge	2747	#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
		2748	#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
		2749	#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
		2750	#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
		2751	#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
		2752	#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
		2753	#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
		2754	#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
		2755	#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
		2756	#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
		2757	#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
		2758	#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
		2759	#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
		2760	#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
		2761	#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
		2762	#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
		2763	#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
		2764	#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
6104	serge	2765	#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
		2766	#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
1117	serge	2767
1179	serge	2768	/* Common functions */
1403	serge	2769	/* AGP */
1963	serge	2770	extern int radeon_gpu_reset(struct radeon_device *rdev);
5078	serge	2771	extern void radeon_pci_config_reset(struct radeon_device *rdev);
3764	Serge	2772	extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1403	serge	2773	extern void radeon_agp_disable(struct radeon_device *rdev);
1179	serge	2774	extern int radeon_modeset_init(struct radeon_device *rdev);
		2775	extern void radeon_modeset_fini(struct radeon_device *rdev);
		2776	extern bool radeon_card_posted(struct radeon_device *rdev);
1963	serge	2777	extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
		2778	extern void radeon_update_display_priority(struct radeon_device *rdev);
1321	serge	2779	extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1179	serge	2780	extern void radeon_scratch_init(struct radeon_device *rdev);
1963	serge	2781	extern void radeon_wb_fini(struct radeon_device *rdev);
		2782	extern int radeon_wb_init(struct radeon_device *rdev);
		2783	extern void radeon_wb_disable(struct radeon_device *rdev);
1179	serge	2784	extern void radeon_surface_init(struct radeon_device *rdev);
		2785	extern int radeon_cs_parser_init(struct radeon_cs_parser p, void data);
1221	serge	2786	extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
		2787	extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1321	serge	2788	extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1403	serge	2789	extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
5271	serge	2790	extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
		2791	uint32_t flags);
		2792	extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
		2793	extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
1430	serge	2794	extern void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base);
		2795	extern void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc);
5078	serge	2796	extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
		2797	extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
1963	serge	2798	extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
3764	Serge	2799	extern void radeon_program_register_sequence(struct radeon_device *rdev,
		2800	const u32 *registers,
		2801	const u32 array_size);
1117	serge	2802
1963	serge	2803	/*
2997	Serge	2804	* vm
		2805	*/
		2806	int radeon_vm_manager_init(struct radeon_device *rdev);
		2807	void radeon_vm_manager_fini(struct radeon_device *rdev);
5078	serge	2808	int radeon_vm_init(struct radeon_device rdev, struct radeon_vm vm);
2997	Serge	2809	void radeon_vm_fini(struct radeon_device rdev, struct radeon_vm vm);
5271	serge	2810	struct radeon_bo_list radeon_vm_get_bos(struct radeon_device rdev,
5078	serge	2811	struct radeon_vm *vm,
		2812	struct list_head *head);
2997	Serge	2813	struct radeon_fence radeon_vm_grab_id(struct radeon_device rdev,
		2814	struct radeon_vm *vm, int ring);
5078	serge	2815	void radeon_vm_flush(struct radeon_device *rdev,
		2816	struct radeon_vm *vm,
5271	serge	2817	int ring, struct radeon_fence *fence);
2997	Serge	2818	void radeon_vm_fence(struct radeon_device *rdev,
		2819	struct radeon_vm *vm,
		2820	struct radeon_fence *fence);
		2821	uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
5078	serge	2822	int radeon_vm_update_page_directory(struct radeon_device *rdev,
		2823	struct radeon_vm *vm);
		2824	int radeon_vm_clear_freed(struct radeon_device *rdev,
		2825	struct radeon_vm *vm);
		2826	int radeon_vm_clear_invalids(struct radeon_device *rdev,
		2827	struct radeon_vm *vm);
		2828	int radeon_vm_bo_update(struct radeon_device *rdev,
		2829	struct radeon_bo_va *bo_va,
		2830	struct ttm_mem_reg *mem);
2997	Serge	2831	void radeon_vm_bo_invalidate(struct radeon_device *rdev,
		2832	struct radeon_bo *bo);
		2833	struct radeon_bo_va radeon_vm_bo_find(struct radeon_vm vm,
		2834	struct radeon_bo *bo);
		2835	struct radeon_bo_va radeon_vm_bo_add(struct radeon_device rdev,
		2836	struct radeon_vm *vm,
		2837	struct radeon_bo *bo);
		2838	int radeon_vm_bo_set_addr(struct radeon_device *rdev,
		2839	struct radeon_bo_va *bo_va,
		2840	uint64_t offset,
		2841	uint32_t flags);
5078	serge	2842	void radeon_vm_bo_rmv(struct radeon_device *rdev,
6104	serge	2843	struct radeon_bo_va *bo_va);
2997	Serge	2844
		2845	/* audio */
		2846	void r600_audio_update_hdmi(struct work_struct *work);
5078	serge	2847	struct r600_audio_pin r600_audio_get_pin(struct radeon_device rdev);
		2848	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev);
		2849	void r600_audio_enable(struct radeon_device *rdev,
		2850	struct r600_audio_pin *pin,
5271	serge	2851	u8 enable_mask);
5078	serge	2852	void dce6_audio_enable(struct radeon_device *rdev,
		2853	struct r600_audio_pin *pin,
5271	serge	2854	u8 enable_mask);
2997	Serge	2855
		2856	/*
		2857	* R600 vram scratch functions
		2858	*/
		2859	int r600_vram_scratch_init(struct radeon_device *rdev);
		2860	void r600_vram_scratch_fini(struct radeon_device *rdev);
		2861
		2862	/*
		2863	* r600 cs checking helper
		2864	*/
		2865	unsigned r600_mip_minify(unsigned size, unsigned level);
		2866	bool r600_fmt_is_valid_color(u32 format);
		2867	bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
		2868	int r600_fmt_get_blocksize(u32 format);
		2869	int r600_fmt_get_nblocksx(u32 format, u32 w);
		2870	int r600_fmt_get_nblocksy(u32 format, u32 h);
		2871
		2872	/*
1963	serge	2873	* r600 functions used by radeon_encoder.c
		2874	*/
2997	Serge	2875	struct radeon_hdmi_acr {
		2876	u32 clock;
		2877
		2878	int n_32khz;
		2879	int cts_32khz;
		2880
		2881	int n_44_1khz;
		2882	int cts_44_1khz;
		2883
		2884	int n_48khz;
		2885	int cts_48khz;
		2886
		2887	};
		2888
		2889	extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
		2890
		2891	extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
		2892	u32 tiling_pipe_num,
		2893	u32 max_rb_num,
		2894	u32 total_max_rb_num,
		2895	u32 enabled_rb_mask);
1179	serge	2896
2997	Serge	2897	/*
		2898	* evergreen functions used by radeon_encoder.c
		2899	*/
		2900
1963	serge	2901	extern int ni_init_microcode(struct radeon_device *rdev);
		2902	extern int ni_mc_load_microcode(struct radeon_device *rdev);
1221	serge	2903
1963	serge	2904	/* radeon_acpi.c */
		2905	#if defined(CONFIG_ACPI)
		2906	extern int radeon_acpi_init(struct radeon_device *rdev);
2997	Serge	2907	extern void radeon_acpi_fini(struct radeon_device *rdev);
5078	serge	2908	extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
		2909	extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
		2910	u8 perf_req, bool advertise);
		2911	extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
1963	serge	2912	#else
		2913	static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2997	Serge	2914	static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1963	serge	2915	#endif
1179	serge	2916
5078	serge	2917	int radeon_cs_packet_parse(struct radeon_cs_parser *p,
		2918	struct radeon_cs_packet *pkt,
		2919	unsigned idx);
		2920	bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
		2921	void radeon_cs_dump_packet(struct radeon_cs_parser *p,
		2922	struct radeon_cs_packet *pkt);
		2923	int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
5271	serge	2924	struct radeon_bo_list **cs_reloc,
5078	serge	2925	int nomm);
		2926	int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
		2927	uint32_t *vline_start_end,
		2928	uint32_t *vline_status);
		2929
1321	serge	2930	#include "radeon_object.h"
1179	serge	2931
5271	serge	2932	#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
6104	serge	2933	#define PCI_VENDOR_ID_ATI 0x1002
1117	serge	2934
		2935	resource_size_t
		2936	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		2937	resource_size_t
		2938	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		2939
		2940
3764	Serge	2941	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h – Rev 6104