WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	/* TODO: Here are things that needs to be done :
		32	* - surface allocator & initializer : (bit like scratch reg) should
		33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		34	* related to surface
		35	* - WB : write back stuff (do it bit like scratch reg things)
		36	* - Vblank : look at Jesse's rework and what we should do
		37	* - r600/r700: gart & cp
		38	* - cs : clean cs ioctl use bitmap & things like that.
		39	* - power management stuff
		40	* - Barrier in gart code
		41	* - Unmappabled vram ?
		42	* - TESTING, TESTING, TESTING
		43	*/
		44
1221	serge	45	/* Initialization path:
		46	* We expect that acceleration initialization might fail for various
		47	* reasons even thought we work hard to make it works on most
		48	* configurations. In order to still have a working userspace in such
		49	* situation the init path must succeed up to the memory controller
		50	* initialization point. Failure before this point are considered as
		51	* fatal error. Here is the init callchain :
		52	* radeon_device_init perform common structure, mutex initialization
		53	* asic_init setup the GPU memory layout and perform all
		54	* one time initialization (failure in this
		55	* function are considered fatal)
		56	* asic_startup setup the GPU acceleration, in order to
		57	* follow guideline the first thing this
		58	* function should do is setting the GPU
		59	* memory controller (only MC setup failure
		60	* are considered as fatal)
		61	*/
		62
5271	serge	63	#include
2997	Serge	64	#include
1321	serge	65	#include
		66	#include
5078	serge	67	#include
2997	Serge	68	#include
5271	serge	69	#include
1221	serge	70
1321	serge	71	#include
		72	#include
		73	#include
5078	serge	74	//#include
		75	#include
5346	serge	76	#include
1221	serge	77
5271	serge	78	#include
		79
2004	serge	80	#include
5271	serge	81	#include
1117	serge	82
1179	serge	83	#include "radeon_family.h"
1117	serge	84	#include "radeon_mode.h"
		85	#include "radeon_reg.h"
		86
		87	#include
		88
1179	serge	89	/*
		90	* Modules parameters.
		91	*/
		92	extern int radeon_no_wb;
1123	serge	93	extern int radeon_modeset;
1117	serge	94	extern int radeon_dynclks;
1123	serge	95	extern int radeon_r4xx_atom;
1128	serge	96	extern int radeon_agpmode;
		97	extern int radeon_vram_limit;
1117	serge	98	extern int radeon_gart_size;
1128	serge	99	extern int radeon_benchmarking;
1179	serge	100	extern int radeon_testing;
1123	serge	101	extern int radeon_connector_table;
1179	serge	102	extern int radeon_tv;
1403	serge	103	extern int radeon_audio;
1963	serge	104	extern int radeon_disp_priority;
		105	extern int radeon_hw_i2c;
		106	extern int radeon_pcie_gen2;
2997	Serge	107	extern int radeon_msi;
		108	extern int radeon_lockup_timeout;
3764	Serge	109	extern int radeon_fastfb;
5078	serge	110	extern int radeon_dpm;
		111	extern int radeon_aspm;
		112	extern int radeon_runtime_pm;
		113	extern int radeon_hard_reset;
		114	extern int radeon_vm_size;
		115	extern int radeon_vm_block_size;
		116	extern int radeon_deep_color;
		117	extern int radeon_use_pflipirq;
		118	extern int radeon_bapm;
5179	serge	119	extern int radeon_backlight;
2997	Serge	120
		121
1430	serge	122	typedef struct pm_message {
		123	int event;
		124	} pm_message_t;
		125
1233	serge	126	typedef struct
		127	{
		128	int width;
		129	int height;
		130	int bpp;
		131	int freq;
1321	serge	132	}videomode_t;
1179	serge	133
		134
		135
1963	serge	136	static inline u32 ioread32(const volatile void __iomem *addr)
		137	{
		138	return in32((u32)addr);
		139	}
		140
3764	Serge	141	//static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
		142	//{
		143	// out32((u32)addr, b);
		144	//}
1963	serge	145
		146
1117	serge	147	/*
		148	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		149	* symbol;
		150	*/
1120	serge	151	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1963	serge	152	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
1428	serge	153	/* RADEON_IB_POOL_SIZE must be a power of 2 */
1120	serge	154	#define RADEON_IB_POOL_SIZE 16
2997	Serge	155	#define RADEON_DEBUGFS_MAX_COMPONENTS 32
1120	serge	156	#define RADEONFB_CONN_LIMIT 4
1179	serge	157	#define RADEON_BIOS_NUM_SCRATCH 8
1117	serge	158
2997	Serge	159	/* internal ring indices */
		160	/* r1xx+ has gfx CP ring */
		161	#define RADEON_RING_TYPE_GFX_INDEX 0
		162
		163	/* cayman has 2 compute CP rings */
		164	#define CAYMAN_RING_TYPE_CP1_INDEX 1
		165	#define CAYMAN_RING_TYPE_CP2_INDEX 2
		166
3192	Serge	167	/* R600+ has an async dma ring */
		168	#define R600_RING_TYPE_DMA_INDEX 3
		169	/* cayman add a second async dma ring */
		170	#define CAYMAN_RING_TYPE_DMA1_INDEX 4
		171
3764	Serge	172	/* R600+ */
		173	#define R600_RING_TYPE_UVD_INDEX 5
		174
5078	serge	175	/* TN+ */
		176	#define TN_RING_TYPE_VCE1_INDEX 6
		177	#define TN_RING_TYPE_VCE2_INDEX 7
		178
		179	/* max number of rings */
		180	#define RADEON_NUM_RINGS 8
		181
		182	/* number of hw syncs before falling back on blocking */
		183	#define RADEON_NUM_SYNCS 4
		184
2997	Serge	185	/* hardcode those limit for now */
		186	#define RADEON_VA_IB_OFFSET (1 << 20)
		187	#define RADEON_VA_RESERVED_SIZE (8 << 20)
		188	#define RADEON_IB_VM_MAX_SIZE (64 << 10)
		189
5078	serge	190	/* hard reset data */
		191	#define RADEON_ASIC_RESET_DATA 0x39d5e86b
		192
3192	Serge	193	/* reset flags */
		194	#define RADEON_RESET_GFX (1 << 0)
		195	#define RADEON_RESET_COMPUTE (1 << 1)
		196	#define RADEON_RESET_DMA (1 << 2)
3764	Serge	197	#define RADEON_RESET_CP (1 << 3)
		198	#define RADEON_RESET_GRBM (1 << 4)
		199	#define RADEON_RESET_DMA1 (1 << 5)
		200	#define RADEON_RESET_RLC (1 << 6)
		201	#define RADEON_RESET_SEM (1 << 7)
		202	#define RADEON_RESET_IH (1 << 8)
		203	#define RADEON_RESET_VMC (1 << 9)
		204	#define RADEON_RESET_MC (1 << 10)
		205	#define RADEON_RESET_DISPLAY (1 << 11)
3192	Serge	206
5078	serge	207	/* CG block flags */
		208	#define RADEON_CG_BLOCK_GFX (1 << 0)
		209	#define RADEON_CG_BLOCK_MC (1 << 1)
		210	#define RADEON_CG_BLOCK_SDMA (1 << 2)
		211	#define RADEON_CG_BLOCK_UVD (1 << 3)
		212	#define RADEON_CG_BLOCK_VCE (1 << 4)
		213	#define RADEON_CG_BLOCK_HDP (1 << 5)
		214	#define RADEON_CG_BLOCK_BIF (1 << 6)
		215
		216	/* CG flags */
		217	#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
		218	#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
		219	#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
		220	#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
		221	#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
		222	#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
		223	#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
		224	#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
		225	#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
		226	#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
		227	#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
		228	#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
		229	#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
		230	#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
		231	#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
		232	#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
		233	#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
		234
		235	/* PG flags */
		236	#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
		237	#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
		238	#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
		239	#define RADEON_PG_SUPPORT_UVD (1 << 3)
		240	#define RADEON_PG_SUPPORT_VCE (1 << 4)
		241	#define RADEON_PG_SUPPORT_CP (1 << 5)
		242	#define RADEON_PG_SUPPORT_GDS (1 << 6)
		243	#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
		244	#define RADEON_PG_SUPPORT_SDMA (1 << 8)
		245	#define RADEON_PG_SUPPORT_ACP (1 << 9)
		246	#define RADEON_PG_SUPPORT_SAMU (1 << 10)
		247
		248	/* max cursor sizes (in pixels) */
		249	#define CURSOR_WIDTH 64
		250	#define CURSOR_HEIGHT 64
		251
		252	#define CIK_CURSOR_WIDTH 128
		253	#define CIK_CURSOR_HEIGHT 128
		254
1117	serge	255	/*
		256	* Errata workarounds.
		257	*/
		258	enum radeon_pll_errata {
		259	CHIP_ERRATA_R300_CG = 0x00000001,
		260	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		261	CHIP_ERRATA_PLL_DELAY = 0x00000004
		262	};
		263
		264
		265	struct radeon_device;
		266
		267
		268	/*
		269	* BIOS.
		270	*/
		271	bool radeon_get_bios(struct radeon_device *rdev);
		272
		273	/*
1179	serge	274	* Dummy page
		275	*/
		276	struct radeon_dummy_page {
		277	struct page *page;
		278	dma_addr_t addr;
		279	};
		280	int radeon_dummy_page_init(struct radeon_device *rdev);
		281	void radeon_dummy_page_fini(struct radeon_device *rdev);
		282
		283
		284	/*
1117	serge	285	* Clocks
		286	*/
		287	struct radeon_clock {
		288	struct radeon_pll p1pll;
		289	struct radeon_pll p2pll;
1430	serge	290	struct radeon_pll dcpll;
1117	serge	291	struct radeon_pll spll;
		292	struct radeon_pll mpll;
		293	/* 10 Khz units */
		294	uint32_t default_mclk;
		295	uint32_t default_sclk;
1430	serge	296	uint32_t default_dispclk;
5078	serge	297	uint32_t current_dispclk;
1430	serge	298	uint32_t dp_extclk;
1963	serge	299	uint32_t max_pixel_clock;
1117	serge	300	};
		301
1268	serge	302	/*
		303	* Power management
		304	*/
		305	int radeon_pm_init(struct radeon_device *rdev);
5078	serge	306	int radeon_pm_late_init(struct radeon_device *rdev);
1963	serge	307	void radeon_pm_fini(struct radeon_device *rdev);
1430	serge	308	void radeon_pm_compute_clocks(struct radeon_device *rdev);
1963	serge	309	void radeon_pm_suspend(struct radeon_device *rdev);
		310	void radeon_pm_resume(struct radeon_device *rdev);
1430	serge	311	void radeon_combios_get_power_modes(struct radeon_device *rdev);
		312	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
3764	Serge	313	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		314	u8 clock_type,
		315	u32 clock,
		316	bool strobe_mode,
		317	struct atom_clock_dividers *dividers);
5078	serge	318	int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
		319	u32 clock,
		320	bool strobe_mode,
		321	struct atom_mpll_param *mpll_param);
1963	serge	322	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
5078	serge	323	int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
		324	u16 voltage_level, u8 voltage_type,
		325	u32 gpio_value, u32 gpio_mask);
		326	void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
		327	u32 eng_clock, u32 mem_clock);
		328	int radeon_atom_get_voltage_step(struct radeon_device *rdev,
		329	u8 voltage_type, u16 *voltage_step);
		330	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		331	u16 voltage_id, u16 *voltage);
		332	int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
		333	u16 *voltage,
		334	u16 leakage_idx);
		335	int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
		336	u16 *leakage_id);
		337	int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
		338	u16 vddc, u16 vddci,
		339	u16 virtual_voltage_id,
		340	u16 vbios_voltage_id);
		341	int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
		342	u16 virtual_voltage_id,
		343	u16 *voltage);
		344	int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
		345	u8 voltage_type,
		346	u16 nominal_voltage,
		347	u16 *true_voltage);
		348	int radeon_atom_get_min_voltage(struct radeon_device *rdev,
		349	u8 voltage_type, u16 *min_voltage);
		350	int radeon_atom_get_max_voltage(struct radeon_device *rdev,
		351	u8 voltage_type, u16 *max_voltage);
		352	int radeon_atom_get_voltage_table(struct radeon_device *rdev,
		353	u8 voltage_type, u8 voltage_mode,
		354	struct atom_voltage_table *voltage_table);
		355	bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
		356	u8 voltage_type, u8 voltage_mode);
		357	int radeon_atom_get_svi2_info(struct radeon_device *rdev,
		358	u8 voltage_type,
		359	u8 svd_gpio_id, u8 svc_gpio_id);
		360	void radeon_atom_update_memory_dll(struct radeon_device *rdev,
		361	u32 mem_clock);
		362	void radeon_atom_set_ac_timing(struct radeon_device *rdev,
		363	u32 mem_clock);
		364	int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
		365	u8 module_index,
		366	struct atom_mc_reg_table *reg_table);
		367	int radeon_atom_get_memory_info(struct radeon_device *rdev,
		368	u8 module_index, struct atom_memory_info *mem_info);
		369	int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
		370	bool gddr5, u8 module_index,
		371	struct atom_memory_clock_range_table *mclk_range_table);
		372	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		373	u16 voltage_id, u16 *voltage);
1963	serge	374	void rs690_pm_info(struct radeon_device *rdev);
2997	Serge	375	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
		376	unsigned bankh, unsigned mtaspect,
		377	unsigned *tile_split);
1179	serge	378
1117	serge	379	/*
		380	* Fences.
		381	*/
		382	struct radeon_fence_driver {
5271	serge	383	struct radeon_device *rdev;
1117	serge	384	uint32_t scratch_reg;
2997	Serge	385	uint64_t gpu_addr;
		386	volatile uint32_t *cpu_addr;
		387	/* sync_seq is protected by ring emission lock */
		388	uint64_t sync_seq[RADEON_NUM_RINGS];
		389	atomic64_t last_seq;
5271	serge	390	bool initialized, delayed_irq;
		391	struct delayed_work lockup_work;
1117	serge	392	};
		393
		394	struct radeon_fence {
5271	serge	395	struct fence base;
		396
2997	Serge	397	struct radeon_device *rdev;
		398	uint64_t seq;
		399	/* RB, DMA, etc. */
		400	unsigned ring;
5271	serge	401	bool is_vm_update;
		402
		403	wait_queue_t fence_wake;
1117	serge	404	};
		405
2997	Serge	406	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
1117	serge	407	int radeon_fence_driver_init(struct radeon_device *rdev);
		408	void radeon_fence_driver_fini(struct radeon_device *rdev);
5271	serge	409	void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
2997	Serge	410	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);
		411	void radeon_fence_process(struct radeon_device *rdev, int ring);
1117	serge	412	bool radeon_fence_signaled(struct radeon_fence *fence);
		413	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
5078	serge	414	int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
		415	int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
2997	Serge	416	int radeon_fence_wait_any(struct radeon_device *rdev,
		417	struct radeon_fence **fences,
		418	bool intr);
1117	serge	419	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		420	void radeon_fence_unref(struct radeon_fence **fence);
2997	Serge	421	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
		422	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
		423	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
		424	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,
		425	struct radeon_fence *b)
		426	{
		427	if (!a) {
		428	return b;
		429	}
1117	serge	430
2997	Serge	431	if (!b) {
		432	return a;
		433	}
		434
		435	BUG_ON(a->ring != b->ring);
		436
		437	if (a->seq > b->seq) {
		438	return a;
		439	} else {
		440	return b;
		441	}
		442	}
		443
		444	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
		445	struct radeon_fence *b)
		446	{
		447	if (!a) {
		448	return false;
		449	}
		450
		451	if (!b) {
		452	return true;
		453	}
		454
		455	BUG_ON(a->ring != b->ring);
		456
		457	return a->seq < b->seq;
		458	}
		459
1179	serge	460	/*
		461	* Tiling registers
		462	*/
		463	struct radeon_surface_reg {
1321	serge	464	struct radeon_bo *bo;
1179	serge	465	};
1117	serge	466
1179	serge	467	#define RADEON_GEM_MAX_SURFACES 8
		468
1117	serge	469	/*
1321	serge	470	* TTM.
1117	serge	471	*/
1321	serge	472	struct radeon_mman {
		473	struct ttm_bo_global_ref bo_global_ref;
3764	Serge	474	struct drm_global_reference mem_global_ref;
1403	serge	475	struct ttm_bo_device bdev;
1321	serge	476	bool mem_global_referenced;
1403	serge	477	bool initialized;
5078	serge	478
		479	#if defined(CONFIG_DEBUG_FS)
		480	struct dentry *vram;
		481	struct dentry *gtt;
		482	#endif
1321	serge	483	};
1117	serge	484
5271	serge	485	struct radeon_bo_list {
		486	struct radeon_bo *robj;
		487	struct ttm_validate_buffer tv;
		488	uint64_t gpu_offset;
		489	unsigned prefered_domains;
		490	unsigned allowed_domains;
		491	uint32_t tiling_flags;
		492	};
		493
2997	Serge	494	/* bo virtual address in a specific vm */
		495	struct radeon_bo_va {
		496	/* protected by bo being reserved */
		497	struct list_head bo_list;
		498	uint32_t flags;
5078	serge	499	uint64_t addr;
5271	serge	500	struct radeon_fence *last_pt_update;
2997	Serge	501	unsigned ref_count;
		502
		503	/* protected by vm mutex */
5078	serge	504	struct interval_tree_node it;
		505	struct list_head vm_status;
2997	Serge	506
		507	/* constant after initialization */
		508	struct radeon_vm *vm;
		509	struct radeon_bo *bo;
		510	};
		511
1321	serge	512	struct radeon_bo {
		513	/* Protected by gem.mutex */
		514	struct list_head list;
		515	/* Protected by tbo.reserved */
5078	serge	516	u32 initial_domain;
5271	serge	517	struct ttm_place placements[4];
5078	serge	518	struct ttm_placement placement;
		519	struct ttm_buffer_object tbo;
1321	serge	520	struct ttm_bo_kmap_obj kmap;
5078	serge	521	u32 flags;
1404	serge	522	unsigned pin_count;
		523	void *kptr;
		524	u32 tiling_flags;
		525	u32 pitch;
		526	int surface_reg;
2997	Serge	527	/* list of all virtual address to which this bo
		528	* is associated to
		529	*/
		530	struct list_head va;
1321	serge	531	/* Constant after initialization */
		532	struct radeon_device *rdev;
1963	serge	533	struct drm_gem_object gem_base;
3120	serge	534
5078	serge	535	pid_t pid;
5271	serge	536
		537	struct radeon_mn *mn;
1321	serge	538	};
1963	serge	539	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
1321	serge	540
3764	Serge	541	int radeon_gem_debugfs_init(struct radeon_device *rdev);
		542
2997	Serge	543	/* sub-allocation manager, it has to be protected by another lock.
		544	* By conception this is an helper for other part of the driver
		545	* like the indirect buffer or semaphore, which both have their
		546	* locking.
		547	*
		548	* Principe is simple, we keep a list of sub allocation in offset
		549	* order (first entry has offset == 0, last entry has the highest
		550	* offset).
		551	*
		552	* When allocating new object we first check if there is room at
		553	* the end total_size - (last_object_offset + last_object_size) >=
		554	* alloc_size. If so we allocate new object there.
		555	*
		556	* When there is not enough room at the end, we start waiting for
		557	* each sub object until we reach object_offset+object_size >=
		558	* alloc_size, this object then become the sub object we return.
		559	*
		560	* Alignment can't be bigger than page size.
		561	*
		562	* Hole are not considered for allocation to keep things simple.
		563	* Assumption is that there won't be hole (all object on same
		564	* alignment).
		565	*/
		566	struct radeon_sa_manager {
		567	wait_queue_head_t wq;
		568	struct radeon_bo *bo;
		569	struct list_head *hole;
		570	struct list_head flist[RADEON_NUM_RINGS];
		571	struct list_head olist;
		572	unsigned size;
		573	uint64_t gpu_addr;
		574	void *cpu_ptr;
		575	uint32_t domain;
5078	serge	576	uint32_t align;
2997	Serge	577	};
		578
		579	struct radeon_sa_bo;
		580
		581	/* sub-allocation buffer */
		582	struct radeon_sa_bo {
		583	struct list_head olist;
		584	struct list_head flist;
		585	struct radeon_sa_manager *manager;
		586	unsigned soffset;
		587	unsigned eoffset;
		588	struct radeon_fence *fence;
		589	};
		590
1123	serge	591	/*
		592	* GEM objects.
		593	*/
		594	struct radeon_gem {
1630	serge	595	struct mutex mutex;
1123	serge	596	struct list_head objects;
		597	};
1117	serge	598
1126	serge	599	int radeon_gem_init(struct radeon_device *rdev);
		600	void radeon_gem_fini(struct radeon_device *rdev);
5078	serge	601	int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
1126	serge	602	int alignment, int initial_domain,
5078	serge	603	u32 flags, bool kernel,
1126	serge	604	struct drm_gem_object **obj);
1117	serge	605
2004	serge	606	int radeon_mode_dumb_create(struct drm_file *file_priv,
		607	struct drm_device *dev,
		608	struct drm_mode_create_dumb *args);
		609	int radeon_mode_dumb_mmap(struct drm_file *filp,
		610	struct drm_device *dev,
		611	uint32_t handle, uint64_t *offset_p);
1117	serge	612
		613	/*
2997	Serge	614	* Semaphores.
1117	serge	615	*/
2997	Serge	616	struct radeon_semaphore {
		617	struct radeon_sa_bo *sa_bo;
		618	signed waiters;
		619	uint64_t gpu_addr;
1117	serge	620	};
		621
2997	Serge	622	int radeon_semaphore_create(struct radeon_device *rdev,
		623	struct radeon_semaphore **semaphore);
5078	serge	624	bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
2997	Serge	625	struct radeon_semaphore *semaphore);
5078	serge	626	bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
2997	Serge	627	struct radeon_semaphore *semaphore);
		628	void radeon_semaphore_free(struct radeon_device *rdev,
		629	struct radeon_semaphore **semaphore,
		630	struct radeon_fence *fence);
1117	serge	631
2997	Serge	632	/*
5271	serge	633	* Synchronization
		634	*/
		635	struct radeon_sync {
		636	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
		637	struct radeon_fence *sync_to[RADEON_NUM_RINGS];
		638	struct radeon_fence *last_vm_update;
		639	};
		640
		641	void radeon_sync_create(struct radeon_sync *sync);
		642	void radeon_sync_fence(struct radeon_sync *sync,
		643	struct radeon_fence *fence);
		644	int radeon_sync_resv(struct radeon_device *rdev,
		645	struct radeon_sync *sync,
		646	struct reservation_object *resv,
		647	bool shared);
		648	int radeon_sync_rings(struct radeon_device *rdev,
		649	struct radeon_sync *sync,
		650	int waiting_ring);
		651	void radeon_sync_free(struct radeon_device rdev, struct radeon_sync sync,
		652	struct radeon_fence *fence);
		653
		654	/*
2997	Serge	655	* GART structures, functions & helpers
		656	*/
		657	struct radeon_mc;
1117	serge	658
1268	serge	659	#define RADEON_GPU_PAGE_SIZE 4096
1430	serge	660	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
2997	Serge	661	#define RADEON_GPU_PAGE_SHIFT 12
		662	#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
1268	serge	663
5078	serge	664	#define RADEON_GART_PAGE_DUMMY 0
		665	#define RADEON_GART_PAGE_VALID (1 << 0)
		666	#define RADEON_GART_PAGE_READ (1 << 1)
		667	#define RADEON_GART_PAGE_WRITE (1 << 2)
		668	#define RADEON_GART_PAGE_SNOOP (1 << 3)
		669
1117	serge	670	struct radeon_gart {
		671	dma_addr_t table_addr;
2997	Serge	672	struct radeon_bo *robj;
		673	void *ptr;
1117	serge	674	unsigned num_gpu_pages;
		675	unsigned num_cpu_pages;
		676	unsigned table_size;
		677	struct page **pages;
		678	dma_addr_t *pages_addr;
		679	bool ready;
		680	};
		681
		682	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		683	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		684	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		685	void radeon_gart_table_vram_free(struct radeon_device *rdev);
2997	Serge	686	int radeon_gart_table_vram_pin(struct radeon_device *rdev);
		687	void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
1117	serge	688	int radeon_gart_init(struct radeon_device *rdev);
		689	void radeon_gart_fini(struct radeon_device *rdev);
		690	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		691	int pages);
1120	serge	692	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
5078	serge	693	int pages, struct page **pagelist,
		694	dma_addr_t *dma_addr, uint32_t flags);
1117	serge	695
		696
		697	/*
		698	* GPU MC structures, functions & helpers
		699	*/
		700	struct radeon_mc {
		701	resource_size_t aper_size;
		702	resource_size_t aper_base;
		703	resource_size_t agp_base;
1179	serge	704	/* for some chips with <= 32MB we need to lie
		705	* about vram size near mc fb location */
		706	u64 mc_vram_size;
1430	serge	707	u64 visible_vram_size;
1179	serge	708	u64 gtt_size;
		709	u64 gtt_start;
		710	u64 gtt_end;
		711	u64 vram_start;
		712	u64 vram_end;
1117	serge	713	unsigned vram_width;
1179	serge	714	u64 real_vram_size;
1117	serge	715	int vram_mtrr;
		716	bool vram_is_ddr;
1403	serge	717	bool igp_sideport_enabled;
1963	serge	718	u64 gtt_base_align;
3764	Serge	719	u64 mc_mask;
1117	serge	720	};
		721
1403	serge	722	bool radeon_combios_sideport_present(struct radeon_device *rdev);
		723	bool radeon_atombios_sideport_present(struct radeon_device *rdev);
1117	serge	724
		725	/*
		726	* GPU scratch registers structures, functions & helpers
		727	*/
		728	struct radeon_scratch {
		729	unsigned num_reg;
1963	serge	730	uint32_t reg_base;
1117	serge	731	bool free[32];
		732	uint32_t reg[32];
		733	};
		734
		735	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		736	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		737
5078	serge	738	/*
		739	* GPU doorbell structures, functions & helpers
		740	*/
		741	#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
1117	serge	742
5078	serge	743	struct radeon_doorbell {
		744	/* doorbell mmio */
		745	resource_size_t base;
		746	resource_size_t size;
		747	u32 __iomem *ptr;
		748	u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
		749	unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
		750	};
		751
		752	int radeon_doorbell_get(struct radeon_device rdev, u32 page);
		753	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
5271	serge	754	void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
		755	phys_addr_t *aperture_base,
		756	size_t *aperture_size,
		757	size_t *start_offset);
5078	serge	758
1117	serge	759	/*
		760	* IRQS.
		761	*/
1963	serge	762	struct r500_irq_stat_regs {
		763	u32 disp_int;
2997	Serge	764	u32 hdmi0_status;
1963	serge	765	};
		766
		767	struct r600_irq_stat_regs {
		768	u32 disp_int;
		769	u32 disp_int_cont;
		770	u32 disp_int_cont2;
		771	u32 d1grph_int;
		772	u32 d2grph_int;
2997	Serge	773	u32 hdmi0_status;
		774	u32 hdmi1_status;
1963	serge	775	};
		776
		777	struct evergreen_irq_stat_regs {
		778	u32 disp_int;
		779	u32 disp_int_cont;
		780	u32 disp_int_cont2;
		781	u32 disp_int_cont3;
		782	u32 disp_int_cont4;
		783	u32 disp_int_cont5;
		784	u32 d1grph_int;
		785	u32 d2grph_int;
		786	u32 d3grph_int;
		787	u32 d4grph_int;
		788	u32 d5grph_int;
		789	u32 d6grph_int;
2997	Serge	790	u32 afmt_status1;
		791	u32 afmt_status2;
		792	u32 afmt_status3;
		793	u32 afmt_status4;
		794	u32 afmt_status5;
		795	u32 afmt_status6;
1963	serge	796	};
		797
5078	serge	798	struct cik_irq_stat_regs {
		799	u32 disp_int;
		800	u32 disp_int_cont;
		801	u32 disp_int_cont2;
		802	u32 disp_int_cont3;
		803	u32 disp_int_cont4;
		804	u32 disp_int_cont5;
		805	u32 disp_int_cont6;
		806	u32 d1grph_int;
		807	u32 d2grph_int;
		808	u32 d3grph_int;
		809	u32 d4grph_int;
		810	u32 d5grph_int;
		811	u32 d6grph_int;
		812	};
		813
1963	serge	814	union radeon_irq_stat_regs {
		815	struct r500_irq_stat_regs r500;
		816	struct r600_irq_stat_regs r600;
		817	struct evergreen_irq_stat_regs evergreen;
5078	serge	818	struct cik_irq_stat_regs cik;
1963	serge	819	};
		820
1117	serge	821	struct radeon_irq {
		822	bool installed;
2997	Serge	823	spinlock_t lock;
		824	atomic_t ring_int[RADEON_NUM_RINGS];
		825	bool crtc_vblank_int[RADEON_MAX_CRTCS];
		826	atomic_t pflip[RADEON_MAX_CRTCS];
1963	serge	827	wait_queue_head_t vblank_queue;
2997	Serge	828	bool hpd[RADEON_MAX_HPD_PINS];
		829	bool afmt[RADEON_MAX_AFMT_BLOCKS];
1963	serge	830	union radeon_irq_stat_regs stat_regs;
5078	serge	831	bool dpm_thermal;
1117	serge	832	};
		833
		834	int radeon_irq_kms_init(struct radeon_device *rdev);
		835	void radeon_irq_kms_fini(struct radeon_device *rdev);
2997	Serge	836	void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
5271	serge	837	bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
2997	Serge	838	void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
2004	serge	839	void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
		840	void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
2997	Serge	841	void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
		842	void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
		843	void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
		844	void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
1117	serge	845
		846	/*
2997	Serge	847	* CP & rings.
1117	serge	848	*/
2997	Serge	849
1117	serge	850	struct radeon_ib {
2997	Serge	851	struct radeon_sa_bo *sa_bo;
		852	uint32_t length_dw;
1403	serge	853	uint64_t gpu_addr;
2997	Serge	854	uint32_t *ptr;
		855	int ring;
1117	serge	856	struct radeon_fence *fence;
2997	Serge	857	struct radeon_vm *vm;
		858	bool is_const_ib;
5271	serge	859	struct radeon_sync sync;
1117	serge	860	};
		861
2997	Serge	862	struct radeon_ring {
1321	serge	863	struct radeon_bo *ring_obj;
1117	serge	864	volatile uint32_t *ring;
2997	Serge	865	unsigned rptr_offs;
		866	unsigned rptr_save_reg;
		867	u64 next_rptr_gpu_addr;
		868	volatile u32 *next_rptr_cpu_addr;
5078	serge	869	unsigned wptr;
		870	unsigned wptr_old;
		871	unsigned ring_size;
		872	unsigned ring_free_dw;
		873	int count_dw;
		874	atomic_t last_rptr;
		875	atomic64_t last_activity;
		876	uint64_t gpu_addr;
		877	uint32_t align_mask;
		878	uint32_t ptr_mask;
		879	bool ready;
2997	Serge	880	u32 nop;
		881	u32 idx;
3764	Serge	882	u64 last_semaphore_signal_addr;
		883	u64 last_semaphore_wait_addr;
5078	serge	884	/* for CIK queues */
		885	u32 me;
		886	u32 pipe;
		887	u32 queue;
		888	struct radeon_bo *mqd_obj;
		889	u32 doorbell_index;
		890	unsigned wptr_offs;
1117	serge	891	};
		892
5078	serge	893	struct radeon_mec {
		894	struct radeon_bo *hpd_eop_obj;
		895	u64 hpd_eop_gpu_addr;
		896	u32 num_pipe;
		897	u32 num_mec;
		898	u32 num_queue;
		899	};
		900
1321	serge	901	/*
2997	Serge	902	* VM
		903	*/
		904
		905	/* maximum number of VMIDs */
		906	#define RADEON_NUM_VM 16
		907
		908	/* number of entries in page table */
5078	serge	909	#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
2997	Serge	910
5078	serge	911	/* PTBs (Page Table Blocks) need to be aligned to 32K */
		912	#define RADEON_VM_PTB_ALIGN_SIZE 32768
		913	#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
		914	#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
		915
		916	#define R600_PTE_VALID (1 << 0)
		917	#define R600_PTE_SYSTEM (1 << 1)
		918	#define R600_PTE_SNOOPED (1 << 2)
		919	#define R600_PTE_READABLE (1 << 5)
		920	#define R600_PTE_WRITEABLE (1 << 6)
		921
		922	/* PTE (Page Table Entry) fragment field for different page sizes */
		923	#define R600_PTE_FRAG_4KB (0 << 7)
		924	#define R600_PTE_FRAG_64KB (4 << 7)
		925	#define R600_PTE_FRAG_256KB (6 << 7)
		926
		927	/* flags needed to be set so we can copy directly from the GART table */
		928	#define R600_PTE_GART_MASK ( R600_PTE_READABLE \| R600_PTE_WRITEABLE \| \
		929	R600_PTE_SYSTEM \| R600_PTE_VALID )
		930
		931	struct radeon_vm_pt {
		932	struct radeon_bo *bo;
		933	uint64_t addr;
		934	};
		935
5271	serge	936	struct radeon_vm_id {
		937	unsigned id;
		938	uint64_t pd_gpu_addr;
		939	/* last flushed PD/PT update */
		940	struct radeon_fence *flushed_updates;
		941	/* last use of vmid */
		942	struct radeon_fence *last_id_use;
		943	};
		944
2997	Serge	945	struct radeon_vm {
5271	serge	946	struct mutex mutex;
		947
5078	serge	948	struct rb_root va;
2997	Serge	949
5271	serge	950	/* protecting invalidated and freed */
		951	spinlock_t status_lock;
		952
5078	serge	953	/* BOs moved, but not yet updated in the PT */
		954	struct list_head invalidated;
		955
		956	/* BOs freed, but not yet updated in the PT */
		957	struct list_head freed;
		958
2997	Serge	959	/* contains the page directory */
5078	serge	960	struct radeon_bo *page_directory;
		961	unsigned max_pde_used;
2997	Serge	962
		963	/* array of page tables, one for each page directory entry */
5078	serge	964	struct radeon_vm_pt *page_tables;
2997	Serge	965
5078	serge	966	struct radeon_bo_va *ib_bo_va;
		967
5271	serge	968	/* for id and flush management per ring */
		969	struct radeon_vm_id ids[RADEON_NUM_RINGS];
2997	Serge	970	};
		971
		972	struct radeon_vm_manager {
		973	struct radeon_fence *active[RADEON_NUM_VM];
		974	uint32_t max_pfn;
		975	/* number of VMIDs */
		976	unsigned nvm;
		977	/* vram base address for page table entry */
		978	u64 vram_base_offset;
		979	/* is vm enabled? */
		980	bool enabled;
5078	serge	981	/* for hw to save the PD addr on suspend/resume */
		982	uint32_t saved_table_addr[RADEON_NUM_VM];
2997	Serge	983	};
		984
		985	/*
		986	* file private structure
		987	*/
		988	struct radeon_fpriv {
		989	struct radeon_vm vm;
		990	};
		991
		992	/*
1321	serge	993	* R6xx+ IH ring
		994	*/
		995	struct r600_ih {
		996	struct radeon_bo *ring_obj;
		997	volatile uint32_t *ring;
		998	unsigned rptr;
		999	unsigned ring_size;
		1000	uint64_t gpu_addr;
		1001	uint32_t ptr_mask;
2997	Serge	1002	atomic_t lock;
1321	serge	1003	bool enabled;
		1004	};
		1005
2997	Serge	1006	/*
5078	serge	1007	* RLC stuff
2997	Serge	1008	*/
5078	serge	1009	#include "clearstate_defs.h"
		1010
		1011	struct radeon_rlc {
2997	Serge	1012	/* for power gating */
		1013	struct radeon_bo *save_restore_obj;
		1014	uint64_t save_restore_gpu_addr;
5078	serge	1015	volatile uint32_t *sr_ptr;
		1016	const u32 *reg_list;
		1017	u32 reg_list_size;
2997	Serge	1018	/* for clear state */
		1019	struct radeon_bo *clear_state_obj;
		1020	uint64_t clear_state_gpu_addr;
5078	serge	1021	volatile uint32_t *cs_ptr;
		1022	const struct cs_section_def *cs_data;
		1023	u32 clear_state_size;
		1024	/* for cp tables */
		1025	struct radeon_bo *cp_table_obj;
		1026	uint64_t cp_table_gpu_addr;
		1027	volatile uint32_t *cp_table_ptr;
		1028	u32 cp_table_size;
2997	Serge	1029	};
		1030
		1031	int radeon_ib_get(struct radeon_device *rdev, int ring,
		1032	struct radeon_ib ib, struct radeon_vm vm,
		1033	unsigned size);
		1034	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib);
		1035	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
5078	serge	1036	struct radeon_ib *const_ib, bool hdp_flush);
1117	serge	1037	int radeon_ib_pool_init(struct radeon_device *rdev);
		1038	void radeon_ib_pool_fini(struct radeon_device *rdev);
2997	Serge	1039	int radeon_ib_ring_tests(struct radeon_device *rdev);
1117	serge	1040	/* Ring access between begin & end cannot sleep */
2997	Serge	1041	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
		1042	struct radeon_ring *ring);
		1043	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring cp);
		1044	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		1045	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
5078	serge	1046	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring cp,
		1047	bool hdp_flush);
		1048	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring cp,
		1049	bool hdp_flush);
2997	Serge	1050	void radeon_ring_undo(struct radeon_ring *ring);
		1051	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring cp);
		1052	int radeon_ring_test(struct radeon_device rdev, struct radeon_ring cp);
5078	serge	1053	void radeon_ring_lockup_update(struct radeon_device *rdev,
		1054	struct radeon_ring *ring);
2997	Serge	1055	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring);
		1056	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
		1057	uint32_t **data);
		1058	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
		1059	unsigned size, uint32_t *data);
		1060	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring cp, unsigned ring_size,
5078	serge	1061	unsigned rptr_offs, u32 nop);
2997	Serge	1062	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring cp);
1117	serge	1063
		1064
3192	Serge	1065	/* r600 async dma */
		1066	void r600_dma_stop(struct radeon_device *rdev);
		1067	int r600_dma_resume(struct radeon_device *rdev);
		1068	void r600_dma_fini(struct radeon_device *rdev);
		1069
		1070	void cayman_dma_stop(struct radeon_device *rdev);
		1071	int cayman_dma_resume(struct radeon_device *rdev);
		1072	void cayman_dma_fini(struct radeon_device *rdev);
		1073
1117	serge	1074	/*
		1075	* CS.
		1076	*/
		1077	struct radeon_cs_chunk {
		1078	uint32_t length_dw;
		1079	uint32_t *kdata;
1221	serge	1080	void __user *user_ptr;
1117	serge	1081	};
		1082
		1083	struct radeon_cs_parser {
1430	serge	1084	struct device *dev;
1117	serge	1085	struct radeon_device *rdev;
2004	serge	1086	struct drm_file *filp;
1117	serge	1087	/* chunks */
		1088	unsigned nchunks;
		1089	struct radeon_cs_chunk *chunks;
		1090	uint64_t *chunks_array;
		1091	/* IB */
		1092	unsigned idx;
		1093	/* relocations */
		1094	unsigned nrelocs;
5271	serge	1095	struct radeon_bo_list *relocs;
		1096	struct radeon_bo_list *vm_bos;
1120	serge	1097	struct list_head validated;
3192	Serge	1098	unsigned dma_reloc_idx;
1117	serge	1099	/* indices of various chunks */
5271	serge	1100	struct radeon_cs_chunk *chunk_ib;
		1101	struct radeon_cs_chunk *chunk_relocs;
		1102	struct radeon_cs_chunk *chunk_flags;
		1103	struct radeon_cs_chunk *chunk_const_ib;
2997	Serge	1104	struct radeon_ib ib;
		1105	struct radeon_ib const_ib;
1117	serge	1106	void *track;
1179	serge	1107	unsigned family;
1221	serge	1108	int parser_error;
2997	Serge	1109	u32 cs_flags;
		1110	u32 ring;
		1111	s32 priority;
5078	serge	1112	struct ww_acquire_ctx ticket;
1117	serge	1113	};
		1114
5078	serge	1115	static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
		1116	{
5271	serge	1117	struct radeon_cs_chunk *ibc = p->chunk_ib;
1221	serge	1118
5078	serge	1119	if (ibc->kdata)
		1120	return ibc->kdata[idx];
		1121	return p->ib.ptr[idx];
		1122	}
		1123
		1124
1117	serge	1125	struct radeon_cs_packet {
		1126	unsigned idx;
		1127	unsigned type;
		1128	unsigned reg;
		1129	unsigned opcode;
		1130	int count;
		1131	unsigned one_reg_wr;
		1132	};
		1133
		1134	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		1135	struct radeon_cs_packet *pkt,
		1136	unsigned idx, unsigned reg);
		1137	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		1138	struct radeon_cs_packet *pkt);
		1139
		1140
		1141	/*
		1142	* AGP
		1143	*/
		1144	int radeon_agp_init(struct radeon_device *rdev);
1321	serge	1145	void radeon_agp_resume(struct radeon_device *rdev);
1963	serge	1146	void radeon_agp_suspend(struct radeon_device *rdev);
1117	serge	1147	void radeon_agp_fini(struct radeon_device *rdev);
		1148
		1149
		1150	/*
		1151	* Writeback
		1152	*/
		1153	struct radeon_wb {
1321	serge	1154	struct radeon_bo *wb_obj;
1117	serge	1155	volatile uint32_t *wb;
		1156	uint64_t gpu_addr;
1963	serge	1157	bool enabled;
		1158	bool use_event;
1117	serge	1159	};
		1160
1963	serge	1161	#define RADEON_WB_SCRATCH_OFFSET 0
2997	Serge	1162	#define RADEON_WB_RING0_NEXT_RPTR 256
1963	serge	1163	#define RADEON_WB_CP_RPTR_OFFSET 1024
		1164	#define RADEON_WB_CP1_RPTR_OFFSET 1280
		1165	#define RADEON_WB_CP2_RPTR_OFFSET 1536
3192	Serge	1166	#define R600_WB_DMA_RPTR_OFFSET 1792
1963	serge	1167	#define R600_WB_IH_WPTR_OFFSET 2048
3192	Serge	1168	#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1963	serge	1169	#define R600_WB_EVENT_OFFSET 3072
5078	serge	1170	#define CIK_WB_CP1_WPTR_OFFSET 3328
		1171	#define CIK_WB_CP2_WPTR_OFFSET 3584
5179	serge	1172	#define R600_WB_DMA_RING_TEST_OFFSET 3588
		1173	#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1963	serge	1174
1179	serge	1175	/**
		1176	* struct radeon_pm - power management datas
		1177	* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
		1178	* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
		1179	* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
		1180	* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
		1181	* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
		1182	* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
		1183	* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
		1184	* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
		1185	* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1963	serge	1186	* @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1179	serge	1187	* @needed_bandwidth: current bandwidth needs
		1188	*
		1189	* It keeps track of various data needed to take powermanagement decision.
1963	serge	1190	* Bandwidth need is used to determine minimun clock of the GPU and memory.
1179	serge	1191	* Equation between gpu/memory clock and available bandwidth is hw dependent
		1192	* (type of memory, bus size, efficiency, ...)
		1193	*/
1963	serge	1194
		1195	enum radeon_pm_method {
		1196	PM_METHOD_PROFILE,
		1197	PM_METHOD_DYNPM,
5078	serge	1198	PM_METHOD_DPM,
1430	serge	1199	};
1963	serge	1200
		1201	enum radeon_dynpm_state {
		1202	DYNPM_STATE_DISABLED,
		1203	DYNPM_STATE_MINIMUM,
		1204	DYNPM_STATE_PAUSED,
		1205	DYNPM_STATE_ACTIVE,
		1206	DYNPM_STATE_SUSPENDED,
1430	serge	1207	};
1963	serge	1208	enum radeon_dynpm_action {
		1209	DYNPM_ACTION_NONE,
		1210	DYNPM_ACTION_MINIMUM,
		1211	DYNPM_ACTION_DOWNCLOCK,
		1212	DYNPM_ACTION_UPCLOCK,
		1213	DYNPM_ACTION_DEFAULT
		1214	};
1430	serge	1215
		1216	enum radeon_voltage_type {
		1217	VOLTAGE_NONE = 0,
		1218	VOLTAGE_GPIO,
		1219	VOLTAGE_VDDC,
		1220	VOLTAGE_SW
		1221	};
		1222
		1223	enum radeon_pm_state_type {
5078	serge	1224	/* not used for dpm */
1430	serge	1225	POWER_STATE_TYPE_DEFAULT,
		1226	POWER_STATE_TYPE_POWERSAVE,
5078	serge	1227	/* user selectable states */
1430	serge	1228	POWER_STATE_TYPE_BATTERY,
		1229	POWER_STATE_TYPE_BALANCED,
		1230	POWER_STATE_TYPE_PERFORMANCE,
5078	serge	1231	/* internal states */
		1232	POWER_STATE_TYPE_INTERNAL_UVD,
		1233	POWER_STATE_TYPE_INTERNAL_UVD_SD,
		1234	POWER_STATE_TYPE_INTERNAL_UVD_HD,
		1235	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
		1236	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
		1237	POWER_STATE_TYPE_INTERNAL_BOOT,
		1238	POWER_STATE_TYPE_INTERNAL_THERMAL,
		1239	POWER_STATE_TYPE_INTERNAL_ACPI,
		1240	POWER_STATE_TYPE_INTERNAL_ULV,
		1241	POWER_STATE_TYPE_INTERNAL_3DPERF,
1430	serge	1242	};
		1243
1963	serge	1244	enum radeon_pm_profile_type {
		1245	PM_PROFILE_DEFAULT,
		1246	PM_PROFILE_AUTO,
		1247	PM_PROFILE_LOW,
		1248	PM_PROFILE_MID,
		1249	PM_PROFILE_HIGH,
1430	serge	1250	};
		1251
1963	serge	1252	#define PM_PROFILE_DEFAULT_IDX 0
		1253	#define PM_PROFILE_LOW_SH_IDX 1
		1254	#define PM_PROFILE_MID_SH_IDX 2
		1255	#define PM_PROFILE_HIGH_SH_IDX 3
		1256	#define PM_PROFILE_LOW_MH_IDX 4
		1257	#define PM_PROFILE_MID_MH_IDX 5
		1258	#define PM_PROFILE_HIGH_MH_IDX 6
		1259	#define PM_PROFILE_MAX 7
		1260
		1261	struct radeon_pm_profile {
		1262	int dpms_off_ps_idx;
		1263	int dpms_on_ps_idx;
		1264	int dpms_off_cm_idx;
		1265	int dpms_on_cm_idx;
		1266	};
		1267
		1268	enum radeon_int_thermal_type {
		1269	THERMAL_TYPE_NONE,
5078	serge	1270	THERMAL_TYPE_EXTERNAL,
		1271	THERMAL_TYPE_EXTERNAL_GPIO,
1963	serge	1272	THERMAL_TYPE_RV6XX,
		1273	THERMAL_TYPE_RV770,
5078	serge	1274	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1963	serge	1275	THERMAL_TYPE_EVERGREEN,
		1276	THERMAL_TYPE_SUMO,
		1277	THERMAL_TYPE_NI,
2997	Serge	1278	THERMAL_TYPE_SI,
5078	serge	1279	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
		1280	THERMAL_TYPE_CI,
		1281	THERMAL_TYPE_KV,
1963	serge	1282	};
		1283
1430	serge	1284	struct radeon_voltage {
		1285	enum radeon_voltage_type type;
		1286	/* gpio voltage */
		1287	struct radeon_gpio_rec gpio;
		1288	u32 delay; /* delay in usec from voltage drop to sclk change */
		1289	bool active_high; /* voltage drop is active when bit is high */
		1290	/* VDDC voltage */
		1291	u8 vddc_id; /* index into vddc voltage table */
		1292	u8 vddci_id; /* index into vddci voltage table */
		1293	bool vddci_enabled;
		1294	/* r6xx+ sw */
1963	serge	1295	u16 voltage;
		1296	/* evergreen+ vddci */
		1297	u16 vddci;
1430	serge	1298	};
		1299
1963	serge	1300	/* clock mode flags */
		1301	#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1430	serge	1302
		1303	struct radeon_pm_clock_info {
		1304	/* memory clock */
		1305	u32 mclk;
		1306	/* engine clock */
		1307	u32 sclk;
		1308	/* voltage info */
		1309	struct radeon_voltage voltage;
1963	serge	1310	/* standardized clock flags */
1430	serge	1311	u32 flags;
		1312	};
		1313
1963	serge	1314	/* state flags */
		1315	#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
		1316
1430	serge	1317	struct radeon_power_state {
		1318	enum radeon_pm_state_type type;
2997	Serge	1319	struct radeon_pm_clock_info *clock_info;
1430	serge	1320	/* number of valid clock modes in this power state */
		1321	int num_clock_modes;
		1322	struct radeon_pm_clock_info *default_clock_mode;
1963	serge	1323	/* standardized state flags */
		1324	u32 flags;
		1325	u32 misc; /* vbios specific flags */
		1326	u32 misc2; /* vbios specific flags */
		1327	int pcie_lanes; /* pcie lanes */
1430	serge	1328	};
		1329
		1330	/*
		1331	* Some modes are overclocked by very low value, accept them
		1332	*/
		1333	#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
		1334
5078	serge	1335	enum radeon_dpm_auto_throttle_src {
		1336	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
		1337	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
		1338	};
		1339
		1340	enum radeon_dpm_event_src {
		1341	RADEON_DPM_EVENT_SRC_ANALOG = 0,
		1342	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
		1343	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
		1344	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
		1345	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		1346	};
		1347
		1348	#define RADEON_MAX_VCE_LEVELS 6
		1349
		1350	enum radeon_vce_level {
		1351	RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
		1352	RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
		1353	RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
		1354	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
		1355	RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
		1356	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
		1357	};
		1358
		1359	struct radeon_ps {
		1360	u32 caps; /* vbios flags */
		1361	u32 class; /* vbios flags */
		1362	u32 class2; /* vbios flags */
		1363	/* UVD clocks */
		1364	u32 vclk;
		1365	u32 dclk;
		1366	/* VCE clocks */
		1367	u32 evclk;
		1368	u32 ecclk;
		1369	bool vce_active;
		1370	enum radeon_vce_level vce_level;
		1371	/* asic priv */
		1372	void *ps_priv;
		1373	};
		1374
		1375	struct radeon_dpm_thermal {
		1376	/* thermal interrupt work */
		1377	struct work_struct work;
		1378	/* low temperature threshold */
		1379	int min_temp;
		1380	/* high temperature threshold */
		1381	int max_temp;
		1382	/* was interrupt low to high or high to low */
		1383	bool high_to_low;
		1384	};
		1385
		1386	enum radeon_clk_action
		1387	{
		1388	RADEON_SCLK_UP = 1,
		1389	RADEON_SCLK_DOWN
		1390	};
		1391
		1392	struct radeon_blacklist_clocks
		1393	{
		1394	u32 sclk;
		1395	u32 mclk;
		1396	enum radeon_clk_action action;
		1397	};
		1398
		1399	struct radeon_clock_and_voltage_limits {
		1400	u32 sclk;
		1401	u32 mclk;
		1402	u16 vddc;
		1403	u16 vddci;
		1404	};
		1405
		1406	struct radeon_clock_array {
		1407	u32 count;
		1408	u32 *values;
		1409	};
		1410
		1411	struct radeon_clock_voltage_dependency_entry {
		1412	u32 clk;
		1413	u16 v;
		1414	};
		1415
		1416	struct radeon_clock_voltage_dependency_table {
		1417	u32 count;
		1418	struct radeon_clock_voltage_dependency_entry *entries;
		1419	};
		1420
		1421	union radeon_cac_leakage_entry {
		1422	struct {
		1423	u16 vddc;
		1424	u32 leakage;
		1425	};
		1426	struct {
		1427	u16 vddc1;
		1428	u16 vddc2;
		1429	u16 vddc3;
		1430	};
		1431	};
		1432
		1433	struct radeon_cac_leakage_table {
		1434	u32 count;
		1435	union radeon_cac_leakage_entry *entries;
		1436	};
		1437
		1438	struct radeon_phase_shedding_limits_entry {
		1439	u16 voltage;
		1440	u32 sclk;
		1441	u32 mclk;
		1442	};
		1443
		1444	struct radeon_phase_shedding_limits_table {
		1445	u32 count;
		1446	struct radeon_phase_shedding_limits_entry *entries;
		1447	};
		1448
		1449	struct radeon_uvd_clock_voltage_dependency_entry {
		1450	u32 vclk;
		1451	u32 dclk;
		1452	u16 v;
		1453	};
		1454
		1455	struct radeon_uvd_clock_voltage_dependency_table {
		1456	u8 count;
		1457	struct radeon_uvd_clock_voltage_dependency_entry *entries;
		1458	};
		1459
		1460	struct radeon_vce_clock_voltage_dependency_entry {
		1461	u32 ecclk;
		1462	u32 evclk;
		1463	u16 v;
		1464	};
		1465
		1466	struct radeon_vce_clock_voltage_dependency_table {
		1467	u8 count;
		1468	struct radeon_vce_clock_voltage_dependency_entry *entries;
		1469	};
		1470
		1471	struct radeon_ppm_table {
		1472	u8 ppm_design;
		1473	u16 cpu_core_number;
		1474	u32 platform_tdp;
		1475	u32 small_ac_platform_tdp;
		1476	u32 platform_tdc;
		1477	u32 small_ac_platform_tdc;
		1478	u32 apu_tdp;
		1479	u32 dgpu_tdp;
		1480	u32 dgpu_ulv_power;
		1481	u32 tj_max;
		1482	};
		1483
		1484	struct radeon_cac_tdp_table {
		1485	u16 tdp;
		1486	u16 configurable_tdp;
		1487	u16 tdc;
		1488	u16 battery_power_limit;
		1489	u16 small_power_limit;
		1490	u16 low_cac_leakage;
		1491	u16 high_cac_leakage;
		1492	u16 maximum_power_delivery_limit;
		1493	};
		1494
		1495	struct radeon_dpm_dynamic_state {
		1496	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
		1497	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
		1498	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
		1499	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
		1500	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
		1501	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
		1502	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
		1503	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
		1504	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
		1505	struct radeon_clock_array valid_sclk_values;
		1506	struct radeon_clock_array valid_mclk_values;
		1507	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
		1508	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
		1509	u32 mclk_sclk_ratio;
		1510	u32 sclk_mclk_delta;
		1511	u16 vddc_vddci_delta;
		1512	u16 min_vddc_for_pcie_gen2;
		1513	struct radeon_cac_leakage_table cac_leakage_table;
		1514	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
		1515	struct radeon_ppm_table *ppm_table;
		1516	struct radeon_cac_tdp_table *cac_tdp_table;
		1517	};
		1518
		1519	struct radeon_dpm_fan {
		1520	u16 t_min;
		1521	u16 t_med;
		1522	u16 t_high;
		1523	u16 pwm_min;
		1524	u16 pwm_med;
		1525	u16 pwm_high;
		1526	u8 t_hyst;
		1527	u32 cycle_delay;
		1528	u16 t_max;
5271	serge	1529	u8 control_mode;
		1530	u16 default_max_fan_pwm;
		1531	u16 default_fan_output_sensitivity;
		1532	u16 fan_output_sensitivity;
5078	serge	1533	bool ucode_fan_control;
		1534	};
		1535
		1536	enum radeon_pcie_gen {
		1537	RADEON_PCIE_GEN1 = 0,
		1538	RADEON_PCIE_GEN2 = 1,
		1539	RADEON_PCIE_GEN3 = 2,
		1540	RADEON_PCIE_GEN_INVALID = 0xffff
		1541	};
		1542
		1543	enum radeon_dpm_forced_level {
		1544	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
		1545	RADEON_DPM_FORCED_LEVEL_LOW = 1,
		1546	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
		1547	};
		1548
		1549	struct radeon_vce_state {
		1550	/* vce clocks */
		1551	u32 evclk;
		1552	u32 ecclk;
		1553	/* gpu clocks */
		1554	u32 sclk;
		1555	u32 mclk;
		1556	u8 clk_idx;
		1557	u8 pstate;
		1558	};
		1559
		1560	struct radeon_dpm {
		1561	struct radeon_ps *ps;
		1562	/* number of valid power states */
		1563	int num_ps;
		1564	/* current power state that is active */
		1565	struct radeon_ps *current_ps;
		1566	/* requested power state */
		1567	struct radeon_ps *requested_ps;
		1568	/* boot up power state */
		1569	struct radeon_ps *boot_ps;
		1570	/* default uvd power state */
		1571	struct radeon_ps *uvd_ps;
		1572	/* vce requirements */
		1573	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
		1574	enum radeon_vce_level vce_level;
		1575	enum radeon_pm_state_type state;
		1576	enum radeon_pm_state_type user_state;
		1577	u32 platform_caps;
		1578	u32 voltage_response_time;
		1579	u32 backbias_response_time;
		1580	void *priv;
		1581	u32 new_active_crtcs;
		1582	int new_active_crtc_count;
		1583	u32 current_active_crtcs;
		1584	int current_active_crtc_count;
		1585	struct radeon_dpm_dynamic_state dyn_state;
		1586	struct radeon_dpm_fan fan;
		1587	u32 tdp_limit;
		1588	u32 near_tdp_limit;
		1589	u32 near_tdp_limit_adjusted;
		1590	u32 sq_ramping_threshold;
		1591	u32 cac_leakage;
		1592	u16 tdp_od_limit;
		1593	u32 tdp_adjustment;
		1594	u16 load_line_slope;
		1595	bool power_control;
		1596	bool ac_power;
		1597	/* special states active */
		1598	bool thermal_active;
		1599	bool uvd_active;
		1600	bool vce_active;
		1601	/* thermal handling */
		1602	struct radeon_dpm_thermal thermal;
		1603	/* forced levels */
		1604	enum radeon_dpm_forced_level forced_level;
		1605	/* track UVD streams */
		1606	unsigned sd;
		1607	unsigned hd;
		1608	};
		1609
		1610	void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
		1611	void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
		1612
1179	serge	1613	struct radeon_pm {
1630	serge	1614	struct mutex mutex;
2997	Serge	1615	/* write locked while reprogramming mclk */
		1616	struct rw_semaphore mclk_lock;
1963	serge	1617	u32 active_crtcs;
		1618	int active_crtc_count;
1430	serge	1619	int req_vblank;
1963	serge	1620	bool vblank_sync;
1179	serge	1621	fixed20_12 max_bandwidth;
		1622	fixed20_12 igp_sideport_mclk;
		1623	fixed20_12 igp_system_mclk;
		1624	fixed20_12 igp_ht_link_clk;
		1625	fixed20_12 igp_ht_link_width;
		1626	fixed20_12 k8_bandwidth;
		1627	fixed20_12 sideport_bandwidth;
		1628	fixed20_12 ht_bandwidth;
		1629	fixed20_12 core_bandwidth;
		1630	fixed20_12 sclk;
1963	serge	1631	fixed20_12 mclk;
1179	serge	1632	fixed20_12 needed_bandwidth;
1963	serge	1633	struct radeon_power_state *power_state;
1430	serge	1634	/* number of valid power states */
		1635	int num_power_states;
1963	serge	1636	int current_power_state_index;
		1637	int current_clock_mode_index;
		1638	int requested_power_state_index;
		1639	int requested_clock_mode_index;
		1640	int default_power_state_index;
		1641	u32 current_sclk;
		1642	u32 current_mclk;
		1643	u16 current_vddc;
		1644	u16 current_vddci;
		1645	u32 default_sclk;
		1646	u32 default_mclk;
		1647	u16 default_vddc;
		1648	u16 default_vddci;
		1649	struct radeon_i2c_chan *i2c_bus;
		1650	/* selected pm method */
		1651	enum radeon_pm_method pm_method;
		1652	/* dynpm power management */
5078	serge	1653	struct delayed_work dynpm_idle_work;
1963	serge	1654	enum radeon_dynpm_state dynpm_state;
		1655	enum radeon_dynpm_action dynpm_planned_action;
		1656	unsigned long dynpm_action_timeout;
		1657	bool dynpm_can_upclock;
		1658	bool dynpm_can_downclock;
		1659	/* profile-based power management */
		1660	enum radeon_pm_profile_type profile;
		1661	int profile_index;
		1662	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
		1663	/* internal thermal controller on rv6xx+ */
		1664	enum radeon_int_thermal_type int_thermal_type;
		1665	struct device *int_hwmon_dev;
5271	serge	1666	/* fan control parameters */
		1667	bool no_fan;
		1668	u8 fan_pulses_per_revolution;
		1669	u8 fan_min_rpm;
		1670	u8 fan_max_rpm;
5078	serge	1671	/* dpm */
		1672	bool dpm_enabled;
		1673	struct radeon_dpm dpm;
1179	serge	1674	};
1117	serge	1675
2997	Serge	1676	int radeon_pm_get_type_index(struct radeon_device *rdev,
		1677	enum radeon_pm_state_type ps_type,
		1678	int instance);
3764	Serge	1679	/*
		1680	* UVD
		1681	*/
		1682	#define RADEON_MAX_UVD_HANDLES 10
		1683	#define RADEON_UVD_STACK_SIZE (1024*1024)
		1684	#define RADEON_UVD_HEAP_SIZE (1024*1024)
2997	Serge	1685
3764	Serge	1686	struct radeon_uvd {
		1687	struct radeon_bo *vcpu_bo;
		1688	void *cpu_addr;
		1689	uint64_t gpu_addr;
5078	serge	1690	void *saved_bo;
3764	Serge	1691	atomic_t handles[RADEON_MAX_UVD_HANDLES];
		1692	struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
5078	serge	1693	unsigned img_size[RADEON_MAX_UVD_HANDLES];
3764	Serge	1694	struct delayed_work idle_work;
		1695	};
		1696
		1697	int radeon_uvd_init(struct radeon_device *rdev);
		1698	void radeon_uvd_fini(struct radeon_device *rdev);
		1699	int radeon_uvd_suspend(struct radeon_device *rdev);
		1700	int radeon_uvd_resume(struct radeon_device *rdev);
		1701	int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
		1702	uint32_t handle, struct radeon_fence **fence);
		1703	int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
		1704	uint32_t handle, struct radeon_fence **fence);
5271	serge	1705	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
		1706	uint32_t allowed_domains);
3764	Serge	1707	void radeon_uvd_free_handles(struct radeon_device *rdev,
		1708	struct drm_file *filp);
		1709	int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
		1710	void radeon_uvd_note_usage(struct radeon_device *rdev);
		1711	int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
		1712	unsigned vclk, unsigned dclk,
		1713	unsigned vco_min, unsigned vco_max,
		1714	unsigned fb_factor, unsigned fb_mask,
		1715	unsigned pd_min, unsigned pd_max,
		1716	unsigned pd_even,
		1717	unsigned *optimal_fb_div,
		1718	unsigned *optimal_vclk_div,
		1719	unsigned *optimal_dclk_div);
		1720	int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
		1721	unsigned cg_upll_func_cntl);
		1722
5078	serge	1723	/*
		1724	* VCE
		1725	*/
		1726	#define RADEON_MAX_VCE_HANDLES 16
		1727	#define RADEON_VCE_STACK_SIZE (1024*1024)
		1728	#define RADEON_VCE_HEAP_SIZE (410241024)
		1729
		1730	struct radeon_vce {
		1731	struct radeon_bo *vcpu_bo;
		1732	uint64_t gpu_addr;
		1733	unsigned fw_version;
		1734	unsigned fb_version;
		1735	atomic_t handles[RADEON_MAX_VCE_HANDLES];
		1736	struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
		1737	unsigned img_size[RADEON_MAX_VCE_HANDLES];
		1738	struct delayed_work idle_work;
		1739	};
		1740
		1741	int radeon_vce_init(struct radeon_device *rdev);
		1742	void radeon_vce_fini(struct radeon_device *rdev);
		1743	int radeon_vce_suspend(struct radeon_device *rdev);
		1744	int radeon_vce_resume(struct radeon_device *rdev);
		1745	int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
		1746	uint32_t handle, struct radeon_fence **fence);
		1747	int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
		1748	uint32_t handle, struct radeon_fence **fence);
		1749	void radeon_vce_free_handles(struct radeon_device rdev, struct drm_file filp);
		1750	void radeon_vce_note_usage(struct radeon_device *rdev);
		1751	int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
		1752	int radeon_vce_cs_parse(struct radeon_cs_parser *p);
		1753	bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
		1754	struct radeon_ring *ring,
		1755	struct radeon_semaphore *semaphore,
		1756	bool emit_wait);
		1757	void radeon_vce_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
		1758	void radeon_vce_fence_emit(struct radeon_device *rdev,
		1759	struct radeon_fence *fence);
		1760	int radeon_vce_ring_test(struct radeon_device rdev, struct radeon_ring ring);
		1761	int radeon_vce_ib_test(struct radeon_device rdev, struct radeon_ring ring);
		1762
		1763	struct r600_audio_pin {
2997	Serge	1764	int channels;
		1765	int rate;
		1766	int bits_per_sample;
		1767	u8 status_bits;
		1768	u8 category_code;
5078	serge	1769	u32 offset;
		1770	bool connected;
		1771	u32 id;
2997	Serge	1772	};
5078	serge	1773
		1774	struct r600_audio {
		1775	bool enabled;
		1776	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
		1777	int num_pins;
		1778	};
		1779
1117	serge	1780	/*
5078	serge	1781	* Benchmarking
		1782	*/
		1783	void radeon_benchmark(struct radeon_device *rdev, int test_number);
		1784
		1785
		1786	/*
		1787	* Testing
		1788	*/
		1789	void radeon_test_moves(struct radeon_device *rdev);
		1790	void radeon_test_ring_sync(struct radeon_device *rdev,
		1791	struct radeon_ring *cpA,
		1792	struct radeon_ring *cpB);
		1793	void radeon_test_syncing(struct radeon_device *rdev);
		1794
5271	serge	1795	/*
		1796	* MMU Notifier
		1797	*/
		1798	int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
		1799	void radeon_mn_unregister(struct radeon_bo *bo);
5078	serge	1800
		1801	/*
		1802	* Debugfs
		1803	*/
		1804	struct radeon_debugfs {
		1805	struct drm_info_list *files;
		1806	unsigned num_files;
		1807	};
		1808
		1809	int radeon_debugfs_add_files(struct radeon_device *rdev,
		1810	struct drm_info_list *files,
		1811	unsigned nfiles);
		1812	int radeon_debugfs_fence_init(struct radeon_device *rdev);
		1813
		1814	/*
		1815	* ASIC ring specific functions.
		1816	*/
		1817	struct radeon_asic_ring {
		1818	/* ring read/write ptr handling */
		1819	u32 (get_rptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1820	u32 (get_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1821	void (set_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1822
		1823	/* validating and patching of IBs */
		1824	int (ib_parse)(struct radeon_device rdev, struct radeon_ib *ib);
		1825	int (cs_parse)(struct radeon_cs_parser p);
		1826
		1827	/* command emmit functions */
		1828	void (ib_execute)(struct radeon_device rdev, struct radeon_ib *ib);
		1829	void (emit_fence)(struct radeon_device rdev, struct radeon_fence *fence);
		1830	void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);
		1831	bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,
		1832	struct radeon_semaphore *semaphore, bool emit_wait);
5271	serge	1833	void (vm_flush)(struct radeon_device rdev, struct radeon_ring *ring,
		1834	unsigned vm_id, uint64_t pd_addr);
5078	serge	1835
		1836	/* testing functions */
		1837	int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1838	int (ib_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1839	bool (is_lockup)(struct radeon_device rdev, struct radeon_ring *cp);
		1840
		1841	/* deprecated */
		1842	void (ring_start)(struct radeon_device rdev, struct radeon_ring *cp);
		1843	};
		1844
		1845	/*
1117	serge	1846	* ASIC specific functions.
		1847	*/
		1848	struct radeon_asic {
		1849	int (init)(struct radeon_device rdev);
1179	serge	1850	void (fini)(struct radeon_device rdev);
		1851	int (resume)(struct radeon_device rdev);
		1852	int (suspend)(struct radeon_device rdev);
		1853	void (vga_set_state)(struct radeon_device rdev, bool state);
1963	serge	1854	int (asic_reset)(struct radeon_device rdev);
5078	serge	1855	/* Flush the HDP cache via MMIO */
		1856	void (mmio_hdp_flush)(struct radeon_device rdev);
2997	Serge	1857	/* check if 3D engine is idle */
		1858	bool (gui_idle)(struct radeon_device rdev);
		1859	/* wait for mc_idle */
		1860	int (mc_wait_for_idle)(struct radeon_device rdev);
3764	Serge	1861	/* get the reference clock */
		1862	u32 (get_xclk)(struct radeon_device rdev);
		1863	/* get the gpu clock counter */
		1864	uint64_t (get_gpu_clock_counter)(struct radeon_device rdev);
2997	Serge	1865	/* gart */
		1866	struct {
		1867	void (tlb_flush)(struct radeon_device rdev);
5078	serge	1868	void (set_page)(struct radeon_device rdev, unsigned i,
		1869	uint64_t addr, uint32_t flags);
2997	Serge	1870	} gart;
		1871	struct {
		1872	int (init)(struct radeon_device rdev);
		1873	void (fini)(struct radeon_device rdev);
5078	serge	1874	void (copy_pages)(struct radeon_device rdev,
		1875	struct radeon_ib *ib,
		1876	uint64_t pe, uint64_t src,
		1877	unsigned count);
		1878	void (write_pages)(struct radeon_device rdev,
		1879	struct radeon_ib *ib,
		1880	uint64_t pe,
		1881	uint64_t addr, unsigned count,
		1882	uint32_t incr, uint32_t flags);
		1883	void (set_pages)(struct radeon_device rdev,
3764	Serge	1884	struct radeon_ib *ib,
		1885	uint64_t pe,
2997	Serge	1886	uint64_t addr, unsigned count,
		1887	uint32_t incr, uint32_t flags);
5078	serge	1888	void (pad_ib)(struct radeon_ib ib);
2997	Serge	1889	} vm;
		1890	/* ring specific callbacks */
5078	serge	1891	struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
2997	Serge	1892	/* irqs */
		1893	struct {
		1894	int (set)(struct radeon_device rdev);
		1895	int (process)(struct radeon_device rdev);
		1896	} irq;
		1897	/* displays */
		1898	struct {
		1899	/* display watermarks */
		1900	void (bandwidth_update)(struct radeon_device rdev);
		1901	/* get frame count */
1179	serge	1902	u32 (get_vblank_counter)(struct radeon_device rdev, int crtc);
2997	Serge	1903	/* wait for vblank */
		1904	void (wait_for_vblank)(struct radeon_device rdev, int crtc);
		1905	/* set backlight level */
		1906	void (set_backlight_level)(struct radeon_encoder radeon_encoder, u8 level);
		1907	/* get backlight level */
		1908	u8 (get_backlight_level)(struct radeon_encoder radeon_encoder);
3764	Serge	1909	/* audio callbacks */
		1910	void (hdmi_enable)(struct drm_encoder encoder, bool enable);
		1911	void (hdmi_setmode)(struct drm_encoder encoder, struct drm_display_mode *mode);
2997	Serge	1912	} display;
		1913	/* copy functions for bo handling */
		1914	struct {
5271	serge	1915	struct radeon_fence (blit)(struct radeon_device *rdev,
1117	serge	1916	uint64_t src_offset,
		1917	uint64_t dst_offset,
2997	Serge	1918	unsigned num_gpu_pages,
5271	serge	1919	struct reservation_object *resv);
2997	Serge	1920	u32 blit_ring_index;
5271	serge	1921	struct radeon_fence (dma)(struct radeon_device *rdev,
1117	serge	1922	uint64_t src_offset,
		1923	uint64_t dst_offset,
2997	Serge	1924	unsigned num_gpu_pages,
5271	serge	1925	struct reservation_object *resv);
2997	Serge	1926	u32 dma_ring_index;
		1927	/* method used for bo copy */
5271	serge	1928	struct radeon_fence (copy)(struct radeon_device *rdev,
1117	serge	1929	uint64_t src_offset,
		1930	uint64_t dst_offset,
2997	Serge	1931	unsigned num_gpu_pages,
5271	serge	1932	struct reservation_object *resv);
2997	Serge	1933	/* ring used for bo copies */
		1934	u32 copy_ring_index;
		1935	} copy;
		1936	/* surfaces */
		1937	struct {
		1938	int (set_reg)(struct radeon_device rdev, int reg,
		1939	uint32_t tiling_flags, uint32_t pitch,
		1940	uint32_t offset, uint32_t obj_size);
		1941	void (clear_reg)(struct radeon_device rdev, int reg);
		1942	} surface;
		1943	/* hotplug detect */
		1944	struct {
		1945	void (init)(struct radeon_device rdev);
		1946	void (fini)(struct radeon_device rdev);
		1947	bool (sense)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1948	void (set_polarity)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1949	} hpd;
5078	serge	1950	/* static power management */
2997	Serge	1951	struct {
		1952	void (misc)(struct radeon_device rdev);
		1953	void (prepare)(struct radeon_device rdev);
		1954	void (finish)(struct radeon_device rdev);
		1955	void (init_profile)(struct radeon_device rdev);
		1956	void (get_dynpm_state)(struct radeon_device rdev);
1268	serge	1957	uint32_t (get_engine_clock)(struct radeon_device rdev);
1117	serge	1958	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
1268	serge	1959	uint32_t (get_memory_clock)(struct radeon_device rdev);
1117	serge	1960	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
1430	serge	1961	int (get_pcie_lanes)(struct radeon_device rdev);
1117	serge	1962	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		1963	void (set_clock_gating)(struct radeon_device rdev, int enable);
3764	Serge	1964	int (set_uvd_clocks)(struct radeon_device rdev, u32 vclk, u32 dclk);
5078	serge	1965	int (set_vce_clocks)(struct radeon_device rdev, u32 evclk, u32 ecclk);
		1966	int (get_temperature)(struct radeon_device rdev);
2997	Serge	1967	} pm;
5078	serge	1968	/* dynamic power management */
		1969	struct {
		1970	int (init)(struct radeon_device rdev);
		1971	void (setup_asic)(struct radeon_device rdev);
		1972	int (enable)(struct radeon_device rdev);
		1973	int (late_enable)(struct radeon_device rdev);
		1974	void (disable)(struct radeon_device rdev);
		1975	int (pre_set_power_state)(struct radeon_device rdev);
		1976	int (set_power_state)(struct radeon_device rdev);
		1977	void (post_set_power_state)(struct radeon_device rdev);
		1978	void (display_configuration_changed)(struct radeon_device rdev);
		1979	void (fini)(struct radeon_device rdev);
		1980	u32 (get_sclk)(struct radeon_device rdev, bool low);
		1981	u32 (get_mclk)(struct radeon_device rdev, bool low);
		1982	void (print_power_state)(struct radeon_device rdev, struct radeon_ps *ps);
		1983	void (debugfs_print_current_performance_level)(struct radeon_device rdev, struct seq_file *m);
		1984	int (force_performance_level)(struct radeon_device rdev, enum radeon_dpm_forced_level level);
		1985	bool (vblank_too_short)(struct radeon_device rdev);
		1986	void (powergate_uvd)(struct radeon_device rdev, bool gate);
		1987	void (enable_bapm)(struct radeon_device rdev, bool enable);
		1988	} dpm;
1963	serge	1989	/* pageflipping */
2997	Serge	1990	struct {
5078	serge	1991	void (page_flip)(struct radeon_device rdev, int crtc, u64 crtc_base);
		1992	bool (page_flip_pending)(struct radeon_device rdev, int crtc);
2997	Serge	1993	} pflip;
1117	serge	1994	};
		1995
1179	serge	1996	/*
		1997	* Asic structures
		1998	*/
		1999	struct r100_asic {
		2000	const unsigned *reg_safe_bm;
		2001	unsigned reg_safe_bm_size;
1403	serge	2002	u32 hdp_cntl;
1179	serge	2003	};
		2004
		2005	struct r300_asic {
		2006	const unsigned *reg_safe_bm;
		2007	unsigned reg_safe_bm_size;
1403	serge	2008	u32 resync_scratch;
		2009	u32 hdp_cntl;
1179	serge	2010	};
		2011
		2012	struct r600_asic {
		2013	unsigned max_pipes;
		2014	unsigned max_tile_pipes;
		2015	unsigned max_simds;
		2016	unsigned max_backends;
		2017	unsigned max_gprs;
		2018	unsigned max_threads;
		2019	unsigned max_stack_entries;
		2020	unsigned max_hw_contexts;
		2021	unsigned max_gs_threads;
		2022	unsigned sx_max_export_size;
		2023	unsigned sx_max_export_pos_size;
		2024	unsigned sx_max_export_smx_size;
		2025	unsigned sq_num_cf_insts;
1430	serge	2026	unsigned tiling_nbanks;
		2027	unsigned tiling_npipes;
		2028	unsigned tiling_group_size;
1963	serge	2029	unsigned tile_config;
2160	serge	2030	unsigned backend_map;
5078	serge	2031	unsigned active_simds;
1179	serge	2032	};
		2033
		2034	struct rv770_asic {
		2035	unsigned max_pipes;
		2036	unsigned max_tile_pipes;
		2037	unsigned max_simds;
		2038	unsigned max_backends;
		2039	unsigned max_gprs;
		2040	unsigned max_threads;
		2041	unsigned max_stack_entries;
		2042	unsigned max_hw_contexts;
		2043	unsigned max_gs_threads;
		2044	unsigned sx_max_export_size;
		2045	unsigned sx_max_export_pos_size;
		2046	unsigned sx_max_export_smx_size;
		2047	unsigned sq_num_cf_insts;
		2048	unsigned sx_num_of_sets;
		2049	unsigned sc_prim_fifo_size;
		2050	unsigned sc_hiz_tile_fifo_size;
		2051	unsigned sc_earlyz_tile_fifo_fize;
1430	serge	2052	unsigned tiling_nbanks;
		2053	unsigned tiling_npipes;
		2054	unsigned tiling_group_size;
1963	serge	2055	unsigned tile_config;
2160	serge	2056	unsigned backend_map;
5078	serge	2057	unsigned active_simds;
1179	serge	2058	};
		2059
1963	serge	2060	struct evergreen_asic {
		2061	unsigned num_ses;
		2062	unsigned max_pipes;
		2063	unsigned max_tile_pipes;
		2064	unsigned max_simds;
		2065	unsigned max_backends;
		2066	unsigned max_gprs;
		2067	unsigned max_threads;
		2068	unsigned max_stack_entries;
		2069	unsigned max_hw_contexts;
		2070	unsigned max_gs_threads;
		2071	unsigned sx_max_export_size;
		2072	unsigned sx_max_export_pos_size;
		2073	unsigned sx_max_export_smx_size;
		2074	unsigned sq_num_cf_insts;
		2075	unsigned sx_num_of_sets;
		2076	unsigned sc_prim_fifo_size;
		2077	unsigned sc_hiz_tile_fifo_size;
		2078	unsigned sc_earlyz_tile_fifo_size;
		2079	unsigned tiling_nbanks;
		2080	unsigned tiling_npipes;
		2081	unsigned tiling_group_size;
		2082	unsigned tile_config;
2160	serge	2083	unsigned backend_map;
5078	serge	2084	unsigned active_simds;
1963	serge	2085	};
		2086
		2087	struct cayman_asic {
		2088	unsigned max_shader_engines;
		2089	unsigned max_pipes_per_simd;
		2090	unsigned max_tile_pipes;
		2091	unsigned max_simds_per_se;
		2092	unsigned max_backends_per_se;
		2093	unsigned max_texture_channel_caches;
		2094	unsigned max_gprs;
		2095	unsigned max_threads;
		2096	unsigned max_gs_threads;
		2097	unsigned max_stack_entries;
		2098	unsigned sx_num_of_sets;
		2099	unsigned sx_max_export_size;
		2100	unsigned sx_max_export_pos_size;
		2101	unsigned sx_max_export_smx_size;
		2102	unsigned max_hw_contexts;
		2103	unsigned sq_num_cf_insts;
		2104	unsigned sc_prim_fifo_size;
		2105	unsigned sc_hiz_tile_fifo_size;
		2106	unsigned sc_earlyz_tile_fifo_size;
		2107
		2108	unsigned num_shader_engines;
		2109	unsigned num_shader_pipes_per_simd;
		2110	unsigned num_tile_pipes;
		2111	unsigned num_simds_per_se;
		2112	unsigned num_backends_per_se;
		2113	unsigned backend_disable_mask_per_asic;
		2114	unsigned backend_map;
		2115	unsigned num_texture_channel_caches;
		2116	unsigned mem_max_burst_length_bytes;
		2117	unsigned mem_row_size_in_kb;
		2118	unsigned shader_engine_tile_size;
		2119	unsigned num_gpus;
		2120	unsigned multi_gpu_tile_size;
		2121
		2122	unsigned tile_config;
5078	serge	2123	unsigned active_simds;
1963	serge	2124	};
		2125
2997	Serge	2126	struct si_asic {
		2127	unsigned max_shader_engines;
		2128	unsigned max_tile_pipes;
		2129	unsigned max_cu_per_sh;
		2130	unsigned max_sh_per_se;
		2131	unsigned max_backends_per_se;
		2132	unsigned max_texture_channel_caches;
		2133	unsigned max_gprs;
		2134	unsigned max_gs_threads;
		2135	unsigned max_hw_contexts;
		2136	unsigned sc_prim_fifo_size_frontend;
		2137	unsigned sc_prim_fifo_size_backend;
		2138	unsigned sc_hiz_tile_fifo_size;
		2139	unsigned sc_earlyz_tile_fifo_size;
		2140
		2141	unsigned num_tile_pipes;
5078	serge	2142	unsigned backend_enable_mask;
2997	Serge	2143	unsigned backend_disable_mask_per_asic;
		2144	unsigned backend_map;
		2145	unsigned num_texture_channel_caches;
		2146	unsigned mem_max_burst_length_bytes;
		2147	unsigned mem_row_size_in_kb;
		2148	unsigned shader_engine_tile_size;
		2149	unsigned num_gpus;
		2150	unsigned multi_gpu_tile_size;
		2151
		2152	unsigned tile_config;
3764	Serge	2153	uint32_t tile_mode_array[32];
5078	serge	2154	uint32_t active_cus;
2997	Serge	2155	};
		2156
5078	serge	2157	struct cik_asic {
		2158	unsigned max_shader_engines;
		2159	unsigned max_tile_pipes;
		2160	unsigned max_cu_per_sh;
		2161	unsigned max_sh_per_se;
		2162	unsigned max_backends_per_se;
		2163	unsigned max_texture_channel_caches;
		2164	unsigned max_gprs;
		2165	unsigned max_gs_threads;
		2166	unsigned max_hw_contexts;
		2167	unsigned sc_prim_fifo_size_frontend;
		2168	unsigned sc_prim_fifo_size_backend;
		2169	unsigned sc_hiz_tile_fifo_size;
		2170	unsigned sc_earlyz_tile_fifo_size;
		2171
		2172	unsigned num_tile_pipes;
		2173	unsigned backend_enable_mask;
		2174	unsigned backend_disable_mask_per_asic;
		2175	unsigned backend_map;
		2176	unsigned num_texture_channel_caches;
		2177	unsigned mem_max_burst_length_bytes;
		2178	unsigned mem_row_size_in_kb;
		2179	unsigned shader_engine_tile_size;
		2180	unsigned num_gpus;
		2181	unsigned multi_gpu_tile_size;
		2182
		2183	unsigned tile_config;
		2184	uint32_t tile_mode_array[32];
		2185	uint32_t macrotile_mode_array[16];
		2186	uint32_t active_cus;
		2187	};
		2188
1117	serge	2189	union radeon_asic_config {
		2190	struct r300_asic r300;
1179	serge	2191	struct r100_asic r100;
		2192	struct r600_asic r600;
		2193	struct rv770_asic rv770;
1963	serge	2194	struct evergreen_asic evergreen;
		2195	struct cayman_asic cayman;
2997	Serge	2196	struct si_asic si;
5078	serge	2197	struct cik_asic cik;
1117	serge	2198	};
		2199
		2200	/*
1963	serge	2201	* asic initizalization from radeon_asic.c
		2202	*/
		2203	void radeon_agp_disable(struct radeon_device *rdev);
		2204	int radeon_asic_init(struct radeon_device *rdev);
1179	serge	2205
		2206
		2207
2997	Serge	2208	/* VRAM scratch page for HDP bug, default vram page */
		2209	struct r600_vram_scratch {
1963	serge	2210	struct radeon_bo *robj;
		2211	volatile uint32_t *ptr;
2997	Serge	2212	u64 gpu_addr;
1963	serge	2213	};
1179	serge	2214
5078	serge	2215	/*
		2216	* ACPI
		2217	*/
		2218	struct radeon_atif_notification_cfg {
		2219	bool enabled;
		2220	int command_code;
		2221	};
2997	Serge	2222
5078	serge	2223	struct radeon_atif_notifications {
		2224	bool display_switch;
		2225	bool expansion_mode_change;
		2226	bool thermal_state;
		2227	bool forced_power_state;
		2228	bool system_power_state;
		2229	bool display_conf_change;
		2230	bool px_gfx_switch;
		2231	bool brightness_change;
		2232	bool dgpu_display_event;
		2233	};
		2234
		2235	struct radeon_atif_functions {
		2236	bool system_params;
		2237	bool sbios_requests;
		2238	bool select_active_disp;
		2239	bool lid_state;
		2240	bool get_tv_standard;
		2241	bool set_tv_standard;
		2242	bool get_panel_expansion_mode;
		2243	bool set_panel_expansion_mode;
		2244	bool temperature_change;
		2245	bool graphics_device_types;
		2246	};
		2247
		2248	struct radeon_atif {
		2249	struct radeon_atif_notifications notifications;
		2250	struct radeon_atif_functions functions;
		2251	struct radeon_atif_notification_cfg notification_cfg;
		2252	struct radeon_encoder *encoder_for_bl;
		2253	};
		2254
		2255	struct radeon_atcs_functions {
		2256	bool get_ext_state;
		2257	bool pcie_perf_req;
		2258	bool pcie_dev_rdy;
		2259	bool pcie_bus_width;
		2260	};
		2261
		2262	struct radeon_atcs {
		2263	struct radeon_atcs_functions functions;
		2264	};
		2265
1117	serge	2266	/*
		2267	* Core structure, functions and helpers.
		2268	*/
		2269	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		2270	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		2271
		2272	struct radeon_device {
2997	Serge	2273	struct device *dev;
1117	serge	2274	struct drm_device *ddev;
		2275	struct pci_dev *pdev;
2997	Serge	2276	struct rw_semaphore exclusive_lock;
1117	serge	2277	/* ASIC */
		2278	union radeon_asic_config config;
		2279	enum radeon_family family;
		2280	unsigned long flags;
		2281	int usec_timeout;
		2282	enum radeon_pll_errata pll_errata;
		2283	int num_gb_pipes;
1413	serge	2284	int num_z_pipes;
1117	serge	2285	int disp_priority;
		2286	/* BIOS */
		2287	uint8_t *bios;
		2288	bool is_atom_bios;
		2289	uint16_t bios_header_start;
1413	serge	2290	struct radeon_bo *stollen_vga_memory;
1117	serge	2291	/* Register mmio */
1963	serge	2292	resource_size_t rmmio_base;
		2293	resource_size_t rmmio_size;
3192	Serge	2294	/* protects concurrent MM_INDEX/DATA based register access */
		2295	spinlock_t mmio_idx_lock;
5078	serge	2296	/* protects concurrent SMC based register access */
		2297	spinlock_t smc_idx_lock;
		2298	/* protects concurrent PLL register access */
		2299	spinlock_t pll_idx_lock;
		2300	/* protects concurrent MC register access */
		2301	spinlock_t mc_idx_lock;
		2302	/* protects concurrent PCIE register access */
		2303	spinlock_t pcie_idx_lock;
		2304	/* protects concurrent PCIE_PORT register access */
		2305	spinlock_t pciep_idx_lock;
		2306	/* protects concurrent PIF register access */
		2307	spinlock_t pif_idx_lock;
		2308	/* protects concurrent CG register access */
		2309	spinlock_t cg_idx_lock;
		2310	/* protects concurrent UVD register access */
		2311	spinlock_t uvd_idx_lock;
		2312	/* protects concurrent RCU register access */
		2313	spinlock_t rcu_idx_lock;
		2314	/* protects concurrent DIDT register access */
		2315	spinlock_t didt_idx_lock;
		2316	/* protects concurrent ENDPOINT (audio) register access */
		2317	spinlock_t end_idx_lock;
2997	Serge	2318	void __iomem *rmmio;
1120	serge	2319	radeon_rreg_t mc_rreg;
		2320	radeon_wreg_t mc_wreg;
		2321	radeon_rreg_t pll_rreg;
		2322	radeon_wreg_t pll_wreg;
1179	serge	2323	uint32_t pcie_reg_mask;
1120	serge	2324	radeon_rreg_t pciep_rreg;
		2325	radeon_wreg_t pciep_wreg;
1963	serge	2326	/* io port */
		2327	void __iomem *rio_mem;
		2328	resource_size_t rio_mem_size;
1120	serge	2329	struct radeon_clock clock;
1117	serge	2330	struct radeon_mc mc;
		2331	struct radeon_gart gart;
		2332	struct radeon_mode_info mode_info;
		2333	struct radeon_scratch scratch;
5078	serge	2334	struct radeon_doorbell doorbell;
1321	serge	2335	struct radeon_mman mman;
2997	Serge	2336	struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
		2337	wait_queue_head_t fence_queue;
5271	serge	2338	unsigned fence_context;
2997	Serge	2339	struct mutex ring_lock;
		2340	struct radeon_ring ring[RADEON_NUM_RINGS];
		2341	bool ib_pool_ready;
		2342	struct radeon_sa_manager ring_tmp_bo;
1963	serge	2343	struct radeon_irq irq;
1117	serge	2344	struct radeon_asic *asic;
1126	serge	2345	struct radeon_gem gem;
1179	serge	2346	struct radeon_pm pm;
3764	Serge	2347	struct radeon_uvd uvd;
5078	serge	2348	struct radeon_vce vce;
1179	serge	2349	uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1117	serge	2350	struct radeon_wb wb;
1179	serge	2351	struct radeon_dummy_page dummy_page;
1117	serge	2352	bool shutdown;
		2353	bool suspend;
1179	serge	2354	bool need_dma32;
		2355	bool accel_working;
3764	Serge	2356	bool fastfb_working; /* IGP feature*/
5271	serge	2357	bool needs_reset, in_reset;
1179	serge	2358	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
		2359	const struct firmware me_fw; / all family ME firmware */
		2360	const struct firmware pfp_fw; / r6/700 PFP firmware */
1403	serge	2361	const struct firmware rlc_fw; / r6/700 RLC firmware */
1963	serge	2362	const struct firmware mc_fw; / NI MC firmware */
2997	Serge	2363	const struct firmware ce_fw; / SI CE firmware */
5078	serge	2364	const struct firmware mec_fw; / CIK MEC firmware */
		2365	const struct firmware mec2_fw; / KV MEC2 firmware */
		2366	const struct firmware sdma_fw; / CIK SDMA firmware */
		2367	const struct firmware smc_fw; / SMC firmware */
3764	Serge	2368	const struct firmware uvd_fw; / UVD firmware */
5078	serge	2369	const struct firmware vce_fw; / VCE firmware */
		2370	bool new_fw;
2997	Serge	2371	struct r600_vram_scratch vram_scratch;
1268	serge	2372	int msi_enabled; /* msi enabled */
2004	serge	2373	struct r600_ih ih; /* r6/700 interrupt ring */
5078	serge	2374	struct radeon_rlc rlc;
		2375	struct radeon_mec mec;
		2376	struct work_struct hotplug_work;
		2377	struct work_struct audio_work;
1430	serge	2378	int num_crtc; /* number of crtcs */
1630	serge	2379	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3764	Serge	2380	bool has_uvd;
5078	serge	2381	struct r600_audio audio; /* audio stuff */
2997	Serge	2382	/* only one userspace can use Hyperz features or CMASK at a time */
5078	serge	2383	struct drm_file *hyperz_filp;
		2384	struct drm_file *cmask_filp;
1963	serge	2385	/* i2c buses */
		2386	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2997	Serge	2387	/* debugfs */
5078	serge	2388	struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2997	Serge	2389	unsigned debugfs_count;
		2390	/* virtual memory */
		2391	struct radeon_vm_manager vm_manager;
		2392	struct mutex gpu_clock_mutex;
5078	serge	2393	/* memory stats */
		2394	atomic64_t vram_usage;
		2395	atomic64_t gtt_usage;
		2396	atomic64_t num_bytes_moved;
2997	Serge	2397	/* ACPI interface */
5078	serge	2398	struct radeon_atif atif;
		2399	struct radeon_atcs atcs;
		2400	/* srbm instance registers */
		2401	struct mutex srbm_mutex;
5271	serge	2402	/* GRBM index mutex. Protects concurrents access to GRBM index */
		2403	struct mutex grbm_idx_mutex;
5078	serge	2404	/* clock, powergating flags */
		2405	u32 cg_flags;
		2406	u32 pg_flags;
		2407
		2408	// struct dev_pm_domain vga_pm_domain;
		2409	bool have_disp_power_ref;
		2410	u32 px_quirk_flags;
		2411
		2412	/* tracking pinned memory */
		2413	u64 vram_pin_size;
		2414	u64 gart_pin_size;
5271	serge	2415	struct mutex mn_lock;
1117	serge	2416	};
		2417
5078	serge	2418	bool radeon_is_px(struct drm_device *dev);
1117	serge	2419	int radeon_device_init(struct radeon_device *rdev,
		2420	struct drm_device *ddev,
		2421	struct pci_dev *pdev,
		2422	uint32_t flags);
		2423	void radeon_device_fini(struct radeon_device *rdev);
		2424	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		2425
5078	serge	2426	#define RADEON_MIN_MMIO_SIZE 0x10000
		2427
		2428	static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		2429	bool always_indirect)
		2430	{
		2431	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
		2432	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2433	return readl(((void __iomem *)rdev->rmmio) + reg);
		2434	else {
		2435	unsigned long flags;
		2436	uint32_t ret;
		2437
		2438	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		2439	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		2440	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		2441	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		2442
		2443	return ret;
		2444	}
		2445	}
		2446
		2447	static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		2448	bool always_indirect)
		2449	{
		2450	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2451	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		2452	else {
		2453	unsigned long flags;
		2454
		2455	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		2456	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		2457	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		2458	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		2459	}
		2460	}
		2461
2997	Serge	2462	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
		2463	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2464
5078	serge	2465	u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
		2466	void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
		2467
1321	serge	2468	/*
		2469	* Cast helper
		2470	*/
5271	serge	2471	extern const struct fence_ops radeon_fence_ops;
1117	serge	2472
5271	serge	2473	static inline struct radeon_fence to_radeon_fence(struct fence f)
		2474	{
		2475	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
		2476
		2477	if (__f->base.ops == &radeon_fence_ops)
		2478	return __f;
		2479
		2480	return NULL;
		2481	}
		2482
1117	serge	2483	/*
		2484	* Registers read & write functions.
		2485	*/
2997	Serge	2486	#define RREG8(reg) readb((rdev->rmmio) + (reg))
		2487	#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
		2488	#define RREG16(reg) readw((rdev->rmmio) + (reg))
		2489	#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
3192	Serge	2490	#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
		2491	#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
		2492	#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
		2493	#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
		2494	#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1117	serge	2495	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2496	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2497	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		2498	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		2499	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		2500	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179	serge	2501	#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
		2502	#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
3764	Serge	2503	#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
		2504	#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
5078	serge	2505	#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
		2506	#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
		2507	#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
		2508	#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
		2509	#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
		2510	#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
		2511	#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
		2512	#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
		2513	#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
		2514	#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
		2515	#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
		2516	#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
		2517	#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
		2518	#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
1117	serge	2519	#define WREG32_P(reg, val, mask) \
		2520	do { \
		2521	uint32_t tmp_ = RREG32(reg); \
		2522	tmp_ &= (mask); \
		2523	tmp_ \|= ((val) & ~(mask)); \
		2524	WREG32(reg, tmp_); \
		2525	} while (0)
3764	Serge	2526	#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
5078	serge	2527	#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1117	serge	2528	#define WREG32_PLL_P(reg, val, mask) \
		2529	do { \
		2530	uint32_t tmp_ = RREG32_PLL(reg); \
		2531	tmp_ &= (mask); \
		2532	tmp_ \|= ((val) & ~(mask)); \
		2533	WREG32_PLL(reg, tmp_); \
		2534	} while (0)
5078	serge	2535	#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1963	serge	2536	#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
		2537	#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1117	serge	2538
5078	serge	2539	#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
		2540	#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
		2541
1179	serge	2542	/*
		2543	* Indirect registers accessor
		2544	*/
		2545	static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
		2546	{
5078	serge	2547	unsigned long flags;
1179	serge	2548	uint32_t r;
1117	serge	2549
5078	serge	2550	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
1179	serge	2551	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		2552	r = RREG32(RADEON_PCIE_DATA);
5078	serge	2553	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
1179	serge	2554	return r;
		2555	}
		2556
		2557	static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2558	{
5078	serge	2559	unsigned long flags;
		2560
		2561	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
1179	serge	2562	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		2563	WREG32(RADEON_PCIE_DATA, (v));
5078	serge	2564	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
1179	serge	2565	}
		2566
5078	serge	2567	static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
		2568	{
		2569	unsigned long flags;
		2570	u32 r;
		2571
		2572	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
		2573	WREG32(TN_SMC_IND_INDEX_0, (reg));
		2574	r = RREG32(TN_SMC_IND_DATA_0);
		2575	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		2576	return r;
		2577	}
		2578
		2579	static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2580	{
		2581	unsigned long flags;
		2582
		2583	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
		2584	WREG32(TN_SMC_IND_INDEX_0, (reg));
		2585	WREG32(TN_SMC_IND_DATA_0, (v));
		2586	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		2587	}
		2588
		2589	static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
		2590	{
		2591	unsigned long flags;
		2592	u32 r;
		2593
		2594	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
		2595	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
		2596	r = RREG32(R600_RCU_DATA);
		2597	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
		2598	return r;
		2599	}
		2600
		2601	static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2602	{
		2603	unsigned long flags;
		2604
		2605	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
		2606	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
		2607	WREG32(R600_RCU_DATA, (v));
		2608	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
		2609	}
		2610
		2611	static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
		2612	{
		2613	unsigned long flags;
		2614	u32 r;
		2615
		2616	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
		2617	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
		2618	r = RREG32(EVERGREEN_CG_IND_DATA);
		2619	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
		2620	return r;
		2621	}
		2622
		2623	static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2624	{
		2625	unsigned long flags;
		2626
		2627	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
		2628	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
		2629	WREG32(EVERGREEN_CG_IND_DATA, (v));
		2630	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
		2631	}
		2632
		2633	static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
		2634	{
		2635	unsigned long flags;
		2636	u32 r;
		2637
		2638	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2639	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		2640	r = RREG32(EVERGREEN_PIF_PHY0_DATA);
		2641	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2642	return r;
		2643	}
		2644
		2645	static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2646	{
		2647	unsigned long flags;
		2648
		2649	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2650	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		2651	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
		2652	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2653	}
		2654
		2655	static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
		2656	{
		2657	unsigned long flags;
		2658	u32 r;
		2659
		2660	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2661	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		2662	r = RREG32(EVERGREEN_PIF_PHY1_DATA);
		2663	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2664	return r;
		2665	}
		2666
		2667	static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2668	{
		2669	unsigned long flags;
		2670
		2671	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2672	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		2673	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
		2674	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2675	}
		2676
		2677	static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
		2678	{
		2679	unsigned long flags;
		2680	u32 r;
		2681
		2682	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
		2683	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
		2684	r = RREG32(R600_UVD_CTX_DATA);
		2685	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
		2686	return r;
		2687	}
		2688
		2689	static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2690	{
		2691	unsigned long flags;
		2692
		2693	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
		2694	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
		2695	WREG32(R600_UVD_CTX_DATA, (v));
		2696	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
		2697	}
		2698
		2699
		2700	static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
		2701	{
		2702	unsigned long flags;
		2703	u32 r;
		2704
		2705	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
		2706	WREG32(CIK_DIDT_IND_INDEX, (reg));
		2707	r = RREG32(CIK_DIDT_IND_DATA);
		2708	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
		2709	return r;
		2710	}
		2711
		2712	static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2713	{
		2714	unsigned long flags;
		2715
		2716	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
		2717	WREG32(CIK_DIDT_IND_INDEX, (reg));
		2718	WREG32(CIK_DIDT_IND_DATA, (v));
		2719	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
		2720	}
		2721
1179	serge	2722	void r100_pll_errata_after_index(struct radeon_device *rdev);
		2723
		2724
1117	serge	2725	/*
		2726	* ASICs helpers.
		2727	*/
1179	serge	2728	#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) \|\| \
		2729	(rdev->pdev->device == 0x5969))
1117	serge	2730	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
		2731	(rdev->family == CHIP_RV200) \|\| \
		2732	(rdev->family == CHIP_RS100) \|\| \
		2733	(rdev->family == CHIP_RS200) \|\| \
		2734	(rdev->family == CHIP_RV250) \|\| \
		2735	(rdev->family == CHIP_RV280) \|\| \
		2736	(rdev->family == CHIP_RS300))
		2737	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		2738	(rdev->family == CHIP_RV350) \|\| \
		2739	(rdev->family == CHIP_R350) \|\| \
		2740	(rdev->family == CHIP_RV380) \|\| \
		2741	(rdev->family == CHIP_R420) \|\| \
		2742	(rdev->family == CHIP_R423) \|\| \
		2743	(rdev->family == CHIP_RV410) \|\| \
		2744	(rdev->family == CHIP_RS400) \|\| \
		2745	(rdev->family == CHIP_RS480))
1963	serge	2746	#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \
		2747	(rdev->ddev->pdev->device == 0x9443) \|\| \
		2748	(rdev->ddev->pdev->device == 0x944B) \|\| \
		2749	(rdev->ddev->pdev->device == 0x9506) \|\| \
		2750	(rdev->ddev->pdev->device == 0x9509) \|\| \
		2751	(rdev->ddev->pdev->device == 0x950F) \|\| \
		2752	(rdev->ddev->pdev->device == 0x689C) \|\| \
		2753	(rdev->ddev->pdev->device == 0x689D))
1117	serge	2754	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1963	serge	2755	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
		2756	(rdev->family == CHIP_RS690) \|\| \
		2757	(rdev->family == CHIP_RS740) \|\| \
		2758	(rdev->family >= CHIP_R600))
1117	serge	2759	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		2760	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1430	serge	2761	#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1963	serge	2762	#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
		2763	(rdev->flags & RADEON_IS_IGP))
		2764	#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2997	Serge	2765	#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
		2766	#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
		2767	(rdev->flags & RADEON_IS_IGP))
3764	Serge	2768	#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
		2769	#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
5078	serge	2770	#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
		2771	#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
		2772	#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
		2773	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
		2774	(rdev->family == CHIP_MULLINS))
1117	serge	2775
5078	serge	2776	#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \
		2777	(rdev->ddev->pdev->device == 0x6850) \|\| \
		2778	(rdev->ddev->pdev->device == 0x6858) \|\| \
		2779	(rdev->ddev->pdev->device == 0x6859) \|\| \
		2780	(rdev->ddev->pdev->device == 0x6840) \|\| \
		2781	(rdev->ddev->pdev->device == 0x6841) \|\| \
		2782	(rdev->ddev->pdev->device == 0x6842) \|\| \
		2783	(rdev->ddev->pdev->device == 0x6843))
		2784
1117	serge	2785	/*
		2786	* BIOS helpers.
		2787	*/
		2788	#define RBIOS8(i) (rdev->bios[i])
		2789	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		2790	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		2791
		2792	int radeon_combios_init(struct radeon_device *rdev);
		2793	void radeon_combios_fini(struct radeon_device *rdev);
		2794	int radeon_atombios_init(struct radeon_device *rdev);
		2795	void radeon_atombios_fini(struct radeon_device *rdev);
		2796
		2797
		2798	/*
		2799	* RING helpers.
		2800	*/
5271	serge	2801
		2802	/**
		2803	* radeon_ring_write - write a value to the ring
		2804	*
		2805	* @ring: radeon_ring structure holding ring information
		2806	* @v: dword (dw) value to write
		2807	*
		2808	* Write a value to the requested ring buffer (all asics).
		2809	*/
2997	Serge	2810	static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1117	serge	2811	{
5271	serge	2812	if (ring->count_dw <= 0)
		2813	DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
		2814
2997	Serge	2815	ring->ring[ring->wptr++] = v;
		2816	ring->wptr &= ring->ptr_mask;
		2817	ring->count_dw--;
		2818	ring->ring_free_dw--;
		2819	}
1117	serge	2820
		2821	/*
		2822	* ASICs macro.
		2823	*/
		2824	#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179	serge	2825	#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
		2826	#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
		2827	#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
5078	serge	2828	#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
1179	serge	2829	#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1963	serge	2830	#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2997	Serge	2831	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
5078	serge	2832	#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2997	Serge	2833	#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
		2834	#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
5078	serge	2835	#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
		2836	#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2837	#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2838	#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
		2839	#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
		2840	#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
		2841	#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
		2842	#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
		2843	#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
		2844	#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
5271	serge	2845	#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
5078	serge	2846	#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
		2847	#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
		2848	#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2997	Serge	2849	#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
		2850	#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
		2851	#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
		2852	#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
		2853	#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
3764	Serge	2854	#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
		2855	#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
5078	serge	2856	#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
		2857	#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
5271	serge	2858	#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
		2859	#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
		2860	#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2997	Serge	2861	#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
		2862	#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
		2863	#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
		2864	#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
		2865	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
		2866	#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
		2867	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
		2868	#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
		2869	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
		2870	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
3764	Serge	2871	#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
5078	serge	2872	#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
		2873	#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2997	Serge	2874	#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
		2875	#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
		2876	#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
		2877	#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
		2878	#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
		2879	#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
		2880	#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1963	serge	2881	#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2997	Serge	2882	#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
		2883	#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
		2884	#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
		2885	#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
		2886	#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
		2887	#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
5078	serge	2888	#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2997	Serge	2889	#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
		2890	#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
3764	Serge	2891	#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
		2892	#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
5078	serge	2893	#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
		2894	#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
		2895	#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
		2896	#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
		2897	#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
		2898	#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
		2899	#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
		2900	#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
		2901	#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
		2902	#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
		2903	#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
		2904	#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
		2905	#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
		2906	#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
		2907	#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
		2908	#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
		2909	#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
		2910	#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
1117	serge	2911
1179	serge	2912	/* Common functions */
1403	serge	2913	/* AGP */
1963	serge	2914	extern int radeon_gpu_reset(struct radeon_device *rdev);
5078	serge	2915	extern void radeon_pci_config_reset(struct radeon_device *rdev);
3764	Serge	2916	extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1403	serge	2917	extern void radeon_agp_disable(struct radeon_device *rdev);
1179	serge	2918	extern int radeon_modeset_init(struct radeon_device *rdev);
		2919	extern void radeon_modeset_fini(struct radeon_device *rdev);
		2920	extern bool radeon_card_posted(struct radeon_device *rdev);
1963	serge	2921	extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
		2922	extern void radeon_update_display_priority(struct radeon_device *rdev);
1321	serge	2923	extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1179	serge	2924	extern void radeon_scratch_init(struct radeon_device *rdev);
1963	serge	2925	extern void radeon_wb_fini(struct radeon_device *rdev);
		2926	extern int radeon_wb_init(struct radeon_device *rdev);
		2927	extern void radeon_wb_disable(struct radeon_device *rdev);
1179	serge	2928	extern void radeon_surface_init(struct radeon_device *rdev);
		2929	extern int radeon_cs_parser_init(struct radeon_cs_parser p, void data);
1221	serge	2930	extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
		2931	extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1321	serge	2932	extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1403	serge	2933	extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
5271	serge	2934	extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
		2935	uint32_t flags);
		2936	extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
		2937	extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
1430	serge	2938	extern void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base);
		2939	extern void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc);
5078	serge	2940	extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
		2941	extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
1963	serge	2942	extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
3764	Serge	2943	extern void radeon_program_register_sequence(struct radeon_device *rdev,
		2944	const u32 *registers,
		2945	const u32 array_size);
1117	serge	2946
1963	serge	2947	/*
2997	Serge	2948	* vm
		2949	*/
		2950	int radeon_vm_manager_init(struct radeon_device *rdev);
		2951	void radeon_vm_manager_fini(struct radeon_device *rdev);
5078	serge	2952	int radeon_vm_init(struct radeon_device rdev, struct radeon_vm vm);
2997	Serge	2953	void radeon_vm_fini(struct radeon_device rdev, struct radeon_vm vm);
5271	serge	2954	struct radeon_bo_list radeon_vm_get_bos(struct radeon_device rdev,
5078	serge	2955	struct radeon_vm *vm,
		2956	struct list_head *head);
2997	Serge	2957	struct radeon_fence radeon_vm_grab_id(struct radeon_device rdev,
		2958	struct radeon_vm *vm, int ring);
5078	serge	2959	void radeon_vm_flush(struct radeon_device *rdev,
		2960	struct radeon_vm *vm,
5271	serge	2961	int ring, struct radeon_fence *fence);
2997	Serge	2962	void radeon_vm_fence(struct radeon_device *rdev,
		2963	struct radeon_vm *vm,
		2964	struct radeon_fence *fence);
		2965	uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
5078	serge	2966	int radeon_vm_update_page_directory(struct radeon_device *rdev,
		2967	struct radeon_vm *vm);
		2968	int radeon_vm_clear_freed(struct radeon_device *rdev,
		2969	struct radeon_vm *vm);
		2970	int radeon_vm_clear_invalids(struct radeon_device *rdev,
		2971	struct radeon_vm *vm);
		2972	int radeon_vm_bo_update(struct radeon_device *rdev,
		2973	struct radeon_bo_va *bo_va,
		2974	struct ttm_mem_reg *mem);
2997	Serge	2975	void radeon_vm_bo_invalidate(struct radeon_device *rdev,
		2976	struct radeon_bo *bo);
		2977	struct radeon_bo_va radeon_vm_bo_find(struct radeon_vm vm,
		2978	struct radeon_bo *bo);
		2979	struct radeon_bo_va radeon_vm_bo_add(struct radeon_device rdev,
		2980	struct radeon_vm *vm,
		2981	struct radeon_bo *bo);
		2982	int radeon_vm_bo_set_addr(struct radeon_device *rdev,
		2983	struct radeon_bo_va *bo_va,
		2984	uint64_t offset,
		2985	uint32_t flags);
5078	serge	2986	void radeon_vm_bo_rmv(struct radeon_device *rdev,
2997	Serge	2987	struct radeon_bo_va *bo_va);
		2988
		2989	/* audio */
		2990	void r600_audio_update_hdmi(struct work_struct *work);
5078	serge	2991	struct r600_audio_pin r600_audio_get_pin(struct radeon_device rdev);
		2992	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev);
		2993	void r600_audio_enable(struct radeon_device *rdev,
		2994	struct r600_audio_pin *pin,
5271	serge	2995	u8 enable_mask);
5078	serge	2996	void dce6_audio_enable(struct radeon_device *rdev,
		2997	struct r600_audio_pin *pin,
5271	serge	2998	u8 enable_mask);
2997	Serge	2999
		3000	/*
		3001	* R600 vram scratch functions
		3002	*/
		3003	int r600_vram_scratch_init(struct radeon_device *rdev);
		3004	void r600_vram_scratch_fini(struct radeon_device *rdev);
		3005
		3006	/*
		3007	* r600 cs checking helper
		3008	*/
		3009	unsigned r600_mip_minify(unsigned size, unsigned level);
		3010	bool r600_fmt_is_valid_color(u32 format);
		3011	bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
		3012	int r600_fmt_get_blocksize(u32 format);
		3013	int r600_fmt_get_nblocksx(u32 format, u32 w);
		3014	int r600_fmt_get_nblocksy(u32 format, u32 h);
		3015
		3016	/*
1963	serge	3017	* r600 functions used by radeon_encoder.c
		3018	*/
2997	Serge	3019	struct radeon_hdmi_acr {
		3020	u32 clock;
		3021
		3022	int n_32khz;
		3023	int cts_32khz;
		3024
		3025	int n_44_1khz;
		3026	int cts_44_1khz;
		3027
		3028	int n_48khz;
		3029	int cts_48khz;
		3030
		3031	};
		3032
		3033	extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
		3034
		3035	extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
		3036	u32 tiling_pipe_num,
		3037	u32 max_rb_num,
		3038	u32 total_max_rb_num,
		3039	u32 enabled_rb_mask);
1179	serge	3040
2997	Serge	3041	/*
		3042	* evergreen functions used by radeon_encoder.c
		3043	*/
		3044
1963	serge	3045	extern int ni_init_microcode(struct radeon_device *rdev);
		3046	extern int ni_mc_load_microcode(struct radeon_device *rdev);
1221	serge	3047
1963	serge	3048	/* radeon_acpi.c */
		3049	#if defined(CONFIG_ACPI)
		3050	extern int radeon_acpi_init(struct radeon_device *rdev);
2997	Serge	3051	extern void radeon_acpi_fini(struct radeon_device *rdev);
5078	serge	3052	extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
		3053	extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
		3054	u8 perf_req, bool advertise);
		3055	extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
1963	serge	3056	#else
		3057	static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2997	Serge	3058	static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1963	serge	3059	#endif
1179	serge	3060
5078	serge	3061	int radeon_cs_packet_parse(struct radeon_cs_parser *p,
		3062	struct radeon_cs_packet *pkt,
		3063	unsigned idx);
		3064	bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
		3065	void radeon_cs_dump_packet(struct radeon_cs_parser *p,
		3066	struct radeon_cs_packet *pkt);
		3067	int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
5271	serge	3068	struct radeon_bo_list **cs_reloc,
5078	serge	3069	int nomm);
		3070	int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
		3071	uint32_t *vline_start_end,
		3072	uint32_t *vline_status);
		3073
1321	serge	3074	#include "radeon_object.h"
1179	serge	3075
5271	serge	3076	#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
1117	serge	3077
		3078	resource_size_t
		3079	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		3080	resource_size_t
		3081	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		3082
		3083
3764	Serge	3084	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h – Rev 5346