WebSVN – Kolibri OS – Blame – /drivers/video/drm/radeon/radeon.h

Rev	Author	Line No.	Line
1117	serge	1	/*
		2	* Copyright 2008 Advanced Micro Devices, Inc.
		3	* Copyright 2008 Red Hat Inc.
		4	* Copyright 2009 Jerome Glisse.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the "Software"),
		8	* to deal in the Software without restriction, including without limitation
		9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		10	* and/or sell copies of the Software, and to permit persons to whom the
		11	* Software is furnished to do so, subject to the following conditions:
		12	*
		13	* The above copyright notice and this permission notice shall be included in
		14	* all copies or substantial portions of the Software.
		15	*
		16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		22	* OTHER DEALINGS IN THE SOFTWARE.
		23	*
		24	* Authors: Dave Airlie
		25	* Alex Deucher
		26	* Jerome Glisse
		27	*/
		28	#ifndef __RADEON_H__
		29	#define __RADEON_H__
		30
		31	/* TODO: Here are things that needs to be done :
		32	* - surface allocator & initializer : (bit like scratch reg) should
		33	* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
		34	* related to surface
		35	* - WB : write back stuff (do it bit like scratch reg things)
		36	* - Vblank : look at Jesse's rework and what we should do
		37	* - r600/r700: gart & cp
		38	* - cs : clean cs ioctl use bitmap & things like that.
		39	* - power management stuff
		40	* - Barrier in gart code
		41	* - Unmappabled vram ?
		42	* - TESTING, TESTING, TESTING
		43	*/
		44
1221	serge	45	/* Initialization path:
		46	* We expect that acceleration initialization might fail for various
		47	* reasons even thought we work hard to make it works on most
		48	* configurations. In order to still have a working userspace in such
		49	* situation the init path must succeed up to the memory controller
		50	* initialization point. Failure before this point are considered as
		51	* fatal error. Here is the init callchain :
		52	* radeon_device_init perform common structure, mutex initialization
		53	* asic_init setup the GPU memory layout and perform all
		54	* one time initialization (failure in this
		55	* function are considered fatal)
		56	* asic_startup setup the GPU acceleration, in order to
		57	* follow guideline the first thing this
		58	* function should do is setting the GPU
		59	* memory controller (only MC setup failure
		60	* are considered as fatal)
		61	*/
		62
1321	serge	63	#include
2997	Serge	64	#include
1321	serge	65	#include
		66	#include
5078	serge	67	#include
2997	Serge	68	#include
1221	serge	69
1321	serge	70	#include
		71	#include
		72	#include
5078	serge	73	//#include
		74	#include
1221	serge	75
2004	serge	76	#include
1120	serge	77	#include
1117	serge	78
1120	serge	79	#include
1179	serge	80
		81	#include "radeon_family.h"
1117	serge	82	#include "radeon_mode.h"
		83	#include "radeon_reg.h"
		84
		85	#include
		86
1179	serge	87	/*
		88	* Modules parameters.
		89	*/
		90	extern int radeon_no_wb;
1123	serge	91	extern int radeon_modeset;
1117	serge	92	extern int radeon_dynclks;
1123	serge	93	extern int radeon_r4xx_atom;
1128	serge	94	extern int radeon_agpmode;
		95	extern int radeon_vram_limit;
1117	serge	96	extern int radeon_gart_size;
1128	serge	97	extern int radeon_benchmarking;
1179	serge	98	extern int radeon_testing;
1123	serge	99	extern int radeon_connector_table;
1179	serge	100	extern int radeon_tv;
1403	serge	101	extern int radeon_audio;
1963	serge	102	extern int radeon_disp_priority;
		103	extern int radeon_hw_i2c;
		104	extern int radeon_pcie_gen2;
2997	Serge	105	extern int radeon_msi;
		106	extern int radeon_lockup_timeout;
3764	Serge	107	extern int radeon_fastfb;
5078	serge	108	extern int radeon_dpm;
		109	extern int radeon_aspm;
		110	extern int radeon_runtime_pm;
		111	extern int radeon_hard_reset;
		112	extern int radeon_vm_size;
		113	extern int radeon_vm_block_size;
		114	extern int radeon_deep_color;
		115	extern int radeon_use_pflipirq;
		116	extern int radeon_bapm;
5179	serge	117	extern int radeon_backlight;
2997	Serge	118
		119
1430	serge	120	typedef struct pm_message {
		121	int event;
		122	} pm_message_t;
		123
1233	serge	124	typedef struct
		125	{
		126	int width;
		127	int height;
		128	int bpp;
		129	int freq;
1321	serge	130	}videomode_t;
1179	serge	131
		132
		133
1963	serge	134	static inline u32 ioread32(const volatile void __iomem *addr)
		135	{
		136	return in32((u32)addr);
		137	}
		138
3764	Serge	139	//static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
		140	//{
		141	// out32((u32)addr, b);
		142	//}
1963	serge	143
		144
1117	serge	145	/*
		146	* Copy from radeon_drv.h so we don't have to include both and have conflicting
		147	* symbol;
		148	*/
1120	serge	149	#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1963	serge	150	#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
1428	serge	151	/* RADEON_IB_POOL_SIZE must be a power of 2 */
1120	serge	152	#define RADEON_IB_POOL_SIZE 16
2997	Serge	153	#define RADEON_DEBUGFS_MAX_COMPONENTS 32
1120	serge	154	#define RADEONFB_CONN_LIMIT 4
1179	serge	155	#define RADEON_BIOS_NUM_SCRATCH 8
1117	serge	156
2997	Serge	157	/* fence seq are set to this number when signaled */
		158	#define RADEON_FENCE_SIGNALED_SEQ 0LL
		159
		160	/* internal ring indices */
		161	/* r1xx+ has gfx CP ring */
		162	#define RADEON_RING_TYPE_GFX_INDEX 0
		163
		164	/* cayman has 2 compute CP rings */
		165	#define CAYMAN_RING_TYPE_CP1_INDEX 1
		166	#define CAYMAN_RING_TYPE_CP2_INDEX 2
		167
3192	Serge	168	/* R600+ has an async dma ring */
		169	#define R600_RING_TYPE_DMA_INDEX 3
		170	/* cayman add a second async dma ring */
		171	#define CAYMAN_RING_TYPE_DMA1_INDEX 4
		172
3764	Serge	173	/* R600+ */
		174	#define R600_RING_TYPE_UVD_INDEX 5
		175
5078	serge	176	/* TN+ */
		177	#define TN_RING_TYPE_VCE1_INDEX 6
		178	#define TN_RING_TYPE_VCE2_INDEX 7
		179
		180	/* max number of rings */
		181	#define RADEON_NUM_RINGS 8
		182
		183	/* number of hw syncs before falling back on blocking */
		184	#define RADEON_NUM_SYNCS 4
		185
		186	/* number of hw syncs before falling back on blocking */
		187	#define RADEON_NUM_SYNCS 4
		188
2997	Serge	189	/* hardcode those limit for now */
		190	#define RADEON_VA_IB_OFFSET (1 << 20)
		191	#define RADEON_VA_RESERVED_SIZE (8 << 20)
		192	#define RADEON_IB_VM_MAX_SIZE (64 << 10)
		193
5078	serge	194	/* hard reset data */
		195	#define RADEON_ASIC_RESET_DATA 0x39d5e86b
		196
3192	Serge	197	/* reset flags */
		198	#define RADEON_RESET_GFX (1 << 0)
		199	#define RADEON_RESET_COMPUTE (1 << 1)
		200	#define RADEON_RESET_DMA (1 << 2)
3764	Serge	201	#define RADEON_RESET_CP (1 << 3)
		202	#define RADEON_RESET_GRBM (1 << 4)
		203	#define RADEON_RESET_DMA1 (1 << 5)
		204	#define RADEON_RESET_RLC (1 << 6)
		205	#define RADEON_RESET_SEM (1 << 7)
		206	#define RADEON_RESET_IH (1 << 8)
		207	#define RADEON_RESET_VMC (1 << 9)
		208	#define RADEON_RESET_MC (1 << 10)
		209	#define RADEON_RESET_DISPLAY (1 << 11)
3192	Serge	210
5078	serge	211	/* CG block flags */
		212	#define RADEON_CG_BLOCK_GFX (1 << 0)
		213	#define RADEON_CG_BLOCK_MC (1 << 1)
		214	#define RADEON_CG_BLOCK_SDMA (1 << 2)
		215	#define RADEON_CG_BLOCK_UVD (1 << 3)
		216	#define RADEON_CG_BLOCK_VCE (1 << 4)
		217	#define RADEON_CG_BLOCK_HDP (1 << 5)
		218	#define RADEON_CG_BLOCK_BIF (1 << 6)
		219
		220	/* CG flags */
		221	#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
		222	#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
		223	#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
		224	#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
		225	#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
		226	#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
		227	#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
		228	#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
		229	#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
		230	#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
		231	#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
		232	#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
		233	#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
		234	#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
		235	#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
		236	#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
		237	#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
		238
		239	/* PG flags */
		240	#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
		241	#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
		242	#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
		243	#define RADEON_PG_SUPPORT_UVD (1 << 3)
		244	#define RADEON_PG_SUPPORT_VCE (1 << 4)
		245	#define RADEON_PG_SUPPORT_CP (1 << 5)
		246	#define RADEON_PG_SUPPORT_GDS (1 << 6)
		247	#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
		248	#define RADEON_PG_SUPPORT_SDMA (1 << 8)
		249	#define RADEON_PG_SUPPORT_ACP (1 << 9)
		250	#define RADEON_PG_SUPPORT_SAMU (1 << 10)
		251
		252	/* max cursor sizes (in pixels) */
		253	#define CURSOR_WIDTH 64
		254	#define CURSOR_HEIGHT 64
		255
		256	#define CIK_CURSOR_WIDTH 128
		257	#define CIK_CURSOR_HEIGHT 128
		258
1117	serge	259	/*
		260	* Errata workarounds.
		261	*/
		262	enum radeon_pll_errata {
		263	CHIP_ERRATA_R300_CG = 0x00000001,
		264	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
		265	CHIP_ERRATA_PLL_DELAY = 0x00000004
		266	};
		267
		268
		269	struct radeon_device;
		270
		271
		272	/*
		273	* BIOS.
		274	*/
		275	bool radeon_get_bios(struct radeon_device *rdev);
		276
		277	/*
1179	serge	278	* Dummy page
		279	*/
		280	struct radeon_dummy_page {
		281	struct page *page;
		282	dma_addr_t addr;
		283	};
		284	int radeon_dummy_page_init(struct radeon_device *rdev);
		285	void radeon_dummy_page_fini(struct radeon_device *rdev);
		286
		287
		288	/*
1117	serge	289	* Clocks
		290	*/
		291	struct radeon_clock {
		292	struct radeon_pll p1pll;
		293	struct radeon_pll p2pll;
1430	serge	294	struct radeon_pll dcpll;
1117	serge	295	struct radeon_pll spll;
		296	struct radeon_pll mpll;
		297	/* 10 Khz units */
		298	uint32_t default_mclk;
		299	uint32_t default_sclk;
1430	serge	300	uint32_t default_dispclk;
5078	serge	301	uint32_t current_dispclk;
1430	serge	302	uint32_t dp_extclk;
1963	serge	303	uint32_t max_pixel_clock;
1117	serge	304	};
		305
1268	serge	306	/*
		307	* Power management
		308	*/
		309	int radeon_pm_init(struct radeon_device *rdev);
5078	serge	310	int radeon_pm_late_init(struct radeon_device *rdev);
1963	serge	311	void radeon_pm_fini(struct radeon_device *rdev);
1430	serge	312	void radeon_pm_compute_clocks(struct radeon_device *rdev);
1963	serge	313	void radeon_pm_suspend(struct radeon_device *rdev);
		314	void radeon_pm_resume(struct radeon_device *rdev);
1430	serge	315	void radeon_combios_get_power_modes(struct radeon_device *rdev);
		316	void radeon_atombios_get_power_modes(struct radeon_device *rdev);
3764	Serge	317	int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
		318	u8 clock_type,
		319	u32 clock,
		320	bool strobe_mode,
		321	struct atom_clock_dividers *dividers);
5078	serge	322	int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
		323	u32 clock,
		324	bool strobe_mode,
		325	struct atom_mpll_param *mpll_param);
1963	serge	326	void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
5078	serge	327	int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
		328	u16 voltage_level, u8 voltage_type,
		329	u32 gpio_value, u32 gpio_mask);
		330	void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
		331	u32 eng_clock, u32 mem_clock);
		332	int radeon_atom_get_voltage_step(struct radeon_device *rdev,
		333	u8 voltage_type, u16 *voltage_step);
		334	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		335	u16 voltage_id, u16 *voltage);
		336	int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
		337	u16 *voltage,
		338	u16 leakage_idx);
		339	int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
		340	u16 *leakage_id);
		341	int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
		342	u16 vddc, u16 vddci,
		343	u16 virtual_voltage_id,
		344	u16 vbios_voltage_id);
		345	int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
		346	u16 virtual_voltage_id,
		347	u16 *voltage);
		348	int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
		349	u8 voltage_type,
		350	u16 nominal_voltage,
		351	u16 *true_voltage);
		352	int radeon_atom_get_min_voltage(struct radeon_device *rdev,
		353	u8 voltage_type, u16 *min_voltage);
		354	int radeon_atom_get_max_voltage(struct radeon_device *rdev,
		355	u8 voltage_type, u16 *max_voltage);
		356	int radeon_atom_get_voltage_table(struct radeon_device *rdev,
		357	u8 voltage_type, u8 voltage_mode,
		358	struct atom_voltage_table *voltage_table);
		359	bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
		360	u8 voltage_type, u8 voltage_mode);
		361	int radeon_atom_get_svi2_info(struct radeon_device *rdev,
		362	u8 voltage_type,
		363	u8 svd_gpio_id, u8 svc_gpio_id);
		364	void radeon_atom_update_memory_dll(struct radeon_device *rdev,
		365	u32 mem_clock);
		366	void radeon_atom_set_ac_timing(struct radeon_device *rdev,
		367	u32 mem_clock);
		368	int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
		369	u8 module_index,
		370	struct atom_mc_reg_table *reg_table);
		371	int radeon_atom_get_memory_info(struct radeon_device *rdev,
		372	u8 module_index, struct atom_memory_info *mem_info);
		373	int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
		374	bool gddr5, u8 module_index,
		375	struct atom_memory_clock_range_table *mclk_range_table);
		376	int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
		377	u16 voltage_id, u16 *voltage);
1963	serge	378	void rs690_pm_info(struct radeon_device *rdev);
2997	Serge	379	extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
		380	unsigned bankh, unsigned mtaspect,
		381	unsigned *tile_split);
1179	serge	382
1117	serge	383	/*
		384	* Fences.
		385	*/
		386	struct radeon_fence_driver {
		387	uint32_t scratch_reg;
2997	Serge	388	uint64_t gpu_addr;
		389	volatile uint32_t *cpu_addr;
		390	/* sync_seq is protected by ring emission lock */
		391	uint64_t sync_seq[RADEON_NUM_RINGS];
		392	atomic64_t last_seq;
1403	serge	393	bool initialized;
1117	serge	394	};
		395
		396	struct radeon_fence {
2997	Serge	397	struct radeon_device *rdev;
		398	struct kref kref;
1117	serge	399	/* protected by radeon_fence.lock */
2997	Serge	400	uint64_t seq;
		401	/* RB, DMA, etc. */
		402	unsigned ring;
1117	serge	403	};
		404
2997	Serge	405	int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
1117	serge	406	int radeon_fence_driver_init(struct radeon_device *rdev);
		407	void radeon_fence_driver_fini(struct radeon_device *rdev);
3192	Serge	408	void radeon_fence_driver_force_completion(struct radeon_device *rdev);
2997	Serge	409	int radeon_fence_emit(struct radeon_device rdev, struct radeon_fence *fence, int ring);
		410	void radeon_fence_process(struct radeon_device *rdev, int ring);
1117	serge	411	bool radeon_fence_signaled(struct radeon_fence *fence);
		412	int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
5078	serge	413	int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
		414	int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
2997	Serge	415	int radeon_fence_wait_any(struct radeon_device *rdev,
		416	struct radeon_fence **fences,
		417	bool intr);
1117	serge	418	struct radeon_fence radeon_fence_ref(struct radeon_fence fence);
		419	void radeon_fence_unref(struct radeon_fence **fence);
2997	Serge	420	unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
		421	bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
		422	void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
		423	static inline struct radeon_fence radeon_fence_later(struct radeon_fence a,
		424	struct radeon_fence *b)
		425	{
		426	if (!a) {
		427	return b;
		428	}
1117	serge	429
2997	Serge	430	if (!b) {
		431	return a;
		432	}
		433
		434	BUG_ON(a->ring != b->ring);
		435
		436	if (a->seq > b->seq) {
		437	return a;
		438	} else {
		439	return b;
		440	}
		441	}
		442
		443	static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
		444	struct radeon_fence *b)
		445	{
		446	if (!a) {
		447	return false;
		448	}
		449
		450	if (!b) {
		451	return true;
		452	}
		453
		454	BUG_ON(a->ring != b->ring);
		455
		456	return a->seq < b->seq;
		457	}
		458
1179	serge	459	/*
		460	* Tiling registers
		461	*/
		462	struct radeon_surface_reg {
1321	serge	463	struct radeon_bo *bo;
1179	serge	464	};
1117	serge	465
1179	serge	466	#define RADEON_GEM_MAX_SURFACES 8
		467
1117	serge	468	/*
1321	serge	469	* TTM.
1117	serge	470	*/
1321	serge	471	struct radeon_mman {
		472	struct ttm_bo_global_ref bo_global_ref;
3764	Serge	473	struct drm_global_reference mem_global_ref;
1403	serge	474	struct ttm_bo_device bdev;
1321	serge	475	bool mem_global_referenced;
1403	serge	476	bool initialized;
5078	serge	477
		478	#if defined(CONFIG_DEBUG_FS)
		479	struct dentry *vram;
		480	struct dentry *gtt;
		481	#endif
1321	serge	482	};
1117	serge	483
2997	Serge	484	/* bo virtual address in a specific vm */
		485	struct radeon_bo_va {
		486	/* protected by bo being reserved */
		487	struct list_head bo_list;
		488	uint32_t flags;
5078	serge	489	uint64_t addr;
2997	Serge	490	unsigned ref_count;
		491
		492	/* protected by vm mutex */
5078	serge	493	struct interval_tree_node it;
		494	struct list_head vm_status;
2997	Serge	495
		496	/* constant after initialization */
		497	struct radeon_vm *vm;
		498	struct radeon_bo *bo;
		499	};
		500
1321	serge	501	struct radeon_bo {
		502	/* Protected by gem.mutex */
		503	struct list_head list;
		504	/* Protected by tbo.reserved */
5078	serge	505	u32 initial_domain;
1321	serge	506	u32 placements[3];
5078	serge	507	struct ttm_placement placement;
		508	struct ttm_buffer_object tbo;
1321	serge	509	struct ttm_bo_kmap_obj kmap;
5078	serge	510	u32 flags;
1404	serge	511	unsigned pin_count;
		512	void *kptr;
		513	u32 tiling_flags;
		514	u32 pitch;
		515	int surface_reg;
2997	Serge	516	/* list of all virtual address to which this bo
		517	* is associated to
		518	*/
		519	struct list_head va;
1321	serge	520	/* Constant after initialization */
		521	struct radeon_device *rdev;
1963	serge	522	struct drm_gem_object gem_base;
3120	serge	523
5078	serge	524	pid_t pid;
1321	serge	525	};
1963	serge	526	#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
1321	serge	527
3764	Serge	528	int radeon_gem_debugfs_init(struct radeon_device *rdev);
		529
2997	Serge	530	/* sub-allocation manager, it has to be protected by another lock.
		531	* By conception this is an helper for other part of the driver
		532	* like the indirect buffer or semaphore, which both have their
		533	* locking.
		534	*
		535	* Principe is simple, we keep a list of sub allocation in offset
		536	* order (first entry has offset == 0, last entry has the highest
		537	* offset).
		538	*
		539	* When allocating new object we first check if there is room at
		540	* the end total_size - (last_object_offset + last_object_size) >=
		541	* alloc_size. If so we allocate new object there.
		542	*
		543	* When there is not enough room at the end, we start waiting for
		544	* each sub object until we reach object_offset+object_size >=
		545	* alloc_size, this object then become the sub object we return.
		546	*
		547	* Alignment can't be bigger than page size.
		548	*
		549	* Hole are not considered for allocation to keep things simple.
		550	* Assumption is that there won't be hole (all object on same
		551	* alignment).
		552	*/
		553	struct radeon_sa_manager {
		554	wait_queue_head_t wq;
		555	struct radeon_bo *bo;
		556	struct list_head *hole;
		557	struct list_head flist[RADEON_NUM_RINGS];
		558	struct list_head olist;
		559	unsigned size;
		560	uint64_t gpu_addr;
		561	void *cpu_ptr;
		562	uint32_t domain;
5078	serge	563	uint32_t align;
2997	Serge	564	};
		565
		566	struct radeon_sa_bo;
		567
		568	/* sub-allocation buffer */
		569	struct radeon_sa_bo {
		570	struct list_head olist;
		571	struct list_head flist;
		572	struct radeon_sa_manager *manager;
		573	unsigned soffset;
		574	unsigned eoffset;
		575	struct radeon_fence *fence;
		576	};
		577
1123	serge	578	/*
		579	* GEM objects.
		580	*/
		581	struct radeon_gem {
1630	serge	582	struct mutex mutex;
1123	serge	583	struct list_head objects;
		584	};
1117	serge	585
1126	serge	586	int radeon_gem_init(struct radeon_device *rdev);
		587	void radeon_gem_fini(struct radeon_device *rdev);
5078	serge	588	int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
1126	serge	589	int alignment, int initial_domain,
5078	serge	590	u32 flags, bool kernel,
1126	serge	591	struct drm_gem_object **obj);
1117	serge	592
2004	serge	593	int radeon_mode_dumb_create(struct drm_file *file_priv,
		594	struct drm_device *dev,
		595	struct drm_mode_create_dumb *args);
		596	int radeon_mode_dumb_mmap(struct drm_file *filp,
		597	struct drm_device *dev,
		598	uint32_t handle, uint64_t *offset_p);
1117	serge	599
		600	/*
2997	Serge	601	* Semaphores.
1117	serge	602	*/
2997	Serge	603	struct radeon_semaphore {
		604	struct radeon_sa_bo *sa_bo;
		605	signed waiters;
		606	uint64_t gpu_addr;
5078	serge	607	struct radeon_fence *sync_to[RADEON_NUM_RINGS];
1117	serge	608	};
		609
2997	Serge	610	int radeon_semaphore_create(struct radeon_device *rdev,
		611	struct radeon_semaphore **semaphore);
5078	serge	612	bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
2997	Serge	613	struct radeon_semaphore *semaphore);
5078	serge	614	bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
2997	Serge	615	struct radeon_semaphore *semaphore);
5078	serge	616	void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
		617	struct radeon_fence *fence);
2997	Serge	618	int radeon_semaphore_sync_rings(struct radeon_device *rdev,
		619	struct radeon_semaphore *semaphore,
5078	serge	620	int waiting_ring);
2997	Serge	621	void radeon_semaphore_free(struct radeon_device *rdev,
		622	struct radeon_semaphore **semaphore,
		623	struct radeon_fence *fence);
1117	serge	624
2997	Serge	625	/*
		626	* GART structures, functions & helpers
		627	*/
		628	struct radeon_mc;
1117	serge	629
1268	serge	630	#define RADEON_GPU_PAGE_SIZE 4096
1430	serge	631	#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
2997	Serge	632	#define RADEON_GPU_PAGE_SHIFT 12
		633	#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
1268	serge	634
5078	serge	635	#define RADEON_GART_PAGE_DUMMY 0
		636	#define RADEON_GART_PAGE_VALID (1 << 0)
		637	#define RADEON_GART_PAGE_READ (1 << 1)
		638	#define RADEON_GART_PAGE_WRITE (1 << 2)
		639	#define RADEON_GART_PAGE_SNOOP (1 << 3)
		640
1117	serge	641	struct radeon_gart {
		642	dma_addr_t table_addr;
2997	Serge	643	struct radeon_bo *robj;
		644	void *ptr;
1117	serge	645	unsigned num_gpu_pages;
		646	unsigned num_cpu_pages;
		647	unsigned table_size;
		648	struct page **pages;
		649	dma_addr_t *pages_addr;
		650	bool ready;
		651	};
		652
		653	int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
		654	void radeon_gart_table_ram_free(struct radeon_device *rdev);
		655	int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
		656	void radeon_gart_table_vram_free(struct radeon_device *rdev);
2997	Serge	657	int radeon_gart_table_vram_pin(struct radeon_device *rdev);
		658	void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
1117	serge	659	int radeon_gart_init(struct radeon_device *rdev);
		660	void radeon_gart_fini(struct radeon_device *rdev);
		661	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
		662	int pages);
1120	serge	663	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
5078	serge	664	int pages, struct page **pagelist,
		665	dma_addr_t *dma_addr, uint32_t flags);
1117	serge	666
		667
		668	/*
		669	* GPU MC structures, functions & helpers
		670	*/
		671	struct radeon_mc {
		672	resource_size_t aper_size;
		673	resource_size_t aper_base;
		674	resource_size_t agp_base;
1179	serge	675	/* for some chips with <= 32MB we need to lie
		676	* about vram size near mc fb location */
		677	u64 mc_vram_size;
1430	serge	678	u64 visible_vram_size;
1179	serge	679	u64 gtt_size;
		680	u64 gtt_start;
		681	u64 gtt_end;
		682	u64 vram_start;
		683	u64 vram_end;
1117	serge	684	unsigned vram_width;
1179	serge	685	u64 real_vram_size;
1117	serge	686	int vram_mtrr;
		687	bool vram_is_ddr;
1403	serge	688	bool igp_sideport_enabled;
1963	serge	689	u64 gtt_base_align;
3764	Serge	690	u64 mc_mask;
1117	serge	691	};
		692
1403	serge	693	bool radeon_combios_sideport_present(struct radeon_device *rdev);
		694	bool radeon_atombios_sideport_present(struct radeon_device *rdev);
1117	serge	695
		696	/*
		697	* GPU scratch registers structures, functions & helpers
		698	*/
		699	struct radeon_scratch {
		700	unsigned num_reg;
1963	serge	701	uint32_t reg_base;
1117	serge	702	bool free[32];
		703	uint32_t reg[32];
		704	};
		705
		706	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg);
		707	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
		708
5078	serge	709	/*
		710	* GPU doorbell structures, functions & helpers
		711	*/
		712	#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
1117	serge	713
5078	serge	714	struct radeon_doorbell {
		715	/* doorbell mmio */
		716	resource_size_t base;
		717	resource_size_t size;
		718	u32 __iomem *ptr;
		719	u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
		720	unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
		721	};
		722
		723	int radeon_doorbell_get(struct radeon_device rdev, u32 page);
		724	void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
		725
1117	serge	726	/*
		727	* IRQS.
		728	*/
1963	serge	729	struct r500_irq_stat_regs {
		730	u32 disp_int;
2997	Serge	731	u32 hdmi0_status;
1963	serge	732	};
		733
		734	struct r600_irq_stat_regs {
		735	u32 disp_int;
		736	u32 disp_int_cont;
		737	u32 disp_int_cont2;
		738	u32 d1grph_int;
		739	u32 d2grph_int;
2997	Serge	740	u32 hdmi0_status;
		741	u32 hdmi1_status;
1963	serge	742	};
		743
		744	struct evergreen_irq_stat_regs {
		745	u32 disp_int;
		746	u32 disp_int_cont;
		747	u32 disp_int_cont2;
		748	u32 disp_int_cont3;
		749	u32 disp_int_cont4;
		750	u32 disp_int_cont5;
		751	u32 d1grph_int;
		752	u32 d2grph_int;
		753	u32 d3grph_int;
		754	u32 d4grph_int;
		755	u32 d5grph_int;
		756	u32 d6grph_int;
2997	Serge	757	u32 afmt_status1;
		758	u32 afmt_status2;
		759	u32 afmt_status3;
		760	u32 afmt_status4;
		761	u32 afmt_status5;
		762	u32 afmt_status6;
1963	serge	763	};
		764
5078	serge	765	struct cik_irq_stat_regs {
		766	u32 disp_int;
		767	u32 disp_int_cont;
		768	u32 disp_int_cont2;
		769	u32 disp_int_cont3;
		770	u32 disp_int_cont4;
		771	u32 disp_int_cont5;
		772	u32 disp_int_cont6;
		773	u32 d1grph_int;
		774	u32 d2grph_int;
		775	u32 d3grph_int;
		776	u32 d4grph_int;
		777	u32 d5grph_int;
		778	u32 d6grph_int;
		779	};
		780
1963	serge	781	union radeon_irq_stat_regs {
		782	struct r500_irq_stat_regs r500;
		783	struct r600_irq_stat_regs r600;
		784	struct evergreen_irq_stat_regs evergreen;
5078	serge	785	struct cik_irq_stat_regs cik;
1963	serge	786	};
		787
1117	serge	788	struct radeon_irq {
		789	bool installed;
2997	Serge	790	spinlock_t lock;
		791	atomic_t ring_int[RADEON_NUM_RINGS];
		792	bool crtc_vblank_int[RADEON_MAX_CRTCS];
		793	atomic_t pflip[RADEON_MAX_CRTCS];
1963	serge	794	wait_queue_head_t vblank_queue;
2997	Serge	795	bool hpd[RADEON_MAX_HPD_PINS];
		796	bool afmt[RADEON_MAX_AFMT_BLOCKS];
1963	serge	797	union radeon_irq_stat_regs stat_regs;
5078	serge	798	bool dpm_thermal;
1117	serge	799	};
		800
		801	int radeon_irq_kms_init(struct radeon_device *rdev);
		802	void radeon_irq_kms_fini(struct radeon_device *rdev);
2997	Serge	803	void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
		804	void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
2004	serge	805	void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
		806	void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
2997	Serge	807	void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
		808	void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
		809	void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
		810	void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
1117	serge	811
		812	/*
2997	Serge	813	* CP & rings.
1117	serge	814	*/
2997	Serge	815
1117	serge	816	struct radeon_ib {
2997	Serge	817	struct radeon_sa_bo *sa_bo;
		818	uint32_t length_dw;
1403	serge	819	uint64_t gpu_addr;
2997	Serge	820	uint32_t *ptr;
		821	int ring;
1117	serge	822	struct radeon_fence *fence;
2997	Serge	823	struct radeon_vm *vm;
		824	bool is_const_ib;
		825	struct radeon_semaphore *semaphore;
1117	serge	826	};
		827
2997	Serge	828	struct radeon_ring {
1321	serge	829	struct radeon_bo *ring_obj;
1117	serge	830	volatile uint32_t *ring;
2997	Serge	831	unsigned rptr_offs;
		832	unsigned rptr_save_reg;
		833	u64 next_rptr_gpu_addr;
		834	volatile u32 *next_rptr_cpu_addr;
5078	serge	835	unsigned wptr;
		836	unsigned wptr_old;
		837	unsigned ring_size;
		838	unsigned ring_free_dw;
		839	int count_dw;
		840	atomic_t last_rptr;
		841	atomic64_t last_activity;
		842	uint64_t gpu_addr;
		843	uint32_t align_mask;
		844	uint32_t ptr_mask;
		845	bool ready;
2997	Serge	846	u32 nop;
		847	u32 idx;
3764	Serge	848	u64 last_semaphore_signal_addr;
		849	u64 last_semaphore_wait_addr;
5078	serge	850	/* for CIK queues */
		851	u32 me;
		852	u32 pipe;
		853	u32 queue;
		854	struct radeon_bo *mqd_obj;
		855	u32 doorbell_index;
		856	unsigned wptr_offs;
1117	serge	857	};
		858
5078	serge	859	struct radeon_mec {
		860	struct radeon_bo *hpd_eop_obj;
		861	u64 hpd_eop_gpu_addr;
		862	u32 num_pipe;
		863	u32 num_mec;
		864	u32 num_queue;
		865	};
		866
1321	serge	867	/*
2997	Serge	868	* VM
		869	*/
		870
		871	/* maximum number of VMIDs */
		872	#define RADEON_NUM_VM 16
		873
		874	/* number of entries in page table */
5078	serge	875	#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
2997	Serge	876
5078	serge	877	/* PTBs (Page Table Blocks) need to be aligned to 32K */
		878	#define RADEON_VM_PTB_ALIGN_SIZE 32768
		879	#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
		880	#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
		881
		882	#define R600_PTE_VALID (1 << 0)
		883	#define R600_PTE_SYSTEM (1 << 1)
		884	#define R600_PTE_SNOOPED (1 << 2)
		885	#define R600_PTE_READABLE (1 << 5)
		886	#define R600_PTE_WRITEABLE (1 << 6)
		887
		888	/* PTE (Page Table Entry) fragment field for different page sizes */
		889	#define R600_PTE_FRAG_4KB (0 << 7)
		890	#define R600_PTE_FRAG_64KB (4 << 7)
		891	#define R600_PTE_FRAG_256KB (6 << 7)
		892
		893	/* flags needed to be set so we can copy directly from the GART table */
		894	#define R600_PTE_GART_MASK ( R600_PTE_READABLE \| R600_PTE_WRITEABLE \| \
		895	R600_PTE_SYSTEM \| R600_PTE_VALID )
		896
		897	struct radeon_vm_pt {
		898	struct radeon_bo *bo;
		899	uint64_t addr;
		900	};
		901
2997	Serge	902	struct radeon_vm {
5078	serge	903	struct rb_root va;
2997	Serge	904	unsigned id;
		905
5078	serge	906	/* BOs moved, but not yet updated in the PT */
		907	struct list_head invalidated;
		908
		909	/* BOs freed, but not yet updated in the PT */
		910	struct list_head freed;
		911
2997	Serge	912	/* contains the page directory */
5078	serge	913	struct radeon_bo *page_directory;
2997	Serge	914	uint64_t pd_gpu_addr;
5078	serge	915	unsigned max_pde_used;
2997	Serge	916
		917	/* array of page tables, one for each page directory entry */
5078	serge	918	struct radeon_vm_pt *page_tables;
2997	Serge	919
5078	serge	920	struct radeon_bo_va *ib_bo_va;
		921
2997	Serge	922	struct mutex mutex;
		923	/* last fence for cs using this vm */
		924	struct radeon_fence *fence;
		925	/* last flush or NULL if we still need to flush */
		926	struct radeon_fence *last_flush;
5078	serge	927	/* last use of vmid */
		928	struct radeon_fence *last_id_use;
2997	Serge	929	};
		930
		931	struct radeon_vm_manager {
		932	struct radeon_fence *active[RADEON_NUM_VM];
		933	uint32_t max_pfn;
		934	/* number of VMIDs */
		935	unsigned nvm;
		936	/* vram base address for page table entry */
		937	u64 vram_base_offset;
		938	/* is vm enabled? */
		939	bool enabled;
5078	serge	940	/* for hw to save the PD addr on suspend/resume */
		941	uint32_t saved_table_addr[RADEON_NUM_VM];
2997	Serge	942	};
		943
		944	/*
		945	* file private structure
		946	*/
		947	struct radeon_fpriv {
		948	struct radeon_vm vm;
		949	};
		950
		951	/*
1321	serge	952	* R6xx+ IH ring
		953	*/
		954	struct r600_ih {
		955	struct radeon_bo *ring_obj;
		956	volatile uint32_t *ring;
		957	unsigned rptr;
		958	unsigned ring_size;
		959	uint64_t gpu_addr;
		960	uint32_t ptr_mask;
2997	Serge	961	atomic_t lock;
1321	serge	962	bool enabled;
		963	};
		964
2997	Serge	965	/*
5078	serge	966	* RLC stuff
2997	Serge	967	*/
5078	serge	968	#include "clearstate_defs.h"
		969
		970	struct radeon_rlc {
2997	Serge	971	/* for power gating */
		972	struct radeon_bo *save_restore_obj;
		973	uint64_t save_restore_gpu_addr;
5078	serge	974	volatile uint32_t *sr_ptr;
		975	const u32 *reg_list;
		976	u32 reg_list_size;
2997	Serge	977	/* for clear state */
		978	struct radeon_bo *clear_state_obj;
		979	uint64_t clear_state_gpu_addr;
5078	serge	980	volatile uint32_t *cs_ptr;
		981	const struct cs_section_def *cs_data;
		982	u32 clear_state_size;
		983	/* for cp tables */
		984	struct radeon_bo *cp_table_obj;
		985	uint64_t cp_table_gpu_addr;
		986	volatile uint32_t *cp_table_ptr;
		987	u32 cp_table_size;
2997	Serge	988	};
		989
		990	int radeon_ib_get(struct radeon_device *rdev, int ring,
		991	struct radeon_ib ib, struct radeon_vm vm,
		992	unsigned size);
		993	void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib);
		994	int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
5078	serge	995	struct radeon_ib *const_ib, bool hdp_flush);
1117	serge	996	int radeon_ib_pool_init(struct radeon_device *rdev);
		997	void radeon_ib_pool_fini(struct radeon_device *rdev);
2997	Serge	998	int radeon_ib_ring_tests(struct radeon_device *rdev);
1117	serge	999	/* Ring access between begin & end cannot sleep */
2997	Serge	1000	bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
		1001	struct radeon_ring *ring);
		1002	void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring cp);
		1003	int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		1004	int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
5078	serge	1005	void radeon_ring_commit(struct radeon_device rdev, struct radeon_ring cp,
		1006	bool hdp_flush);
		1007	void radeon_ring_unlock_commit(struct radeon_device rdev, struct radeon_ring cp,
		1008	bool hdp_flush);
2997	Serge	1009	void radeon_ring_undo(struct radeon_ring *ring);
		1010	void radeon_ring_unlock_undo(struct radeon_device rdev, struct radeon_ring cp);
		1011	int radeon_ring_test(struct radeon_device rdev, struct radeon_ring cp);
5078	serge	1012	void radeon_ring_lockup_update(struct radeon_device *rdev,
		1013	struct radeon_ring *ring);
2997	Serge	1014	bool radeon_ring_test_lockup(struct radeon_device rdev, struct radeon_ring ring);
		1015	unsigned radeon_ring_backup(struct radeon_device rdev, struct radeon_ring ring,
		1016	uint32_t **data);
		1017	int radeon_ring_restore(struct radeon_device rdev, struct radeon_ring ring,
		1018	unsigned size, uint32_t *data);
		1019	int radeon_ring_init(struct radeon_device rdev, struct radeon_ring cp, unsigned ring_size,
5078	serge	1020	unsigned rptr_offs, u32 nop);
2997	Serge	1021	void radeon_ring_fini(struct radeon_device rdev, struct radeon_ring cp);
1117	serge	1022
		1023
3192	Serge	1024	/* r600 async dma */
		1025	void r600_dma_stop(struct radeon_device *rdev);
		1026	int r600_dma_resume(struct radeon_device *rdev);
		1027	void r600_dma_fini(struct radeon_device *rdev);
		1028
		1029	void cayman_dma_stop(struct radeon_device *rdev);
		1030	int cayman_dma_resume(struct radeon_device *rdev);
		1031	void cayman_dma_fini(struct radeon_device *rdev);
		1032
1117	serge	1033	/*
		1034	* CS.
		1035	*/
		1036	struct radeon_cs_reloc {
5078	serge	1037	struct drm_gem_object *gobj;
1321	serge	1038	struct radeon_bo *robj;
5078	serge	1039	struct ttm_validate_buffer tv;
		1040	uint64_t gpu_offset;
		1041	unsigned prefered_domains;
		1042	unsigned allowed_domains;
		1043	uint32_t tiling_flags;
1403	serge	1044	uint32_t handle;
1117	serge	1045	};
		1046
		1047	struct radeon_cs_chunk {
		1048	uint32_t chunk_id;
		1049	uint32_t length_dw;
		1050	uint32_t *kdata;
1221	serge	1051	void __user *user_ptr;
1117	serge	1052	};
		1053
		1054	struct radeon_cs_parser {
1430	serge	1055	struct device *dev;
1117	serge	1056	struct radeon_device *rdev;
2004	serge	1057	struct drm_file *filp;
1117	serge	1058	/* chunks */
		1059	unsigned nchunks;
		1060	struct radeon_cs_chunk *chunks;
		1061	uint64_t *chunks_array;
		1062	/* IB */
		1063	unsigned idx;
		1064	/* relocations */
		1065	unsigned nrelocs;
		1066	struct radeon_cs_reloc *relocs;
		1067	struct radeon_cs_reloc **relocs_ptr;
5078	serge	1068	struct radeon_cs_reloc *vm_bos;
1120	serge	1069	struct list_head validated;
3192	Serge	1070	unsigned dma_reloc_idx;
1117	serge	1071	/* indices of various chunks */
		1072	int chunk_ib_idx;
		1073	int chunk_relocs_idx;
2997	Serge	1074	int chunk_flags_idx;
		1075	int chunk_const_ib_idx;
		1076	struct radeon_ib ib;
		1077	struct radeon_ib const_ib;
1117	serge	1078	void *track;
1179	serge	1079	unsigned family;
1221	serge	1080	int parser_error;
2997	Serge	1081	u32 cs_flags;
		1082	u32 ring;
		1083	s32 priority;
5078	serge	1084	struct ww_acquire_ctx ticket;
1117	serge	1085	};
		1086
5078	serge	1087	static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
		1088	{
		1089	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1221	serge	1090
5078	serge	1091	if (ibc->kdata)
		1092	return ibc->kdata[idx];
		1093	return p->ib.ptr[idx];
		1094	}
		1095
		1096
1117	serge	1097	struct radeon_cs_packet {
		1098	unsigned idx;
		1099	unsigned type;
		1100	unsigned reg;
		1101	unsigned opcode;
		1102	int count;
		1103	unsigned one_reg_wr;
		1104	};
		1105
		1106	typedef int (radeon_packet0_check_t)(struct radeon_cs_parser p,
		1107	struct radeon_cs_packet *pkt,
		1108	unsigned idx, unsigned reg);
		1109	typedef int (radeon_packet3_check_t)(struct radeon_cs_parser p,
		1110	struct radeon_cs_packet *pkt);
		1111
		1112
		1113	/*
		1114	* AGP
		1115	*/
		1116	int radeon_agp_init(struct radeon_device *rdev);
1321	serge	1117	void radeon_agp_resume(struct radeon_device *rdev);
1963	serge	1118	void radeon_agp_suspend(struct radeon_device *rdev);
1117	serge	1119	void radeon_agp_fini(struct radeon_device *rdev);
		1120
		1121
		1122	/*
		1123	* Writeback
		1124	*/
		1125	struct radeon_wb {
1321	serge	1126	struct radeon_bo *wb_obj;
1117	serge	1127	volatile uint32_t *wb;
		1128	uint64_t gpu_addr;
1963	serge	1129	bool enabled;
		1130	bool use_event;
1117	serge	1131	};
		1132
1963	serge	1133	#define RADEON_WB_SCRATCH_OFFSET 0
2997	Serge	1134	#define RADEON_WB_RING0_NEXT_RPTR 256
1963	serge	1135	#define RADEON_WB_CP_RPTR_OFFSET 1024
		1136	#define RADEON_WB_CP1_RPTR_OFFSET 1280
		1137	#define RADEON_WB_CP2_RPTR_OFFSET 1536
3192	Serge	1138	#define R600_WB_DMA_RPTR_OFFSET 1792
1963	serge	1139	#define R600_WB_IH_WPTR_OFFSET 2048
3192	Serge	1140	#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1963	serge	1141	#define R600_WB_EVENT_OFFSET 3072
5078	serge	1142	#define CIK_WB_CP1_WPTR_OFFSET 3328
		1143	#define CIK_WB_CP2_WPTR_OFFSET 3584
5179	serge	1144	#define R600_WB_DMA_RING_TEST_OFFSET 3588
		1145	#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1963	serge	1146
1179	serge	1147	/**
		1148	* struct radeon_pm - power management datas
		1149	* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
		1150	* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
		1151	* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
		1152	* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
		1153	* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
		1154	* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
		1155	* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
		1156	* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
		1157	* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1963	serge	1158	* @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1179	serge	1159	* @needed_bandwidth: current bandwidth needs
		1160	*
		1161	* It keeps track of various data needed to take powermanagement decision.
1963	serge	1162	* Bandwidth need is used to determine minimun clock of the GPU and memory.
1179	serge	1163	* Equation between gpu/memory clock and available bandwidth is hw dependent
		1164	* (type of memory, bus size, efficiency, ...)
		1165	*/
1963	serge	1166
		1167	enum radeon_pm_method {
		1168	PM_METHOD_PROFILE,
		1169	PM_METHOD_DYNPM,
5078	serge	1170	PM_METHOD_DPM,
1430	serge	1171	};
1963	serge	1172
		1173	enum radeon_dynpm_state {
		1174	DYNPM_STATE_DISABLED,
		1175	DYNPM_STATE_MINIMUM,
		1176	DYNPM_STATE_PAUSED,
		1177	DYNPM_STATE_ACTIVE,
		1178	DYNPM_STATE_SUSPENDED,
1430	serge	1179	};
1963	serge	1180	enum radeon_dynpm_action {
		1181	DYNPM_ACTION_NONE,
		1182	DYNPM_ACTION_MINIMUM,
		1183	DYNPM_ACTION_DOWNCLOCK,
		1184	DYNPM_ACTION_UPCLOCK,
		1185	DYNPM_ACTION_DEFAULT
		1186	};
1430	serge	1187
		1188	enum radeon_voltage_type {
		1189	VOLTAGE_NONE = 0,
		1190	VOLTAGE_GPIO,
		1191	VOLTAGE_VDDC,
		1192	VOLTAGE_SW
		1193	};
		1194
		1195	enum radeon_pm_state_type {
5078	serge	1196	/* not used for dpm */
1430	serge	1197	POWER_STATE_TYPE_DEFAULT,
		1198	POWER_STATE_TYPE_POWERSAVE,
5078	serge	1199	/* user selectable states */
1430	serge	1200	POWER_STATE_TYPE_BATTERY,
		1201	POWER_STATE_TYPE_BALANCED,
		1202	POWER_STATE_TYPE_PERFORMANCE,
5078	serge	1203	/* internal states */
		1204	POWER_STATE_TYPE_INTERNAL_UVD,
		1205	POWER_STATE_TYPE_INTERNAL_UVD_SD,
		1206	POWER_STATE_TYPE_INTERNAL_UVD_HD,
		1207	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
		1208	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
		1209	POWER_STATE_TYPE_INTERNAL_BOOT,
		1210	POWER_STATE_TYPE_INTERNAL_THERMAL,
		1211	POWER_STATE_TYPE_INTERNAL_ACPI,
		1212	POWER_STATE_TYPE_INTERNAL_ULV,
		1213	POWER_STATE_TYPE_INTERNAL_3DPERF,
1430	serge	1214	};
		1215
1963	serge	1216	enum radeon_pm_profile_type {
		1217	PM_PROFILE_DEFAULT,
		1218	PM_PROFILE_AUTO,
		1219	PM_PROFILE_LOW,
		1220	PM_PROFILE_MID,
		1221	PM_PROFILE_HIGH,
1430	serge	1222	};
		1223
1963	serge	1224	#define PM_PROFILE_DEFAULT_IDX 0
		1225	#define PM_PROFILE_LOW_SH_IDX 1
		1226	#define PM_PROFILE_MID_SH_IDX 2
		1227	#define PM_PROFILE_HIGH_SH_IDX 3
		1228	#define PM_PROFILE_LOW_MH_IDX 4
		1229	#define PM_PROFILE_MID_MH_IDX 5
		1230	#define PM_PROFILE_HIGH_MH_IDX 6
		1231	#define PM_PROFILE_MAX 7
		1232
		1233	struct radeon_pm_profile {
		1234	int dpms_off_ps_idx;
		1235	int dpms_on_ps_idx;
		1236	int dpms_off_cm_idx;
		1237	int dpms_on_cm_idx;
		1238	};
		1239
		1240	enum radeon_int_thermal_type {
		1241	THERMAL_TYPE_NONE,
5078	serge	1242	THERMAL_TYPE_EXTERNAL,
		1243	THERMAL_TYPE_EXTERNAL_GPIO,
1963	serge	1244	THERMAL_TYPE_RV6XX,
		1245	THERMAL_TYPE_RV770,
5078	serge	1246	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1963	serge	1247	THERMAL_TYPE_EVERGREEN,
		1248	THERMAL_TYPE_SUMO,
		1249	THERMAL_TYPE_NI,
2997	Serge	1250	THERMAL_TYPE_SI,
5078	serge	1251	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
		1252	THERMAL_TYPE_CI,
		1253	THERMAL_TYPE_KV,
1963	serge	1254	};
		1255
1430	serge	1256	struct radeon_voltage {
		1257	enum radeon_voltage_type type;
		1258	/* gpio voltage */
		1259	struct radeon_gpio_rec gpio;
		1260	u32 delay; /* delay in usec from voltage drop to sclk change */
		1261	bool active_high; /* voltage drop is active when bit is high */
		1262	/* VDDC voltage */
		1263	u8 vddc_id; /* index into vddc voltage table */
		1264	u8 vddci_id; /* index into vddci voltage table */
		1265	bool vddci_enabled;
		1266	/* r6xx+ sw */
1963	serge	1267	u16 voltage;
		1268	/* evergreen+ vddci */
		1269	u16 vddci;
1430	serge	1270	};
		1271
1963	serge	1272	/* clock mode flags */
		1273	#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1430	serge	1274
		1275	struct radeon_pm_clock_info {
		1276	/* memory clock */
		1277	u32 mclk;
		1278	/* engine clock */
		1279	u32 sclk;
		1280	/* voltage info */
		1281	struct radeon_voltage voltage;
1963	serge	1282	/* standardized clock flags */
1430	serge	1283	u32 flags;
		1284	};
		1285
1963	serge	1286	/* state flags */
		1287	#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
		1288
1430	serge	1289	struct radeon_power_state {
		1290	enum radeon_pm_state_type type;
2997	Serge	1291	struct radeon_pm_clock_info *clock_info;
1430	serge	1292	/* number of valid clock modes in this power state */
		1293	int num_clock_modes;
		1294	struct radeon_pm_clock_info *default_clock_mode;
1963	serge	1295	/* standardized state flags */
		1296	u32 flags;
		1297	u32 misc; /* vbios specific flags */
		1298	u32 misc2; /* vbios specific flags */
		1299	int pcie_lanes; /* pcie lanes */
1430	serge	1300	};
		1301
		1302	/*
		1303	* Some modes are overclocked by very low value, accept them
		1304	*/
		1305	#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
		1306
5078	serge	1307	enum radeon_dpm_auto_throttle_src {
		1308	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
		1309	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
		1310	};
		1311
		1312	enum radeon_dpm_event_src {
		1313	RADEON_DPM_EVENT_SRC_ANALOG = 0,
		1314	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
		1315	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
		1316	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
		1317	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		1318	};
		1319
		1320	#define RADEON_MAX_VCE_LEVELS 6
		1321
		1322	enum radeon_vce_level {
		1323	RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
		1324	RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
		1325	RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
		1326	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
		1327	RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
		1328	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
		1329	};
		1330
		1331	struct radeon_ps {
		1332	u32 caps; /* vbios flags */
		1333	u32 class; /* vbios flags */
		1334	u32 class2; /* vbios flags */
		1335	/* UVD clocks */
		1336	u32 vclk;
		1337	u32 dclk;
		1338	/* VCE clocks */
		1339	u32 evclk;
		1340	u32 ecclk;
		1341	bool vce_active;
		1342	enum radeon_vce_level vce_level;
		1343	/* asic priv */
		1344	void *ps_priv;
		1345	};
		1346
		1347	struct radeon_dpm_thermal {
		1348	/* thermal interrupt work */
		1349	struct work_struct work;
		1350	/* low temperature threshold */
		1351	int min_temp;
		1352	/* high temperature threshold */
		1353	int max_temp;
		1354	/* was interrupt low to high or high to low */
		1355	bool high_to_low;
		1356	};
		1357
		1358	enum radeon_clk_action
		1359	{
		1360	RADEON_SCLK_UP = 1,
		1361	RADEON_SCLK_DOWN
		1362	};
		1363
		1364	struct radeon_blacklist_clocks
		1365	{
		1366	u32 sclk;
		1367	u32 mclk;
		1368	enum radeon_clk_action action;
		1369	};
		1370
		1371	struct radeon_clock_and_voltage_limits {
		1372	u32 sclk;
		1373	u32 mclk;
		1374	u16 vddc;
		1375	u16 vddci;
		1376	};
		1377
		1378	struct radeon_clock_array {
		1379	u32 count;
		1380	u32 *values;
		1381	};
		1382
		1383	struct radeon_clock_voltage_dependency_entry {
		1384	u32 clk;
		1385	u16 v;
		1386	};
		1387
		1388	struct radeon_clock_voltage_dependency_table {
		1389	u32 count;
		1390	struct radeon_clock_voltage_dependency_entry *entries;
		1391	};
		1392
		1393	union radeon_cac_leakage_entry {
		1394	struct {
		1395	u16 vddc;
		1396	u32 leakage;
		1397	};
		1398	struct {
		1399	u16 vddc1;
		1400	u16 vddc2;
		1401	u16 vddc3;
		1402	};
		1403	};
		1404
		1405	struct radeon_cac_leakage_table {
		1406	u32 count;
		1407	union radeon_cac_leakage_entry *entries;
		1408	};
		1409
		1410	struct radeon_phase_shedding_limits_entry {
		1411	u16 voltage;
		1412	u32 sclk;
		1413	u32 mclk;
		1414	};
		1415
		1416	struct radeon_phase_shedding_limits_table {
		1417	u32 count;
		1418	struct radeon_phase_shedding_limits_entry *entries;
		1419	};
		1420
		1421	struct radeon_uvd_clock_voltage_dependency_entry {
		1422	u32 vclk;
		1423	u32 dclk;
		1424	u16 v;
		1425	};
		1426
		1427	struct radeon_uvd_clock_voltage_dependency_table {
		1428	u8 count;
		1429	struct radeon_uvd_clock_voltage_dependency_entry *entries;
		1430	};
		1431
		1432	struct radeon_vce_clock_voltage_dependency_entry {
		1433	u32 ecclk;
		1434	u32 evclk;
		1435	u16 v;
		1436	};
		1437
		1438	struct radeon_vce_clock_voltage_dependency_table {
		1439	u8 count;
		1440	struct radeon_vce_clock_voltage_dependency_entry *entries;
		1441	};
		1442
		1443	struct radeon_ppm_table {
		1444	u8 ppm_design;
		1445	u16 cpu_core_number;
		1446	u32 platform_tdp;
		1447	u32 small_ac_platform_tdp;
		1448	u32 platform_tdc;
		1449	u32 small_ac_platform_tdc;
		1450	u32 apu_tdp;
		1451	u32 dgpu_tdp;
		1452	u32 dgpu_ulv_power;
		1453	u32 tj_max;
		1454	};
		1455
		1456	struct radeon_cac_tdp_table {
		1457	u16 tdp;
		1458	u16 configurable_tdp;
		1459	u16 tdc;
		1460	u16 battery_power_limit;
		1461	u16 small_power_limit;
		1462	u16 low_cac_leakage;
		1463	u16 high_cac_leakage;
		1464	u16 maximum_power_delivery_limit;
		1465	};
		1466
		1467	struct radeon_dpm_dynamic_state {
		1468	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
		1469	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
		1470	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
		1471	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
		1472	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
		1473	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
		1474	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
		1475	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
		1476	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
		1477	struct radeon_clock_array valid_sclk_values;
		1478	struct radeon_clock_array valid_mclk_values;
		1479	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
		1480	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
		1481	u32 mclk_sclk_ratio;
		1482	u32 sclk_mclk_delta;
		1483	u16 vddc_vddci_delta;
		1484	u16 min_vddc_for_pcie_gen2;
		1485	struct radeon_cac_leakage_table cac_leakage_table;
		1486	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
		1487	struct radeon_ppm_table *ppm_table;
		1488	struct radeon_cac_tdp_table *cac_tdp_table;
		1489	};
		1490
		1491	struct radeon_dpm_fan {
		1492	u16 t_min;
		1493	u16 t_med;
		1494	u16 t_high;
		1495	u16 pwm_min;
		1496	u16 pwm_med;
		1497	u16 pwm_high;
		1498	u8 t_hyst;
		1499	u32 cycle_delay;
		1500	u16 t_max;
		1501	bool ucode_fan_control;
		1502	};
		1503
		1504	enum radeon_pcie_gen {
		1505	RADEON_PCIE_GEN1 = 0,
		1506	RADEON_PCIE_GEN2 = 1,
		1507	RADEON_PCIE_GEN3 = 2,
		1508	RADEON_PCIE_GEN_INVALID = 0xffff
		1509	};
		1510
		1511	enum radeon_dpm_forced_level {
		1512	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
		1513	RADEON_DPM_FORCED_LEVEL_LOW = 1,
		1514	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
		1515	};
		1516
		1517	struct radeon_vce_state {
		1518	/* vce clocks */
		1519	u32 evclk;
		1520	u32 ecclk;
		1521	/* gpu clocks */
		1522	u32 sclk;
		1523	u32 mclk;
		1524	u8 clk_idx;
		1525	u8 pstate;
		1526	};
		1527
		1528	struct radeon_dpm {
		1529	struct radeon_ps *ps;
		1530	/* number of valid power states */
		1531	int num_ps;
		1532	/* current power state that is active */
		1533	struct radeon_ps *current_ps;
		1534	/* requested power state */
		1535	struct radeon_ps *requested_ps;
		1536	/* boot up power state */
		1537	struct radeon_ps *boot_ps;
		1538	/* default uvd power state */
		1539	struct radeon_ps *uvd_ps;
		1540	/* vce requirements */
		1541	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
		1542	enum radeon_vce_level vce_level;
		1543	enum radeon_pm_state_type state;
		1544	enum radeon_pm_state_type user_state;
		1545	u32 platform_caps;
		1546	u32 voltage_response_time;
		1547	u32 backbias_response_time;
		1548	void *priv;
		1549	u32 new_active_crtcs;
		1550	int new_active_crtc_count;
		1551	u32 current_active_crtcs;
		1552	int current_active_crtc_count;
		1553	struct radeon_dpm_dynamic_state dyn_state;
		1554	struct radeon_dpm_fan fan;
		1555	u32 tdp_limit;
		1556	u32 near_tdp_limit;
		1557	u32 near_tdp_limit_adjusted;
		1558	u32 sq_ramping_threshold;
		1559	u32 cac_leakage;
		1560	u16 tdp_od_limit;
		1561	u32 tdp_adjustment;
		1562	u16 load_line_slope;
		1563	bool power_control;
		1564	bool ac_power;
		1565	/* special states active */
		1566	bool thermal_active;
		1567	bool uvd_active;
		1568	bool vce_active;
		1569	/* thermal handling */
		1570	struct radeon_dpm_thermal thermal;
		1571	/* forced levels */
		1572	enum radeon_dpm_forced_level forced_level;
		1573	/* track UVD streams */
		1574	unsigned sd;
		1575	unsigned hd;
		1576	};
		1577
		1578	void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
		1579	void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
		1580
1179	serge	1581	struct radeon_pm {
1630	serge	1582	struct mutex mutex;
2997	Serge	1583	/* write locked while reprogramming mclk */
		1584	struct rw_semaphore mclk_lock;
1963	serge	1585	u32 active_crtcs;
		1586	int active_crtc_count;
1430	serge	1587	int req_vblank;
1963	serge	1588	bool vblank_sync;
1179	serge	1589	fixed20_12 max_bandwidth;
		1590	fixed20_12 igp_sideport_mclk;
		1591	fixed20_12 igp_system_mclk;
		1592	fixed20_12 igp_ht_link_clk;
		1593	fixed20_12 igp_ht_link_width;
		1594	fixed20_12 k8_bandwidth;
		1595	fixed20_12 sideport_bandwidth;
		1596	fixed20_12 ht_bandwidth;
		1597	fixed20_12 core_bandwidth;
		1598	fixed20_12 sclk;
1963	serge	1599	fixed20_12 mclk;
1179	serge	1600	fixed20_12 needed_bandwidth;
1963	serge	1601	struct radeon_power_state *power_state;
1430	serge	1602	/* number of valid power states */
		1603	int num_power_states;
1963	serge	1604	int current_power_state_index;
		1605	int current_clock_mode_index;
		1606	int requested_power_state_index;
		1607	int requested_clock_mode_index;
		1608	int default_power_state_index;
		1609	u32 current_sclk;
		1610	u32 current_mclk;
		1611	u16 current_vddc;
		1612	u16 current_vddci;
		1613	u32 default_sclk;
		1614	u32 default_mclk;
		1615	u16 default_vddc;
		1616	u16 default_vddci;
		1617	struct radeon_i2c_chan *i2c_bus;
		1618	/* selected pm method */
		1619	enum radeon_pm_method pm_method;
		1620	/* dynpm power management */
5078	serge	1621	struct delayed_work dynpm_idle_work;
1963	serge	1622	enum radeon_dynpm_state dynpm_state;
		1623	enum radeon_dynpm_action dynpm_planned_action;
		1624	unsigned long dynpm_action_timeout;
		1625	bool dynpm_can_upclock;
		1626	bool dynpm_can_downclock;
		1627	/* profile-based power management */
		1628	enum radeon_pm_profile_type profile;
		1629	int profile_index;
		1630	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
		1631	/* internal thermal controller on rv6xx+ */
		1632	enum radeon_int_thermal_type int_thermal_type;
		1633	struct device *int_hwmon_dev;
5078	serge	1634	/* dpm */
		1635	bool dpm_enabled;
		1636	struct radeon_dpm dpm;
1179	serge	1637	};
1117	serge	1638
2997	Serge	1639	int radeon_pm_get_type_index(struct radeon_device *rdev,
		1640	enum radeon_pm_state_type ps_type,
		1641	int instance);
3764	Serge	1642	/*
		1643	* UVD
		1644	*/
		1645	#define RADEON_MAX_UVD_HANDLES 10
		1646	#define RADEON_UVD_STACK_SIZE (1024*1024)
		1647	#define RADEON_UVD_HEAP_SIZE (1024*1024)
2997	Serge	1648
3764	Serge	1649	struct radeon_uvd {
		1650	struct radeon_bo *vcpu_bo;
		1651	void *cpu_addr;
		1652	uint64_t gpu_addr;
5078	serge	1653	void *saved_bo;
3764	Serge	1654	atomic_t handles[RADEON_MAX_UVD_HANDLES];
		1655	struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
5078	serge	1656	unsigned img_size[RADEON_MAX_UVD_HANDLES];
3764	Serge	1657	struct delayed_work idle_work;
		1658	};
		1659
		1660	int radeon_uvd_init(struct radeon_device *rdev);
		1661	void radeon_uvd_fini(struct radeon_device *rdev);
		1662	int radeon_uvd_suspend(struct radeon_device *rdev);
		1663	int radeon_uvd_resume(struct radeon_device *rdev);
		1664	int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
		1665	uint32_t handle, struct radeon_fence **fence);
		1666	int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
		1667	uint32_t handle, struct radeon_fence **fence);
		1668	void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
		1669	void radeon_uvd_free_handles(struct radeon_device *rdev,
		1670	struct drm_file *filp);
		1671	int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
		1672	void radeon_uvd_note_usage(struct radeon_device *rdev);
		1673	int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
		1674	unsigned vclk, unsigned dclk,
		1675	unsigned vco_min, unsigned vco_max,
		1676	unsigned fb_factor, unsigned fb_mask,
		1677	unsigned pd_min, unsigned pd_max,
		1678	unsigned pd_even,
		1679	unsigned *optimal_fb_div,
		1680	unsigned *optimal_vclk_div,
		1681	unsigned *optimal_dclk_div);
		1682	int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
		1683	unsigned cg_upll_func_cntl);
		1684
5078	serge	1685	/*
		1686	* VCE
		1687	*/
		1688	#define RADEON_MAX_VCE_HANDLES 16
		1689	#define RADEON_VCE_STACK_SIZE (1024*1024)
		1690	#define RADEON_VCE_HEAP_SIZE (410241024)
		1691
		1692	struct radeon_vce {
		1693	struct radeon_bo *vcpu_bo;
		1694	uint64_t gpu_addr;
		1695	unsigned fw_version;
		1696	unsigned fb_version;
		1697	atomic_t handles[RADEON_MAX_VCE_HANDLES];
		1698	struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
		1699	unsigned img_size[RADEON_MAX_VCE_HANDLES];
		1700	struct delayed_work idle_work;
		1701	};
		1702
		1703	int radeon_vce_init(struct radeon_device *rdev);
		1704	void radeon_vce_fini(struct radeon_device *rdev);
		1705	int radeon_vce_suspend(struct radeon_device *rdev);
		1706	int radeon_vce_resume(struct radeon_device *rdev);
		1707	int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
		1708	uint32_t handle, struct radeon_fence **fence);
		1709	int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
		1710	uint32_t handle, struct radeon_fence **fence);
		1711	void radeon_vce_free_handles(struct radeon_device rdev, struct drm_file filp);
		1712	void radeon_vce_note_usage(struct radeon_device *rdev);
		1713	int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
		1714	int radeon_vce_cs_parse(struct radeon_cs_parser *p);
		1715	bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
		1716	struct radeon_ring *ring,
		1717	struct radeon_semaphore *semaphore,
		1718	bool emit_wait);
		1719	void radeon_vce_ib_execute(struct radeon_device rdev, struct radeon_ib ib);
		1720	void radeon_vce_fence_emit(struct radeon_device *rdev,
		1721	struct radeon_fence *fence);
		1722	int radeon_vce_ring_test(struct radeon_device rdev, struct radeon_ring ring);
		1723	int radeon_vce_ib_test(struct radeon_device rdev, struct radeon_ring ring);
		1724
		1725	struct r600_audio_pin {
2997	Serge	1726	int channels;
		1727	int rate;
		1728	int bits_per_sample;
		1729	u8 status_bits;
		1730	u8 category_code;
5078	serge	1731	u32 offset;
		1732	bool connected;
		1733	u32 id;
2997	Serge	1734	};
5078	serge	1735
		1736	struct r600_audio {
		1737	bool enabled;
		1738	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
		1739	int num_pins;
		1740	};
		1741
1117	serge	1742	/*
5078	serge	1743	* Benchmarking
		1744	*/
		1745	void radeon_benchmark(struct radeon_device *rdev, int test_number);
		1746
		1747
		1748	/*
		1749	* Testing
		1750	*/
		1751	void radeon_test_moves(struct radeon_device *rdev);
		1752	void radeon_test_ring_sync(struct radeon_device *rdev,
		1753	struct radeon_ring *cpA,
		1754	struct radeon_ring *cpB);
		1755	void radeon_test_syncing(struct radeon_device *rdev);
		1756
		1757
		1758	/*
		1759	* Debugfs
		1760	*/
		1761	struct radeon_debugfs {
		1762	struct drm_info_list *files;
		1763	unsigned num_files;
		1764	};
		1765
		1766	int radeon_debugfs_add_files(struct radeon_device *rdev,
		1767	struct drm_info_list *files,
		1768	unsigned nfiles);
		1769	int radeon_debugfs_fence_init(struct radeon_device *rdev);
		1770
		1771	/*
		1772	* ASIC ring specific functions.
		1773	*/
		1774	struct radeon_asic_ring {
		1775	/* ring read/write ptr handling */
		1776	u32 (get_rptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1777	u32 (get_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1778	void (set_wptr)(struct radeon_device rdev, struct radeon_ring *ring);
		1779
		1780	/* validating and patching of IBs */
		1781	int (ib_parse)(struct radeon_device rdev, struct radeon_ib *ib);
		1782	int (cs_parse)(struct radeon_cs_parser p);
		1783
		1784	/* command emmit functions */
		1785	void (ib_execute)(struct radeon_device rdev, struct radeon_ib *ib);
		1786	void (emit_fence)(struct radeon_device rdev, struct radeon_fence *fence);
		1787	void (hdp_flush)(struct radeon_device rdev, struct radeon_ring *ring);
		1788	bool (emit_semaphore)(struct radeon_device rdev, struct radeon_ring *cp,
		1789	struct radeon_semaphore *semaphore, bool emit_wait);
		1790	void (vm_flush)(struct radeon_device rdev, int ridx, struct radeon_vm *vm);
		1791
		1792	/* testing functions */
		1793	int (ring_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1794	int (ib_test)(struct radeon_device rdev, struct radeon_ring *cp);
		1795	bool (is_lockup)(struct radeon_device rdev, struct radeon_ring *cp);
		1796
		1797	/* deprecated */
		1798	void (ring_start)(struct radeon_device rdev, struct radeon_ring *cp);
		1799	};
		1800
		1801	/*
1117	serge	1802	* ASIC specific functions.
		1803	*/
		1804	struct radeon_asic {
		1805	int (init)(struct radeon_device rdev);
1179	serge	1806	void (fini)(struct radeon_device rdev);
		1807	int (resume)(struct radeon_device rdev);
		1808	int (suspend)(struct radeon_device rdev);
		1809	void (vga_set_state)(struct radeon_device rdev, bool state);
1963	serge	1810	int (asic_reset)(struct radeon_device rdev);
5078	serge	1811	/* Flush the HDP cache via MMIO */
		1812	void (mmio_hdp_flush)(struct radeon_device rdev);
2997	Serge	1813	/* check if 3D engine is idle */
		1814	bool (gui_idle)(struct radeon_device rdev);
		1815	/* wait for mc_idle */
		1816	int (mc_wait_for_idle)(struct radeon_device rdev);
3764	Serge	1817	/* get the reference clock */
		1818	u32 (get_xclk)(struct radeon_device rdev);
		1819	/* get the gpu clock counter */
		1820	uint64_t (get_gpu_clock_counter)(struct radeon_device rdev);
2997	Serge	1821	/* gart */
		1822	struct {
		1823	void (tlb_flush)(struct radeon_device rdev);
5078	serge	1824	void (set_page)(struct radeon_device rdev, unsigned i,
		1825	uint64_t addr, uint32_t flags);
2997	Serge	1826	} gart;
		1827	struct {
		1828	int (init)(struct radeon_device rdev);
		1829	void (fini)(struct radeon_device rdev);
5078	serge	1830	void (copy_pages)(struct radeon_device rdev,
		1831	struct radeon_ib *ib,
		1832	uint64_t pe, uint64_t src,
		1833	unsigned count);
		1834	void (write_pages)(struct radeon_device rdev,
		1835	struct radeon_ib *ib,
		1836	uint64_t pe,
		1837	uint64_t addr, unsigned count,
		1838	uint32_t incr, uint32_t flags);
		1839	void (set_pages)(struct radeon_device rdev,
3764	Serge	1840	struct radeon_ib *ib,
		1841	uint64_t pe,
2997	Serge	1842	uint64_t addr, unsigned count,
		1843	uint32_t incr, uint32_t flags);
5078	serge	1844	void (pad_ib)(struct radeon_ib ib);
2997	Serge	1845	} vm;
		1846	/* ring specific callbacks */
5078	serge	1847	struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
2997	Serge	1848	/* irqs */
		1849	struct {
		1850	int (set)(struct radeon_device rdev);
		1851	int (process)(struct radeon_device rdev);
		1852	} irq;
		1853	/* displays */
		1854	struct {
		1855	/* display watermarks */
		1856	void (bandwidth_update)(struct radeon_device rdev);
		1857	/* get frame count */
1179	serge	1858	u32 (get_vblank_counter)(struct radeon_device rdev, int crtc);
2997	Serge	1859	/* wait for vblank */
		1860	void (wait_for_vblank)(struct radeon_device rdev, int crtc);
		1861	/* set backlight level */
		1862	void (set_backlight_level)(struct radeon_encoder radeon_encoder, u8 level);
		1863	/* get backlight level */
		1864	u8 (get_backlight_level)(struct radeon_encoder radeon_encoder);
3764	Serge	1865	/* audio callbacks */
		1866	void (hdmi_enable)(struct drm_encoder encoder, bool enable);
		1867	void (hdmi_setmode)(struct drm_encoder encoder, struct drm_display_mode *mode);
2997	Serge	1868	} display;
		1869	/* copy functions for bo handling */
		1870	struct {
		1871	int (blit)(struct radeon_device rdev,
1117	serge	1872	uint64_t src_offset,
		1873	uint64_t dst_offset,
2997	Serge	1874	unsigned num_gpu_pages,
		1875	struct radeon_fence **fence);
		1876	u32 blit_ring_index;
		1877	int (dma)(struct radeon_device rdev,
1117	serge	1878	uint64_t src_offset,
		1879	uint64_t dst_offset,
2997	Serge	1880	unsigned num_gpu_pages,
		1881	struct radeon_fence **fence);
		1882	u32 dma_ring_index;
		1883	/* method used for bo copy */
1117	serge	1884	int (copy)(struct radeon_device rdev,
		1885	uint64_t src_offset,
		1886	uint64_t dst_offset,
2997	Serge	1887	unsigned num_gpu_pages,
		1888	struct radeon_fence **fence);
		1889	/* ring used for bo copies */
		1890	u32 copy_ring_index;
		1891	} copy;
		1892	/* surfaces */
		1893	struct {
		1894	int (set_reg)(struct radeon_device rdev, int reg,
		1895	uint32_t tiling_flags, uint32_t pitch,
		1896	uint32_t offset, uint32_t obj_size);
		1897	void (clear_reg)(struct radeon_device rdev, int reg);
		1898	} surface;
		1899	/* hotplug detect */
		1900	struct {
		1901	void (init)(struct radeon_device rdev);
		1902	void (fini)(struct radeon_device rdev);
		1903	bool (sense)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1904	void (set_polarity)(struct radeon_device rdev, enum radeon_hpd_id hpd);
		1905	} hpd;
5078	serge	1906	/* static power management */
2997	Serge	1907	struct {
		1908	void (misc)(struct radeon_device rdev);
		1909	void (prepare)(struct radeon_device rdev);
		1910	void (finish)(struct radeon_device rdev);
		1911	void (init_profile)(struct radeon_device rdev);
		1912	void (get_dynpm_state)(struct radeon_device rdev);
1268	serge	1913	uint32_t (get_engine_clock)(struct radeon_device rdev);
1117	serge	1914	void (set_engine_clock)(struct radeon_device rdev, uint32_t eng_clock);
1268	serge	1915	uint32_t (get_memory_clock)(struct radeon_device rdev);
1117	serge	1916	void (set_memory_clock)(struct radeon_device rdev, uint32_t mem_clock);
1430	serge	1917	int (get_pcie_lanes)(struct radeon_device rdev);
1117	serge	1918	void (set_pcie_lanes)(struct radeon_device rdev, int lanes);
		1919	void (set_clock_gating)(struct radeon_device rdev, int enable);
3764	Serge	1920	int (set_uvd_clocks)(struct radeon_device rdev, u32 vclk, u32 dclk);
5078	serge	1921	int (set_vce_clocks)(struct radeon_device rdev, u32 evclk, u32 ecclk);
		1922	int (get_temperature)(struct radeon_device rdev);
2997	Serge	1923	} pm;
5078	serge	1924	/* dynamic power management */
		1925	struct {
		1926	int (init)(struct radeon_device rdev);
		1927	void (setup_asic)(struct radeon_device rdev);
		1928	int (enable)(struct radeon_device rdev);
		1929	int (late_enable)(struct radeon_device rdev);
		1930	void (disable)(struct radeon_device rdev);
		1931	int (pre_set_power_state)(struct radeon_device rdev);
		1932	int (set_power_state)(struct radeon_device rdev);
		1933	void (post_set_power_state)(struct radeon_device rdev);
		1934	void (display_configuration_changed)(struct radeon_device rdev);
		1935	void (fini)(struct radeon_device rdev);
		1936	u32 (get_sclk)(struct radeon_device rdev, bool low);
		1937	u32 (get_mclk)(struct radeon_device rdev, bool low);
		1938	void (print_power_state)(struct radeon_device rdev, struct radeon_ps *ps);
		1939	void (debugfs_print_current_performance_level)(struct radeon_device rdev, struct seq_file *m);
		1940	int (force_performance_level)(struct radeon_device rdev, enum radeon_dpm_forced_level level);
		1941	bool (vblank_too_short)(struct radeon_device rdev);
		1942	void (powergate_uvd)(struct radeon_device rdev, bool gate);
		1943	void (enable_bapm)(struct radeon_device rdev, bool enable);
		1944	} dpm;
1963	serge	1945	/* pageflipping */
2997	Serge	1946	struct {
5078	serge	1947	void (page_flip)(struct radeon_device rdev, int crtc, u64 crtc_base);
		1948	bool (page_flip_pending)(struct radeon_device rdev, int crtc);
2997	Serge	1949	} pflip;
1117	serge	1950	};
		1951
1179	serge	1952	/*
		1953	* Asic structures
		1954	*/
		1955	struct r100_asic {
		1956	const unsigned *reg_safe_bm;
		1957	unsigned reg_safe_bm_size;
1403	serge	1958	u32 hdp_cntl;
1179	serge	1959	};
		1960
		1961	struct r300_asic {
		1962	const unsigned *reg_safe_bm;
		1963	unsigned reg_safe_bm_size;
1403	serge	1964	u32 resync_scratch;
		1965	u32 hdp_cntl;
1179	serge	1966	};
		1967
		1968	struct r600_asic {
		1969	unsigned max_pipes;
		1970	unsigned max_tile_pipes;
		1971	unsigned max_simds;
		1972	unsigned max_backends;
		1973	unsigned max_gprs;
		1974	unsigned max_threads;
		1975	unsigned max_stack_entries;
		1976	unsigned max_hw_contexts;
		1977	unsigned max_gs_threads;
		1978	unsigned sx_max_export_size;
		1979	unsigned sx_max_export_pos_size;
		1980	unsigned sx_max_export_smx_size;
		1981	unsigned sq_num_cf_insts;
1430	serge	1982	unsigned tiling_nbanks;
		1983	unsigned tiling_npipes;
		1984	unsigned tiling_group_size;
1963	serge	1985	unsigned tile_config;
2160	serge	1986	unsigned backend_map;
5078	serge	1987	unsigned active_simds;
1179	serge	1988	};
		1989
		1990	struct rv770_asic {
		1991	unsigned max_pipes;
		1992	unsigned max_tile_pipes;
		1993	unsigned max_simds;
		1994	unsigned max_backends;
		1995	unsigned max_gprs;
		1996	unsigned max_threads;
		1997	unsigned max_stack_entries;
		1998	unsigned max_hw_contexts;
		1999	unsigned max_gs_threads;
		2000	unsigned sx_max_export_size;
		2001	unsigned sx_max_export_pos_size;
		2002	unsigned sx_max_export_smx_size;
		2003	unsigned sq_num_cf_insts;
		2004	unsigned sx_num_of_sets;
		2005	unsigned sc_prim_fifo_size;
		2006	unsigned sc_hiz_tile_fifo_size;
		2007	unsigned sc_earlyz_tile_fifo_fize;
1430	serge	2008	unsigned tiling_nbanks;
		2009	unsigned tiling_npipes;
		2010	unsigned tiling_group_size;
1963	serge	2011	unsigned tile_config;
2160	serge	2012	unsigned backend_map;
5078	serge	2013	unsigned active_simds;
1179	serge	2014	};
		2015
1963	serge	2016	struct evergreen_asic {
		2017	unsigned num_ses;
		2018	unsigned max_pipes;
		2019	unsigned max_tile_pipes;
		2020	unsigned max_simds;
		2021	unsigned max_backends;
		2022	unsigned max_gprs;
		2023	unsigned max_threads;
		2024	unsigned max_stack_entries;
		2025	unsigned max_hw_contexts;
		2026	unsigned max_gs_threads;
		2027	unsigned sx_max_export_size;
		2028	unsigned sx_max_export_pos_size;
		2029	unsigned sx_max_export_smx_size;
		2030	unsigned sq_num_cf_insts;
		2031	unsigned sx_num_of_sets;
		2032	unsigned sc_prim_fifo_size;
		2033	unsigned sc_hiz_tile_fifo_size;
		2034	unsigned sc_earlyz_tile_fifo_size;
		2035	unsigned tiling_nbanks;
		2036	unsigned tiling_npipes;
		2037	unsigned tiling_group_size;
		2038	unsigned tile_config;
2160	serge	2039	unsigned backend_map;
5078	serge	2040	unsigned active_simds;
1963	serge	2041	};
		2042
		2043	struct cayman_asic {
		2044	unsigned max_shader_engines;
		2045	unsigned max_pipes_per_simd;
		2046	unsigned max_tile_pipes;
		2047	unsigned max_simds_per_se;
		2048	unsigned max_backends_per_se;
		2049	unsigned max_texture_channel_caches;
		2050	unsigned max_gprs;
		2051	unsigned max_threads;
		2052	unsigned max_gs_threads;
		2053	unsigned max_stack_entries;
		2054	unsigned sx_num_of_sets;
		2055	unsigned sx_max_export_size;
		2056	unsigned sx_max_export_pos_size;
		2057	unsigned sx_max_export_smx_size;
		2058	unsigned max_hw_contexts;
		2059	unsigned sq_num_cf_insts;
		2060	unsigned sc_prim_fifo_size;
		2061	unsigned sc_hiz_tile_fifo_size;
		2062	unsigned sc_earlyz_tile_fifo_size;
		2063
		2064	unsigned num_shader_engines;
		2065	unsigned num_shader_pipes_per_simd;
		2066	unsigned num_tile_pipes;
		2067	unsigned num_simds_per_se;
		2068	unsigned num_backends_per_se;
		2069	unsigned backend_disable_mask_per_asic;
		2070	unsigned backend_map;
		2071	unsigned num_texture_channel_caches;
		2072	unsigned mem_max_burst_length_bytes;
		2073	unsigned mem_row_size_in_kb;
		2074	unsigned shader_engine_tile_size;
		2075	unsigned num_gpus;
		2076	unsigned multi_gpu_tile_size;
		2077
		2078	unsigned tile_config;
5078	serge	2079	unsigned active_simds;
1963	serge	2080	};
		2081
2997	Serge	2082	struct si_asic {
		2083	unsigned max_shader_engines;
		2084	unsigned max_tile_pipes;
		2085	unsigned max_cu_per_sh;
		2086	unsigned max_sh_per_se;
		2087	unsigned max_backends_per_se;
		2088	unsigned max_texture_channel_caches;
		2089	unsigned max_gprs;
		2090	unsigned max_gs_threads;
		2091	unsigned max_hw_contexts;
		2092	unsigned sc_prim_fifo_size_frontend;
		2093	unsigned sc_prim_fifo_size_backend;
		2094	unsigned sc_hiz_tile_fifo_size;
		2095	unsigned sc_earlyz_tile_fifo_size;
		2096
		2097	unsigned num_tile_pipes;
5078	serge	2098	unsigned backend_enable_mask;
2997	Serge	2099	unsigned backend_disable_mask_per_asic;
		2100	unsigned backend_map;
		2101	unsigned num_texture_channel_caches;
		2102	unsigned mem_max_burst_length_bytes;
		2103	unsigned mem_row_size_in_kb;
		2104	unsigned shader_engine_tile_size;
		2105	unsigned num_gpus;
		2106	unsigned multi_gpu_tile_size;
		2107
		2108	unsigned tile_config;
3764	Serge	2109	uint32_t tile_mode_array[32];
5078	serge	2110	uint32_t active_cus;
2997	Serge	2111	};
		2112
5078	serge	2113	struct cik_asic {
		2114	unsigned max_shader_engines;
		2115	unsigned max_tile_pipes;
		2116	unsigned max_cu_per_sh;
		2117	unsigned max_sh_per_se;
		2118	unsigned max_backends_per_se;
		2119	unsigned max_texture_channel_caches;
		2120	unsigned max_gprs;
		2121	unsigned max_gs_threads;
		2122	unsigned max_hw_contexts;
		2123	unsigned sc_prim_fifo_size_frontend;
		2124	unsigned sc_prim_fifo_size_backend;
		2125	unsigned sc_hiz_tile_fifo_size;
		2126	unsigned sc_earlyz_tile_fifo_size;
		2127
		2128	unsigned num_tile_pipes;
		2129	unsigned backend_enable_mask;
		2130	unsigned backend_disable_mask_per_asic;
		2131	unsigned backend_map;
		2132	unsigned num_texture_channel_caches;
		2133	unsigned mem_max_burst_length_bytes;
		2134	unsigned mem_row_size_in_kb;
		2135	unsigned shader_engine_tile_size;
		2136	unsigned num_gpus;
		2137	unsigned multi_gpu_tile_size;
		2138
		2139	unsigned tile_config;
		2140	uint32_t tile_mode_array[32];
		2141	uint32_t macrotile_mode_array[16];
		2142	uint32_t active_cus;
		2143	};
		2144
1117	serge	2145	union radeon_asic_config {
		2146	struct r300_asic r300;
1179	serge	2147	struct r100_asic r100;
		2148	struct r600_asic r600;
		2149	struct rv770_asic rv770;
1963	serge	2150	struct evergreen_asic evergreen;
		2151	struct cayman_asic cayman;
2997	Serge	2152	struct si_asic si;
5078	serge	2153	struct cik_asic cik;
1117	serge	2154	};
		2155
		2156	/*
1963	serge	2157	* asic initizalization from radeon_asic.c
		2158	*/
		2159	void radeon_agp_disable(struct radeon_device *rdev);
		2160	int radeon_asic_init(struct radeon_device *rdev);
1179	serge	2161
		2162
		2163
2997	Serge	2164	/* VRAM scratch page for HDP bug, default vram page */
		2165	struct r600_vram_scratch {
1963	serge	2166	struct radeon_bo *robj;
		2167	volatile uint32_t *ptr;
2997	Serge	2168	u64 gpu_addr;
1963	serge	2169	};
1179	serge	2170
5078	serge	2171	/*
		2172	* ACPI
		2173	*/
		2174	struct radeon_atif_notification_cfg {
		2175	bool enabled;
		2176	int command_code;
		2177	};
2997	Serge	2178
5078	serge	2179	struct radeon_atif_notifications {
		2180	bool display_switch;
		2181	bool expansion_mode_change;
		2182	bool thermal_state;
		2183	bool forced_power_state;
		2184	bool system_power_state;
		2185	bool display_conf_change;
		2186	bool px_gfx_switch;
		2187	bool brightness_change;
		2188	bool dgpu_display_event;
		2189	};
		2190
		2191	struct radeon_atif_functions {
		2192	bool system_params;
		2193	bool sbios_requests;
		2194	bool select_active_disp;
		2195	bool lid_state;
		2196	bool get_tv_standard;
		2197	bool set_tv_standard;
		2198	bool get_panel_expansion_mode;
		2199	bool set_panel_expansion_mode;
		2200	bool temperature_change;
		2201	bool graphics_device_types;
		2202	};
		2203
		2204	struct radeon_atif {
		2205	struct radeon_atif_notifications notifications;
		2206	struct radeon_atif_functions functions;
		2207	struct radeon_atif_notification_cfg notification_cfg;
		2208	struct radeon_encoder *encoder_for_bl;
		2209	};
		2210
		2211	struct radeon_atcs_functions {
		2212	bool get_ext_state;
		2213	bool pcie_perf_req;
		2214	bool pcie_dev_rdy;
		2215	bool pcie_bus_width;
		2216	};
		2217
		2218	struct radeon_atcs {
		2219	struct radeon_atcs_functions functions;
		2220	};
		2221
1117	serge	2222	/*
		2223	* Core structure, functions and helpers.
		2224	*/
		2225	typedef uint32_t (radeon_rreg_t)(struct radeon_device, uint32_t);
		2226	typedef void (radeon_wreg_t)(struct radeon_device, uint32_t, uint32_t);
		2227
		2228	struct radeon_device {
2997	Serge	2229	struct device *dev;
1117	serge	2230	struct drm_device *ddev;
		2231	struct pci_dev *pdev;
2997	Serge	2232	struct rw_semaphore exclusive_lock;
1117	serge	2233	/* ASIC */
		2234	union radeon_asic_config config;
		2235	enum radeon_family family;
		2236	unsigned long flags;
		2237	int usec_timeout;
		2238	enum radeon_pll_errata pll_errata;
		2239	int num_gb_pipes;
1413	serge	2240	int num_z_pipes;
1117	serge	2241	int disp_priority;
		2242	/* BIOS */
		2243	uint8_t *bios;
		2244	bool is_atom_bios;
		2245	uint16_t bios_header_start;
1413	serge	2246	struct radeon_bo *stollen_vga_memory;
1117	serge	2247	/* Register mmio */
1963	serge	2248	resource_size_t rmmio_base;
		2249	resource_size_t rmmio_size;
3192	Serge	2250	/* protects concurrent MM_INDEX/DATA based register access */
		2251	spinlock_t mmio_idx_lock;
5078	serge	2252	/* protects concurrent SMC based register access */
		2253	spinlock_t smc_idx_lock;
		2254	/* protects concurrent PLL register access */
		2255	spinlock_t pll_idx_lock;
		2256	/* protects concurrent MC register access */
		2257	spinlock_t mc_idx_lock;
		2258	/* protects concurrent PCIE register access */
		2259	spinlock_t pcie_idx_lock;
		2260	/* protects concurrent PCIE_PORT register access */
		2261	spinlock_t pciep_idx_lock;
		2262	/* protects concurrent PIF register access */
		2263	spinlock_t pif_idx_lock;
		2264	/* protects concurrent CG register access */
		2265	spinlock_t cg_idx_lock;
		2266	/* protects concurrent UVD register access */
		2267	spinlock_t uvd_idx_lock;
		2268	/* protects concurrent RCU register access */
		2269	spinlock_t rcu_idx_lock;
		2270	/* protects concurrent DIDT register access */
		2271	spinlock_t didt_idx_lock;
		2272	/* protects concurrent ENDPOINT (audio) register access */
		2273	spinlock_t end_idx_lock;
2997	Serge	2274	void __iomem *rmmio;
1120	serge	2275	radeon_rreg_t mc_rreg;
		2276	radeon_wreg_t mc_wreg;
		2277	radeon_rreg_t pll_rreg;
		2278	radeon_wreg_t pll_wreg;
1179	serge	2279	uint32_t pcie_reg_mask;
1120	serge	2280	radeon_rreg_t pciep_rreg;
		2281	radeon_wreg_t pciep_wreg;
1963	serge	2282	/* io port */
		2283	void __iomem *rio_mem;
		2284	resource_size_t rio_mem_size;
1120	serge	2285	struct radeon_clock clock;
1117	serge	2286	struct radeon_mc mc;
		2287	struct radeon_gart gart;
		2288	struct radeon_mode_info mode_info;
		2289	struct radeon_scratch scratch;
5078	serge	2290	struct radeon_doorbell doorbell;
1321	serge	2291	struct radeon_mman mman;
2997	Serge	2292	struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
		2293	wait_queue_head_t fence_queue;
		2294	struct mutex ring_lock;
		2295	struct radeon_ring ring[RADEON_NUM_RINGS];
		2296	bool ib_pool_ready;
		2297	struct radeon_sa_manager ring_tmp_bo;
1963	serge	2298	struct radeon_irq irq;
1117	serge	2299	struct radeon_asic *asic;
1126	serge	2300	struct radeon_gem gem;
1179	serge	2301	struct radeon_pm pm;
3764	Serge	2302	struct radeon_uvd uvd;
5078	serge	2303	struct radeon_vce vce;
1179	serge	2304	uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1117	serge	2305	struct radeon_wb wb;
1179	serge	2306	struct radeon_dummy_page dummy_page;
1117	serge	2307	bool shutdown;
		2308	bool suspend;
1179	serge	2309	bool need_dma32;
		2310	bool accel_working;
3764	Serge	2311	bool fastfb_working; /* IGP feature*/
5078	serge	2312	bool needs_reset;
1179	serge	2313	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
		2314	const struct firmware me_fw; / all family ME firmware */
		2315	const struct firmware pfp_fw; / r6/700 PFP firmware */
1403	serge	2316	const struct firmware rlc_fw; / r6/700 RLC firmware */
1963	serge	2317	const struct firmware mc_fw; / NI MC firmware */
2997	Serge	2318	const struct firmware ce_fw; / SI CE firmware */
5078	serge	2319	const struct firmware mec_fw; / CIK MEC firmware */
		2320	const struct firmware mec2_fw; / KV MEC2 firmware */
		2321	const struct firmware sdma_fw; / CIK SDMA firmware */
		2322	const struct firmware smc_fw; / SMC firmware */
3764	Serge	2323	const struct firmware uvd_fw; / UVD firmware */
5078	serge	2324	const struct firmware vce_fw; / VCE firmware */
		2325	bool new_fw;
2997	Serge	2326	struct r600_vram_scratch vram_scratch;
1268	serge	2327	int msi_enabled; /* msi enabled */
2004	serge	2328	struct r600_ih ih; /* r6/700 interrupt ring */
5078	serge	2329	struct radeon_rlc rlc;
		2330	struct radeon_mec mec;
		2331	struct work_struct hotplug_work;
		2332	struct work_struct audio_work;
		2333	struct work_struct reset_work;
1430	serge	2334	int num_crtc; /* number of crtcs */
1630	serge	2335	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3764	Serge	2336	bool has_uvd;
5078	serge	2337	struct r600_audio audio; /* audio stuff */
2997	Serge	2338	/* only one userspace can use Hyperz features or CMASK at a time */
5078	serge	2339	struct drm_file *hyperz_filp;
		2340	struct drm_file *cmask_filp;
1963	serge	2341	/* i2c buses */
		2342	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2997	Serge	2343	/* debugfs */
5078	serge	2344	struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2997	Serge	2345	unsigned debugfs_count;
		2346	/* virtual memory */
		2347	struct radeon_vm_manager vm_manager;
		2348	struct mutex gpu_clock_mutex;
5078	serge	2349	/* memory stats */
		2350	atomic64_t vram_usage;
		2351	atomic64_t gtt_usage;
		2352	atomic64_t num_bytes_moved;
2997	Serge	2353	/* ACPI interface */
5078	serge	2354	struct radeon_atif atif;
		2355	struct radeon_atcs atcs;
		2356	/* srbm instance registers */
		2357	struct mutex srbm_mutex;
		2358	/* clock, powergating flags */
		2359	u32 cg_flags;
		2360	u32 pg_flags;
		2361
		2362	// struct dev_pm_domain vga_pm_domain;
		2363	bool have_disp_power_ref;
		2364	u32 px_quirk_flags;
		2365
		2366	/* tracking pinned memory */
		2367	u64 vram_pin_size;
		2368	u64 gart_pin_size;
1117	serge	2369	};
		2370
5078	serge	2371	bool radeon_is_px(struct drm_device *dev);
1117	serge	2372	int radeon_device_init(struct radeon_device *rdev,
		2373	struct drm_device *ddev,
		2374	struct pci_dev *pdev,
		2375	uint32_t flags);
		2376	void radeon_device_fini(struct radeon_device *rdev);
		2377	int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
		2378
5078	serge	2379	#define RADEON_MIN_MMIO_SIZE 0x10000
		2380
		2381	static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		2382	bool always_indirect)
		2383	{
		2384	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
		2385	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2386	return readl(((void __iomem *)rdev->rmmio) + reg);
		2387	else {
		2388	unsigned long flags;
		2389	uint32_t ret;
		2390
		2391	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		2392	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		2393	ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		2394	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		2395
		2396	return ret;
		2397	}
		2398	}
		2399
		2400	static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		2401	bool always_indirect)
		2402	{
		2403	if ((reg < rdev->rmmio_size \|\| reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
		2404	writel(v, ((void __iomem *)rdev->rmmio) + reg);
		2405	else {
		2406	unsigned long flags;
		2407
		2408	spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
		2409	writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
		2410	writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
		2411	spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
		2412	}
		2413	}
		2414
2997	Serge	2415	u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
		2416	void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1117	serge	2417
5078	serge	2418	u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
		2419	void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
		2420
1321	serge	2421	/*
		2422	* Cast helper
		2423	*/
		2424	#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1117	serge	2425
		2426	/*
		2427	* Registers read & write functions.
		2428	*/
2997	Serge	2429	#define RREG8(reg) readb((rdev->rmmio) + (reg))
		2430	#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
		2431	#define RREG16(reg) readw((rdev->rmmio) + (reg))
		2432	#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
3192	Serge	2433	#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
		2434	#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
		2435	#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
		2436	#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
		2437	#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1117	serge	2438	#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2439	#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
		2440	#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
		2441	#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
		2442	#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
		2443	#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1179	serge	2444	#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
		2445	#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
3764	Serge	2446	#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
		2447	#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
5078	serge	2448	#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
		2449	#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
		2450	#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
		2451	#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
		2452	#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
		2453	#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
		2454	#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
		2455	#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
		2456	#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
		2457	#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
		2458	#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
		2459	#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
		2460	#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
		2461	#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
1117	serge	2462	#define WREG32_P(reg, val, mask) \
		2463	do { \
		2464	uint32_t tmp_ = RREG32(reg); \
		2465	tmp_ &= (mask); \
		2466	tmp_ \|= ((val) & ~(mask)); \
		2467	WREG32(reg, tmp_); \
		2468	} while (0)
3764	Serge	2469	#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
5078	serge	2470	#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1117	serge	2471	#define WREG32_PLL_P(reg, val, mask) \
		2472	do { \
		2473	uint32_t tmp_ = RREG32_PLL(reg); \
		2474	tmp_ &= (mask); \
		2475	tmp_ \|= ((val) & ~(mask)); \
		2476	WREG32_PLL(reg, tmp_); \
		2477	} while (0)
5078	serge	2478	#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1963	serge	2479	#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
		2480	#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1117	serge	2481
5078	serge	2482	#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
		2483	#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
		2484
1179	serge	2485	/*
		2486	* Indirect registers accessor
		2487	*/
		2488	static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
		2489	{
5078	serge	2490	unsigned long flags;
1179	serge	2491	uint32_t r;
1117	serge	2492
5078	serge	2493	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
1179	serge	2494	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		2495	r = RREG32(RADEON_PCIE_DATA);
5078	serge	2496	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
1179	serge	2497	return r;
		2498	}
		2499
		2500	static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
		2501	{
5078	serge	2502	unsigned long flags;
		2503
		2504	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
1179	serge	2505	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
		2506	WREG32(RADEON_PCIE_DATA, (v));
5078	serge	2507	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
1179	serge	2508	}
		2509
5078	serge	2510	static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
		2511	{
		2512	unsigned long flags;
		2513	u32 r;
		2514
		2515	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
		2516	WREG32(TN_SMC_IND_INDEX_0, (reg));
		2517	r = RREG32(TN_SMC_IND_DATA_0);
		2518	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		2519	return r;
		2520	}
		2521
		2522	static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2523	{
		2524	unsigned long flags;
		2525
		2526	spin_lock_irqsave(&rdev->smc_idx_lock, flags);
		2527	WREG32(TN_SMC_IND_INDEX_0, (reg));
		2528	WREG32(TN_SMC_IND_DATA_0, (v));
		2529	spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
		2530	}
		2531
		2532	static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
		2533	{
		2534	unsigned long flags;
		2535	u32 r;
		2536
		2537	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
		2538	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
		2539	r = RREG32(R600_RCU_DATA);
		2540	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
		2541	return r;
		2542	}
		2543
		2544	static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2545	{
		2546	unsigned long flags;
		2547
		2548	spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
		2549	WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
		2550	WREG32(R600_RCU_DATA, (v));
		2551	spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
		2552	}
		2553
		2554	static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
		2555	{
		2556	unsigned long flags;
		2557	u32 r;
		2558
		2559	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
		2560	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
		2561	r = RREG32(EVERGREEN_CG_IND_DATA);
		2562	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
		2563	return r;
		2564	}
		2565
		2566	static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2567	{
		2568	unsigned long flags;
		2569
		2570	spin_lock_irqsave(&rdev->cg_idx_lock, flags);
		2571	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
		2572	WREG32(EVERGREEN_CG_IND_DATA, (v));
		2573	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
		2574	}
		2575
		2576	static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
		2577	{
		2578	unsigned long flags;
		2579	u32 r;
		2580
		2581	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2582	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		2583	r = RREG32(EVERGREEN_PIF_PHY0_DATA);
		2584	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2585	return r;
		2586	}
		2587
		2588	static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2589	{
		2590	unsigned long flags;
		2591
		2592	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2593	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		2594	WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
		2595	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2596	}
		2597
		2598	static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
		2599	{
		2600	unsigned long flags;
		2601	u32 r;
		2602
		2603	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2604	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		2605	r = RREG32(EVERGREEN_PIF_PHY1_DATA);
		2606	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2607	return r;
		2608	}
		2609
		2610	static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2611	{
		2612	unsigned long flags;
		2613
		2614	spin_lock_irqsave(&rdev->pif_idx_lock, flags);
		2615	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		2616	WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
		2617	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
		2618	}
		2619
		2620	static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
		2621	{
		2622	unsigned long flags;
		2623	u32 r;
		2624
		2625	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
		2626	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
		2627	r = RREG32(R600_UVD_CTX_DATA);
		2628	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
		2629	return r;
		2630	}
		2631
		2632	static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2633	{
		2634	unsigned long flags;
		2635
		2636	spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
		2637	WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
		2638	WREG32(R600_UVD_CTX_DATA, (v));
		2639	spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
		2640	}
		2641
		2642
		2643	static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
		2644	{
		2645	unsigned long flags;
		2646	u32 r;
		2647
		2648	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
		2649	WREG32(CIK_DIDT_IND_INDEX, (reg));
		2650	r = RREG32(CIK_DIDT_IND_DATA);
		2651	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
		2652	return r;
		2653	}
		2654
		2655	static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		2656	{
		2657	unsigned long flags;
		2658
		2659	spin_lock_irqsave(&rdev->didt_idx_lock, flags);
		2660	WREG32(CIK_DIDT_IND_INDEX, (reg));
		2661	WREG32(CIK_DIDT_IND_DATA, (v));
		2662	spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
		2663	}
		2664
1179	serge	2665	void r100_pll_errata_after_index(struct radeon_device *rdev);
		2666
		2667
1117	serge	2668	/*
		2669	* ASICs helpers.
		2670	*/
1179	serge	2671	#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) \|\| \
		2672	(rdev->pdev->device == 0x5969))
1117	serge	2673	#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) \|\| \
		2674	(rdev->family == CHIP_RV200) \|\| \
		2675	(rdev->family == CHIP_RS100) \|\| \
		2676	(rdev->family == CHIP_RS200) \|\| \
		2677	(rdev->family == CHIP_RV250) \|\| \
		2678	(rdev->family == CHIP_RV280) \|\| \
		2679	(rdev->family == CHIP_RS300))
		2680	#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) \|\| \
		2681	(rdev->family == CHIP_RV350) \|\| \
		2682	(rdev->family == CHIP_R350) \|\| \
		2683	(rdev->family == CHIP_RV380) \|\| \
		2684	(rdev->family == CHIP_R420) \|\| \
		2685	(rdev->family == CHIP_R423) \|\| \
		2686	(rdev->family == CHIP_RV410) \|\| \
		2687	(rdev->family == CHIP_RS400) \|\| \
		2688	(rdev->family == CHIP_RS480))
1963	serge	2689	#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) \|\| \
		2690	(rdev->ddev->pdev->device == 0x9443) \|\| \
		2691	(rdev->ddev->pdev->device == 0x944B) \|\| \
		2692	(rdev->ddev->pdev->device == 0x9506) \|\| \
		2693	(rdev->ddev->pdev->device == 0x9509) \|\| \
		2694	(rdev->ddev->pdev->device == 0x950F) \|\| \
		2695	(rdev->ddev->pdev->device == 0x689C) \|\| \
		2696	(rdev->ddev->pdev->device == 0x689D))
1117	serge	2697	#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1963	serge	2698	#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) \|\| \
		2699	(rdev->family == CHIP_RS690) \|\| \
		2700	(rdev->family == CHIP_RS740) \|\| \
		2701	(rdev->family >= CHIP_R600))
1117	serge	2702	#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
		2703	#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1430	serge	2704	#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1963	serge	2705	#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
		2706	(rdev->flags & RADEON_IS_IGP))
		2707	#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2997	Serge	2708	#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
		2709	#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
		2710	(rdev->flags & RADEON_IS_IGP))
3764	Serge	2711	#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
		2712	#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
5078	serge	2713	#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
		2714	#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
		2715	#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
		2716	#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) \|\| \
		2717	(rdev->family == CHIP_MULLINS))
1117	serge	2718
5078	serge	2719	#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) \|\| \
		2720	(rdev->ddev->pdev->device == 0x6850) \|\| \
		2721	(rdev->ddev->pdev->device == 0x6858) \|\| \
		2722	(rdev->ddev->pdev->device == 0x6859) \|\| \
		2723	(rdev->ddev->pdev->device == 0x6840) \|\| \
		2724	(rdev->ddev->pdev->device == 0x6841) \|\| \
		2725	(rdev->ddev->pdev->device == 0x6842) \|\| \
		2726	(rdev->ddev->pdev->device == 0x6843))
		2727
1117	serge	2728	/*
		2729	* BIOS helpers.
		2730	*/
		2731	#define RBIOS8(i) (rdev->bios[i])
		2732	#define RBIOS16(i) (RBIOS8(i) \| (RBIOS8((i)+1) << 8))
		2733	#define RBIOS32(i) ((RBIOS16(i)) \| (RBIOS16((i)+2) << 16))
		2734
		2735	int radeon_combios_init(struct radeon_device *rdev);
		2736	void radeon_combios_fini(struct radeon_device *rdev);
		2737	int radeon_atombios_init(struct radeon_device *rdev);
		2738	void radeon_atombios_fini(struct radeon_device *rdev);
		2739
		2740
		2741	/*
		2742	* RING helpers.
		2743	*/
2997	Serge	2744	#if DRM_DEBUG_CODE == 0
		2745	static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1117	serge	2746	{
2997	Serge	2747	ring->ring[ring->wptr++] = v;
		2748	ring->wptr &= ring->ptr_mask;
		2749	ring->count_dw--;
		2750	ring->ring_free_dw--;
		2751	}
		2752	#else
		2753	/* With debugging this is just too big to inline */
		2754	void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1117	serge	2755	#endif
		2756
		2757	/*
		2758	* ASICs macro.
		2759	*/
		2760	#define radeon_init(rdev) (rdev)->asic->init((rdev))
1179	serge	2761	#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
		2762	#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
		2763	#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
5078	serge	2764	#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
1179	serge	2765	#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1963	serge	2766	#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2997	Serge	2767	#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
5078	serge	2768	#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
2997	Serge	2769	#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
		2770	#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
5078	serge	2771	#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
		2772	#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2773	#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
		2774	#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
		2775	#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
		2776	#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
		2777	#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
		2778	#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
		2779	#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
		2780	#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
		2781	#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
		2782	#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
		2783	#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
		2784	#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2997	Serge	2785	#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
		2786	#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
		2787	#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
		2788	#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
		2789	#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
3764	Serge	2790	#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
		2791	#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
5078	serge	2792	#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
		2793	#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2997	Serge	2794	#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
		2795	#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
		2796	#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
		2797	#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
		2798	#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
		2799	#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
		2800	#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
		2801	#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
		2802	#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
		2803	#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
		2804	#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
		2805	#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
		2806	#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
3764	Serge	2807	#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
5078	serge	2808	#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
		2809	#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2997	Serge	2810	#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
		2811	#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
		2812	#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
		2813	#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
		2814	#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
		2815	#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
		2816	#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1963	serge	2817	#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2997	Serge	2818	#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
		2819	#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
		2820	#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
		2821	#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
		2822	#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
		2823	#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
5078	serge	2824	#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2997	Serge	2825	#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
		2826	#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
3764	Serge	2827	#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
		2828	#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
5078	serge	2829	#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
		2830	#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
		2831	#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
		2832	#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
		2833	#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
		2834	#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
		2835	#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
		2836	#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
		2837	#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
		2838	#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
		2839	#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
		2840	#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
		2841	#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
		2842	#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
		2843	#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
		2844	#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
		2845	#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
		2846	#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
1117	serge	2847
1179	serge	2848	/* Common functions */
1403	serge	2849	/* AGP */
1963	serge	2850	extern int radeon_gpu_reset(struct radeon_device *rdev);
5078	serge	2851	extern void radeon_pci_config_reset(struct radeon_device *rdev);
3764	Serge	2852	extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1403	serge	2853	extern void radeon_agp_disable(struct radeon_device *rdev);
1179	serge	2854	extern int radeon_modeset_init(struct radeon_device *rdev);
		2855	extern void radeon_modeset_fini(struct radeon_device *rdev);
		2856	extern bool radeon_card_posted(struct radeon_device *rdev);
1963	serge	2857	extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
		2858	extern void radeon_update_display_priority(struct radeon_device *rdev);
1321	serge	2859	extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1179	serge	2860	extern void radeon_scratch_init(struct radeon_device *rdev);
1963	serge	2861	extern void radeon_wb_fini(struct radeon_device *rdev);
		2862	extern int radeon_wb_init(struct radeon_device *rdev);
		2863	extern void radeon_wb_disable(struct radeon_device *rdev);
1179	serge	2864	extern void radeon_surface_init(struct radeon_device *rdev);
		2865	extern int radeon_cs_parser_init(struct radeon_cs_parser p, void data);
1221	serge	2866	extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
		2867	extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1321	serge	2868	extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1403	serge	2869	extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1430	serge	2870	extern void radeon_vram_location(struct radeon_device rdev, struct radeon_mc mc, u64 base);
		2871	extern void radeon_gtt_location(struct radeon_device rdev, struct radeon_mc mc);
5078	serge	2872	extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
		2873	extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
1963	serge	2874	extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
3764	Serge	2875	extern void radeon_program_register_sequence(struct radeon_device *rdev,
		2876	const u32 *registers,
		2877	const u32 array_size);
1117	serge	2878
1963	serge	2879	/*
2997	Serge	2880	* vm
		2881	*/
		2882	int radeon_vm_manager_init(struct radeon_device *rdev);
		2883	void radeon_vm_manager_fini(struct radeon_device *rdev);
5078	serge	2884	int radeon_vm_init(struct radeon_device rdev, struct radeon_vm vm);
2997	Serge	2885	void radeon_vm_fini(struct radeon_device rdev, struct radeon_vm vm);
5078	serge	2886	struct radeon_cs_reloc radeon_vm_get_bos(struct radeon_device rdev,
		2887	struct radeon_vm *vm,
		2888	struct list_head *head);
2997	Serge	2889	struct radeon_fence radeon_vm_grab_id(struct radeon_device rdev,
		2890	struct radeon_vm *vm, int ring);
5078	serge	2891	void radeon_vm_flush(struct radeon_device *rdev,
		2892	struct radeon_vm *vm,
		2893	int ring);
2997	Serge	2894	void radeon_vm_fence(struct radeon_device *rdev,
		2895	struct radeon_vm *vm,
		2896	struct radeon_fence *fence);
		2897	uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
5078	serge	2898	int radeon_vm_update_page_directory(struct radeon_device *rdev,
		2899	struct radeon_vm *vm);
		2900	int radeon_vm_clear_freed(struct radeon_device *rdev,
		2901	struct radeon_vm *vm);
		2902	int radeon_vm_clear_invalids(struct radeon_device *rdev,
		2903	struct radeon_vm *vm);
		2904	int radeon_vm_bo_update(struct radeon_device *rdev,
		2905	struct radeon_bo_va *bo_va,
		2906	struct ttm_mem_reg *mem);
2997	Serge	2907	void radeon_vm_bo_invalidate(struct radeon_device *rdev,
		2908	struct radeon_bo *bo);
		2909	struct radeon_bo_va radeon_vm_bo_find(struct radeon_vm vm,
		2910	struct radeon_bo *bo);
		2911	struct radeon_bo_va radeon_vm_bo_add(struct radeon_device rdev,
		2912	struct radeon_vm *vm,
		2913	struct radeon_bo *bo);
		2914	int radeon_vm_bo_set_addr(struct radeon_device *rdev,
		2915	struct radeon_bo_va *bo_va,
		2916	uint64_t offset,
		2917	uint32_t flags);
5078	serge	2918	void radeon_vm_bo_rmv(struct radeon_device *rdev,
2997	Serge	2919	struct radeon_bo_va *bo_va);
		2920
		2921	/* audio */
		2922	void r600_audio_update_hdmi(struct work_struct *work);
5078	serge	2923	struct r600_audio_pin r600_audio_get_pin(struct radeon_device rdev);
		2924	struct r600_audio_pin dce6_audio_get_pin(struct radeon_device rdev);
		2925	void r600_audio_enable(struct radeon_device *rdev,
		2926	struct r600_audio_pin *pin,
		2927	bool enable);
		2928	void dce6_audio_enable(struct radeon_device *rdev,
		2929	struct r600_audio_pin *pin,
		2930	bool enable);
2997	Serge	2931
		2932	/*
		2933	* R600 vram scratch functions
		2934	*/
		2935	int r600_vram_scratch_init(struct radeon_device *rdev);
		2936	void r600_vram_scratch_fini(struct radeon_device *rdev);
		2937
		2938	/*
		2939	* r600 cs checking helper
		2940	*/
		2941	unsigned r600_mip_minify(unsigned size, unsigned level);
		2942	bool r600_fmt_is_valid_color(u32 format);
		2943	bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
		2944	int r600_fmt_get_blocksize(u32 format);
		2945	int r600_fmt_get_nblocksx(u32 format, u32 w);
		2946	int r600_fmt_get_nblocksy(u32 format, u32 h);
		2947
		2948	/*
1963	serge	2949	* r600 functions used by radeon_encoder.c
		2950	*/
2997	Serge	2951	struct radeon_hdmi_acr {
		2952	u32 clock;
		2953
		2954	int n_32khz;
		2955	int cts_32khz;
		2956
		2957	int n_44_1khz;
		2958	int cts_44_1khz;
		2959
		2960	int n_48khz;
		2961	int cts_48khz;
		2962
		2963	};
		2964
		2965	extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
		2966
		2967	extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
		2968	u32 tiling_pipe_num,
		2969	u32 max_rb_num,
		2970	u32 total_max_rb_num,
		2971	u32 enabled_rb_mask);
1179	serge	2972
2997	Serge	2973	/*
		2974	* evergreen functions used by radeon_encoder.c
		2975	*/
		2976
1963	serge	2977	extern int ni_init_microcode(struct radeon_device *rdev);
		2978	extern int ni_mc_load_microcode(struct radeon_device *rdev);
1221	serge	2979
1963	serge	2980	/* radeon_acpi.c */
		2981	#if defined(CONFIG_ACPI)
		2982	extern int radeon_acpi_init(struct radeon_device *rdev);
2997	Serge	2983	extern void radeon_acpi_fini(struct radeon_device *rdev);
5078	serge	2984	extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
		2985	extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
		2986	u8 perf_req, bool advertise);
		2987	extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
1963	serge	2988	#else
		2989	static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2997	Serge	2990	static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1963	serge	2991	#endif
1179	serge	2992
5078	serge	2993	int radeon_cs_packet_parse(struct radeon_cs_parser *p,
		2994	struct radeon_cs_packet *pkt,
		2995	unsigned idx);
		2996	bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
		2997	void radeon_cs_dump_packet(struct radeon_cs_parser *p,
		2998	struct radeon_cs_packet *pkt);
		2999	int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
		3000	struct radeon_cs_reloc **cs_reloc,
		3001	int nomm);
		3002	int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
		3003	uint32_t *vline_start_end,
		3004	uint32_t *vline_status);
		3005
1321	serge	3006	#include "radeon_object.h"
1179	serge	3007
1117	serge	3008	#define DRM_UDELAY(d) udelay(d)
		3009
		3010	resource_size_t
		3011	drm_get_resource_start(struct drm_device *dev, unsigned int resource);
		3012	resource_size_t
		3013	drm_get_resource_len(struct drm_device *dev, unsigned int resource);
		3014
		3015
3764	Serge	3016	#endif

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon.h – Rev 5179