Rev 2997 | Rev 3764 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * Copyright 2009 Jerome Glisse. |
||
5 | * |
||
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
7 | * copy of this software and associated documentation files (the "Software"), |
||
8 | * to deal in the Software without restriction, including without limitation |
||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
11 | * Software is furnished to do so, subject to the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice shall be included in |
||
14 | * all copies or substantial portions of the Software. |
||
15 | * |
||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
23 | * |
||
24 | * Authors: Dave Airlie |
||
25 | * Alex Deucher |
||
26 | * Jerome Glisse |
||
27 | */ |
||
28 | #ifndef __RADEON_H__ |
||
29 | #define __RADEON_H__ |
||
30 | |||
31 | /* TODO: Here are things that needs to be done : |
||
32 | * - surface allocator & initializer : (bit like scratch reg) should |
||
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
||
34 | * related to surface |
||
35 | * - WB : write back stuff (do it bit like scratch reg things) |
||
36 | * - Vblank : look at Jesse's rework and what we should do |
||
37 | * - r600/r700: gart & cp |
||
38 | * - cs : clean cs ioctl use bitmap & things like that. |
||
39 | * - power management stuff |
||
40 | * - Barrier in gart code |
||
41 | * - Unmappabled vram ? |
||
42 | * - TESTING, TESTING, TESTING |
||
43 | */ |
||
44 | |||
1221 | serge | 45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
||
47 | * reasons even thought we work hard to make it works on most |
||
48 | * configurations. In order to still have a working userspace in such |
||
49 | * situation the init path must succeed up to the memory controller |
||
50 | * initialization point. Failure before this point are considered as |
||
51 | * fatal error. Here is the init callchain : |
||
52 | * radeon_device_init perform common structure, mutex initialization |
||
53 | * asic_init setup the GPU memory layout and perform all |
||
54 | * one time initialization (failure in this |
||
55 | * function are considered fatal) |
||
56 | * asic_startup setup the GPU acceleration, in order to |
||
57 | * follow guideline the first thing this |
||
58 | * function should do is setting the GPU |
||
59 | * memory controller (only MC setup failure |
||
60 | * are considered as fatal) |
||
61 | */ |
||
62 | |||
1321 | serge | 63 | #include |
2997 | Serge | 64 | #include |
1321 | serge | 65 | #include |
66 | #include |
||
2997 | Serge | 67 | #include |
1221 | serge | 68 | |
1321 | serge | 69 | #include |
70 | #include |
||
71 | #include |
||
72 | #include |
||
1221 | serge | 73 | |
2004 | serge | 74 | #include |
1120 | serge | 75 | #include |
1117 | serge | 76 | |
1120 | serge | 77 | #include |
1179 | serge | 78 | |
79 | #include "radeon_family.h" |
||
1117 | serge | 80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
||
82 | |||
83 | #include |
||
84 | |||
1179 | serge | 85 | /* |
86 | * Modules parameters. |
||
87 | */ |
||
88 | extern int radeon_no_wb; |
||
1123 | serge | 89 | extern int radeon_modeset; |
1117 | serge | 90 | extern int radeon_dynclks; |
1123 | serge | 91 | extern int radeon_r4xx_atom; |
1128 | serge | 92 | extern int radeon_agpmode; |
93 | extern int radeon_vram_limit; |
||
1117 | serge | 94 | extern int radeon_gart_size; |
1128 | serge | 95 | extern int radeon_benchmarking; |
1179 | serge | 96 | extern int radeon_testing; |
1123 | serge | 97 | extern int radeon_connector_table; |
1179 | serge | 98 | extern int radeon_tv; |
1403 | serge | 99 | extern int radeon_audio; |
1963 | serge | 100 | extern int radeon_disp_priority; |
101 | extern int radeon_hw_i2c; |
||
102 | extern int radeon_pcie_gen2; |
||
2997 | Serge | 103 | extern int radeon_msi; |
104 | extern int radeon_lockup_timeout; |
||
105 | |||
106 | |||
107 | |||
1430 | serge | 108 | typedef struct pm_message { |
109 | int event; |
||
110 | } pm_message_t; |
||
111 | |||
1233 | serge | 112 | typedef struct |
113 | { |
||
114 | int width; |
||
115 | int height; |
||
116 | int bpp; |
||
117 | int freq; |
||
1321 | serge | 118 | }videomode_t; |
1179 | serge | 119 | |
120 | |||
121 | |||
1963 | serge | 122 | static inline u32 ioread32(const volatile void __iomem *addr) |
123 | { |
||
124 | return in32((u32)addr); |
||
125 | } |
||
126 | |||
127 | static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
||
128 | { |
||
129 | out32((u32)addr, b); |
||
130 | } |
||
131 | |||
2997 | Serge | 132 | //struct __wait_queue_head { |
133 | // spinlock_t lock; |
||
134 | // struct list_head task_list; |
||
135 | //}; |
||
136 | //typedef struct __wait_queue_head wait_queue_head_t; |
||
1963 | serge | 137 | |
138 | |||
1117 | serge | 139 | /* |
140 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
||
141 | * symbol; |
||
142 | */ |
||
1120 | serge | 143 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1963 | serge | 144 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
1428 | serge | 145 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
1120 | serge | 146 | #define RADEON_IB_POOL_SIZE 16 |
2997 | Serge | 147 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
1120 | serge | 148 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 149 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 150 | |
2997 | Serge | 151 | /* max number of rings */ |
152 | #define RADEON_NUM_RINGS 3 |
||
153 | |||
154 | /* fence seq are set to this number when signaled */ |
||
155 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
||
156 | |||
157 | /* internal ring indices */ |
||
158 | /* r1xx+ has gfx CP ring */ |
||
159 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
||
160 | |||
161 | /* cayman has 2 compute CP rings */ |
||
162 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
||
163 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
||
164 | |||
165 | /* hardcode those limit for now */ |
||
166 | #define RADEON_VA_IB_OFFSET (1 << 20) |
||
167 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
||
168 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
||
169 | |||
1117 | serge | 170 | /* |
171 | * Errata workarounds. |
||
172 | */ |
||
173 | enum radeon_pll_errata { |
||
174 | CHIP_ERRATA_R300_CG = 0x00000001, |
||
175 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
||
176 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
||
177 | }; |
||
178 | |||
179 | |||
180 | struct radeon_device; |
||
181 | |||
182 | |||
183 | /* |
||
184 | * BIOS. |
||
185 | */ |
||
186 | bool radeon_get_bios(struct radeon_device *rdev); |
||
187 | |||
188 | /* |
||
1179 | serge | 189 | * Dummy page |
190 | */ |
||
191 | struct radeon_dummy_page { |
||
192 | struct page *page; |
||
193 | dma_addr_t addr; |
||
194 | }; |
||
195 | int radeon_dummy_page_init(struct radeon_device *rdev); |
||
196 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
||
197 | |||
198 | |||
199 | /* |
||
1117 | serge | 200 | * Clocks |
201 | */ |
||
202 | struct radeon_clock { |
||
203 | struct radeon_pll p1pll; |
||
204 | struct radeon_pll p2pll; |
||
1430 | serge | 205 | struct radeon_pll dcpll; |
1117 | serge | 206 | struct radeon_pll spll; |
207 | struct radeon_pll mpll; |
||
208 | /* 10 Khz units */ |
||
209 | uint32_t default_mclk; |
||
210 | uint32_t default_sclk; |
||
1430 | serge | 211 | uint32_t default_dispclk; |
212 | uint32_t dp_extclk; |
||
1963 | serge | 213 | uint32_t max_pixel_clock; |
1117 | serge | 214 | }; |
215 | |||
1268 | serge | 216 | /* |
217 | * Power management |
||
218 | */ |
||
219 | int radeon_pm_init(struct radeon_device *rdev); |
||
1963 | serge | 220 | void radeon_pm_fini(struct radeon_device *rdev); |
1430 | serge | 221 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
1963 | serge | 222 | void radeon_pm_suspend(struct radeon_device *rdev); |
223 | void radeon_pm_resume(struct radeon_device *rdev); |
||
1430 | serge | 224 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
225 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
||
1963 | serge | 226 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
227 | void rs690_pm_info(struct radeon_device *rdev); |
||
228 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
||
229 | extern int rv770_get_temp(struct radeon_device *rdev); |
||
230 | extern int evergreen_get_temp(struct radeon_device *rdev); |
||
231 | extern int sumo_get_temp(struct radeon_device *rdev); |
||
2997 | Serge | 232 | extern int si_get_temp(struct radeon_device *rdev); |
233 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
||
234 | unsigned *bankh, unsigned *mtaspect, |
||
235 | unsigned *tile_split); |
||
1179 | serge | 236 | |
1117 | serge | 237 | /* |
238 | * Fences. |
||
239 | */ |
||
240 | struct radeon_fence_driver { |
||
241 | uint32_t scratch_reg; |
||
2997 | Serge | 242 | uint64_t gpu_addr; |
243 | volatile uint32_t *cpu_addr; |
||
244 | /* sync_seq is protected by ring emission lock */ |
||
245 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
||
246 | atomic64_t last_seq; |
||
247 | unsigned long last_activity; |
||
1403 | serge | 248 | bool initialized; |
1117 | serge | 249 | }; |
250 | |||
251 | struct radeon_fence { |
||
2997 | Serge | 252 | struct radeon_device *rdev; |
253 | struct kref kref; |
||
1117 | serge | 254 | /* protected by radeon_fence.lock */ |
2997 | Serge | 255 | uint64_t seq; |
256 | /* RB, DMA, etc. */ |
||
257 | unsigned ring; |
||
1117 | serge | 258 | }; |
259 | |||
2997 | Serge | 260 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
1117 | serge | 261 | int radeon_fence_driver_init(struct radeon_device *rdev); |
262 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
||
2997 | Serge | 263 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
264 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
||
1117 | serge | 265 | bool radeon_fence_signaled(struct radeon_fence *fence); |
266 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
||
2997 | Serge | 267 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
268 | void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
||
269 | int radeon_fence_wait_any(struct radeon_device *rdev, |
||
270 | struct radeon_fence **fences, |
||
271 | bool intr); |
||
1117 | serge | 272 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
273 | void radeon_fence_unref(struct radeon_fence **fence); |
||
2997 | Serge | 274 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
275 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
||
276 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
||
277 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
||
278 | struct radeon_fence *b) |
||
279 | { |
||
280 | if (!a) { |
||
281 | return b; |
||
282 | } |
||
1117 | serge | 283 | |
2997 | Serge | 284 | if (!b) { |
285 | return a; |
||
286 | } |
||
287 | |||
288 | BUG_ON(a->ring != b->ring); |
||
289 | |||
290 | if (a->seq > b->seq) { |
||
291 | return a; |
||
292 | } else { |
||
293 | return b; |
||
294 | } |
||
295 | } |
||
296 | |||
297 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
||
298 | struct radeon_fence *b) |
||
299 | { |
||
300 | if (!a) { |
||
301 | return false; |
||
302 | } |
||
303 | |||
304 | if (!b) { |
||
305 | return true; |
||
306 | } |
||
307 | |||
308 | BUG_ON(a->ring != b->ring); |
||
309 | |||
310 | return a->seq < b->seq; |
||
311 | } |
||
312 | |||
1179 | serge | 313 | /* |
314 | * Tiling registers |
||
315 | */ |
||
316 | struct radeon_surface_reg { |
||
1321 | serge | 317 | struct radeon_bo *bo; |
1179 | serge | 318 | }; |
1117 | serge | 319 | |
1179 | serge | 320 | #define RADEON_GEM_MAX_SURFACES 8 |
321 | |||
1117 | serge | 322 | /* |
1321 | serge | 323 | * TTM. |
1117 | serge | 324 | */ |
1321 | serge | 325 | struct radeon_mman { |
326 | struct ttm_bo_global_ref bo_global_ref; |
||
1963 | serge | 327 | // struct drm_global_reference mem_global_ref; |
1403 | serge | 328 | struct ttm_bo_device bdev; |
1321 | serge | 329 | bool mem_global_referenced; |
1403 | serge | 330 | bool initialized; |
1321 | serge | 331 | }; |
1117 | serge | 332 | |
2997 | Serge | 333 | /* bo virtual address in a specific vm */ |
334 | struct radeon_bo_va { |
||
335 | /* protected by bo being reserved */ |
||
336 | struct list_head bo_list; |
||
337 | uint64_t soffset; |
||
338 | uint64_t eoffset; |
||
339 | uint32_t flags; |
||
340 | bool valid; |
||
341 | unsigned ref_count; |
||
342 | |||
343 | /* protected by vm mutex */ |
||
344 | struct list_head vm_list; |
||
345 | |||
346 | /* constant after initialization */ |
||
347 | struct radeon_vm *vm; |
||
348 | struct radeon_bo *bo; |
||
349 | }; |
||
350 | |||
1321 | serge | 351 | struct radeon_bo { |
352 | /* Protected by gem.mutex */ |
||
353 | struct list_head list; |
||
354 | /* Protected by tbo.reserved */ |
||
355 | u32 placements[3]; |
||
356 | struct ttm_placement placement; |
||
357 | struct ttm_buffer_object tbo; |
||
358 | struct ttm_bo_kmap_obj kmap; |
||
1404 | serge | 359 | unsigned pin_count; |
360 | void *kptr; |
||
2007 | serge | 361 | void *uptr; |
1404 | serge | 362 | u32 cpu_addr; |
363 | u32 tiling_flags; |
||
364 | u32 pitch; |
||
365 | int surface_reg; |
||
2997 | Serge | 366 | /* list of all virtual address to which this bo |
367 | * is associated to |
||
368 | */ |
||
369 | struct list_head va; |
||
1321 | serge | 370 | /* Constant after initialization */ |
371 | struct radeon_device *rdev; |
||
1963 | serge | 372 | struct drm_gem_object gem_base; |
3120 | serge | 373 | |
1404 | serge | 374 | u32 domain; |
2997 | Serge | 375 | int vmapping_count; |
1321 | serge | 376 | }; |
1963 | serge | 377 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
1321 | serge | 378 | |
379 | struct radeon_bo_list { |
||
380 | struct radeon_bo *bo; |
||
1117 | serge | 381 | uint64_t gpu_offset; |
382 | unsigned rdomain; |
||
383 | unsigned wdomain; |
||
1321 | serge | 384 | u32 tiling_flags; |
1117 | serge | 385 | }; |
386 | |||
2997 | Serge | 387 | /* sub-allocation manager, it has to be protected by another lock. |
388 | * By conception this is an helper for other part of the driver |
||
389 | * like the indirect buffer or semaphore, which both have their |
||
390 | * locking. |
||
391 | * |
||
392 | * Principe is simple, we keep a list of sub allocation in offset |
||
393 | * order (first entry has offset == 0, last entry has the highest |
||
394 | * offset). |
||
395 | * |
||
396 | * When allocating new object we first check if there is room at |
||
397 | * the end total_size - (last_object_offset + last_object_size) >= |
||
398 | * alloc_size. If so we allocate new object there. |
||
399 | * |
||
400 | * When there is not enough room at the end, we start waiting for |
||
401 | * each sub object until we reach object_offset+object_size >= |
||
402 | * alloc_size, this object then become the sub object we return. |
||
403 | * |
||
404 | * Alignment can't be bigger than page size. |
||
405 | * |
||
406 | * Hole are not considered for allocation to keep things simple. |
||
407 | * Assumption is that there won't be hole (all object on same |
||
408 | * alignment). |
||
409 | */ |
||
410 | struct radeon_sa_manager { |
||
411 | wait_queue_head_t wq; |
||
412 | struct radeon_bo *bo; |
||
413 | struct list_head *hole; |
||
414 | struct list_head flist[RADEON_NUM_RINGS]; |
||
415 | struct list_head olist; |
||
416 | unsigned size; |
||
417 | uint64_t gpu_addr; |
||
418 | void *cpu_ptr; |
||
419 | uint32_t domain; |
||
420 | }; |
||
421 | |||
422 | struct radeon_sa_bo; |
||
423 | |||
424 | /* sub-allocation buffer */ |
||
425 | struct radeon_sa_bo { |
||
426 | struct list_head olist; |
||
427 | struct list_head flist; |
||
428 | struct radeon_sa_manager *manager; |
||
429 | unsigned soffset; |
||
430 | unsigned eoffset; |
||
431 | struct radeon_fence *fence; |
||
432 | }; |
||
433 | |||
1123 | serge | 434 | /* |
435 | * GEM objects. |
||
436 | */ |
||
437 | struct radeon_gem { |
||
1630 | serge | 438 | struct mutex mutex; |
1123 | serge | 439 | struct list_head objects; |
440 | }; |
||
1117 | serge | 441 | |
1126 | serge | 442 | int radeon_gem_init(struct radeon_device *rdev); |
443 | void radeon_gem_fini(struct radeon_device *rdev); |
||
444 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
||
445 | int alignment, int initial_domain, |
||
446 | bool discardable, bool kernel, |
||
447 | struct drm_gem_object **obj); |
||
1117 | serge | 448 | |
2004 | serge | 449 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
450 | struct drm_device *dev, |
||
451 | struct drm_mode_create_dumb *args); |
||
452 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
||
453 | struct drm_device *dev, |
||
454 | uint32_t handle, uint64_t *offset_p); |
||
455 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
||
456 | struct drm_device *dev, |
||
457 | uint32_t handle); |
||
1117 | serge | 458 | |
459 | /* |
||
2997 | Serge | 460 | * Semaphores. |
1117 | serge | 461 | */ |
2997 | Serge | 462 | /* everything here is constant */ |
463 | struct radeon_semaphore { |
||
464 | struct radeon_sa_bo *sa_bo; |
||
465 | signed waiters; |
||
466 | uint64_t gpu_addr; |
||
1117 | serge | 467 | }; |
468 | |||
2997 | Serge | 469 | int radeon_semaphore_create(struct radeon_device *rdev, |
470 | struct radeon_semaphore **semaphore); |
||
471 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
||
472 | struct radeon_semaphore *semaphore); |
||
473 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
||
474 | struct radeon_semaphore *semaphore); |
||
475 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
||
476 | struct radeon_semaphore *semaphore, |
||
477 | int signaler, int waiter); |
||
478 | void radeon_semaphore_free(struct radeon_device *rdev, |
||
479 | struct radeon_semaphore **semaphore, |
||
480 | struct radeon_fence *fence); |
||
1117 | serge | 481 | |
2997 | Serge | 482 | /* |
483 | * GART structures, functions & helpers |
||
484 | */ |
||
485 | struct radeon_mc; |
||
1117 | serge | 486 | |
1268 | serge | 487 | #define RADEON_GPU_PAGE_SIZE 4096 |
1430 | serge | 488 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
2997 | Serge | 489 | #define RADEON_GPU_PAGE_SHIFT 12 |
490 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
||
1268 | serge | 491 | |
1117 | serge | 492 | struct radeon_gart { |
493 | dma_addr_t table_addr; |
||
2997 | Serge | 494 | struct radeon_bo *robj; |
495 | void *ptr; |
||
1117 | serge | 496 | unsigned num_gpu_pages; |
497 | unsigned num_cpu_pages; |
||
498 | unsigned table_size; |
||
499 | struct page **pages; |
||
500 | dma_addr_t *pages_addr; |
||
501 | bool ready; |
||
502 | }; |
||
503 | |||
504 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
||
505 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
||
506 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
||
507 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
||
2997 | Serge | 508 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
509 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
||
1117 | serge | 510 | int radeon_gart_init(struct radeon_device *rdev); |
511 | void radeon_gart_fini(struct radeon_device *rdev); |
||
512 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
||
513 | int pages); |
||
1120 | serge | 514 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
2997 | Serge | 515 | int pages, u32 *pagelist, |
516 | dma_addr_t *dma_addr); |
||
517 | void radeon_gart_restore(struct radeon_device *rdev); |
||
1117 | serge | 518 | |
519 | |||
520 | /* |
||
521 | * GPU MC structures, functions & helpers |
||
522 | */ |
||
523 | struct radeon_mc { |
||
524 | resource_size_t aper_size; |
||
525 | resource_size_t aper_base; |
||
526 | resource_size_t agp_base; |
||
1179 | serge | 527 | /* for some chips with <= 32MB we need to lie |
528 | * about vram size near mc fb location */ |
||
529 | u64 mc_vram_size; |
||
1430 | serge | 530 | u64 visible_vram_size; |
1179 | serge | 531 | u64 gtt_size; |
532 | u64 gtt_start; |
||
533 | u64 gtt_end; |
||
534 | u64 vram_start; |
||
535 | u64 vram_end; |
||
1117 | serge | 536 | unsigned vram_width; |
1179 | serge | 537 | u64 real_vram_size; |
1117 | serge | 538 | int vram_mtrr; |
539 | bool vram_is_ddr; |
||
1403 | serge | 540 | bool igp_sideport_enabled; |
1963 | serge | 541 | u64 gtt_base_align; |
1117 | serge | 542 | }; |
543 | |||
1403 | serge | 544 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
545 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
||
1117 | serge | 546 | |
547 | /* |
||
548 | * GPU scratch registers structures, functions & helpers |
||
549 | */ |
||
550 | struct radeon_scratch { |
||
551 | unsigned num_reg; |
||
1963 | serge | 552 | uint32_t reg_base; |
1117 | serge | 553 | bool free[32]; |
554 | uint32_t reg[32]; |
||
555 | }; |
||
556 | |||
557 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
||
558 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
||
559 | |||
560 | |||
561 | /* |
||
562 | * IRQS. |
||
563 | */ |
||
1963 | serge | 564 | struct r500_irq_stat_regs { |
565 | u32 disp_int; |
||
2997 | Serge | 566 | u32 hdmi0_status; |
1963 | serge | 567 | }; |
568 | |||
569 | struct r600_irq_stat_regs { |
||
570 | u32 disp_int; |
||
571 | u32 disp_int_cont; |
||
572 | u32 disp_int_cont2; |
||
573 | u32 d1grph_int; |
||
574 | u32 d2grph_int; |
||
2997 | Serge | 575 | u32 hdmi0_status; |
576 | u32 hdmi1_status; |
||
1963 | serge | 577 | }; |
578 | |||
579 | struct evergreen_irq_stat_regs { |
||
580 | u32 disp_int; |
||
581 | u32 disp_int_cont; |
||
582 | u32 disp_int_cont2; |
||
583 | u32 disp_int_cont3; |
||
584 | u32 disp_int_cont4; |
||
585 | u32 disp_int_cont5; |
||
586 | u32 d1grph_int; |
||
587 | u32 d2grph_int; |
||
588 | u32 d3grph_int; |
||
589 | u32 d4grph_int; |
||
590 | u32 d5grph_int; |
||
591 | u32 d6grph_int; |
||
2997 | Serge | 592 | u32 afmt_status1; |
593 | u32 afmt_status2; |
||
594 | u32 afmt_status3; |
||
595 | u32 afmt_status4; |
||
596 | u32 afmt_status5; |
||
597 | u32 afmt_status6; |
||
1963 | serge | 598 | }; |
599 | |||
600 | union radeon_irq_stat_regs { |
||
601 | struct r500_irq_stat_regs r500; |
||
602 | struct r600_irq_stat_regs r600; |
||
603 | struct evergreen_irq_stat_regs evergreen; |
||
604 | }; |
||
605 | |||
2997 | Serge | 606 | #define RADEON_MAX_HPD_PINS 6 |
607 | #define RADEON_MAX_CRTCS 6 |
||
608 | #define RADEON_MAX_AFMT_BLOCKS 6 |
||
609 | |||
1117 | serge | 610 | struct radeon_irq { |
611 | bool installed; |
||
2997 | Serge | 612 | spinlock_t lock; |
613 | atomic_t ring_int[RADEON_NUM_RINGS]; |
||
614 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
||
615 | atomic_t pflip[RADEON_MAX_CRTCS]; |
||
1963 | serge | 616 | wait_queue_head_t vblank_queue; |
2997 | Serge | 617 | bool hpd[RADEON_MAX_HPD_PINS]; |
618 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
||
1963 | serge | 619 | union radeon_irq_stat_regs stat_regs; |
1117 | serge | 620 | }; |
621 | |||
622 | int radeon_irq_kms_init(struct radeon_device *rdev); |
||
623 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
||
2997 | Serge | 624 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
625 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
||
2004 | serge | 626 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
627 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 628 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
629 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
||
630 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
631 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
1117 | serge | 632 | |
633 | /* |
||
2997 | Serge | 634 | * CP & rings. |
1117 | serge | 635 | */ |
2997 | Serge | 636 | |
1117 | serge | 637 | struct radeon_ib { |
2997 | Serge | 638 | struct radeon_sa_bo *sa_bo; |
639 | uint32_t length_dw; |
||
1403 | serge | 640 | uint64_t gpu_addr; |
2997 | Serge | 641 | uint32_t *ptr; |
642 | int ring; |
||
1117 | serge | 643 | struct radeon_fence *fence; |
2997 | Serge | 644 | struct radeon_vm *vm; |
645 | bool is_const_ib; |
||
646 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
||
647 | struct radeon_semaphore *semaphore; |
||
1117 | serge | 648 | }; |
649 | |||
2997 | Serge | 650 | struct radeon_ring { |
1321 | serge | 651 | struct radeon_bo *ring_obj; |
1117 | serge | 652 | volatile uint32_t *ring; |
1403 | serge | 653 | unsigned rptr; |
2997 | Serge | 654 | unsigned rptr_offs; |
655 | unsigned rptr_reg; |
||
656 | unsigned rptr_save_reg; |
||
657 | u64 next_rptr_gpu_addr; |
||
658 | volatile u32 *next_rptr_cpu_addr; |
||
1403 | serge | 659 | unsigned wptr; |
660 | unsigned wptr_old; |
||
2997 | Serge | 661 | unsigned wptr_reg; |
1403 | serge | 662 | unsigned ring_size; |
663 | unsigned ring_free_dw; |
||
664 | int count_dw; |
||
2997 | Serge | 665 | unsigned long last_activity; |
666 | unsigned last_rptr; |
||
1403 | serge | 667 | uint64_t gpu_addr; |
668 | uint32_t align_mask; |
||
669 | uint32_t ptr_mask; |
||
670 | bool ready; |
||
2997 | Serge | 671 | u32 ptr_reg_shift; |
672 | u32 ptr_reg_mask; |
||
673 | u32 nop; |
||
674 | u32 idx; |
||
1117 | serge | 675 | }; |
676 | |||
1321 | serge | 677 | /* |
2997 | Serge | 678 | * VM |
679 | */ |
||
680 | |||
681 | /* maximum number of VMIDs */ |
||
682 | #define RADEON_NUM_VM 16 |
||
683 | |||
684 | /* defines number of bits in page table versus page directory, |
||
685 | * a page is 4KB so we have 12 bits offset, 9 bits in the page |
||
686 | * table and the remaining 19 bits are in the page directory */ |
||
687 | #define RADEON_VM_BLOCK_SIZE 9 |
||
688 | |||
689 | /* number of entries in page table */ |
||
690 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) |
||
691 | |||
692 | struct radeon_vm { |
||
693 | struct list_head list; |
||
694 | struct list_head va; |
||
695 | unsigned id; |
||
696 | |||
697 | /* contains the page directory */ |
||
698 | struct radeon_sa_bo *page_directory; |
||
699 | uint64_t pd_gpu_addr; |
||
700 | |||
701 | /* array of page tables, one for each page directory entry */ |
||
702 | struct radeon_sa_bo **page_tables; |
||
703 | |||
704 | struct mutex mutex; |
||
705 | /* last fence for cs using this vm */ |
||
706 | struct radeon_fence *fence; |
||
707 | /* last flush or NULL if we still need to flush */ |
||
708 | struct radeon_fence *last_flush; |
||
709 | }; |
||
710 | |||
711 | struct radeon_vm_manager { |
||
712 | struct mutex lock; |
||
713 | struct list_head lru_vm; |
||
714 | struct radeon_fence *active[RADEON_NUM_VM]; |
||
715 | struct radeon_sa_manager sa_manager; |
||
716 | uint32_t max_pfn; |
||
717 | /* number of VMIDs */ |
||
718 | unsigned nvm; |
||
719 | /* vram base address for page table entry */ |
||
720 | u64 vram_base_offset; |
||
721 | /* is vm enabled? */ |
||
722 | bool enabled; |
||
723 | }; |
||
724 | |||
725 | /* |
||
726 | * file private structure |
||
727 | */ |
||
728 | struct radeon_fpriv { |
||
729 | struct radeon_vm vm; |
||
730 | }; |
||
731 | |||
732 | /* |
||
1321 | serge | 733 | * R6xx+ IH ring |
734 | */ |
||
735 | struct r600_ih { |
||
736 | struct radeon_bo *ring_obj; |
||
737 | volatile uint32_t *ring; |
||
738 | unsigned rptr; |
||
739 | unsigned ring_size; |
||
740 | uint64_t gpu_addr; |
||
741 | uint32_t ptr_mask; |
||
2997 | Serge | 742 | atomic_t lock; |
1321 | serge | 743 | bool enabled; |
744 | }; |
||
745 | |||
2997 | Serge | 746 | struct r600_blit_cp_primitives { |
747 | void (*set_render_target)(struct radeon_device *rdev, int format, |
||
748 | int w, int h, u64 gpu_addr); |
||
749 | void (*cp_set_surface_sync)(struct radeon_device *rdev, |
||
750 | u32 sync_type, u32 size, |
||
751 | u64 mc_addr); |
||
752 | void (*set_shaders)(struct radeon_device *rdev); |
||
753 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); |
||
754 | void (*set_tex_resource)(struct radeon_device *rdev, |
||
755 | int format, int w, int h, int pitch, |
||
756 | u64 gpu_addr, u32 size); |
||
757 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
||
758 | int x2, int y2); |
||
759 | void (*draw_auto)(struct radeon_device *rdev); |
||
760 | void (*set_default_state)(struct radeon_device *rdev); |
||
761 | }; |
||
762 | |||
1179 | serge | 763 | struct r600_blit { |
1321 | serge | 764 | struct radeon_bo *shader_obj; |
2997 | Serge | 765 | struct r600_blit_cp_primitives primitives; |
766 | int max_dim; |
||
767 | int ring_size_common; |
||
768 | int ring_size_per_loop; |
||
1179 | serge | 769 | u64 shader_gpu_addr; |
770 | u32 vs_offset, ps_offset; |
||
771 | u32 state_offset; |
||
772 | u32 state_len; |
||
773 | }; |
||
774 | |||
2997 | Serge | 775 | /* |
776 | * SI RLC stuff |
||
777 | */ |
||
778 | struct si_rlc { |
||
779 | /* for power gating */ |
||
780 | struct radeon_bo *save_restore_obj; |
||
781 | uint64_t save_restore_gpu_addr; |
||
782 | /* for clear state */ |
||
783 | struct radeon_bo *clear_state_obj; |
||
784 | uint64_t clear_state_gpu_addr; |
||
785 | }; |
||
786 | |||
787 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
||
788 | struct radeon_ib *ib, struct radeon_vm *vm, |
||
789 | unsigned size); |
||
790 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
||
791 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
||
792 | struct radeon_ib *const_ib); |
||
1117 | serge | 793 | int radeon_ib_pool_init(struct radeon_device *rdev); |
794 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
||
2997 | Serge | 795 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1117 | serge | 796 | /* Ring access between begin & end cannot sleep */ |
2997 | Serge | 797 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
798 | struct radeon_ring *ring); |
||
799 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
||
800 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
801 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
802 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
803 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
804 | void radeon_ring_undo(struct radeon_ring *ring); |
||
805 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
||
806 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
||
807 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
||
808 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
||
809 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
||
810 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
||
811 | uint32_t **data); |
||
812 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
||
813 | unsigned size, uint32_t *data); |
||
814 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
||
815 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
||
816 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); |
||
817 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1117 | serge | 818 | |
819 | |||
820 | /* |
||
821 | * CS. |
||
822 | */ |
||
823 | struct radeon_cs_reloc { |
||
824 | // struct drm_gem_object *gobj; |
||
1321 | serge | 825 | struct radeon_bo *robj; |
1630 | serge | 826 | struct radeon_bo_list lobj; |
1403 | serge | 827 | uint32_t handle; |
828 | uint32_t flags; |
||
1117 | serge | 829 | }; |
830 | |||
831 | struct radeon_cs_chunk { |
||
832 | uint32_t chunk_id; |
||
833 | uint32_t length_dw; |
||
1221 | serge | 834 | int kpage_idx[2]; |
835 | uint32_t *kpage[2]; |
||
1117 | serge | 836 | uint32_t *kdata; |
1221 | serge | 837 | void __user *user_ptr; |
838 | int last_copied_page; |
||
839 | int last_page_index; |
||
1117 | serge | 840 | }; |
841 | |||
842 | struct radeon_cs_parser { |
||
1430 | serge | 843 | struct device *dev; |
1117 | serge | 844 | struct radeon_device *rdev; |
2004 | serge | 845 | struct drm_file *filp; |
1117 | serge | 846 | /* chunks */ |
847 | unsigned nchunks; |
||
848 | struct radeon_cs_chunk *chunks; |
||
849 | uint64_t *chunks_array; |
||
850 | /* IB */ |
||
851 | unsigned idx; |
||
852 | /* relocations */ |
||
853 | unsigned nrelocs; |
||
854 | struct radeon_cs_reloc *relocs; |
||
855 | struct radeon_cs_reloc **relocs_ptr; |
||
1120 | serge | 856 | struct list_head validated; |
1117 | serge | 857 | /* indices of various chunks */ |
858 | int chunk_ib_idx; |
||
859 | int chunk_relocs_idx; |
||
2997 | Serge | 860 | int chunk_flags_idx; |
861 | int chunk_const_ib_idx; |
||
862 | struct radeon_ib ib; |
||
863 | struct radeon_ib const_ib; |
||
1117 | serge | 864 | void *track; |
1179 | serge | 865 | unsigned family; |
1221 | serge | 866 | int parser_error; |
2997 | Serge | 867 | u32 cs_flags; |
868 | u32 ring; |
||
869 | s32 priority; |
||
1117 | serge | 870 | }; |
871 | |||
1221 | serge | 872 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
2997 | Serge | 873 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
1221 | serge | 874 | |
1117 | serge | 875 | struct radeon_cs_packet { |
876 | unsigned idx; |
||
877 | unsigned type; |
||
878 | unsigned reg; |
||
879 | unsigned opcode; |
||
880 | int count; |
||
881 | unsigned one_reg_wr; |
||
882 | }; |
||
883 | |||
884 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
885 | struct radeon_cs_packet *pkt, |
||
886 | unsigned idx, unsigned reg); |
||
887 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
888 | struct radeon_cs_packet *pkt); |
||
889 | |||
890 | |||
891 | /* |
||
892 | * AGP |
||
893 | */ |
||
894 | int radeon_agp_init(struct radeon_device *rdev); |
||
1321 | serge | 895 | void radeon_agp_resume(struct radeon_device *rdev); |
1963 | serge | 896 | void radeon_agp_suspend(struct radeon_device *rdev); |
1117 | serge | 897 | void radeon_agp_fini(struct radeon_device *rdev); |
898 | |||
899 | |||
900 | /* |
||
901 | * Writeback |
||
902 | */ |
||
903 | struct radeon_wb { |
||
1321 | serge | 904 | struct radeon_bo *wb_obj; |
1117 | serge | 905 | volatile uint32_t *wb; |
906 | uint64_t gpu_addr; |
||
1963 | serge | 907 | bool enabled; |
908 | bool use_event; |
||
1117 | serge | 909 | }; |
910 | |||
1963 | serge | 911 | #define RADEON_WB_SCRATCH_OFFSET 0 |
2997 | Serge | 912 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1963 | serge | 913 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
914 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
||
915 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
||
916 | #define R600_WB_IH_WPTR_OFFSET 2048 |
||
917 | #define R600_WB_EVENT_OFFSET 3072 |
||
918 | |||
1179 | serge | 919 | /** |
920 | * struct radeon_pm - power management datas |
||
921 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
922 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
923 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
924 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
925 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
926 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
927 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
928 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
929 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
1963 | serge | 930 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1179 | serge | 931 | * @needed_bandwidth: current bandwidth needs |
932 | * |
||
933 | * It keeps track of various data needed to take powermanagement decision. |
||
1963 | serge | 934 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1179 | serge | 935 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
936 | * (type of memory, bus size, efficiency, ...) |
||
937 | */ |
||
1963 | serge | 938 | |
939 | enum radeon_pm_method { |
||
940 | PM_METHOD_PROFILE, |
||
941 | PM_METHOD_DYNPM, |
||
1430 | serge | 942 | }; |
1963 | serge | 943 | |
944 | enum radeon_dynpm_state { |
||
945 | DYNPM_STATE_DISABLED, |
||
946 | DYNPM_STATE_MINIMUM, |
||
947 | DYNPM_STATE_PAUSED, |
||
948 | DYNPM_STATE_ACTIVE, |
||
949 | DYNPM_STATE_SUSPENDED, |
||
1430 | serge | 950 | }; |
1963 | serge | 951 | enum radeon_dynpm_action { |
952 | DYNPM_ACTION_NONE, |
||
953 | DYNPM_ACTION_MINIMUM, |
||
954 | DYNPM_ACTION_DOWNCLOCK, |
||
955 | DYNPM_ACTION_UPCLOCK, |
||
956 | DYNPM_ACTION_DEFAULT |
||
957 | }; |
||
1430 | serge | 958 | |
959 | enum radeon_voltage_type { |
||
960 | VOLTAGE_NONE = 0, |
||
961 | VOLTAGE_GPIO, |
||
962 | VOLTAGE_VDDC, |
||
963 | VOLTAGE_SW |
||
964 | }; |
||
965 | |||
966 | enum radeon_pm_state_type { |
||
967 | POWER_STATE_TYPE_DEFAULT, |
||
968 | POWER_STATE_TYPE_POWERSAVE, |
||
969 | POWER_STATE_TYPE_BATTERY, |
||
970 | POWER_STATE_TYPE_BALANCED, |
||
971 | POWER_STATE_TYPE_PERFORMANCE, |
||
972 | }; |
||
973 | |||
1963 | serge | 974 | enum radeon_pm_profile_type { |
975 | PM_PROFILE_DEFAULT, |
||
976 | PM_PROFILE_AUTO, |
||
977 | PM_PROFILE_LOW, |
||
978 | PM_PROFILE_MID, |
||
979 | PM_PROFILE_HIGH, |
||
1430 | serge | 980 | }; |
981 | |||
1963 | serge | 982 | #define PM_PROFILE_DEFAULT_IDX 0 |
983 | #define PM_PROFILE_LOW_SH_IDX 1 |
||
984 | #define PM_PROFILE_MID_SH_IDX 2 |
||
985 | #define PM_PROFILE_HIGH_SH_IDX 3 |
||
986 | #define PM_PROFILE_LOW_MH_IDX 4 |
||
987 | #define PM_PROFILE_MID_MH_IDX 5 |
||
988 | #define PM_PROFILE_HIGH_MH_IDX 6 |
||
989 | #define PM_PROFILE_MAX 7 |
||
990 | |||
991 | struct radeon_pm_profile { |
||
992 | int dpms_off_ps_idx; |
||
993 | int dpms_on_ps_idx; |
||
994 | int dpms_off_cm_idx; |
||
995 | int dpms_on_cm_idx; |
||
996 | }; |
||
997 | |||
998 | enum radeon_int_thermal_type { |
||
999 | THERMAL_TYPE_NONE, |
||
1000 | THERMAL_TYPE_RV6XX, |
||
1001 | THERMAL_TYPE_RV770, |
||
1002 | THERMAL_TYPE_EVERGREEN, |
||
1003 | THERMAL_TYPE_SUMO, |
||
1004 | THERMAL_TYPE_NI, |
||
2997 | Serge | 1005 | THERMAL_TYPE_SI, |
1963 | serge | 1006 | }; |
1007 | |||
1430 | serge | 1008 | struct radeon_voltage { |
1009 | enum radeon_voltage_type type; |
||
1010 | /* gpio voltage */ |
||
1011 | struct radeon_gpio_rec gpio; |
||
1012 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
||
1013 | bool active_high; /* voltage drop is active when bit is high */ |
||
1014 | /* VDDC voltage */ |
||
1015 | u8 vddc_id; /* index into vddc voltage table */ |
||
1016 | u8 vddci_id; /* index into vddci voltage table */ |
||
1017 | bool vddci_enabled; |
||
1018 | /* r6xx+ sw */ |
||
1963 | serge | 1019 | u16 voltage; |
1020 | /* evergreen+ vddci */ |
||
1021 | u16 vddci; |
||
1430 | serge | 1022 | }; |
1023 | |||
1963 | serge | 1024 | /* clock mode flags */ |
1025 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
||
1430 | serge | 1026 | |
1027 | struct radeon_pm_clock_info { |
||
1028 | /* memory clock */ |
||
1029 | u32 mclk; |
||
1030 | /* engine clock */ |
||
1031 | u32 sclk; |
||
1032 | /* voltage info */ |
||
1033 | struct radeon_voltage voltage; |
||
1963 | serge | 1034 | /* standardized clock flags */ |
1430 | serge | 1035 | u32 flags; |
1036 | }; |
||
1037 | |||
1963 | serge | 1038 | /* state flags */ |
1039 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
||
1040 | |||
1430 | serge | 1041 | struct radeon_power_state { |
1042 | enum radeon_pm_state_type type; |
||
2997 | Serge | 1043 | struct radeon_pm_clock_info *clock_info; |
1430 | serge | 1044 | /* number of valid clock modes in this power state */ |
1045 | int num_clock_modes; |
||
1046 | struct radeon_pm_clock_info *default_clock_mode; |
||
1963 | serge | 1047 | /* standardized state flags */ |
1048 | u32 flags; |
||
1049 | u32 misc; /* vbios specific flags */ |
||
1050 | u32 misc2; /* vbios specific flags */ |
||
1051 | int pcie_lanes; /* pcie lanes */ |
||
1430 | serge | 1052 | }; |
1053 | |||
1054 | /* |
||
1055 | * Some modes are overclocked by very low value, accept them |
||
1056 | */ |
||
1057 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
||
1058 | |||
1179 | serge | 1059 | struct radeon_pm { |
1630 | serge | 1060 | struct mutex mutex; |
2997 | Serge | 1061 | /* write locked while reprogramming mclk */ |
1062 | struct rw_semaphore mclk_lock; |
||
1963 | serge | 1063 | u32 active_crtcs; |
1064 | int active_crtc_count; |
||
1430 | serge | 1065 | int req_vblank; |
1963 | serge | 1066 | bool vblank_sync; |
1179 | serge | 1067 | fixed20_12 max_bandwidth; |
1068 | fixed20_12 igp_sideport_mclk; |
||
1069 | fixed20_12 igp_system_mclk; |
||
1070 | fixed20_12 igp_ht_link_clk; |
||
1071 | fixed20_12 igp_ht_link_width; |
||
1072 | fixed20_12 k8_bandwidth; |
||
1073 | fixed20_12 sideport_bandwidth; |
||
1074 | fixed20_12 ht_bandwidth; |
||
1075 | fixed20_12 core_bandwidth; |
||
1076 | fixed20_12 sclk; |
||
1963 | serge | 1077 | fixed20_12 mclk; |
1179 | serge | 1078 | fixed20_12 needed_bandwidth; |
1963 | serge | 1079 | struct radeon_power_state *power_state; |
1430 | serge | 1080 | /* number of valid power states */ |
1081 | int num_power_states; |
||
1963 | serge | 1082 | int current_power_state_index; |
1083 | int current_clock_mode_index; |
||
1084 | int requested_power_state_index; |
||
1085 | int requested_clock_mode_index; |
||
1086 | int default_power_state_index; |
||
1087 | u32 current_sclk; |
||
1088 | u32 current_mclk; |
||
1089 | u16 current_vddc; |
||
1090 | u16 current_vddci; |
||
1091 | u32 default_sclk; |
||
1092 | u32 default_mclk; |
||
1093 | u16 default_vddc; |
||
1094 | u16 default_vddci; |
||
1095 | struct radeon_i2c_chan *i2c_bus; |
||
1096 | /* selected pm method */ |
||
1097 | enum radeon_pm_method pm_method; |
||
1098 | /* dynpm power management */ |
||
1099 | // struct delayed_work dynpm_idle_work; |
||
1100 | enum radeon_dynpm_state dynpm_state; |
||
1101 | enum radeon_dynpm_action dynpm_planned_action; |
||
1102 | unsigned long dynpm_action_timeout; |
||
1103 | bool dynpm_can_upclock; |
||
1104 | bool dynpm_can_downclock; |
||
1105 | /* profile-based power management */ |
||
1106 | enum radeon_pm_profile_type profile; |
||
1107 | int profile_index; |
||
1108 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
||
1109 | /* internal thermal controller on rv6xx+ */ |
||
1110 | enum radeon_int_thermal_type int_thermal_type; |
||
1111 | struct device *int_hwmon_dev; |
||
1179 | serge | 1112 | }; |
1117 | serge | 1113 | |
2997 | Serge | 1114 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1115 | enum radeon_pm_state_type ps_type, |
||
1116 | int instance); |
||
1117 | |||
1118 | struct r600_audio { |
||
1119 | int channels; |
||
1120 | int rate; |
||
1121 | int bits_per_sample; |
||
1122 | u8 status_bits; |
||
1123 | u8 category_code; |
||
1124 | }; |
||
1117 | serge | 1125 | /* |
1126 | * ASIC specific functions. |
||
1127 | */ |
||
1128 | struct radeon_asic { |
||
1129 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 1130 | void (*fini)(struct radeon_device *rdev); |
1131 | int (*resume)(struct radeon_device *rdev); |
||
1132 | int (*suspend)(struct radeon_device *rdev); |
||
1133 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1963 | serge | 1134 | int (*asic_reset)(struct radeon_device *rdev); |
2997 | Serge | 1135 | /* ioctl hw specific callback. Some hw might want to perform special |
1136 | * operation on specific ioctl. For instance on wait idle some hw |
||
1137 | * might want to perform and HDP flush through MMIO as it seems that |
||
1138 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
||
1139 | * through ring. |
||
1140 | */ |
||
1141 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
||
1142 | /* check if 3D engine is idle */ |
||
1143 | bool (*gui_idle)(struct radeon_device *rdev); |
||
1144 | /* wait for mc_idle */ |
||
1145 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
||
1146 | /* gart */ |
||
1147 | struct { |
||
1148 | void (*tlb_flush)(struct radeon_device *rdev); |
||
1149 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
1150 | } gart; |
||
1151 | struct { |
||
1152 | int (*init)(struct radeon_device *rdev); |
||
1153 | void (*fini)(struct radeon_device *rdev); |
||
1154 | |||
1155 | u32 pt_ring_index; |
||
1156 | void (*set_page)(struct radeon_device *rdev, uint64_t pe, |
||
1157 | uint64_t addr, unsigned count, |
||
1158 | uint32_t incr, uint32_t flags); |
||
1159 | } vm; |
||
1160 | /* ring specific callbacks */ |
||
1161 | struct { |
||
1162 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1163 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1164 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
||
1165 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
||
1166 | struct radeon_semaphore *semaphore, bool emit_wait); |
||
1167 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
1168 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1169 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1170 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1171 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1172 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
||
1173 | } ring[RADEON_NUM_RINGS]; |
||
1174 | /* irqs */ |
||
1175 | struct { |
||
1176 | int (*set)(struct radeon_device *rdev); |
||
1177 | int (*process)(struct radeon_device *rdev); |
||
1178 | } irq; |
||
1179 | /* displays */ |
||
1180 | struct { |
||
1181 | /* display watermarks */ |
||
1182 | void (*bandwidth_update)(struct radeon_device *rdev); |
||
1183 | /* get frame count */ |
||
1179 | serge | 1184 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
2997 | Serge | 1185 | /* wait for vblank */ |
1186 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
||
1187 | /* set backlight level */ |
||
1188 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
||
1189 | /* get backlight level */ |
||
1190 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
||
1191 | } display; |
||
1192 | /* copy functions for bo handling */ |
||
1193 | struct { |
||
1194 | int (*blit)(struct radeon_device *rdev, |
||
1117 | serge | 1195 | uint64_t src_offset, |
1196 | uint64_t dst_offset, |
||
2997 | Serge | 1197 | unsigned num_gpu_pages, |
1198 | struct radeon_fence **fence); |
||
1199 | u32 blit_ring_index; |
||
1200 | int (*dma)(struct radeon_device *rdev, |
||
1117 | serge | 1201 | uint64_t src_offset, |
1202 | uint64_t dst_offset, |
||
2997 | Serge | 1203 | unsigned num_gpu_pages, |
1204 | struct radeon_fence **fence); |
||
1205 | u32 dma_ring_index; |
||
1206 | /* method used for bo copy */ |
||
1117 | serge | 1207 | int (*copy)(struct radeon_device *rdev, |
1208 | uint64_t src_offset, |
||
1209 | uint64_t dst_offset, |
||
2997 | Serge | 1210 | unsigned num_gpu_pages, |
1211 | struct radeon_fence **fence); |
||
1212 | /* ring used for bo copies */ |
||
1213 | u32 copy_ring_index; |
||
1214 | } copy; |
||
1215 | /* surfaces */ |
||
1216 | struct { |
||
1217 | int (*set_reg)(struct radeon_device *rdev, int reg, |
||
1218 | uint32_t tiling_flags, uint32_t pitch, |
||
1219 | uint32_t offset, uint32_t obj_size); |
||
1220 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
||
1221 | } surface; |
||
1222 | /* hotplug detect */ |
||
1223 | struct { |
||
1224 | void (*init)(struct radeon_device *rdev); |
||
1225 | void (*fini)(struct radeon_device *rdev); |
||
1226 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1227 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1228 | } hpd; |
||
1229 | /* power management */ |
||
1230 | struct { |
||
1231 | void (*misc)(struct radeon_device *rdev); |
||
1232 | void (*prepare)(struct radeon_device *rdev); |
||
1233 | void (*finish)(struct radeon_device *rdev); |
||
1234 | void (*init_profile)(struct radeon_device *rdev); |
||
1235 | void (*get_dynpm_state)(struct radeon_device *rdev); |
||
1268 | serge | 1236 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 1237 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 1238 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 1239 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1430 | serge | 1240 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1117 | serge | 1241 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1242 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
2997 | Serge | 1243 | } pm; |
1963 | serge | 1244 | /* pageflipping */ |
2997 | Serge | 1245 | struct { |
1963 | serge | 1246 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
1247 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
||
1248 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 1249 | } pflip; |
1117 | serge | 1250 | }; |
1251 | |||
1179 | serge | 1252 | /* |
1253 | * Asic structures |
||
1254 | */ |
||
1255 | struct r100_asic { |
||
1256 | const unsigned *reg_safe_bm; |
||
1257 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1258 | u32 hdp_cntl; |
1179 | serge | 1259 | }; |
1260 | |||
1261 | struct r300_asic { |
||
1262 | const unsigned *reg_safe_bm; |
||
1263 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1264 | u32 resync_scratch; |
1265 | u32 hdp_cntl; |
||
1179 | serge | 1266 | }; |
1267 | |||
1268 | struct r600_asic { |
||
1269 | unsigned max_pipes; |
||
1270 | unsigned max_tile_pipes; |
||
1271 | unsigned max_simds; |
||
1272 | unsigned max_backends; |
||
1273 | unsigned max_gprs; |
||
1274 | unsigned max_threads; |
||
1275 | unsigned max_stack_entries; |
||
1276 | unsigned max_hw_contexts; |
||
1277 | unsigned max_gs_threads; |
||
1278 | unsigned sx_max_export_size; |
||
1279 | unsigned sx_max_export_pos_size; |
||
1280 | unsigned sx_max_export_smx_size; |
||
1281 | unsigned sq_num_cf_insts; |
||
1430 | serge | 1282 | unsigned tiling_nbanks; |
1283 | unsigned tiling_npipes; |
||
1284 | unsigned tiling_group_size; |
||
1963 | serge | 1285 | unsigned tile_config; |
2160 | serge | 1286 | unsigned backend_map; |
1179 | serge | 1287 | }; |
1288 | |||
1289 | struct rv770_asic { |
||
1290 | unsigned max_pipes; |
||
1291 | unsigned max_tile_pipes; |
||
1292 | unsigned max_simds; |
||
1293 | unsigned max_backends; |
||
1294 | unsigned max_gprs; |
||
1295 | unsigned max_threads; |
||
1296 | unsigned max_stack_entries; |
||
1297 | unsigned max_hw_contexts; |
||
1298 | unsigned max_gs_threads; |
||
1299 | unsigned sx_max_export_size; |
||
1300 | unsigned sx_max_export_pos_size; |
||
1301 | unsigned sx_max_export_smx_size; |
||
1302 | unsigned sq_num_cf_insts; |
||
1303 | unsigned sx_num_of_sets; |
||
1304 | unsigned sc_prim_fifo_size; |
||
1305 | unsigned sc_hiz_tile_fifo_size; |
||
1306 | unsigned sc_earlyz_tile_fifo_fize; |
||
1430 | serge | 1307 | unsigned tiling_nbanks; |
1308 | unsigned tiling_npipes; |
||
1309 | unsigned tiling_group_size; |
||
1963 | serge | 1310 | unsigned tile_config; |
2160 | serge | 1311 | unsigned backend_map; |
1179 | serge | 1312 | }; |
1313 | |||
1963 | serge | 1314 | struct evergreen_asic { |
1315 | unsigned num_ses; |
||
1316 | unsigned max_pipes; |
||
1317 | unsigned max_tile_pipes; |
||
1318 | unsigned max_simds; |
||
1319 | unsigned max_backends; |
||
1320 | unsigned max_gprs; |
||
1321 | unsigned max_threads; |
||
1322 | unsigned max_stack_entries; |
||
1323 | unsigned max_hw_contexts; |
||
1324 | unsigned max_gs_threads; |
||
1325 | unsigned sx_max_export_size; |
||
1326 | unsigned sx_max_export_pos_size; |
||
1327 | unsigned sx_max_export_smx_size; |
||
1328 | unsigned sq_num_cf_insts; |
||
1329 | unsigned sx_num_of_sets; |
||
1330 | unsigned sc_prim_fifo_size; |
||
1331 | unsigned sc_hiz_tile_fifo_size; |
||
1332 | unsigned sc_earlyz_tile_fifo_size; |
||
1333 | unsigned tiling_nbanks; |
||
1334 | unsigned tiling_npipes; |
||
1335 | unsigned tiling_group_size; |
||
1336 | unsigned tile_config; |
||
2160 | serge | 1337 | unsigned backend_map; |
1963 | serge | 1338 | }; |
1339 | |||
1340 | struct cayman_asic { |
||
1341 | unsigned max_shader_engines; |
||
1342 | unsigned max_pipes_per_simd; |
||
1343 | unsigned max_tile_pipes; |
||
1344 | unsigned max_simds_per_se; |
||
1345 | unsigned max_backends_per_se; |
||
1346 | unsigned max_texture_channel_caches; |
||
1347 | unsigned max_gprs; |
||
1348 | unsigned max_threads; |
||
1349 | unsigned max_gs_threads; |
||
1350 | unsigned max_stack_entries; |
||
1351 | unsigned sx_num_of_sets; |
||
1352 | unsigned sx_max_export_size; |
||
1353 | unsigned sx_max_export_pos_size; |
||
1354 | unsigned sx_max_export_smx_size; |
||
1355 | unsigned max_hw_contexts; |
||
1356 | unsigned sq_num_cf_insts; |
||
1357 | unsigned sc_prim_fifo_size; |
||
1358 | unsigned sc_hiz_tile_fifo_size; |
||
1359 | unsigned sc_earlyz_tile_fifo_size; |
||
1360 | |||
1361 | unsigned num_shader_engines; |
||
1362 | unsigned num_shader_pipes_per_simd; |
||
1363 | unsigned num_tile_pipes; |
||
1364 | unsigned num_simds_per_se; |
||
1365 | unsigned num_backends_per_se; |
||
1366 | unsigned backend_disable_mask_per_asic; |
||
1367 | unsigned backend_map; |
||
1368 | unsigned num_texture_channel_caches; |
||
1369 | unsigned mem_max_burst_length_bytes; |
||
1370 | unsigned mem_row_size_in_kb; |
||
1371 | unsigned shader_engine_tile_size; |
||
1372 | unsigned num_gpus; |
||
1373 | unsigned multi_gpu_tile_size; |
||
1374 | |||
1375 | unsigned tile_config; |
||
1376 | }; |
||
1377 | |||
2997 | Serge | 1378 | struct si_asic { |
1379 | unsigned max_shader_engines; |
||
1380 | unsigned max_tile_pipes; |
||
1381 | unsigned max_cu_per_sh; |
||
1382 | unsigned max_sh_per_se; |
||
1383 | unsigned max_backends_per_se; |
||
1384 | unsigned max_texture_channel_caches; |
||
1385 | unsigned max_gprs; |
||
1386 | unsigned max_gs_threads; |
||
1387 | unsigned max_hw_contexts; |
||
1388 | unsigned sc_prim_fifo_size_frontend; |
||
1389 | unsigned sc_prim_fifo_size_backend; |
||
1390 | unsigned sc_hiz_tile_fifo_size; |
||
1391 | unsigned sc_earlyz_tile_fifo_size; |
||
1392 | |||
1393 | unsigned num_tile_pipes; |
||
1394 | unsigned num_backends_per_se; |
||
1395 | unsigned backend_disable_mask_per_asic; |
||
1396 | unsigned backend_map; |
||
1397 | unsigned num_texture_channel_caches; |
||
1398 | unsigned mem_max_burst_length_bytes; |
||
1399 | unsigned mem_row_size_in_kb; |
||
1400 | unsigned shader_engine_tile_size; |
||
1401 | unsigned num_gpus; |
||
1402 | unsigned multi_gpu_tile_size; |
||
1403 | |||
1404 | unsigned tile_config; |
||
1405 | }; |
||
1406 | |||
1117 | serge | 1407 | union radeon_asic_config { |
1408 | struct r300_asic r300; |
||
1179 | serge | 1409 | struct r100_asic r100; |
1410 | struct r600_asic r600; |
||
1411 | struct rv770_asic rv770; |
||
1963 | serge | 1412 | struct evergreen_asic evergreen; |
1413 | struct cayman_asic cayman; |
||
2997 | Serge | 1414 | struct si_asic si; |
1117 | serge | 1415 | }; |
1416 | |||
1417 | /* |
||
1963 | serge | 1418 | * asic initizalization from radeon_asic.c |
1419 | */ |
||
1420 | void radeon_agp_disable(struct radeon_device *rdev); |
||
1421 | int radeon_asic_init(struct radeon_device *rdev); |
||
1179 | serge | 1422 | |
1423 | |||
1424 | |||
2997 | Serge | 1425 | /* VRAM scratch page for HDP bug, default vram page */ |
1426 | struct r600_vram_scratch { |
||
1963 | serge | 1427 | struct radeon_bo *robj; |
1428 | volatile uint32_t *ptr; |
||
2997 | Serge | 1429 | u64 gpu_addr; |
1963 | serge | 1430 | }; |
1179 | serge | 1431 | |
2997 | Serge | 1432 | |
1117 | serge | 1433 | /* |
1434 | * Core structure, functions and helpers. |
||
1435 | */ |
||
1436 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
1437 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
1438 | |||
1439 | struct radeon_device { |
||
2997 | Serge | 1440 | struct device *dev; |
1117 | serge | 1441 | struct drm_device *ddev; |
1442 | struct pci_dev *pdev; |
||
2997 | Serge | 1443 | struct rw_semaphore exclusive_lock; |
1117 | serge | 1444 | /* ASIC */ |
1445 | union radeon_asic_config config; |
||
1446 | enum radeon_family family; |
||
1447 | unsigned long flags; |
||
1448 | int usec_timeout; |
||
1449 | enum radeon_pll_errata pll_errata; |
||
1450 | int num_gb_pipes; |
||
1413 | serge | 1451 | int num_z_pipes; |
1117 | serge | 1452 | int disp_priority; |
1453 | /* BIOS */ |
||
1454 | uint8_t *bios; |
||
1455 | bool is_atom_bios; |
||
1456 | uint16_t bios_header_start; |
||
1413 | serge | 1457 | struct radeon_bo *stollen_vga_memory; |
1117 | serge | 1458 | /* Register mmio */ |
1963 | serge | 1459 | resource_size_t rmmio_base; |
1460 | resource_size_t rmmio_size; |
||
2997 | Serge | 1461 | void __iomem *rmmio; |
1120 | serge | 1462 | radeon_rreg_t mc_rreg; |
1463 | radeon_wreg_t mc_wreg; |
||
1464 | radeon_rreg_t pll_rreg; |
||
1465 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 1466 | uint32_t pcie_reg_mask; |
1120 | serge | 1467 | radeon_rreg_t pciep_rreg; |
1468 | radeon_wreg_t pciep_wreg; |
||
1963 | serge | 1469 | /* io port */ |
1470 | void __iomem *rio_mem; |
||
1471 | resource_size_t rio_mem_size; |
||
1120 | serge | 1472 | struct radeon_clock clock; |
1117 | serge | 1473 | struct radeon_mc mc; |
1474 | struct radeon_gart gart; |
||
1475 | struct radeon_mode_info mode_info; |
||
1476 | struct radeon_scratch scratch; |
||
1321 | serge | 1477 | struct radeon_mman mman; |
2997 | Serge | 1478 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
1479 | wait_queue_head_t fence_queue; |
||
1480 | struct mutex ring_lock; |
||
1481 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
||
1482 | bool ib_pool_ready; |
||
1483 | struct radeon_sa_manager ring_tmp_bo; |
||
1963 | serge | 1484 | struct radeon_irq irq; |
1117 | serge | 1485 | struct radeon_asic *asic; |
1126 | serge | 1486 | struct radeon_gem gem; |
1179 | serge | 1487 | struct radeon_pm pm; |
1488 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
||
1117 | serge | 1489 | struct radeon_wb wb; |
1179 | serge | 1490 | struct radeon_dummy_page dummy_page; |
1117 | serge | 1491 | bool shutdown; |
1492 | bool suspend; |
||
1179 | serge | 1493 | bool need_dma32; |
1494 | bool accel_working; |
||
1495 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
||
1496 | const struct firmware *me_fw; /* all family ME firmware */ |
||
1497 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
1403 | serge | 1498 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1963 | serge | 1499 | const struct firmware *mc_fw; /* NI MC firmware */ |
2997 | Serge | 1500 | const struct firmware *ce_fw; /* SI CE firmware */ |
1179 | serge | 1501 | struct r600_blit r600_blit; |
2997 | Serge | 1502 | struct r600_vram_scratch vram_scratch; |
1268 | serge | 1503 | int msi_enabled; /* msi enabled */ |
2004 | serge | 1504 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2997 | Serge | 1505 | struct si_rlc rlc; |
1963 | serge | 1506 | // struct work_struct hotplug_work; |
2997 | Serge | 1507 | // struct work_struct audio_work; |
1430 | serge | 1508 | int num_crtc; /* number of crtcs */ |
1630 | serge | 1509 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1963 | serge | 1510 | bool audio_enabled; |
2997 | Serge | 1511 | // struct r600_audio audio_status; /* audio stuff */ |
1512 | // struct notifier_block acpi_nb; |
||
1513 | /* only one userspace can use Hyperz features or CMASK at a time */ |
||
1514 | // struct drm_file *hyperz_filp; |
||
1515 | // struct drm_file *cmask_filp; |
||
1963 | serge | 1516 | /* i2c buses */ |
1517 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
||
2997 | Serge | 1518 | /* debugfs */ |
1519 | // struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
||
1520 | unsigned debugfs_count; |
||
1521 | /* virtual memory */ |
||
1522 | struct radeon_vm_manager vm_manager; |
||
1523 | struct mutex gpu_clock_mutex; |
||
1524 | /* ACPI interface */ |
||
1525 | // struct radeon_atif atif; |
||
1526 | // struct radeon_atcs atcs; |
||
1117 | serge | 1527 | }; |
1528 | |||
1529 | int radeon_device_init(struct radeon_device *rdev, |
||
1530 | struct drm_device *ddev, |
||
1531 | struct pci_dev *pdev, |
||
1532 | uint32_t flags); |
||
1533 | void radeon_device_fini(struct radeon_device *rdev); |
||
1534 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
1535 | |||
2997 | Serge | 1536 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
1537 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
||
1538 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
||
1539 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
||
1117 | serge | 1540 | |
1321 | serge | 1541 | /* |
1542 | * Cast helper |
||
1543 | */ |
||
1544 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
||
1117 | serge | 1545 | |
1546 | /* |
||
1547 | * Registers read & write functions. |
||
1548 | */ |
||
2997 | Serge | 1549 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1550 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
||
1551 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
||
1552 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
||
1179 | serge | 1553 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
2004 | serge | 1554 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
1179 | serge | 1555 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1117 | serge | 1556 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1557 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
1558 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
1559 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
1560 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
1561 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 1562 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1563 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
1430 | serge | 1564 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1565 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1566 | #define WREG32_P(reg, val, mask) \ |
1567 | do { \ |
||
1568 | uint32_t tmp_ = RREG32(reg); \ |
||
1569 | tmp_ &= (mask); \ |
||
1570 | tmp_ |= ((val) & ~(mask)); \ |
||
1571 | WREG32(reg, tmp_); \ |
||
1572 | } while (0) |
||
1573 | #define WREG32_PLL_P(reg, val, mask) \ |
||
1574 | do { \ |
||
1575 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
1576 | tmp_ &= (mask); \ |
||
1577 | tmp_ |= ((val) & ~(mask)); \ |
||
1578 | WREG32_PLL(reg, tmp_); \ |
||
1579 | } while (0) |
||
1963 | serge | 1580 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1581 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1582 | |
1179 | serge | 1583 | /* |
1584 | * Indirect registers accessor |
||
1585 | */ |
||
1586 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
1587 | { |
||
1588 | uint32_t r; |
||
1117 | serge | 1589 | |
1179 | serge | 1590 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1591 | r = RREG32(RADEON_PCIE_DATA); |
||
1592 | return r; |
||
1593 | } |
||
1594 | |||
1595 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
1596 | { |
||
1597 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
1598 | WREG32(RADEON_PCIE_DATA, (v)); |
||
1599 | } |
||
1600 | |||
1601 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
1602 | |||
1603 | |||
1117 | serge | 1604 | /* |
1605 | * ASICs helpers. |
||
1606 | */ |
||
1179 | serge | 1607 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1608 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 1609 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1610 | (rdev->family == CHIP_RV200) || \ |
||
1611 | (rdev->family == CHIP_RS100) || \ |
||
1612 | (rdev->family == CHIP_RS200) || \ |
||
1613 | (rdev->family == CHIP_RV250) || \ |
||
1614 | (rdev->family == CHIP_RV280) || \ |
||
1615 | (rdev->family == CHIP_RS300)) |
||
1616 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
1617 | (rdev->family == CHIP_RV350) || \ |
||
1618 | (rdev->family == CHIP_R350) || \ |
||
1619 | (rdev->family == CHIP_RV380) || \ |
||
1620 | (rdev->family == CHIP_R420) || \ |
||
1621 | (rdev->family == CHIP_R423) || \ |
||
1622 | (rdev->family == CHIP_RV410) || \ |
||
1623 | (rdev->family == CHIP_RS400) || \ |
||
1624 | (rdev->family == CHIP_RS480)) |
||
1963 | serge | 1625 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1626 | (rdev->ddev->pdev->device == 0x9443) || \ |
||
1627 | (rdev->ddev->pdev->device == 0x944B) || \ |
||
1628 | (rdev->ddev->pdev->device == 0x9506) || \ |
||
1629 | (rdev->ddev->pdev->device == 0x9509) || \ |
||
1630 | (rdev->ddev->pdev->device == 0x950F) || \ |
||
1631 | (rdev->ddev->pdev->device == 0x689C) || \ |
||
1632 | (rdev->ddev->pdev->device == 0x689D)) |
||
1117 | serge | 1633 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1963 | serge | 1634 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1635 | (rdev->family == CHIP_RS690) || \ |
||
1636 | (rdev->family == CHIP_RS740) || \ |
||
1637 | (rdev->family >= CHIP_R600)) |
||
1117 | serge | 1638 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1639 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
1430 | serge | 1640 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1963 | serge | 1641 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1642 | (rdev->flags & RADEON_IS_IGP)) |
||
1643 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
||
2997 | Serge | 1644 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1645 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
||
1646 | (rdev->flags & RADEON_IS_IGP)) |
||
1117 | serge | 1647 | |
1648 | /* |
||
1649 | * BIOS helpers. |
||
1650 | */ |
||
1651 | #define RBIOS8(i) (rdev->bios[i]) |
||
1652 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
1653 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
1654 | |||
1655 | int radeon_combios_init(struct radeon_device *rdev); |
||
1656 | void radeon_combios_fini(struct radeon_device *rdev); |
||
1657 | int radeon_atombios_init(struct radeon_device *rdev); |
||
1658 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
1659 | |||
1660 | |||
1661 | /* |
||
1662 | * RING helpers. |
||
1663 | */ |
||
2997 | Serge | 1664 | #if DRM_DEBUG_CODE == 0 |
1665 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
||
1117 | serge | 1666 | { |
2997 | Serge | 1667 | ring->ring[ring->wptr++] = v; |
1668 | ring->wptr &= ring->ptr_mask; |
||
1669 | ring->count_dw--; |
||
1670 | ring->ring_free_dw--; |
||
1671 | } |
||
1672 | #else |
||
1673 | /* With debugging this is just too big to inline */ |
||
1674 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
||
1117 | serge | 1675 | #endif |
1676 | |||
1677 | /* |
||
1678 | * ASICs macro. |
||
1679 | */ |
||
1680 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 1681 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1682 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
1683 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
2997 | Serge | 1684 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
1179 | serge | 1685 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1963 | serge | 1686 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2997 | Serge | 1687 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1688 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) |
||
1689 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
||
1690 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
||
1691 | #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) |
||
1692 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
||
1693 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) |
||
1694 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) |
||
1695 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
||
1696 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
||
1697 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
||
1698 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
||
1699 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
||
1700 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
||
1701 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
||
1702 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
||
1703 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
||
1704 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
||
1705 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
||
1706 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
||
1707 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
||
1708 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
||
1709 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
||
1710 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
||
1711 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
||
1712 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
||
1713 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
||
1714 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
||
1715 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
||
1716 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
||
1717 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
||
1718 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
||
1719 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
||
1720 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
||
1721 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
||
1722 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
||
1723 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
||
1724 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
||
1725 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
||
1963 | serge | 1726 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2997 | Serge | 1727 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1728 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
||
1729 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
||
1730 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
||
1731 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
||
1732 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
||
1733 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
||
1734 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) |
||
1735 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
||
1736 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
||
1117 | serge | 1737 | |
1179 | serge | 1738 | /* Common functions */ |
1403 | serge | 1739 | /* AGP */ |
1963 | serge | 1740 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1403 | serge | 1741 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1179 | serge | 1742 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1743 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
1744 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
1963 | serge | 1745 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
1746 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
||
1321 | serge | 1747 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1179 | serge | 1748 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1963 | serge | 1749 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1750 | extern int radeon_wb_init(struct radeon_device *rdev); |
||
1751 | extern void radeon_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1752 | extern void radeon_surface_init(struct radeon_device *rdev); |
1753 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 1754 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1755 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1321 | serge | 1756 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1403 | serge | 1757 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1430 | serge | 1758 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1759 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
||
1760 | extern int radeon_resume_kms(struct drm_device *dev); |
||
1761 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
||
1963 | serge | 1762 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
1117 | serge | 1763 | |
1963 | serge | 1764 | /* |
2997 | Serge | 1765 | * vm |
1766 | */ |
||
1767 | int radeon_vm_manager_init(struct radeon_device *rdev); |
||
1768 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
||
1769 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1770 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1771 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1772 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1773 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
||
1774 | struct radeon_vm *vm, int ring); |
||
1775 | void radeon_vm_fence(struct radeon_device *rdev, |
||
1776 | struct radeon_vm *vm, |
||
1777 | struct radeon_fence *fence); |
||
1778 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
||
1779 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
||
1780 | struct radeon_vm *vm, |
||
1781 | struct radeon_bo *bo, |
||
1782 | struct ttm_mem_reg *mem); |
||
1783 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
||
1784 | struct radeon_bo *bo); |
||
1785 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
||
1786 | struct radeon_bo *bo); |
||
1787 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
||
1788 | struct radeon_vm *vm, |
||
1789 | struct radeon_bo *bo); |
||
1790 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
||
1791 | struct radeon_bo_va *bo_va, |
||
1792 | uint64_t offset, |
||
1793 | uint32_t flags); |
||
1794 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
||
1795 | struct radeon_bo_va *bo_va); |
||
1796 | |||
1797 | /* audio */ |
||
1798 | void r600_audio_update_hdmi(struct work_struct *work); |
||
1799 | |||
1800 | /* |
||
1801 | * R600 vram scratch functions |
||
1802 | */ |
||
1803 | int r600_vram_scratch_init(struct radeon_device *rdev); |
||
1804 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
||
1805 | |||
1806 | /* |
||
1807 | * r600 cs checking helper |
||
1808 | */ |
||
1809 | unsigned r600_mip_minify(unsigned size, unsigned level); |
||
1810 | bool r600_fmt_is_valid_color(u32 format); |
||
1811 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
||
1812 | int r600_fmt_get_blocksize(u32 format); |
||
1813 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
||
1814 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
||
1815 | |||
1816 | /* |
||
1963 | serge | 1817 | * r600 functions used by radeon_encoder.c |
1818 | */ |
||
2997 | Serge | 1819 | struct radeon_hdmi_acr { |
1820 | u32 clock; |
||
1821 | |||
1822 | int n_32khz; |
||
1823 | int cts_32khz; |
||
1824 | |||
1825 | int n_44_1khz; |
||
1826 | int cts_44_1khz; |
||
1827 | |||
1828 | int n_48khz; |
||
1829 | int cts_48khz; |
||
1830 | |||
1831 | }; |
||
1832 | |||
1833 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
||
1834 | |||
1963 | serge | 1835 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1836 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
||
1837 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
2997 | Serge | 1838 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1839 | u32 tiling_pipe_num, |
||
1840 | u32 max_rb_num, |
||
1841 | u32 total_max_rb_num, |
||
1842 | u32 enabled_rb_mask); |
||
1179 | serge | 1843 | |
2997 | Serge | 1844 | /* |
1845 | * evergreen functions used by radeon_encoder.c |
||
1846 | */ |
||
1847 | |||
1848 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
1849 | |||
1963 | serge | 1850 | extern int ni_init_microcode(struct radeon_device *rdev); |
1851 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
||
1221 | serge | 1852 | |
1963 | serge | 1853 | /* radeon_acpi.c */ |
1854 | #if defined(CONFIG_ACPI) |
||
1855 | extern int radeon_acpi_init(struct radeon_device *rdev); |
||
2997 | Serge | 1856 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
1963 | serge | 1857 | #else |
1858 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
||
2997 | Serge | 1859 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
1963 | serge | 1860 | #endif |
1179 | serge | 1861 | |
1321 | serge | 1862 | #include "radeon_object.h" |
1179 | serge | 1863 | |
1117 | serge | 1864 | #define DRM_UDELAY(d) udelay(d) |
1865 | |||
1866 | resource_size_t |
||
1867 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1868 | resource_size_t |
||
1869 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1870 | |||
1239 | serge | 1871 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1403 | serge | 1872 | videomode_t *mode, bool strict); |
1117 | serge | 1873 | |
1179 | serge | 1874 | |
1963 | serge | 1875 | |
1117 | serge | 1876 | #endif><>><>><>><>><>><>><>=>>><>><>><> |