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1117 serge 1
/*
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 * Copyright 2008 Advanced Micro Devices, Inc.
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 * Copyright 2008 Red Hat Inc.
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 * Copyright 2009 Jerome Glisse.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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 * and/or sell copies of the Software, and to permit persons to whom the
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 * Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
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 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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 * OTHER DEALINGS IN THE SOFTWARE.
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 *
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 * Authors: Dave Airlie
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 *          Alex Deucher
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 *          Jerome Glisse
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 */
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#ifndef __RADEON_H__
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#define __RADEON_H__
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/* TODO: Here are things that needs to be done :
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 *	- surface allocator & initializer : (bit like scratch reg) should
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 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
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 *	  related to surface
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 *	- WB : write back stuff (do it bit like scratch reg things)
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 *	- Vblank : look at Jesse's rework and what we should do
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 *	- r600/r700: gart & cp
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 *	- cs : clean cs ioctl use bitmap & things like that.
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 *	- power management stuff
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 *	- Barrier in gart code
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 *	- Unmappabled vram ?
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 *	- TESTING, TESTING, TESTING
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 */
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1221 serge 45
/* Initialization path:
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 *  We expect that acceleration initialization might fail for various
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 *  reasons even thought we work hard to make it works on most
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 *  configurations. In order to still have a working userspace in such
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 *  situation the init path must succeed up to the memory controller
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 *  initialization point. Failure before this point are considered as
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 *  fatal error. Here is the init callchain :
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 *      radeon_device_init  perform common structure, mutex initialization
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 *      asic_init           setup the GPU memory layout and perform all
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 *                          one time initialization (failure in this
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 *                          function are considered fatal)
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 *      asic_startup        setup the GPU acceleration, in order to
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 *                          follow guideline the first thing this
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 *                          function should do is setting the GPU
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 *                          memory controller (only MC setup failure
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 *                          are considered as fatal)
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 */
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1321 serge 63
#include 
1221 serge 64
 
1321 serge 65
#include 
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#include 
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1321 serge 68
#include 
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#include 
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#include 
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#include 
1221 serge 72
 
1117 serge 73
 
1120 serge 74
#include 
1117 serge 75
 
1120 serge 76
#include 
1123 serge 77
#include "drm_edid.h"
1179 serge 78
 
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#include "radeon_family.h"
1117 serge 80
#include "radeon_mode.h"
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#include "radeon_reg.h"
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#include 
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1179 serge 85
/*
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 * Modules parameters.
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 */
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extern int radeon_no_wb;
1123 serge 89
extern int radeon_modeset;
1117 serge 90
extern int radeon_dynclks;
1123 serge 91
extern int radeon_r4xx_atom;
1128 serge 92
extern int radeon_agpmode;
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extern int radeon_vram_limit;
1117 serge 94
extern int radeon_gart_size;
1128 serge 95
extern int radeon_benchmarking;
1179 serge 96
extern int radeon_testing;
1123 serge 97
extern int radeon_connector_table;
1179 serge 98
extern int radeon_tv;
1321 serge 99
extern int radeon_new_pll;
1117 serge 100
 
1321 serge 101
 
1233 serge 102
typedef struct
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{
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  int width;
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  int height;
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  int bpp;
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  int freq;
1321 serge 108
}videomode_t;
1179 serge 109
 
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static inline uint8_t __raw_readb(const volatile void __iomem *addr)
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{
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    return *(const volatile uint8_t __force *) addr;
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}
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static inline uint16_t __raw_readw(const volatile void __iomem *addr)
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{
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    return *(const volatile uint16_t __force *) addr;
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}
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static inline uint32_t __raw_readl(const volatile void __iomem *addr)
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{
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    return *(const volatile uint32_t __force *) addr;
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}
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#define readb __raw_readb
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#define readw __raw_readw
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#define readl __raw_readl
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static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
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{
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    *(volatile uint8_t __force *) addr = b;
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}
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static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
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{
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    *(volatile uint16_t __force *) addr = b;
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}
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static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
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{
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    *(volatile uint32_t __force *) addr = b;
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}
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static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
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{
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        *(volatile __u64 *)addr = b;
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}
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#define writeb __raw_writeb
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#define writew __raw_writew
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#define writel __raw_writel
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#define writeq __raw_writeq
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1117 serge 157
/*
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 * Copy from radeon_drv.h so we don't have to include both and have conflicting
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 * symbol;
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 */
1120 serge 161
#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
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#define RADEON_IB_POOL_SIZE             16
1117 serge 163
#define RADEON_DEBUGFS_MAX_NUM_FILES	32
1120 serge 164
#define RADEONFB_CONN_LIMIT             4
1179 serge 165
#define RADEON_BIOS_NUM_SCRATCH		8
1117 serge 166
 
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/*
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 * Errata workarounds.
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 */
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enum radeon_pll_errata {
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    CHIP_ERRATA_R300_CG             = 0x00000001,
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    CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
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    CHIP_ERRATA_PLL_DELAY           = 0x00000004
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};
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struct radeon_device;
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/*
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 * BIOS.
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 */
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bool radeon_get_bios(struct radeon_device *rdev);
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1179 serge 185
 
1117 serge 186
/*
1179 serge 187
 * Dummy page
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 */
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struct radeon_dummy_page {
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	struct page	*page;
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	dma_addr_t	addr;
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};
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int radeon_dummy_page_init(struct radeon_device *rdev);
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void radeon_dummy_page_fini(struct radeon_device *rdev);
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/*
1117 serge 198
 * Clocks
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 */
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struct radeon_clock {
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	struct radeon_pll p1pll;
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	struct radeon_pll p2pll;
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	struct radeon_pll spll;
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	struct radeon_pll mpll;
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	/* 10 Khz units */
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	uint32_t default_mclk;
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	uint32_t default_sclk;
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};
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1268 serge 210
/*
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 * Power management
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 */
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int radeon_pm_init(struct radeon_device *rdev);
1179 serge 214
 
1117 serge 215
/*
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 * Fences.
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 */
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struct radeon_fence_driver {
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	uint32_t			scratch_reg;
1321 serge 220
	atomic_t			seq;
1117 serge 221
	uint32_t			last_seq;
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	unsigned long			count_timeout;
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//	wait_queue_head_t		queue;
1321 serge 224
	rwlock_t			lock;
1120 serge 225
	struct list_head		created;
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	struct list_head		emited;
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	struct list_head		signaled;
1117 serge 228
};
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struct radeon_fence {
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	struct radeon_device		*rdev;