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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_H__ |
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29 | #define __RADEON_H__ |
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30 | |||
31 | //#include "radeon_object.h" |
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32 | |||
33 | /* TODO: Here are things that needs to be done : |
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34 | * - surface allocator & initializer : (bit like scratch reg) should |
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35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
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36 | * related to surface |
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37 | * - WB : write back stuff (do it bit like scratch reg things) |
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38 | * - Vblank : look at Jesse's rework and what we should do |
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39 | * - r600/r700: gart & cp |
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40 | * - cs : clean cs ioctl use bitmap & things like that. |
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41 | * - power management stuff |
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42 | * - Barrier in gart code |
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43 | * - Unmappabled vram ? |
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44 | * - TESTING, TESTING, TESTING |
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45 | */ |
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46 | |||
1221 | serge | 47 | /* Initialization path: |
48 | * We expect that acceleration initialization might fail for various |
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49 | * reasons even thought we work hard to make it works on most |
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50 | * configurations. In order to still have a working userspace in such |
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51 | * situation the init path must succeed up to the memory controller |
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52 | * initialization point. Failure before this point are considered as |
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53 | * fatal error. Here is the init callchain : |
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54 | * radeon_device_init perform common structure, mutex initialization |
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55 | * asic_init setup the GPU memory layout and perform all |
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56 | * one time initialization (failure in this |
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57 | * function are considered fatal) |
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58 | * asic_startup setup the GPU acceleration, in order to |
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59 | * follow guideline the first thing this |
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60 | * function should do is setting the GPU |
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61 | * memory controller (only MC setup failure |
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62 | * are considered as fatal) |
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63 | */ |
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64 | |||
65 | |||
1120 | serge | 66 | #include |
1221 | serge | 67 | |
68 | |||
1179 | serge | 69 | #include |
1117 | serge | 70 | |
1120 | serge | 71 | #include |
1117 | serge | 72 | |
1120 | serge | 73 | #include |
1123 | serge | 74 | #include "drm_edid.h" |
1179 | serge | 75 | |
76 | #include "radeon_family.h" |
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1117 | serge | 77 | #include "radeon_mode.h" |
78 | #include "radeon_reg.h" |
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79 | |||
80 | #include |
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81 | |||
1179 | serge | 82 | /* |
83 | * Modules parameters. |
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84 | */ |
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85 | extern int radeon_no_wb; |
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1123 | serge | 86 | extern int radeon_modeset; |
1117 | serge | 87 | extern int radeon_dynclks; |
1123 | serge | 88 | extern int radeon_r4xx_atom; |
1128 | serge | 89 | extern int radeon_agpmode; |
90 | extern int radeon_vram_limit; |
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1117 | serge | 91 | extern int radeon_gart_size; |
1128 | serge | 92 | extern int radeon_benchmarking; |
1179 | serge | 93 | extern int radeon_testing; |
1123 | serge | 94 | extern int radeon_connector_table; |
1179 | serge | 95 | extern int radeon_tv; |
1117 | serge | 96 | |
1233 | serge | 97 | typedef struct |
98 | { |
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99 | int width; |
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100 | int height; |
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101 | int bpp; |
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102 | int freq; |
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103 | }mode_t; |
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1179 | serge | 104 | |
105 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
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106 | { |
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107 | return *(const volatile uint8_t __force *) addr; |
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108 | } |
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109 | |||
110 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
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111 | { |
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112 | return *(const volatile uint16_t __force *) addr; |
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113 | } |
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114 | |||
115 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
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116 | { |
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117 | return *(const volatile uint32_t __force *) addr; |
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118 | } |
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119 | |||
120 | #define readb __raw_readb |
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121 | #define readw __raw_readw |
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122 | #define readl __raw_readl |
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123 | |||
124 | |||
125 | |||
126 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
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127 | { |
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128 | *(volatile uint8_t __force *) addr = b; |
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129 | } |
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130 | |||
131 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
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132 | { |
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133 | *(volatile uint16_t __force *) addr = b; |
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134 | } |
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135 | |||
136 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
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137 | { |
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138 | *(volatile uint32_t __force *) addr = b; |
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139 | } |
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140 | |||
141 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
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142 | { |
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143 | *(volatile __u64 *)addr = b; |
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144 | } |
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145 | |||
146 | #define writeb __raw_writeb |
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147 | #define writew __raw_writew |
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148 | #define writel __raw_writel |
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149 | #define writeq __raw_writeq |
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150 | |||
151 | |||
1117 | serge | 152 | /* |
153 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
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154 | * symbol; |
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155 | */ |
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1120 | serge | 156 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
157 | #define RADEON_IB_POOL_SIZE 16 |
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1117 | serge | 158 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
1120 | serge | 159 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 160 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 161 | |
162 | /* |
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163 | * Errata workarounds. |
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164 | */ |
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165 | enum radeon_pll_errata { |
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166 | CHIP_ERRATA_R300_CG = 0x00000001, |
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167 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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168 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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169 | }; |
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170 | |||
171 | |||
172 | struct radeon_device; |
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173 | |||
174 | |||
175 | /* |
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176 | * BIOS. |
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177 | */ |
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178 | bool radeon_get_bios(struct radeon_device *rdev); |
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179 | |||
1179 | serge | 180 | |
1117 | serge | 181 | /* |
1179 | serge | 182 | * Dummy page |
183 | */ |
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184 | struct radeon_dummy_page { |
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185 | struct page *page; |
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186 | dma_addr_t addr; |
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187 | }; |
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188 | int radeon_dummy_page_init(struct radeon_device *rdev); |
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189 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
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190 | |||
191 | |||
192 | /* |
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1117 | serge | 193 | * Clocks |
194 | */ |
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195 | struct radeon_clock { |
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196 | struct radeon_pll p1pll; |
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197 | struct radeon_pll p2pll; |
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198 | struct radeon_pll spll; |
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199 | struct radeon_pll mpll; |
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200 | /* 10 Khz units */ |
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201 | uint32_t default_mclk; |
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202 | uint32_t default_sclk; |
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203 | }; |
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204 | |||
1268 | serge | 205 | /* |
206 | * Power management |
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207 | */ |
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208 | int radeon_pm_init(struct radeon_device *rdev); |
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1179 | serge | 209 | |
1117 | serge | 210 | /* |
211 | * Fences. |
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212 | */ |
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213 | struct radeon_fence_driver { |
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214 | uint32_t scratch_reg; |
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215 | // atomic_t seq; |
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216 | uint32_t last_seq; |
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217 | unsigned long count_timeout; |
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218 | // wait_queue_head_t queue; |
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219 | // rwlock_t lock; |
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1120 | serge | 220 | struct list_head created; |
221 | struct list_head emited; |
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222 | struct list_head signaled; |
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1117 | serge | 223 | }; |
224 | |||
225 | struct radeon_fence { |
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226 | struct radeon_device *rdev; |
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227 | // struct kref kref; |
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1120 | serge | 228 | struct list_head list; |
1117 | serge | 229 | /* protected by radeon_fence.lock */ |
230 | uint32_t seq; |
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231 | unsigned long timeout; |
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232 | bool emited; |
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233 | bool signaled; |
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234 | }; |
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235 | |||
236 | int radeon_fence_driver_init(struct radeon_device *rdev); |
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237 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
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238 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
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239 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
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240 | void radeon_fence_process(struct radeon_device *rdev); |
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241 | bool radeon_fence_signaled(struct radeon_fence *fence); |
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242 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
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243 | int radeon_fence_wait_next(struct radeon_device *rdev); |
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244 | int radeon_fence_wait_last(struct radeon_device *rdev); |
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245 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
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246 | void radeon_fence_unref(struct radeon_fence **fence); |
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247 | |||
1179 | serge | 248 | /* |
249 | * Tiling registers |
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250 | */ |
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251 | struct radeon_surface_reg { |
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252 | struct radeon_object *robj; |
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253 | }; |
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1117 | serge | 254 | |
1179 | serge | 255 | #define RADEON_GEM_MAX_SURFACES 8 |
256 | |||
1117 | serge | 257 | /* |
258 | * Radeon buffer. |
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259 | */ |
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260 | struct radeon_object; |
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261 | |||
262 | struct radeon_object_list { |
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1120 | serge | 263 | struct list_head list; |
1117 | serge | 264 | struct radeon_object *robj; |
265 | uint64_t gpu_offset; |
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266 | unsigned rdomain; |
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267 | unsigned wdomain; |
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1179 | serge | 268 | uint32_t tiling_flags; |
1117 | serge | 269 | }; |
270 | |||
1123 | serge | 271 | int radeon_object_init(struct radeon_device *rdev); |
272 | void radeon_object_fini(struct radeon_device *rdev); |
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273 | int radeon_object_create(struct radeon_device *rdev, |
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274 | struct drm_gem_object *gobj, |
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275 | unsigned long size, |
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276 | bool kernel, |
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277 | uint32_t domain, |
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278 | bool interruptible, |
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279 | struct radeon_object **robj_ptr); |
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1117 | serge | 280 | |
281 | |||
1123 | serge | 282 | /* |
283 | * GEM objects. |
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284 | */ |
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285 | struct radeon_gem { |
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286 | struct list_head objects; |
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287 | }; |
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1117 | serge | 288 | |
1126 | serge | 289 | int radeon_gem_init(struct radeon_device *rdev); |
290 | void radeon_gem_fini(struct radeon_device *rdev); |
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291 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
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292 | int alignment, int initial_domain, |
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293 | bool discardable, bool kernel, |
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294 | bool interruptible, |
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295 | struct drm_gem_object **obj); |
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296 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
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297 | uint64_t *gpu_addr); |
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298 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
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1117 | serge | 299 | |
300 | |||
301 | /* |
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302 | * GART structures, functions & helpers |
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303 | */ |
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304 | struct radeon_mc; |
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305 | |||
306 | struct radeon_gart_table_ram { |
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307 | volatile uint32_t *ptr; |
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308 | }; |
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309 | |||
310 | struct radeon_gart_table_vram { |
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311 | struct radeon_object *robj; |
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312 | volatile uint32_t *ptr; |
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313 | }; |
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314 | |||
315 | union radeon_gart_table { |
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316 | struct radeon_gart_table_ram ram; |
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317 | struct radeon_gart_table_vram vram; |
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318 | }; |
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319 | |||
1268 | serge | 320 | #define RADEON_GPU_PAGE_SIZE 4096 |
321 | |||
1117 | serge | 322 | struct radeon_gart { |
323 | dma_addr_t table_addr; |
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324 | unsigned num_gpu_pages; |
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325 | unsigned num_cpu_pages; |
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326 | unsigned table_size; |
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327 | union radeon_gart_table table; |
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328 | struct page **pages; |
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329 | dma_addr_t *pages_addr; |
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330 | bool ready; |
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331 | }; |
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332 | |||
333 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
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334 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
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335 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
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336 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
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337 | int radeon_gart_init(struct radeon_device *rdev); |
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338 | void radeon_gart_fini(struct radeon_device *rdev); |
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339 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
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340 | int pages); |
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1120 | serge | 341 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
342 | int pages, u32_t *pagelist); |
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1117 | serge | 343 | |
344 | |||
345 | /* |
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346 | * GPU MC structures, functions & helpers |
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347 | */ |
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348 | struct radeon_mc { |
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349 | resource_size_t aper_size; |
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350 | resource_size_t aper_base; |
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351 | resource_size_t agp_base; |
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1179 | serge | 352 | /* for some chips with <= 32MB we need to lie |
353 | * about vram size near mc fb location */ |
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354 | u64 mc_vram_size; |
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355 | u64 gtt_location; |
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356 | u64 gtt_size; |
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357 | u64 gtt_start; |
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358 | u64 gtt_end; |
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359 | u64 vram_location; |
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360 | u64 vram_start; |
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361 | u64 vram_end; |
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1117 | serge | 362 | unsigned vram_width; |
1179 | serge | 363 | u64 real_vram_size; |
1117 | serge | 364 | int vram_mtrr; |
365 | bool vram_is_ddr; |
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366 | }; |
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367 | |||
368 | int radeon_mc_setup(struct radeon_device *rdev); |
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369 | |||
370 | |||
371 | /* |
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372 | * GPU scratch registers structures, functions & helpers |
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373 | */ |
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374 | struct radeon_scratch { |
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375 | unsigned num_reg; |
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376 | bool free[32]; |
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377 | uint32_t reg[32]; |
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378 | }; |
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379 | |||
380 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
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381 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
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382 | |||
383 | |||
384 | /* |
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385 | * IRQS. |
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386 | */ |
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387 | struct radeon_irq { |
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388 | bool installed; |
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389 | bool sw_int; |
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390 | /* FIXME: use a define max crtc rather than hardcode it */ |
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391 | bool crtc_vblank_int[2]; |
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392 | }; |
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393 | |||
394 | int radeon_irq_kms_init(struct radeon_device *rdev); |
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395 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
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396 | |||
397 | |||
398 | /* |
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399 | * CP & ring. |
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400 | */ |
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401 | struct radeon_ib { |
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1120 | serge | 402 | struct list_head list; |
1117 | serge | 403 | unsigned long idx; |
404 | uint64_t gpu_addr; |
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405 | struct radeon_fence *fence; |
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1221 | serge | 406 | uint32_t *ptr; |
1117 | serge | 407 | uint32_t length_dw; |
408 | }; |
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409 | |||
1179 | serge | 410 | /* |
411 | * locking - |
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412 | * mutex protects scheduled_ibs, ready, alloc_bm |
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413 | */ |
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1117 | serge | 414 | struct radeon_ib_pool { |
415 | // struct mutex mutex; |
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416 | struct radeon_object *robj; |
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1120 | serge | 417 | struct list_head scheduled_ibs; |
1117 | serge | 418 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
419 | bool ready; |
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1120 | serge | 420 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
1117 | serge | 421 | }; |
422 | |||
423 | struct radeon_cp { |
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424 | struct radeon_object *ring_obj; |
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425 | volatile uint32_t *ring; |
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426 | unsigned rptr; |
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427 | unsigned wptr; |
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428 | unsigned wptr_old; |
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429 | unsigned ring_size; |
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430 | unsigned ring_free_dw; |
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431 | int count_dw; |
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432 | uint64_t gpu_addr; |
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433 | uint32_t align_mask; |
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434 | uint32_t ptr_mask; |
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435 | // struct mutex mutex; |
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436 | bool ready; |
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437 | }; |
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438 | |||
1179 | serge | 439 | struct r600_blit { |
440 | struct radeon_object *shader_obj; |
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441 | u64 shader_gpu_addr; |
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442 | u32 vs_offset, ps_offset; |
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443 | u32 state_offset; |
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444 | u32 state_len; |
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445 | u32 vb_used, vb_total; |
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446 | struct radeon_ib *vb_ib; |
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447 | }; |
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448 | |||
1117 | serge | 449 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
450 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
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451 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
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452 | int radeon_ib_pool_init(struct radeon_device *rdev); |
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453 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
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454 | int radeon_ib_test(struct radeon_device *rdev); |
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455 | /* Ring access between begin & end cannot sleep */ |
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456 | void radeon_ring_free_size(struct radeon_device *rdev); |
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457 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
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458 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
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459 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
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460 | int radeon_ring_test(struct radeon_device *rdev); |
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461 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
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462 | void radeon_ring_fini(struct radeon_device *rdev); |
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463 | |||
464 | |||
465 | /* |
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466 | * CS. |
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467 | */ |
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468 | struct radeon_cs_reloc { |
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469 | // struct drm_gem_object *gobj; |
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470 | struct radeon_object *robj; |
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1120 | serge | 471 | struct radeon_object_list lobj; |
1117 | serge | 472 | uint32_t handle; |
473 | uint32_t flags; |
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474 | }; |
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475 | |||
476 | struct radeon_cs_chunk { |
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477 | uint32_t chunk_id; |
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478 | uint32_t length_dw; |
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1221 | serge | 479 | int kpage_idx[2]; |
480 | uint32_t *kpage[2]; |
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1117 | serge | 481 | uint32_t *kdata; |
1221 | serge | 482 | void __user *user_ptr; |
483 | int last_copied_page; |
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484 | int last_page_index; |
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1117 | serge | 485 | }; |
486 | |||
487 | struct radeon_cs_parser { |
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488 | struct radeon_device *rdev; |
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489 | // struct drm_file *filp; |
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490 | /* chunks */ |
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491 | unsigned nchunks; |
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492 | struct radeon_cs_chunk *chunks; |
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493 | uint64_t *chunks_array; |
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494 | /* IB */ |
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495 | unsigned idx; |
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496 | /* relocations */ |
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497 | unsigned nrelocs; |
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498 | struct radeon_cs_reloc *relocs; |
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499 | struct radeon_cs_reloc **relocs_ptr; |
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1120 | serge | 500 | struct list_head validated; |
1117 | serge | 501 | /* indices of various chunks */ |
502 | int chunk_ib_idx; |
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503 | int chunk_relocs_idx; |
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504 | struct radeon_ib *ib; |
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505 | void *track; |
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1179 | serge | 506 | unsigned family; |
1221 | serge | 507 | int parser_error; |
1117 | serge | 508 | }; |
509 | |||
1221 | serge | 510 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
511 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
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512 | |||
513 | |||
514 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
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515 | { |
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516 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
||
517 | u32 pg_idx, pg_offset; |
||
518 | u32 idx_value = 0; |
||
519 | int new_page; |
||
520 | |||
521 | pg_idx = (idx * 4) / PAGE_SIZE; |
||
522 | pg_offset = (idx * 4) % PAGE_SIZE; |
||
523 | |||
524 | if (ibc->kpage_idx[0] == pg_idx) |
||
525 | return ibc->kpage[0][pg_offset/4]; |
||
526 | if (ibc->kpage_idx[1] == pg_idx) |
||
527 | return ibc->kpage[1][pg_offset/4]; |
||
528 | |||
529 | new_page = radeon_cs_update_pages(p, pg_idx); |
||
530 | if (new_page < 0) { |
||
531 | p->parser_error = new_page; |
||
532 | return 0; |
||
533 | } |
||
534 | |||
535 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
||
536 | return idx_value; |
||
537 | } |
||
538 | |||
1117 | serge | 539 | struct radeon_cs_packet { |
540 | unsigned idx; |
||
541 | unsigned type; |
||
542 | unsigned reg; |
||
543 | unsigned opcode; |
||
544 | int count; |
||
545 | unsigned one_reg_wr; |
||
546 | }; |
||
547 | |||
548 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
549 | struct radeon_cs_packet *pkt, |
||
550 | unsigned idx, unsigned reg); |
||
551 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
552 | struct radeon_cs_packet *pkt); |
||
553 | |||
554 | |||
555 | /* |
||
556 | * AGP |
||
557 | */ |
||
558 | int radeon_agp_init(struct radeon_device *rdev); |
||
559 | void radeon_agp_fini(struct radeon_device *rdev); |
||
560 | |||
561 | |||
562 | /* |
||
563 | * Writeback |
||
564 | */ |
||
565 | struct radeon_wb { |
||
566 | struct radeon_object *wb_obj; |
||
567 | volatile uint32_t *wb; |
||
568 | uint64_t gpu_addr; |
||
569 | }; |
||
570 | |||
1179 | serge | 571 | /** |
572 | * struct radeon_pm - power management datas |
||
573 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
574 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
575 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
576 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
577 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
578 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
579 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
580 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
581 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
582 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) |
||
583 | * @needed_bandwidth: current bandwidth needs |
||
584 | * |
||
585 | * It keeps track of various data needed to take powermanagement decision. |
||
586 | * Bandwith need is used to determine minimun clock of the GPU and memory. |
||
587 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
||
588 | * (type of memory, bus size, efficiency, ...) |
||
589 | */ |
||
590 | struct radeon_pm { |
||
591 | fixed20_12 max_bandwidth; |
||
592 | fixed20_12 igp_sideport_mclk; |
||
593 | fixed20_12 igp_system_mclk; |
||
594 | fixed20_12 igp_ht_link_clk; |
||
595 | fixed20_12 igp_ht_link_width; |
||
596 | fixed20_12 k8_bandwidth; |
||
597 | fixed20_12 sideport_bandwidth; |
||
598 | fixed20_12 ht_bandwidth; |
||
599 | fixed20_12 core_bandwidth; |
||
600 | fixed20_12 sclk; |
||
601 | fixed20_12 needed_bandwidth; |
||
602 | }; |
||
1117 | serge | 603 | |
604 | /* |
||
605 | * ASIC specific functions. |
||
606 | */ |
||
607 | struct radeon_asic { |
||
608 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 609 | void (*fini)(struct radeon_device *rdev); |
610 | int (*resume)(struct radeon_device *rdev); |
||
611 | int (*suspend)(struct radeon_device *rdev); |
||
612 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1117 | serge | 613 | int (*gpu_reset)(struct radeon_device *rdev); |
614 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
||
615 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
616 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
||
617 | void (*cp_fini)(struct radeon_device *rdev); |
||
618 | void (*cp_disable)(struct radeon_device *rdev); |
||
1179 | serge | 619 | void (*cp_commit)(struct radeon_device *rdev); |
1117 | serge | 620 | void (*ring_start)(struct radeon_device *rdev); |
1179 | serge | 621 | int (*ring_test)(struct radeon_device *rdev); |
622 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1117 | serge | 623 | int (*irq_set)(struct radeon_device *rdev); |
624 | int (*irq_process)(struct radeon_device *rdev); |
||
1179 | serge | 625 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1117 | serge | 626 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
627 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
628 | int (*copy_blit)(struct radeon_device *rdev, |
||
629 | uint64_t src_offset, |
||
630 | uint64_t dst_offset, |
||
631 | unsigned num_pages, |
||
632 | struct radeon_fence *fence); |
||
633 | int (*copy_dma)(struct radeon_device *rdev, |
||
634 | uint64_t src_offset, |
||
635 | uint64_t dst_offset, |
||
636 | unsigned num_pages, |
||
637 | struct radeon_fence *fence); |
||
638 | int (*copy)(struct radeon_device *rdev, |
||
639 | uint64_t src_offset, |
||
640 | uint64_t dst_offset, |
||
641 | unsigned num_pages, |
||
642 | struct radeon_fence *fence); |
||
1268 | serge | 643 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 644 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 645 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 646 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
647 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
||
648 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
1179 | serge | 649 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
650 | uint32_t tiling_flags, uint32_t pitch, |
||
651 | uint32_t offset, uint32_t obj_size); |
||
652 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
||
653 | void (*bandwidth_update)(struct radeon_device *rdev); |
||
1117 | serge | 654 | }; |
655 | |||
1179 | serge | 656 | /* |
657 | * Asic structures |
||
658 | */ |
||
659 | struct r100_asic { |
||
660 | const unsigned *reg_safe_bm; |
||
661 | unsigned reg_safe_bm_size; |
||
662 | }; |
||
663 | |||
664 | struct r300_asic { |
||
665 | const unsigned *reg_safe_bm; |
||
666 | unsigned reg_safe_bm_size; |
||
667 | }; |
||
668 | |||
669 | struct r600_asic { |
||
670 | unsigned max_pipes; |
||
671 | unsigned max_tile_pipes; |
||
672 | unsigned max_simds; |
||
673 | unsigned max_backends; |
||
674 | unsigned max_gprs; |
||
675 | unsigned max_threads; |
||
676 | unsigned max_stack_entries; |
||
677 | unsigned max_hw_contexts; |
||
678 | unsigned max_gs_threads; |
||
679 | unsigned sx_max_export_size; |
||
680 | unsigned sx_max_export_pos_size; |
||
681 | unsigned sx_max_export_smx_size; |
||
682 | unsigned sq_num_cf_insts; |
||
683 | }; |
||
684 | |||
685 | struct rv770_asic { |
||
686 | unsigned max_pipes; |
||
687 | unsigned max_tile_pipes; |
||
688 | unsigned max_simds; |
||
689 | unsigned max_backends; |
||
690 | unsigned max_gprs; |
||
691 | unsigned max_threads; |
||
692 | unsigned max_stack_entries; |
||
693 | unsigned max_hw_contexts; |
||
694 | unsigned max_gs_threads; |
||
695 | unsigned sx_max_export_size; |
||
696 | unsigned sx_max_export_pos_size; |
||
697 | unsigned sx_max_export_smx_size; |
||
698 | unsigned sq_num_cf_insts; |
||
699 | unsigned sx_num_of_sets; |
||
700 | unsigned sc_prim_fifo_size; |
||
701 | unsigned sc_hiz_tile_fifo_size; |
||
702 | unsigned sc_earlyz_tile_fifo_fize; |
||
703 | }; |
||
704 | |||
1117 | serge | 705 | union radeon_asic_config { |
706 | struct r300_asic r300; |
||
1179 | serge | 707 | struct r100_asic r100; |
708 | struct r600_asic r600; |
||
709 | struct rv770_asic rv770; |
||
1117 | serge | 710 | }; |
711 | |||
712 | |||
713 | /* |
||
1179 | serge | 714 | |
715 | |||
716 | |||
717 | |||
1117 | serge | 718 | /* |
719 | * Core structure, functions and helpers. |
||
720 | */ |
||
721 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
722 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
723 | |||
724 | struct radeon_device { |
||
1221 | serge | 725 | void *dev; |
1117 | serge | 726 | struct drm_device *ddev; |
727 | struct pci_dev *pdev; |
||
728 | /* ASIC */ |
||
729 | union radeon_asic_config config; |
||
730 | enum radeon_family family; |
||
731 | unsigned long flags; |
||
732 | int usec_timeout; |
||
733 | enum radeon_pll_errata pll_errata; |
||
734 | int num_gb_pipes; |
||
1179 | serge | 735 | int num_z_pipes; |
1117 | serge | 736 | int disp_priority; |
737 | /* BIOS */ |
||
738 | uint8_t *bios; |
||
739 | bool is_atom_bios; |
||
740 | uint16_t bios_header_start; |
||
741 | |||
742 | // struct radeon_object *stollen_vga_memory; |
||
1126 | serge | 743 | struct fb_info *fbdev_info; |
1117 | serge | 744 | struct radeon_object *fbdev_robj; |
745 | struct radeon_framebuffer *fbdev_rfb; |
||
746 | /* Register mmio */ |
||
747 | unsigned long rmmio_base; |
||
748 | unsigned long rmmio_size; |
||
749 | void *rmmio; |
||
1120 | serge | 750 | radeon_rreg_t mc_rreg; |
751 | radeon_wreg_t mc_wreg; |
||
752 | radeon_rreg_t pll_rreg; |
||
753 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 754 | uint32_t pcie_reg_mask; |
1120 | serge | 755 | radeon_rreg_t pciep_rreg; |
756 | radeon_wreg_t pciep_wreg; |
||
757 | struct radeon_clock clock; |
||
1117 | serge | 758 | struct radeon_mc mc; |
759 | struct radeon_gart gart; |
||
760 | struct radeon_mode_info mode_info; |
||
761 | struct radeon_scratch scratch; |
||
1120 | serge | 762 | // struct radeon_mman mman; |
1117 | serge | 763 | struct radeon_fence_driver fence_drv; |
1120 | serge | 764 | struct radeon_cp cp; |
1117 | serge | 765 | struct radeon_ib_pool ib_pool; |
766 | // struct radeon_irq irq; |
||
767 | struct radeon_asic *asic; |
||
1126 | serge | 768 | struct radeon_gem gem; |
1179 | serge | 769 | struct radeon_pm pm; |
770 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
||
1117 | serge | 771 | // struct mutex cs_mutex; |
772 | struct radeon_wb wb; |
||
1179 | serge | 773 | struct radeon_dummy_page dummy_page; |
1117 | serge | 774 | bool gpu_lockup; |
775 | bool shutdown; |
||
776 | bool suspend; |
||
1179 | serge | 777 | bool need_dma32; |
778 | bool accel_working; |
||
779 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
||
780 | const struct firmware *me_fw; /* all family ME firmware */ |
||
781 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
782 | struct r600_blit r600_blit; |
||
1268 | serge | 783 | int msi_enabled; /* msi enabled */ |
1117 | serge | 784 | }; |
785 | |||
786 | int radeon_device_init(struct radeon_device *rdev, |
||
787 | struct drm_device *ddev, |
||
788 | struct pci_dev *pdev, |
||
789 | uint32_t flags); |
||
790 | void radeon_device_fini(struct radeon_device *rdev); |
||
791 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
792 | |||
1179 | serge | 793 | /* r600 blit */ |
794 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); |
||
795 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); |
||
796 | void r600_kms_blit_copy(struct radeon_device *rdev, |
||
797 | u64 src_gpu_addr, u64 dst_gpu_addr, |
||
798 | int size_bytes); |
||
1117 | serge | 799 | |
1179 | serge | 800 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1117 | serge | 801 | { |
1179 | serge | 802 | if (reg < 0x10000) |
803 | return readl(((void __iomem *)rdev->rmmio) + reg); |
||
804 | else { |
||
805 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
806 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
807 | } |
||
1117 | serge | 808 | } |
809 | |||
1179 | serge | 810 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1117 | serge | 811 | { |
1179 | serge | 812 | if (reg < 0x10000) |
813 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
||
814 | else { |
||
815 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
816 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
817 | } |
||
1117 | serge | 818 | } |
819 | |||
820 | |||
821 | /* |
||
822 | * Registers read & write functions. |
||
823 | */ |
||
824 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
||
825 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
||
1179 | serge | 826 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
827 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
||
1117 | serge | 828 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
829 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
830 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
831 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
832 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
833 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 834 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
835 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
1117 | serge | 836 | #define WREG32_P(reg, val, mask) \ |
837 | do { \ |
||
838 | uint32_t tmp_ = RREG32(reg); \ |
||
839 | tmp_ &= (mask); \ |
||
840 | tmp_ |= ((val) & ~(mask)); \ |
||
841 | WREG32(reg, tmp_); \ |
||
842 | } while (0) |
||
843 | #define WREG32_PLL_P(reg, val, mask) \ |
||
844 | do { \ |
||
845 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
846 | tmp_ &= (mask); \ |
||
847 | tmp_ |= ((val) & ~(mask)); \ |
||
848 | WREG32_PLL(reg, tmp_); \ |
||
849 | } while (0) |
||
850 | |||
1179 | serge | 851 | /* |
852 | * Indirect registers accessor |
||
853 | */ |
||
854 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
855 | { |
||
856 | uint32_t r; |
||
1117 | serge | 857 | |
1179 | serge | 858 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
859 | r = RREG32(RADEON_PCIE_DATA); |
||
860 | return r; |
||
861 | } |
||
862 | |||
863 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
864 | { |
||
865 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
866 | WREG32(RADEON_PCIE_DATA, (v)); |
||
867 | } |
||
868 | |||
869 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
870 | |||
871 | |||
1117 | serge | 872 | /* |
873 | * ASICs helpers. |
||
874 | */ |
||
1179 | serge | 875 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
876 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 877 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
878 | (rdev->family == CHIP_RV200) || \ |
||
879 | (rdev->family == CHIP_RS100) || \ |
||
880 | (rdev->family == CHIP_RS200) || \ |
||
881 | (rdev->family == CHIP_RV250) || \ |
||
882 | (rdev->family == CHIP_RV280) || \ |
||
883 | (rdev->family == CHIP_RS300)) |
||
884 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
885 | (rdev->family == CHIP_RV350) || \ |
||
886 | (rdev->family == CHIP_R350) || \ |
||
887 | (rdev->family == CHIP_RV380) || \ |
||
888 | (rdev->family == CHIP_R420) || \ |
||
889 | (rdev->family == CHIP_R423) || \ |
||
890 | (rdev->family == CHIP_RV410) || \ |
||
891 | (rdev->family == CHIP_RS400) || \ |
||
892 | (rdev->family == CHIP_RS480)) |
||
893 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
||
894 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
||
895 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
896 | |||
897 | |||
898 | /* |
||
899 | * BIOS helpers. |
||
900 | */ |
||
901 | #define RBIOS8(i) (rdev->bios[i]) |
||
902 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
903 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
904 | |||
905 | int radeon_combios_init(struct radeon_device *rdev); |
||
906 | void radeon_combios_fini(struct radeon_device *rdev); |
||
907 | int radeon_atombios_init(struct radeon_device *rdev); |
||
908 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
909 | |||
910 | |||
911 | /* |
||
912 | * RING helpers. |
||
913 | */ |
||
914 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
||
915 | { |
||
916 | #if DRM_DEBUG_CODE |
||
917 | if (rdev->cp.count_dw <= 0) { |
||
918 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
||
919 | } |
||
920 | #endif |
||
921 | rdev->cp.ring[rdev->cp.wptr++] = v; |
||
922 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
||
923 | rdev->cp.count_dw--; |
||
924 | rdev->cp.ring_free_dw--; |
||
925 | } |
||
926 | |||
927 | |||
928 | /* |
||
929 | * ASICs macro. |
||
930 | */ |
||
931 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 932 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
933 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
934 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
1117 | serge | 935 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1179 | serge | 936 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1117 | serge | 937 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
938 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
||
939 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
||
1179 | serge | 940 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1117 | serge | 941 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1179 | serge | 942 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
943 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
||
1117 | serge | 944 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
945 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
||
1179 | serge | 946 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1117 | serge | 947 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
948 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
||
949 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
||
950 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
||
1268 | serge | 951 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1117 | serge | 952 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1268 | serge | 953 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1117 | serge | 954 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
955 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
||
956 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
||
1179 | serge | 957 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
958 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
||
959 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
||
1117 | serge | 960 | |
1179 | serge | 961 | /* Common functions */ |
962 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
||
963 | extern int radeon_modeset_init(struct radeon_device *rdev); |
||
964 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
965 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
966 | extern int radeon_clocks_init(struct radeon_device *rdev); |
||
967 | extern void radeon_clocks_fini(struct radeon_device *rdev); |
||
968 | extern void radeon_scratch_init(struct radeon_device *rdev); |
||
969 | extern void radeon_surface_init(struct radeon_device *rdev); |
||
970 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 971 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
972 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1117 | serge | 973 | |
1179 | serge | 974 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
975 | struct r100_mc_save { |
||
976 | u32 GENMO_WT; |
||
977 | u32 CRTC_EXT_CNTL; |
||
978 | u32 CRTC_GEN_CNTL; |
||
979 | u32 CRTC2_GEN_CNTL; |
||
980 | u32 CUR_OFFSET; |
||
981 | u32 CUR2_OFFSET; |
||
982 | }; |
||
983 | extern void r100_cp_disable(struct radeon_device *rdev); |
||
984 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
||
985 | extern void r100_cp_fini(struct radeon_device *rdev); |
||
986 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
||
987 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
||
988 | extern void r100_pci_gart_fini(struct radeon_device *rdev); |
||
989 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
||
990 | extern void r100_pci_gart_disable(struct radeon_device *rdev); |
||
991 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
||
992 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
||
993 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); |
||
994 | extern void r100_ib_fini(struct radeon_device *rdev); |
||
995 | extern int r100_ib_init(struct radeon_device *rdev); |
||
996 | extern void r100_irq_disable(struct radeon_device *rdev); |
||
997 | extern int r100_irq_set(struct radeon_device *rdev); |
||
998 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
||
999 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
||
1000 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
||
1001 | extern void r100_wb_disable(struct radeon_device *rdev); |
||
1002 | extern void r100_wb_fini(struct radeon_device *rdev); |
||
1003 | extern int r100_wb_init(struct radeon_device *rdev); |
||
1221 | serge | 1004 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1005 | extern int r100_rb2d_reset(struct radeon_device *rdev); |
||
1006 | extern int r100_cp_reset(struct radeon_device *rdev); |
||
1007 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
||
1008 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
||
1009 | struct radeon_cs_packet *pkt, |
||
1010 | struct radeon_object *robj); |
||
1011 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
||
1012 | struct radeon_cs_packet *pkt, |
||
1013 | const unsigned *auth, unsigned n, |
||
1014 | radeon_packet0_check_t check); |
||
1015 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, |
||
1016 | struct radeon_cs_packet *pkt, |
||
1017 | unsigned idx); |
||
1179 | serge | 1018 | |
1221 | serge | 1019 | /* rv200,rv250,rv280 */ |
1020 | extern void r200_set_safe_registers(struct radeon_device *rdev); |
||
1021 | |||
1179 | serge | 1022 | /* r300,r350,rv350,rv370,rv380 */ |
1023 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
||
1024 | extern void r300_mc_program(struct radeon_device *rdev); |
||
1025 | extern void r300_vram_info(struct radeon_device *rdev); |
||
1221 | serge | 1026 | extern void r300_clock_startup(struct radeon_device *rdev); |
1027 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
||
1179 | serge | 1028 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1029 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); |
||
1030 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); |
||
1031 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
||
1032 | |||
1033 | /* r420,r423,rv410 */ |
||
1221 | serge | 1034 | extern int r420_mc_init(struct radeon_device *rdev); |
1179 | serge | 1035 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1036 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
||
1037 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
||
1221 | serge | 1038 | extern void r420_pipes_init(struct radeon_device *rdev); |
1179 | serge | 1039 | |
1040 | /* rv515 */ |
||
1221 | serge | 1041 | struct rv515_mc_save { |
1042 | u32 d1vga_control; |
||
1043 | u32 d2vga_control; |
||
1044 | u32 vga_render_control; |
||
1045 | u32 vga_hdp_control; |
||
1046 | u32 d1crtc_control; |
||
1047 | u32 d2crtc_control; |
||
1048 | }; |
||
1179 | serge | 1049 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
1221 | serge | 1050 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1051 | extern void rv515_set_safe_registers(struct radeon_device *rdev); |
||
1052 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
||
1053 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); |
||
1054 | extern void rv515_clock_startup(struct radeon_device *rdev); |
||
1055 | extern void rv515_debugfs(struct radeon_device *rdev); |
||
1056 | extern int rv515_suspend(struct radeon_device *rdev); |
||
1179 | serge | 1057 | |
1221 | serge | 1058 | /* rs400 */ |
1059 | extern int rs400_gart_init(struct radeon_device *rdev); |
||
1060 | extern int rs400_gart_enable(struct radeon_device *rdev); |
||
1061 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); |
||
1062 | extern void rs400_gart_disable(struct radeon_device *rdev); |
||
1063 | extern void rs400_gart_fini(struct radeon_device *rdev); |
||
1064 | |||
1065 | /* rs600 */ |
||
1066 | extern void rs600_set_safe_registers(struct radeon_device *rdev); |
||
1067 | extern int rs600_irq_set(struct radeon_device *rdev); |
||
1068 | extern void rs600_irq_disable(struct radeon_device *rdev); |
||
1069 | |||
1179 | serge | 1070 | /* rs690, rs740 */ |
1071 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, |
||
1072 | struct drm_display_mode *mode1, |
||
1073 | struct drm_display_mode *mode2); |
||
1074 | |||
1075 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ |
||
1076 | extern bool r600_card_posted(struct radeon_device *rdev); |
||
1077 | extern void r600_cp_stop(struct radeon_device *rdev); |
||
1078 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
||
1079 | extern int r600_cp_resume(struct radeon_device *rdev); |
||
1080 | extern int r600_count_pipe_bits(uint32_t val); |
||
1081 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); |
||
1082 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
||
1083 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
||
1084 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
||
1085 | extern int r600_ib_test(struct radeon_device *rdev); |
||
1086 | extern int r600_ring_test(struct radeon_device *rdev); |
||
1087 | extern void r600_wb_fini(struct radeon_device *rdev); |
||
1221 | serge | 1088 | extern int r600_wb_enable(struct radeon_device *rdev); |
1089 | extern void r600_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1090 | extern void r600_scratch_init(struct radeon_device *rdev); |
1091 | extern int r600_blit_init(struct radeon_device *rdev); |
||
1092 | extern void r600_blit_fini(struct radeon_device *rdev); |
||
1093 | extern int r600_cp_init_microcode(struct radeon_device *rdev); |
||
1094 | extern int r600_gpu_reset(struct radeon_device *rdev); |
||
1095 | |||
1096 | |||
1097 | |||
1117 | serge | 1098 | #define DRM_UDELAY(d) udelay(d) |
1099 | |||
1100 | resource_size_t |
||
1101 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1102 | resource_size_t |
||
1103 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1104 | |||
1239 | serge | 1105 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1106 | mode_t *mode, bool strict); |
||
1117 | serge | 1107 | |
1179 | serge | 1108 | |
1117 | serge | 1109 | #endif=>><>><>><>><>>>>=> |