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1403 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Christian König. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Christian König |
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25 | */ |
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26 | #include "drmP.h" |
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27 | #include "radeon_drm.h" |
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28 | #include "radeon.h" |
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29 | #include "atom.h" |
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30 | |||
31 | /* |
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32 | * HDMI color format |
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33 | */ |
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34 | enum r600_hdmi_color_format { |
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35 | RGB = 0, |
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36 | YCC_422 = 1, |
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37 | YCC_444 = 2 |
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38 | }; |
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39 | |||
40 | /* |
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41 | * IEC60958 status bits |
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42 | */ |
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43 | enum r600_hdmi_iec_status_bits { |
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44 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
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45 | AUDIO_STATUS_V = 0x02, |
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46 | AUDIO_STATUS_VCFG = 0x04, |
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47 | AUDIO_STATUS_EMPHASIS = 0x08, |
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48 | AUDIO_STATUS_COPYRIGHT = 0x10, |
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49 | AUDIO_STATUS_NONAUDIO = 0x20, |
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50 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
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51 | AUDIO_STATUS_LEVEL = 0x80 |
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52 | }; |
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53 | |||
54 | struct { |
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55 | uint32_t Clock; |
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56 | |||
57 | int N_32kHz; |
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58 | int CTS_32kHz; |
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59 | |||
60 | int N_44_1kHz; |
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61 | int CTS_44_1kHz; |
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62 | |||
63 | int N_48kHz; |
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64 | int CTS_48kHz; |
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65 | |||
66 | } r600_hdmi_ACR[] = { |
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67 | /* 32kHz 44.1kHz 48kHz */ |
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68 | /* Clock N CTS N CTS N CTS */ |
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69 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ |
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70 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
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71 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
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72 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
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73 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
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74 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
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75 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ |
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76 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
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77 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ |
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78 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
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79 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ |
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80 | }; |
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81 | |||
82 | /* |
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83 | * calculate CTS value if it's not found in the table |
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84 | */ |
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85 | static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) |
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86 | { |
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87 | if (*CTS == 0) |
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88 | *CTS = clock*N/(128*freq)*1000; |
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89 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
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90 | N, *CTS, freq); |
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91 | } |
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92 | |||
93 | /* |
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94 | * update the N and CTS parameters for a given pixel clock rate |
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95 | */ |
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96 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
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97 | { |
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98 | struct drm_device *dev = encoder->dev; |
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99 | struct radeon_device *rdev = dev->dev_private; |
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100 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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101 | int CTS; |
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102 | int N; |
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103 | int i; |
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104 | |||
105 | for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++); |
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106 | |||
107 | CTS = r600_hdmi_ACR[i].CTS_32kHz; |
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108 | N = r600_hdmi_ACR[i].N_32kHz; |
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109 | r600_hdmi_calc_CTS(clock, &CTS, N, 32000); |
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110 | WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12); |
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111 | WREG32(offset+R600_HDMI_32kHz_N, N); |
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112 | |||
113 | CTS = r600_hdmi_ACR[i].CTS_44_1kHz; |
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114 | N = r600_hdmi_ACR[i].N_44_1kHz; |
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115 | r600_hdmi_calc_CTS(clock, &CTS, N, 44100); |
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116 | WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12); |
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117 | WREG32(offset+R600_HDMI_44_1kHz_N, N); |
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118 | |||
119 | CTS = r600_hdmi_ACR[i].CTS_48kHz; |
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120 | N = r600_hdmi_ACR[i].N_48kHz; |
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121 | r600_hdmi_calc_CTS(clock, &CTS, N, 48000); |
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122 | WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12); |
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123 | WREG32(offset+R600_HDMI_48kHz_N, N); |
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124 | } |
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125 | |||
126 | /* |
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127 | * calculate the crc for a given info frame |
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128 | */ |
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129 | static void r600_hdmi_infoframe_checksum(uint8_t packetType, |
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130 | uint8_t versionNumber, |
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131 | uint8_t length, |
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132 | uint8_t *frame) |
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133 | { |
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134 | int i; |
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135 | frame[0] = packetType + versionNumber + length; |
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136 | for (i = 1; i <= length; i++) |
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137 | frame[0] += frame[i]; |
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138 | frame[0] = 0x100 - frame[0]; |
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139 | } |
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140 | |||
141 | /* |
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142 | * build a HDMI Video Info Frame |
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143 | */ |
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144 | static void r600_hdmi_videoinfoframe( |
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145 | struct drm_encoder *encoder, |
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146 | enum r600_hdmi_color_format color_format, |
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147 | int active_information_present, |
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148 | uint8_t active_format_aspect_ratio, |
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149 | uint8_t scan_information, |
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150 | uint8_t colorimetry, |
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151 | uint8_t ex_colorimetry, |
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152 | uint8_t quantization, |
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153 | int ITC, |
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154 | uint8_t picture_aspect_ratio, |
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155 | uint8_t video_format_identification, |
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156 | uint8_t pixel_repetition, |
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157 | uint8_t non_uniform_picture_scaling, |
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158 | uint8_t bar_info_data_valid, |
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159 | uint16_t top_bar, |
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160 | uint16_t bottom_bar, |
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161 | uint16_t left_bar, |
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162 | uint16_t right_bar |
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163 | ) |
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164 | { |
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165 | struct drm_device *dev = encoder->dev; |
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166 | struct radeon_device *rdev = dev->dev_private; |
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167 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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168 | |||
169 | uint8_t frame[14]; |
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170 | |||
171 | frame[0x0] = 0; |
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172 | frame[0x1] = |
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173 | (scan_information & 0x3) | |
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174 | ((bar_info_data_valid & 0x3) << 2) | |
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175 | ((active_information_present & 0x1) << 4) | |
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176 | ((color_format & 0x3) << 5); |
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177 | frame[0x2] = |
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178 | (active_format_aspect_ratio & 0xF) | |
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179 | ((picture_aspect_ratio & 0x3) << 4) | |
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180 | ((colorimetry & 0x3) << 6); |
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181 | frame[0x3] = |
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182 | (non_uniform_picture_scaling & 0x3) | |
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183 | ((quantization & 0x3) << 2) | |
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184 | ((ex_colorimetry & 0x7) << 4) | |
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185 | ((ITC & 0x1) << 7); |
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186 | frame[0x4] = (video_format_identification & 0x7F); |
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187 | frame[0x5] = (pixel_repetition & 0xF); |
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188 | frame[0x6] = (top_bar & 0xFF); |
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189 | frame[0x7] = (top_bar >> 8); |
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190 | frame[0x8] = (bottom_bar & 0xFF); |
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191 | frame[0x9] = (bottom_bar >> 8); |
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192 | frame[0xA] = (left_bar & 0xFF); |
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193 | frame[0xB] = (left_bar >> 8); |
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194 | frame[0xC] = (right_bar & 0xFF); |
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195 | frame[0xD] = (right_bar >> 8); |
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196 | |||
197 | r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); |
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198 | |||
199 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0, |
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200 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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201 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1, |
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202 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
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203 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2, |
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204 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
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205 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3, |
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206 | frame[0xC] | (frame[0xD] << 8)); |
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207 | } |
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208 | |||
209 | /* |
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210 | * build a Audio Info Frame |
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211 | */ |
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212 | static void r600_hdmi_audioinfoframe( |
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213 | struct drm_encoder *encoder, |
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214 | uint8_t channel_count, |
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215 | uint8_t coding_type, |
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216 | uint8_t sample_size, |
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217 | uint8_t sample_frequency, |
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218 | uint8_t format, |
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219 | uint8_t channel_allocation, |
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220 | uint8_t level_shift, |
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221 | int downmix_inhibit |
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222 | ) |
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223 | { |
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224 | struct drm_device *dev = encoder->dev; |
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225 | struct radeon_device *rdev = dev->dev_private; |
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226 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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227 | |||
228 | uint8_t frame[11]; |
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229 | |||
230 | frame[0x0] = 0; |
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231 | frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); |
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232 | frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); |
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233 | frame[0x3] = format; |
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234 | frame[0x4] = channel_allocation; |
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235 | frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); |
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236 | frame[0x6] = 0; |
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237 | frame[0x7] = 0; |
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238 | frame[0x8] = 0; |
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239 | frame[0x9] = 0; |
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240 | frame[0xA] = 0; |
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241 | |||
242 | r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); |
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243 | |||
244 | WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0, |
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245 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
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246 | WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1, |
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247 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
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248 | } |
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249 | |||
250 | /* |
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251 | * test if audio buffer is filled enough to start playing |
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252 | */ |
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253 | static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
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254 | { |
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255 | struct drm_device *dev = encoder->dev; |
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256 | struct radeon_device *rdev = dev->dev_private; |
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257 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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258 | |||
259 | return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0; |
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260 | } |
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261 | |||
262 | /* |
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263 | * have buffer status changed since last call? |
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264 | */ |
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265 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
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266 | { |
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267 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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268 | int status, result; |
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269 | |||
270 | if (!radeon_encoder->hdmi_offset) |
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271 | return 0; |
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272 | |||
273 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
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274 | result = radeon_encoder->hdmi_buffer_status != status; |
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275 | radeon_encoder->hdmi_buffer_status = status; |
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276 | |||
277 | return result; |
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278 | } |
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279 | |||
280 | /* |
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281 | * write the audio workaround status to the hardware |
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282 | */ |
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283 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
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284 | { |
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285 | struct drm_device *dev = encoder->dev; |
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286 | struct radeon_device *rdev = dev->dev_private; |
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287 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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288 | uint32_t offset = radeon_encoder->hdmi_offset; |
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289 | |||
290 | if (!offset) |
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291 | return; |
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292 | |||
293 | if (r600_hdmi_is_audio_buffer_filled(encoder)) { |
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294 | /* disable audio workaround and start delivering of audio frames */ |
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295 | WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); |
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296 | |||
297 | } else if (radeon_encoder->hdmi_audio_workaround) { |
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298 | /* enable audio workaround and start delivering of audio frames */ |
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299 | WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); |
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300 | |||
301 | } else { |
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302 | /* disable audio workaround and stop delivering of audio frames */ |
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303 | WREG32_P(offset+R600_HDMI_CNTL, 0x00000000, ~0x00001001); |
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304 | } |
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305 | } |
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306 | |||
307 | |||
308 | /* |
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309 | * update the info frames with the data from the current display mode |
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310 | */ |
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311 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
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312 | { |
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313 | struct drm_device *dev = encoder->dev; |
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314 | struct radeon_device *rdev = dev->dev_private; |
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315 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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316 | |||
317 | if (!offset) |
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318 | return; |
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319 | |||
320 | r600_audio_set_clock(encoder, mode->clock); |
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321 | |||
322 | WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000); |
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323 | WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0); |
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324 | WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000); |
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325 | |||
326 | r600_hdmi_update_ACR(encoder, mode->clock); |
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327 | |||
328 | WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13); |
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329 | |||
330 | WREG32(offset+R600_HDMI_VERSION, 0x202); |
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331 | |||
332 | r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, |
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333 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); |
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334 | |||
335 | /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */ |
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336 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); |
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337 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); |
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338 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); |
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339 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001); |
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340 | |||
341 | r600_hdmi_audio_workaround(encoder); |
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342 | |||
343 | /* audio packets per line, does anyone know how to calc this ? */ |
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344 | WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); |
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345 | |||
346 | /* update? reset? don't realy know */ |
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347 | WREG32_P(offset+R600_HDMI_CNTL, 0x14000000, ~0x14000000); |
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348 | } |
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349 | |||
350 | /* |
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351 | * update settings with current parameters from audio engine |
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352 | */ |
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353 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, |
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354 | int channels, |
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355 | int rate, |
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356 | int bps, |
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357 | uint8_t status_bits, |
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358 | uint8_t category_code) |
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359 | { |
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360 | struct drm_device *dev = encoder->dev; |
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361 | struct radeon_device *rdev = dev->dev_private; |
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362 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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363 | |||
364 | uint32_t iec; |
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365 | |||
366 | if (!offset) |
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367 | return; |
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368 | |||
369 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
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370 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
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371 | channels, rate, bps); |
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372 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
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373 | (int)status_bits, (int)category_code); |
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374 | |||
375 | iec = 0; |
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376 | if (status_bits & AUDIO_STATUS_PROFESSIONAL) |
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377 | iec |= 1 << 0; |
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378 | if (status_bits & AUDIO_STATUS_NONAUDIO) |
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379 | iec |= 1 << 1; |
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380 | if (status_bits & AUDIO_STATUS_COPYRIGHT) |
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381 | iec |= 1 << 2; |
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382 | if (status_bits & AUDIO_STATUS_EMPHASIS) |
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383 | iec |= 1 << 3; |
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384 | |||
385 | iec |= category_code << 8; |
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386 | |||
387 | switch (rate) { |
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388 | case 32000: iec |= 0x3 << 24; break; |
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389 | case 44100: iec |= 0x0 << 24; break; |
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390 | case 88200: iec |= 0x8 << 24; break; |
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391 | case 176400: iec |= 0xc << 24; break; |
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392 | case 48000: iec |= 0x2 << 24; break; |
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393 | case 96000: iec |= 0xa << 24; break; |
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394 | case 192000: iec |= 0xe << 24; break; |
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395 | } |
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396 | |||
397 | WREG32(offset+R600_HDMI_IEC60958_1, iec); |
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398 | |||
399 | iec = 0; |
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400 | switch (bps) { |
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401 | case 16: iec |= 0x2; break; |
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402 | case 20: iec |= 0x3; break; |
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403 | case 24: iec |= 0xb; break; |
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404 | } |
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405 | if (status_bits & AUDIO_STATUS_V) |
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406 | iec |= 0x5 << 16; |
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407 | |||
408 | WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f); |
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409 | |||
410 | /* 0x021 or 0x031 sets the audio frame length */ |
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411 | WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31); |
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412 | r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); |
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413 | |||
414 | r600_hdmi_audio_workaround(encoder); |
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415 | |||
416 | /* update? reset? don't realy know */ |
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417 | WREG32_P(offset+R600_HDMI_CNTL, 0x04000000, ~0x04000000); |
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418 | } |
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419 | |||
420 | /* |
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421 | * enable/disable the HDMI engine |
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422 | */ |
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423 | void r600_hdmi_enable(struct drm_encoder *encoder, int enable) |
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424 | { |
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425 | struct drm_device *dev = encoder->dev; |
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426 | struct radeon_device *rdev = dev->dev_private; |
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427 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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428 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
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429 | |||
430 | if (!offset) |
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431 | return; |
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432 | |||
433 | DRM_DEBUG("%s HDMI interface @ 0x%04X\n", enable ? "Enabling" : "Disabling", offset); |
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434 | |||
435 | /* some version of atombios ignore the enable HDMI flag |
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436 | * so enabling/disabling HDMI was moved here for TMDS1+2 */ |
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437 | switch (radeon_encoder->encoder_id) { |
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438 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
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439 | WREG32_P(AVIVO_TMDSA_CNTL, enable ? 0x4 : 0x0, ~0x4); |
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440 | WREG32(offset+R600_HDMI_ENABLE, enable ? 0x101 : 0x0); |
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441 | break; |
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442 | |||
443 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
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444 | WREG32_P(AVIVO_LVTMA_CNTL, enable ? 0x4 : 0x0, ~0x4); |
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445 | WREG32(offset+R600_HDMI_ENABLE, enable ? 0x105 : 0x0); |
||
446 | break; |
||
447 | |||
448 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
||
449 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
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450 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
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451 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
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452 | /* This part is doubtfull in my opinion */ |
||
453 | WREG32(offset+R600_HDMI_ENABLE, enable ? 0x110 : 0x0); |
||
454 | break; |
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455 | |||
456 | default: |
||
457 | DRM_ERROR("unknown HDMI output type\n"); |
||
458 | break; |
||
459 | } |
||
460 | } |
||
461 | |||
462 | /* |
||
463 | * determin at which register offset the HDMI encoder is |
||
464 | */ |
||
465 | void r600_hdmi_init(struct drm_encoder *encoder) |
||
466 | { |
||
467 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
468 | |||
469 | switch (radeon_encoder->encoder_id) { |
||
470 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
||
471 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
||
472 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
||
473 | radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; |
||
474 | break; |
||
475 | |||
476 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
||
477 | switch (r600_audio_tmds_index(encoder)) { |
||
478 | case 0: |
||
479 | radeon_encoder->hdmi_offset = R600_HDMI_TMDS1; |
||
480 | break; |
||
481 | case 1: |
||
482 | radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; |
||
483 | break; |
||
484 | default: |
||
485 | radeon_encoder->hdmi_offset = 0; |
||
486 | break; |
||
487 | } |
||
488 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
||
489 | radeon_encoder->hdmi_offset = R600_HDMI_TMDS2; |
||
490 | break; |
||
491 | |||
492 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
||
493 | radeon_encoder->hdmi_offset = R600_HDMI_DIG; |
||
494 | break; |
||
495 | |||
496 | default: |
||
497 | radeon_encoder->hdmi_offset = 0; |
||
498 | break; |
||
499 | } |
||
500 | |||
501 | DRM_DEBUG("using HDMI engine at offset 0x%04X for encoder 0x%x\n", |
||
502 | radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); |
||
503 | |||
504 | /* TODO: make this configureable */ |
||
505 | radeon_encoder->hdmi_audio_workaround = 0; |
||
506 | }><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>=>><>><>><> |