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| Rev | Author | Line No. | Line |
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| 1117 | serge | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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| 3 | * Copyright 2008 Red Hat Inc. |
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| 4 | * Copyright 2009 Jerome Glisse. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Authors: Dave Airlie |
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| 25 | * Alex Deucher |
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| 26 | * Jerome Glisse |
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| 27 | */ |
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| 1125 | serge | 28 | #include "drmP.h" |
| 1117 | serge | 29 | #include "radeon_reg.h" |
| 30 | #include "radeon.h" |
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| 31 | |||
| 32 | /* r520,rv530,rv560,rv570,r580 depends on : */ |
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| 33 | void r100_hdp_reset(struct radeon_device *rdev); |
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| 34 | void r420_pipes_init(struct radeon_device *rdev); |
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| 35 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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| 36 | void rs600_disable_vga(struct radeon_device *rdev); |
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| 37 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
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| 38 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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| 39 | |||
| 40 | /* This files gather functions specifics to: |
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| 41 | * r520,rv530,rv560,rv570,r580 |
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| 42 | * |
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| 43 | * Some of these functions might be used by newer ASICs. |
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| 44 | */ |
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| 45 | void r520_gpu_init(struct radeon_device *rdev); |
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| 46 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
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| 47 | |||
| 1179 | serge | 48 | |
| 1117 | serge | 49 | /* |
| 50 | * MC |
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| 51 | */ |
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| 52 | int r520_mc_init(struct radeon_device *rdev) |
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| 53 | { |
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| 54 | uint32_t tmp; |
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| 55 | int r; |
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| 56 | |||
| 1179 | serge | 57 | ENTER(); |
| 1117 | serge | 58 | |
| 1129 | serge | 59 | if (r100_debugfs_rbbm_init(rdev)) { |
| 60 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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| 61 | } |
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| 62 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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| 63 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 64 | } |
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| 65 | if (rv515_debugfs_ga_info_init(rdev)) { |
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| 66 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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| 67 | } |
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| 1119 | serge | 68 | |
| 1117 | serge | 69 | r520_gpu_init(rdev); |
| 70 | rv370_pcie_gart_disable(rdev); |
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| 71 | |||
| 72 | /* Setup GPU memory space */ |
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| 73 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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| 74 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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| 75 | r = radeon_mc_setup(rdev); |
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| 76 | if (r) { |
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| 77 | return r; |
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| 78 | } |
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| 79 | |||
| 80 | /* Program GPU memory space */ |
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| 1119 | serge | 81 | rs600_mc_disable_clients(rdev); |
| 82 | if (r520_mc_wait_for_idle(rdev)) { |
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| 83 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 1117 | serge | 84 | "programming pipes. Bad things might happen.\n"); |
| 85 | } |
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| 86 | /* Write VRAM size in case we are limiting it */ |
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| 1179 | serge | 87 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| 88 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
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| 1117 | serge | 89 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
| 90 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
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| 91 | WREG32_MC(R520_MC_FB_LOCATION, tmp); |
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| 92 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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| 93 | WREG32(0x310, rdev->mc.vram_location); |
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| 94 | if (rdev->flags & RADEON_IS_AGP) { |
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| 95 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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| 96 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
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| 97 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
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| 98 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
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| 99 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
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| 100 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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| 101 | } else { |
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| 102 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
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| 103 | WREG32_MC(R520_MC_AGP_BASE, 0); |
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| 104 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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| 105 | } |
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| 1119 | serge | 106 | |
| 1179 | serge | 107 | LEAVE(); |
| 1119 | serge | 108 | |
| 1117 | serge | 109 | return 0; |
| 110 | } |
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| 111 | |||
| 112 | void r520_mc_fini(struct radeon_device *rdev) |
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| 113 | { |
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| 114 | } |
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| 115 | |||
| 116 | |||
| 117 | /* |
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| 118 | * Global GPU functions |
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| 119 | */ |
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| 120 | void r520_errata(struct radeon_device *rdev) |
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| 121 | { |
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| 122 | rdev->pll_errata = 0; |
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| 123 | } |
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| 124 | |||
| 125 | int r520_mc_wait_for_idle(struct radeon_device *rdev) |
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| 126 | { |
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| 127 | unsigned i; |
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| 128 | uint32_t tmp; |
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| 129 | |||
| 130 | for (i = 0; i < rdev->usec_timeout; i++) { |
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| 131 | /* read MC_STATUS */ |
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| 132 | tmp = RREG32_MC(R520_MC_STATUS); |
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| 133 | if (tmp & R520_MC_STATUS_IDLE) { |
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| 134 | return 0; |
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| 135 | } |
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| 136 | DRM_UDELAY(1); |
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| 137 | } |
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| 138 | return -1; |
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| 139 | } |
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| 140 | |||
| 141 | void r520_gpu_init(struct radeon_device *rdev) |
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| 142 | { |
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| 143 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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| 1179 | serge | 144 | ENTER(); |
| 1117 | serge | 145 | |
| 146 | r100_hdp_reset(rdev); |
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| 147 | rs600_disable_vga(rdev); |
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| 148 | /* |
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| 149 | * DST_PIPE_CONFIG 0x170C |
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| 150 | * GB_TILE_CONFIG 0x4018 |
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| 151 | * GB_FIFO_SIZE 0x4024 |
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| 152 | * GB_PIPE_SELECT 0x402C |
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| 153 | * GB_PIPE_SELECT2 0x4124 |
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| 154 | * Z_PIPE_SHIFT 0 |
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| 155 | * Z_PIPE_MASK 0x000000003 |
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| 156 | * GB_FIFO_SIZE2 0x4128 |
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| 157 | * SC_SFIFO_SIZE_SHIFT 0 |
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| 158 | * SC_SFIFO_SIZE_MASK 0x000000003 |
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| 159 | * SC_MFIFO_SIZE_SHIFT 2 |
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| 160 | * SC_MFIFO_SIZE_MASK 0x00000000C |
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| 161 | * FG_SFIFO_SIZE_SHIFT 4 |
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| 162 | * FG_SFIFO_SIZE_MASK 0x000000030 |
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| 163 | * ZB_MFIFO_SIZE_SHIFT 6 |
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| 164 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
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| 165 | * GA_ENHANCE 0x4274 |
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| 166 | * SU_REG_DEST 0x42C8 |
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| 167 | */ |
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| 168 | /* workaround for RV530 */ |
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| 169 | if (rdev->family == CHIP_RV530) { |
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| 170 | WREG32(0x4128, 0xFF); |
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| 171 | } |
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| 172 | r420_pipes_init(rdev); |
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| 173 | gb_pipe_select = RREG32(0x402C); |
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| 174 | tmp = RREG32(0x170C); |
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| 175 | pipe_select_current = (tmp >> 2) & 3; |
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| 176 | tmp = (1 << pipe_select_current) | |
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| 177 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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| 178 | WREG32_PLL(0x000D, tmp); |
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| 179 | if (r520_mc_wait_for_idle(rdev)) { |
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| 180 | printk(KERN_WARNING "Failed to wait MC idle while " |
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| 181 | "programming pipes. Bad things might happen.\n"); |
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| 182 | } |
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| 183 | } |
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| 184 | |||
| 185 | |||
| 186 | /* |
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| 187 | * VRAM info |
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| 188 | */ |
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| 189 | static void r520_vram_get_type(struct radeon_device *rdev) |
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| 190 | { |
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| 191 | uint32_t tmp; |
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| 1179 | serge | 192 | ENTER(); |
| 1117 | serge | 193 | |
| 194 | rdev->mc.vram_width = 128; |
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| 195 | rdev->mc.vram_is_ddr = true; |
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| 196 | tmp = RREG32_MC(R520_MC_CNTL0); |
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| 197 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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| 198 | case 0: |
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| 199 | rdev->mc.vram_width = 32; |
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| 200 | break; |
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| 201 | case 1: |
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| 202 | rdev->mc.vram_width = 64; |
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| 203 | break; |
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| 204 | case 2: |
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| 205 | rdev->mc.vram_width = 128; |
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| 206 | break; |
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| 207 | case 3: |
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| 208 | rdev->mc.vram_width = 256; |
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| 209 | break; |
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| 210 | default: |
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| 211 | rdev->mc.vram_width = 128; |
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| 212 | break; |
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| 213 | } |
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| 214 | if (tmp & R520_MC_CHANNEL_SIZE) |
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| 215 | rdev->mc.vram_width *= 2; |
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| 216 | } |
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| 217 | |||
| 218 | void r520_vram_info(struct radeon_device *rdev) |
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| 219 | { |
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| 1179 | serge | 220 | fixed20_12 a; |
| 221 | |||
| 1117 | serge | 222 | r520_vram_get_type(rdev); |
| 223 | |||
| 1179 | serge | 224 | r100_vram_init_sizes(rdev); |
| 225 | /* FIXME: we should enforce default clock in case GPU is not in |
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| 226 | * default setup |
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| 227 | */ |
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| 228 | a.full = rfixed_const(100); |
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| 229 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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| 230 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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| 1117 | serge | 231 | } |
| 232 | |||
| 1179 | serge | 233 | void r520_bandwidth_update(struct radeon_device *rdev) |
| 1119 | serge | 234 | { |
| 1179 | serge | 235 | rv515_bandwidth_avivo_update(rdev); |
| 1119 | serge | 236 | } |