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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1125 | serge | 28 | #include "drmP.h" |
1117 | serge | 29 | #include "radeon_reg.h" |
30 | #include "radeon.h" |
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31 | |||
32 | /* r520,rv530,rv560,rv570,r580 depends on : */ |
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33 | void r100_hdp_reset(struct radeon_device *rdev); |
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34 | int rv370_pcie_gart_enable(struct radeon_device *rdev); |
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35 | void rv370_pcie_gart_disable(struct radeon_device *rdev); |
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36 | void r420_pipes_init(struct radeon_device *rdev); |
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37 | void rs600_mc_disable_clients(struct radeon_device *rdev); |
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38 | void rs600_disable_vga(struct radeon_device *rdev); |
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39 | int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
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40 | int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
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41 | |||
42 | /* This files gather functions specifics to: |
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43 | * r520,rv530,rv560,rv570,r580 |
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44 | * |
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45 | * Some of these functions might be used by newer ASICs. |
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46 | */ |
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47 | void r520_gpu_init(struct radeon_device *rdev); |
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48 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
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49 | |||
50 | /* |
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51 | * MC |
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52 | */ |
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53 | int r520_mc_init(struct radeon_device *rdev) |
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54 | { |
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55 | uint32_t tmp; |
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56 | int r; |
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57 | |||
1119 | serge | 58 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 59 | |
1129 | serge | 60 | if (r100_debugfs_rbbm_init(rdev)) { |
61 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
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62 | } |
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63 | if (rv515_debugfs_pipes_info_init(rdev)) { |
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64 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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65 | } |
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66 | if (rv515_debugfs_ga_info_init(rdev)) { |
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67 | DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
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68 | } |
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1119 | serge | 69 | |
1117 | serge | 70 | r520_gpu_init(rdev); |
71 | rv370_pcie_gart_disable(rdev); |
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72 | |||
73 | /* Setup GPU memory space */ |
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74 | rdev->mc.vram_location = 0xFFFFFFFFUL; |
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75 | rdev->mc.gtt_location = 0xFFFFFFFFUL; |
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76 | if (rdev->flags & RADEON_IS_AGP) { |
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77 | r = radeon_agp_init(rdev); |
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78 | if (r) { |
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79 | printk(KERN_WARNING "[drm] Disabling AGP\n"); |
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80 | rdev->flags &= ~RADEON_IS_AGP; |
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81 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
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82 | } else { |
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83 | rdev->mc.gtt_location = rdev->mc.agp_base; |
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84 | } |
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85 | } |
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86 | r = radeon_mc_setup(rdev); |
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87 | if (r) { |
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88 | return r; |
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89 | } |
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90 | |||
91 | /* Program GPU memory space */ |
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1119 | serge | 92 | rs600_mc_disable_clients(rdev); |
93 | if (r520_mc_wait_for_idle(rdev)) { |
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94 | printk(KERN_WARNING "Failed to wait MC idle while " |
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1117 | serge | 95 | "programming pipes. Bad things might happen.\n"); |
96 | } |
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97 | /* Write VRAM size in case we are limiting it */ |
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98 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
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99 | tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
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100 | tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
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101 | tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
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102 | WREG32_MC(R520_MC_FB_LOCATION, tmp); |
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103 | WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
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104 | WREG32(0x310, rdev->mc.vram_location); |
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105 | if (rdev->flags & RADEON_IS_AGP) { |
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106 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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107 | tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
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108 | tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
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109 | WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
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110 | WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
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111 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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112 | } else { |
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113 | WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
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114 | WREG32_MC(R520_MC_AGP_BASE, 0); |
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115 | WREG32_MC(R520_MC_AGP_BASE_2, 0); |
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116 | } |
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1119 | serge | 117 | |
118 | dbgprintf("done: %s\n",__FUNCTION__); |
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119 | |||
1117 | serge | 120 | return 0; |
121 | } |
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122 | |||
123 | void r520_mc_fini(struct radeon_device *rdev) |
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124 | { |
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125 | rv370_pcie_gart_disable(rdev); |
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126 | radeon_gart_table_vram_free(rdev); |
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127 | radeon_gart_fini(rdev); |
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128 | } |
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129 | |||
130 | |||
131 | /* |
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132 | * Global GPU functions |
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133 | */ |
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134 | void r520_errata(struct radeon_device *rdev) |
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135 | { |
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136 | rdev->pll_errata = 0; |
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137 | } |
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138 | |||
139 | int r520_mc_wait_for_idle(struct radeon_device *rdev) |
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140 | { |
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141 | unsigned i; |
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142 | uint32_t tmp; |
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143 | |||
144 | for (i = 0; i < rdev->usec_timeout; i++) { |
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145 | /* read MC_STATUS */ |
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146 | tmp = RREG32_MC(R520_MC_STATUS); |
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147 | if (tmp & R520_MC_STATUS_IDLE) { |
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148 | return 0; |
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149 | } |
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150 | DRM_UDELAY(1); |
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151 | } |
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152 | return -1; |
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153 | } |
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154 | |||
155 | void r520_gpu_init(struct radeon_device *rdev) |
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156 | { |
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157 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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1120 | serge | 158 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 159 | |
160 | r100_hdp_reset(rdev); |
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161 | rs600_disable_vga(rdev); |
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162 | /* |
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163 | * DST_PIPE_CONFIG 0x170C |
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164 | * GB_TILE_CONFIG 0x4018 |
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165 | * GB_FIFO_SIZE 0x4024 |
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166 | * GB_PIPE_SELECT 0x402C |
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167 | * GB_PIPE_SELECT2 0x4124 |
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168 | * Z_PIPE_SHIFT 0 |
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169 | * Z_PIPE_MASK 0x000000003 |
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170 | * GB_FIFO_SIZE2 0x4128 |
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171 | * SC_SFIFO_SIZE_SHIFT 0 |
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172 | * SC_SFIFO_SIZE_MASK 0x000000003 |
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173 | * SC_MFIFO_SIZE_SHIFT 2 |
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174 | * SC_MFIFO_SIZE_MASK 0x00000000C |
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175 | * FG_SFIFO_SIZE_SHIFT 4 |
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176 | * FG_SFIFO_SIZE_MASK 0x000000030 |
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177 | * ZB_MFIFO_SIZE_SHIFT 6 |
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178 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
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179 | * GA_ENHANCE 0x4274 |
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180 | * SU_REG_DEST 0x42C8 |
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181 | */ |
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182 | /* workaround for RV530 */ |
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183 | if (rdev->family == CHIP_RV530) { |
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184 | WREG32(0x4124, 1); |
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185 | WREG32(0x4128, 0xFF); |
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186 | } |
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187 | r420_pipes_init(rdev); |
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188 | gb_pipe_select = RREG32(0x402C); |
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189 | tmp = RREG32(0x170C); |
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190 | pipe_select_current = (tmp >> 2) & 3; |
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191 | tmp = (1 << pipe_select_current) | |
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192 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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193 | WREG32_PLL(0x000D, tmp); |
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194 | if (r520_mc_wait_for_idle(rdev)) { |
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195 | printk(KERN_WARNING "Failed to wait MC idle while " |
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196 | "programming pipes. Bad things might happen.\n"); |
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197 | } |
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198 | } |
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199 | |||
200 | |||
201 | /* |
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202 | * VRAM info |
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203 | */ |
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204 | static void r520_vram_get_type(struct radeon_device *rdev) |
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205 | { |
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206 | uint32_t tmp; |
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1120 | serge | 207 | dbgprintf("%s\n",__FUNCTION__); |
1117 | serge | 208 | |
209 | rdev->mc.vram_width = 128; |
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210 | rdev->mc.vram_is_ddr = true; |
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211 | tmp = RREG32_MC(R520_MC_CNTL0); |
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212 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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213 | case 0: |
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214 | rdev->mc.vram_width = 32; |
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215 | break; |
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216 | case 1: |
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217 | rdev->mc.vram_width = 64; |
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218 | break; |
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219 | case 2: |
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220 | rdev->mc.vram_width = 128; |
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221 | break; |
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222 | case 3: |
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223 | rdev->mc.vram_width = 256; |
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224 | break; |
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225 | default: |
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226 | rdev->mc.vram_width = 128; |
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227 | break; |
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228 | } |
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229 | if (tmp & R520_MC_CHANNEL_SIZE) |
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230 | rdev->mc.vram_width *= 2; |
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231 | } |
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232 | |||
233 | void r520_vram_info(struct radeon_device *rdev) |
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234 | { |
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235 | r520_vram_get_type(rdev); |
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236 | rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
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237 | |||
238 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
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239 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
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240 | } |
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241 | |||
1119 | serge | 242 | |
243 | int radeon_agp_init(struct radeon_device *rdev) |
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244 | { |
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245 | |||
1120 | serge | 246 | dbgprintf("%s\n",__FUNCTION__); |
1119 | serge | 247 | |
248 | #if __OS_HAS_AGP |
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249 | struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list; |
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250 | struct drm_agp_mode mode; |
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251 | struct drm_agp_info info; |
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252 | uint32_t agp_status; |
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253 | int default_mode; |
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254 | bool is_v3; |
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255 | int ret; |
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256 | |||
257 | /* Acquire AGP. */ |
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258 | if (!rdev->ddev->agp->acquired) { |
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259 | ret = drm_agp_acquire(rdev->ddev); |
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260 | if (ret) { |
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261 | DRM_ERROR("Unable to acquire AGP: %d\n", ret); |
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262 | return ret; |
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263 | } |
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264 | } |
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265 | |||
266 | ret = drm_agp_info(rdev->ddev, &info); |
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267 | if (ret) { |
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268 | DRM_ERROR("Unable to get AGP info: %d\n", ret); |
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269 | return ret; |
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270 | } |
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271 | mode.mode = info.mode; |
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272 | agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; |
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273 | is_v3 = !!(agp_status & RADEON_AGPv3_MODE); |
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274 | |||
275 | if (is_v3) { |
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276 | default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; |
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277 | } else { |
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278 | if (agp_status & RADEON_AGP_4X_MODE) { |
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279 | default_mode = 4; |
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280 | } else if (agp_status & RADEON_AGP_2X_MODE) { |
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281 | default_mode = 2; |
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282 | } else { |
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283 | default_mode = 1; |
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284 | } |
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285 | } |
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286 | |||
287 | /* Apply AGPMode Quirks */ |
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288 | while (p && p->chip_device != 0) { |
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289 | if (info.id_vendor == p->hostbridge_vendor && |
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290 | info.id_device == p->hostbridge_device && |
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291 | rdev->pdev->vendor == p->chip_vendor && |
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292 | rdev->pdev->device == p->chip_device && |
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293 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
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294 | rdev->pdev->subsystem_device == p->subsys_device) { |
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295 | default_mode = p->default_mode; |
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296 | } |
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297 | ++p; |
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298 | } |
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299 | |||
300 | if (radeon_agpmode > 0) { |
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301 | if ((radeon_agpmode < (is_v3 ? 4 : 1)) || |
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302 | (radeon_agpmode > (is_v3 ? 8 : 4)) || |
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303 | (radeon_agpmode & (radeon_agpmode - 1))) { |
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304 | DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n", |
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305 | radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4", |
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306 | default_mode); |
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307 | radeon_agpmode = default_mode; |
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308 | } else { |
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309 | DRM_INFO("AGP mode requested: %d\n", radeon_agpmode); |
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310 | } |
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311 | } else { |
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312 | radeon_agpmode = default_mode; |
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313 | } |
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314 | |||
315 | mode.mode &= ~RADEON_AGP_MODE_MASK; |
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316 | if (is_v3) { |
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317 | switch (radeon_agpmode) { |
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318 | case 8: |
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319 | mode.mode |= RADEON_AGPv3_8X_MODE; |
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320 | break; |
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321 | case 4: |
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322 | default: |
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323 | mode.mode |= RADEON_AGPv3_4X_MODE; |
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324 | break; |
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325 | } |
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326 | } else { |
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327 | switch (radeon_agpmode) { |
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328 | case 4: |
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329 | mode.mode |= RADEON_AGP_4X_MODE; |
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330 | break; |
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331 | case 2: |
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332 | mode.mode |= RADEON_AGP_2X_MODE; |
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333 | break; |
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334 | case 1: |
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335 | default: |
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336 | mode.mode |= RADEON_AGP_1X_MODE; |
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337 | break; |
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338 | } |
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339 | } |
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340 | |||
341 | mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */ |
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342 | ret = drm_agp_enable(rdev->ddev, mode); |
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343 | if (ret) { |
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344 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); |
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345 | return ret; |
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346 | } |
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347 | |||
348 | rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base; |
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349 | rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20; |
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350 | |||
351 | /* workaround some hw issues */ |
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352 | if (rdev->family < CHIP_R200) { |
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353 | WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); |
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354 | } |
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355 | return 0; |
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356 | #else |
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357 | return 0; |
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358 | #endif |
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359 | } |
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360 | |||
361 | |||
362 | |||
363 | |||
364 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
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365 | |||
366 | |||
367 | |||
368 | |||
369 | int radeon_fence_driver_init(struct radeon_device *rdev) |
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370 | { |
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371 | unsigned long irq_flags; |
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372 | int r; |
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373 | |||
374 | // write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
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375 | r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg); |
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376 | if (r) { |
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377 | DRM_ERROR("Fence failed to get a scratch register."); |
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378 | // write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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379 | return r; |
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380 | } |
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381 | WREG32(rdev->fence_drv.scratch_reg, 0); |
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382 | // atomic_set(&rdev->fence_drv.seq, 0); |
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383 | // INIT_LIST_HEAD(&rdev->fence_drv.created); |
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384 | // INIT_LIST_HEAD(&rdev->fence_drv.emited); |
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385 | // INIT_LIST_HEAD(&rdev->fence_drv.signaled); |
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386 | rdev->fence_drv.count_timeout = 0; |
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387 | // init_waitqueue_head(&rdev->fence_drv.queue); |
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388 | // write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
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389 | // if (radeon_debugfs_fence_init(rdev)) { |
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390 | // DRM_ERROR("Failed to register debugfs file for fence !\n"); |
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391 | // } |
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392 | return 0; |
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393 | }>><>>><>><>> |
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394 |