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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __R500_REG_H__ |
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29 | #define __R500_REG_H__ |
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30 | |||
31 | /* pipe config regs */ |
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32 | #define R300_GA_POLY_MODE 0x4288 |
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33 | # define R300_FRONT_PTYPE_POINT (0 << 4) |
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34 | # define R300_FRONT_PTYPE_LINE (1 << 4) |
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35 | # define R300_FRONT_PTYPE_TRIANGE (2 << 4) |
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36 | # define R300_BACK_PTYPE_POINT (0 << 7) |
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37 | # define R300_BACK_PTYPE_LINE (1 << 7) |
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38 | # define R300_BACK_PTYPE_TRIANGE (2 << 7) |
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39 | #define R300_GA_ROUND_MODE 0x428c |
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40 | # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) |
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41 | # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) |
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42 | # define R300_COLOR_ROUND_TRUNC (0 << 2) |
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43 | # define R300_COLOR_ROUND_NEAREST (1 << 2) |
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44 | #define R300_GB_MSPOS0 0x4010 |
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45 | # define R300_MS_X0_SHIFT 0 |
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46 | # define R300_MS_Y0_SHIFT 4 |
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47 | # define R300_MS_X1_SHIFT 8 |
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48 | # define R300_MS_Y1_SHIFT 12 |
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49 | # define R300_MS_X2_SHIFT 16 |
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50 | # define R300_MS_Y2_SHIFT 20 |
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51 | # define R300_MSBD0_Y_SHIFT 24 |
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52 | # define R300_MSBD0_X_SHIFT 28 |
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53 | #define R300_GB_MSPOS1 0x4014 |
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54 | # define R300_MS_X3_SHIFT 0 |
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55 | # define R300_MS_Y3_SHIFT 4 |
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56 | # define R300_MS_X4_SHIFT 8 |
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57 | # define R300_MS_Y4_SHIFT 12 |
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58 | # define R300_MS_X5_SHIFT 16 |
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59 | # define R300_MS_Y5_SHIFT 20 |
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60 | # define R300_MSBD1_SHIFT 24 |
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61 | |||
62 | #define R300_GA_ENHANCE 0x4274 |
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63 | # define R300_GA_DEADLOCK_CNTL (1 << 0) |
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64 | # define R300_GA_FASTSYNC_CNTL (1 << 1) |
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65 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
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66 | # define R300_RB3D_DC_FLUSH (2 << 0) |
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67 | # define R300_RB3D_DC_FREE (2 << 2) |
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68 | # define R300_RB3D_DC_FINISH (1 << 4) |
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69 | #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 |
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70 | # define R300_ZC_FLUSH (1 << 0) |
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71 | # define R300_ZC_FREE (1 << 1) |
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72 | # define R300_ZC_FLUSH_ALL 0x3 |
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73 | #define R400_GB_PIPE_SELECT 0x402c |
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74 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
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75 | #define R500_SU_REG_DEST 0x42c8 |
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76 | #define R300_GB_TILE_CONFIG 0x4018 |
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77 | # define R300_ENABLE_TILING (1 << 0) |
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78 | # define R300_PIPE_COUNT_RV350 (0 << 1) |
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79 | # define R300_PIPE_COUNT_R300 (3 << 1) |
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80 | # define R300_PIPE_COUNT_R420_3P (6 << 1) |
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81 | # define R300_PIPE_COUNT_R420 (7 << 1) |
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82 | # define R300_TILE_SIZE_8 (0 << 4) |
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83 | # define R300_TILE_SIZE_16 (1 << 4) |
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84 | # define R300_TILE_SIZE_32 (2 << 4) |
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85 | # define R300_SUBPIXEL_1_12 (0 << 16) |
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86 | # define R300_SUBPIXEL_1_16 (1 << 16) |
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87 | #define R300_DST_PIPE_CONFIG 0x170c |
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88 | # define R300_PIPE_AUTO_CONFIG (1 << 31) |
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89 | #define R300_RB2D_DSTCACHE_MODE 0x3428 |
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90 | # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) |
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91 | # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) |
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92 | |||
93 | #define RADEON_CP_STAT 0x7C0 |
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94 | #define RADEON_RBBM_CMDFIFO_ADDR 0xE70 |
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95 | #define RADEON_RBBM_CMDFIFO_DATA 0xE74 |
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96 | #define RADEON_ISYNC_CNTL 0x1724 |
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97 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
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98 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
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99 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
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100 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
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101 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
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102 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
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103 | |||
104 | #define RS480_NB_MC_INDEX 0x168 |
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105 | # define RS480_NB_MC_IND_WR_EN (1 << 8) |
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106 | #define RS480_NB_MC_DATA 0x16c |
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107 | |||
108 | /* |
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109 | * RS690 |
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110 | */ |
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111 | #define RS690_MCCFG_FB_LOCATION 0x100 |
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112 | #define RS690_MC_FB_START_MASK 0x0000FFFF |
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113 | #define RS690_MC_FB_START_SHIFT 0 |
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114 | #define RS690_MC_FB_TOP_MASK 0xFFFF0000 |
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115 | #define RS690_MC_FB_TOP_SHIFT 16 |
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116 | #define RS690_MCCFG_AGP_LOCATION 0x101 |
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117 | #define RS690_MC_AGP_START_MASK 0x0000FFFF |
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118 | #define RS690_MC_AGP_START_SHIFT 0 |
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119 | #define RS690_MC_AGP_TOP_MASK 0xFFFF0000 |
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120 | #define RS690_MC_AGP_TOP_SHIFT 16 |
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121 | #define RS690_MCCFG_AGP_BASE 0x102 |
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122 | #define RS690_MCCFG_AGP_BASE_2 0x103 |
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123 | #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 |
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124 | #define RS690_HDP_FB_LOCATION 0x0134 |
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125 | #define RS690_MC_INDEX 0x78 |
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126 | # define RS690_MC_INDEX_MASK 0x1ff |
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127 | # define RS690_MC_INDEX_WR_EN (1 << 9) |
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128 | # define RS690_MC_INDEX_WR_ACK 0x7f |
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129 | #define RS690_MC_DATA 0x7c |
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130 | #define RS690_MC_STATUS 0x90 |
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131 | #define RS690_MC_STATUS_IDLE (1 << 0) |
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132 | #define RS480_AGP_BASE_2 0x0164 |
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133 | #define RS480_MC_MISC_CNTL 0x18 |
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134 | # define RS480_DISABLE_GTW (1 << 1) |
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135 | # define RS480_GART_INDEX_REG_EN (1 << 12) |
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136 | # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
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137 | #define RS480_GART_FEATURE_ID 0x2b |
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138 | # define RS480_HANG_EN (1 << 11) |
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139 | # define RS480_TLB_ENABLE (1 << 18) |
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140 | # define RS480_P2P_ENABLE (1 << 19) |
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141 | # define RS480_GTW_LAC_EN (1 << 25) |
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142 | # define RS480_2LEVEL_GART (0 << 30) |
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143 | # define RS480_1LEVEL_GART (1 << 30) |
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144 | # define RS480_PDC_EN (1 << 31) |
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145 | #define RS480_GART_BASE 0x2c |
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146 | #define RS480_GART_CACHE_CNTRL 0x2e |
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147 | # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ |
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148 | #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 |
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149 | # define RS480_GART_EN (1 << 0) |
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150 | # define RS480_VA_SIZE_32MB (0 << 1) |
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151 | # define RS480_VA_SIZE_64MB (1 << 1) |
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152 | # define RS480_VA_SIZE_128MB (2 << 1) |
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153 | # define RS480_VA_SIZE_256MB (3 << 1) |
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154 | # define RS480_VA_SIZE_512MB (4 << 1) |
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155 | # define RS480_VA_SIZE_1GB (5 << 1) |
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156 | # define RS480_VA_SIZE_2GB (6 << 1) |
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157 | #define RS480_AGP_MODE_CNTL 0x39 |
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158 | # define RS480_POST_GART_Q_SIZE (1 << 18) |
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159 | # define RS480_NONGART_SNOOP (1 << 19) |
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160 | # define RS480_AGP_RD_BUF_SIZE (1 << 20) |
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161 | # define RS480_REQ_TYPE_SNOOP_SHIFT 22 |
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162 | # define RS480_REQ_TYPE_SNOOP_MASK 0x3 |
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163 | # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) |
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164 | |||
165 | #define RS690_AIC_CTRL_SCRATCH 0x3A |
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166 | # define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) |
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167 | |||
168 | /* |
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169 | * RS600 |
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170 | */ |
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171 | #define RS600_MC_STATUS 0x0 |
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172 | #define RS600_MC_STATUS_IDLE (1 << 0) |
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173 | #define RS600_MC_INDEX 0x70 |
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174 | # define RS600_MC_ADDR_MASK 0xffff |
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175 | # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) |
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176 | # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) |
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177 | # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) |
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178 | # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) |
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179 | # define RS600_MC_IND_AIC_RBS (1 << 20) |
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180 | # define RS600_MC_IND_CITF_ARB0 (1 << 21) |
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181 | # define RS600_MC_IND_CITF_ARB1 (1 << 22) |
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182 | # define RS600_MC_IND_WR_EN (1 << 23) |
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183 | #define RS600_MC_DATA 0x74 |
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184 | #define RS600_MC_STATUS 0x0 |
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185 | # define RS600_MC_IDLE (1 << 1) |
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186 | #define RS600_MC_FB_LOCATION 0x4 |
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187 | #define RS600_MC_FB_START_MASK 0x0000FFFF |
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188 | #define RS600_MC_FB_START_SHIFT 0 |
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189 | #define RS600_MC_FB_TOP_MASK 0xFFFF0000 |
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190 | #define RS600_MC_FB_TOP_SHIFT 16 |
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191 | #define RS600_MC_AGP_LOCATION 0x5 |
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192 | #define RS600_MC_AGP_START_MASK 0x0000FFFF |
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193 | #define RS600_MC_AGP_START_SHIFT 0 |
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194 | #define RS600_MC_AGP_TOP_MASK 0xFFFF0000 |
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195 | #define RS600_MC_AGP_TOP_SHIFT 16 |
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196 | #define RS600_MC_AGP_BASE 0x6 |
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197 | #define RS600_MC_AGP_BASE_2 0x7 |
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198 | #define RS600_MC_CNTL1 0x9 |
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199 | # define RS600_ENABLE_PAGE_TABLES (1 << 26) |
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200 | #define RS600_MC_PT0_CNTL 0x100 |
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201 | # define RS600_ENABLE_PT (1 << 0) |
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202 | # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) |
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203 | # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) |
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204 | # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) |
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205 | # define RS600_INVALIDATE_L2_CACHE (1 << 29) |
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206 | #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 |
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207 | # define RS600_ENABLE_PAGE_TABLE (1 << 0) |
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208 | # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) |
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209 | #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 |
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210 | #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 |
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211 | #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c |
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212 | #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c |
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213 | #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c |
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214 | #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c |
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215 | #define RS600_MC_PT0_CLIENT0_CNTL 0x16c |
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216 | # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) |
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217 | # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) |
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218 | # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) |
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219 | # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) |
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220 | # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) |
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221 | # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) |
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222 | # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) |
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223 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) |
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224 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) |
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225 | # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) |
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226 | # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) |
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227 | # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) |
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228 | # define RS600_INVALIDATE_L1_TLB (1 << 20) |
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229 | /* rs600/rs690/rs740 */ |
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230 | # define RS600_BUS_MASTER_DIS (1 << 14) |
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231 | # define RS600_MSI_REARM (1 << 20) |
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232 | /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ |
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233 | |||
234 | |||
235 | |||
236 | #define RV515_MC_FB_LOCATION 0x01 |
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237 | #define RV515_MC_FB_START_MASK 0x0000FFFF |
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238 | #define RV515_MC_FB_START_SHIFT 0 |
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239 | #define RV515_MC_FB_TOP_MASK 0xFFFF0000 |
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240 | #define RV515_MC_FB_TOP_SHIFT 16 |
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241 | #define RV515_MC_AGP_LOCATION 0x02 |
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242 | #define RV515_MC_AGP_START_MASK 0x0000FFFF |
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243 | #define RV515_MC_AGP_START_SHIFT 0 |
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244 | #define RV515_MC_AGP_TOP_MASK 0xFFFF0000 |
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245 | #define RV515_MC_AGP_TOP_SHIFT 16 |
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246 | #define RV515_MC_AGP_BASE 0x03 |
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247 | #define RV515_MC_AGP_BASE_2 0x04 |
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248 | |||
249 | #define R520_MC_FB_LOCATION 0x04 |
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250 | #define R520_MC_FB_START_MASK 0x0000FFFF |
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251 | #define R520_MC_FB_START_SHIFT 0 |
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252 | #define R520_MC_FB_TOP_MASK 0xFFFF0000 |
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253 | #define R520_MC_FB_TOP_SHIFT 16 |
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254 | #define R520_MC_AGP_LOCATION 0x05 |
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255 | #define R520_MC_AGP_START_MASK 0x0000FFFF |
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256 | #define R520_MC_AGP_START_SHIFT 0 |
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257 | #define R520_MC_AGP_TOP_MASK 0xFFFF0000 |
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258 | #define R520_MC_AGP_TOP_SHIFT 16 |
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259 | #define R520_MC_AGP_BASE 0x06 |
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260 | #define R520_MC_AGP_BASE_2 0x07 |
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261 | |||
262 | |||
263 | #define AVIVO_MC_INDEX 0x0070 |
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264 | #define R520_MC_STATUS 0x00 |
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265 | #define R520_MC_STATUS_IDLE (1<<1) |
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266 | #define RV515_MC_STATUS 0x08 |
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267 | #define RV515_MC_STATUS_IDLE (1<<4) |
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268 | #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 |
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269 | #define AVIVO_MC_DATA 0x0074 |
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270 | |||
271 | #define R520_MC_IND_INDEX 0x70 |
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272 | #define R520_MC_IND_WR_EN (1 << 24) |
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273 | #define R520_MC_IND_DATA 0x74 |
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274 | |||
275 | #define RV515_MC_CNTL 0x5 |
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276 | # define RV515_MEM_NUM_CHANNELS_MASK 0x3 |
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277 | #define R520_MC_CNTL0 0x8 |
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278 | # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) |
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279 | # define R520_MEM_NUM_CHANNELS_SHIFT 24 |
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280 | # define R520_MC_CHANNEL_SIZE (1 << 23) |
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281 | |||
282 | #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ |
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283 | # define AVIVO_CP_FORCEON (1 << 0) |
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284 | #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ |
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285 | # define AVIVO_E2_FORCEON (1 << 0) |
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286 | #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ |
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287 | # define AVIVO_IDCT_FORCEON (1 << 0) |
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288 | |||
289 | #define AVIVO_HDP_FB_LOCATION 0x134 |
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290 | |||
291 | #define AVIVO_VGA_RENDER_CONTROL 0x0300 |
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292 | # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) |
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293 | #define AVIVO_D1VGA_CONTROL 0x0330 |
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294 | # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) |
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295 | # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) |
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296 | # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) |
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297 | # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) |
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298 | # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) |
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299 | # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) |
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300 | #define AVIVO_D2VGA_CONTROL 0x0338 |
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301 | |||
302 | #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 |
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303 | #define AVIVO_EXT1_PPLL_REF_DIV 0x404 |
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304 | #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 |
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305 | #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c |
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306 | |||
307 | #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 |
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308 | #define AVIVO_EXT2_PPLL_REF_DIV 0x414 |
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309 | #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 |
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310 | #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c |
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311 | |||
312 | #define AVIVO_EXT1_PPLL_FB_DIV 0x430 |
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313 | #define AVIVO_EXT2_PPLL_FB_DIV 0x434 |
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314 | |||
315 | #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 |
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316 | #define AVIVO_EXT1_PPLL_POST_DIV 0x43c |
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317 | |||
318 | #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 |
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319 | #define AVIVO_EXT2_PPLL_POST_DIV 0x444 |
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320 | |||
321 | #define AVIVO_EXT1_PPLL_CNTL 0x448 |
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322 | #define AVIVO_EXT2_PPLL_CNTL 0x44c |
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323 | |||
324 | #define AVIVO_P1PLL_CNTL 0x450 |
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325 | #define AVIVO_P2PLL_CNTL 0x454 |
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326 | #define AVIVO_P1PLL_INT_SS_CNTL 0x458 |
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327 | #define AVIVO_P2PLL_INT_SS_CNTL 0x45c |
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328 | #define AVIVO_P1PLL_TMDSA_CNTL 0x460 |
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329 | #define AVIVO_P2PLL_LVTMA_CNTL 0x464 |
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330 | |||
331 | #define AVIVO_PCLK_CRTC1_CNTL 0x480 |
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332 | #define AVIVO_PCLK_CRTC2_CNTL 0x484 |
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333 | |||
334 | #define AVIVO_D1CRTC_H_TOTAL 0x6000 |
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335 | #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 |
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336 | #define AVIVO_D1CRTC_H_SYNC_A 0x6008 |
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337 | #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c |
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338 | #define AVIVO_D1CRTC_H_SYNC_B 0x6010 |
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339 | #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 |
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340 | |||
341 | #define AVIVO_D1CRTC_V_TOTAL 0x6020 |
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342 | #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 |
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343 | #define AVIVO_D1CRTC_V_SYNC_A 0x6028 |
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344 | #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c |
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345 | #define AVIVO_D1CRTC_V_SYNC_B 0x6030 |
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346 | #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 |
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347 | |||
348 | #define AVIVO_D1CRTC_CONTROL 0x6080 |
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349 | # define AVIVO_CRTC_EN (1 << 0) |
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1963 | serge | 350 | # define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) |
1117 | serge | 351 | #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 |
352 | #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 |
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353 | #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c |
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2997 | Serge | 354 | #define AVIVO_D1CRTC_STATUS 0x609c |
355 | # define AVIVO_D1CRTC_V_BLANK (1 << 0) |
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1963 | serge | 356 | #define AVIVO_D1CRTC_STATUS_POSITION 0x60a0 |
1179 | serge | 357 | #define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 |
1117 | serge | 358 | #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 |
359 | |||
1963 | serge | 360 | #define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 |
361 | |||
1117 | serge | 362 | /* master controls */ |
363 | #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 |
||
364 | #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc |
||
365 | |||
366 | #define AVIVO_D1GRPH_ENABLE 0x6100 |
||
367 | #define AVIVO_D1GRPH_CONTROL 0x6104 |
||
368 | # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) |
||
369 | # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) |
||
370 | # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) |
||
371 | # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) |
||
372 | |||
373 | # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) |
||
374 | |||
375 | # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) |
||
376 | # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) |
||
377 | # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) |
||
378 | # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) |
||
379 | # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) |
||
380 | |||
381 | # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) |
||
382 | # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) |
||
383 | # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) |
||
384 | # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) |
||
385 | |||
386 | |||
387 | # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) |
||
388 | |||
389 | # define AVIVO_D1GRPH_SWAP_RB (1 << 16) |
||
390 | # define AVIVO_D1GRPH_TILED (1 << 20) |
||
391 | # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) |
||
392 | |||
1963 | serge | 393 | # define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) |
394 | # define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) |
||
395 | # define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) |
||
396 | # define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) |
||
397 | |||
1268 | serge | 398 | /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 |
399 | * block and vice versa. This applies to GRPH, CUR, etc. |
||
400 | */ |
||
1117 | serge | 401 | #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
402 | #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
||
1268 | serge | 403 | #define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 |
404 | #define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 |
||
1117 | serge | 405 | #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
1268 | serge | 406 | #define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c |
407 | #define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c |
||
1117 | serge | 408 | #define AVIVO_D1GRPH_PITCH 0x6120 |
409 | #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 |
||
410 | #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 |
||
411 | #define AVIVO_D1GRPH_X_START 0x612c |
||
412 | #define AVIVO_D1GRPH_Y_START 0x6130 |
||
413 | #define AVIVO_D1GRPH_X_END 0x6134 |
||
414 | #define AVIVO_D1GRPH_Y_END 0x6138 |
||
415 | #define AVIVO_D1GRPH_UPDATE 0x6144 |
||
1963 | serge | 416 | # define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2) |
1117 | serge | 417 | # define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) |
418 | #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 |
||
1963 | serge | 419 | # define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) |
1117 | serge | 420 | |
421 | #define AVIVO_D1CUR_CONTROL 0x6400 |
||
422 | # define AVIVO_D1CURSOR_EN (1 << 0) |
||
423 | # define AVIVO_D1CURSOR_MODE_SHIFT 8 |
||
424 | # define AVIVO_D1CURSOR_MODE_MASK (3 << 8) |
||
425 | # define AVIVO_D1CURSOR_MODE_24BPP 2 |
||
426 | #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 |
||
1268 | serge | 427 | #define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c |
428 | #define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c |
||
1117 | serge | 429 | #define AVIVO_D1CUR_SIZE 0x6410 |
430 | #define AVIVO_D1CUR_POSITION 0x6414 |
||
431 | #define AVIVO_D1CUR_HOT_SPOT 0x6418 |
||
432 | #define AVIVO_D1CUR_UPDATE 0x6424 |
||
433 | # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) |
||
434 | |||
435 | #define AVIVO_DC_LUT_RW_SELECT 0x6480 |
||
436 | #define AVIVO_DC_LUT_RW_MODE 0x6484 |
||
437 | #define AVIVO_DC_LUT_RW_INDEX 0x6488 |
||
438 | #define AVIVO_DC_LUT_SEQ_COLOR 0x648c |
||
439 | #define AVIVO_DC_LUT_PWL_DATA 0x6490 |
||
440 | #define AVIVO_DC_LUT_30_COLOR 0x6494 |
||
441 | #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 |
||
442 | #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c |
||
443 | #define AVIVO_DC_LUT_AUTOFILL 0x64a0 |
||
444 | |||
445 | #define AVIVO_DC_LUTA_CONTROL 0x64c0 |
||
446 | #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 |
||
447 | #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 |
||
448 | #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc |
||
449 | #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 |
||
450 | #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 |
||
451 | #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 |
||
452 | |||
453 | #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 |
||
454 | # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 |
||
455 | # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 |
||
456 | # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 |
||
457 | # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 |
||
458 | # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 |
||
459 | # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 |
||
460 | # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) |
||
461 | # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 |
||
462 | # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff |
||
463 | |||
464 | #define AVIVO_D1MODE_DATA_FORMAT 0x6528 |
||
465 | # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) |
||
466 | #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C |
||
1179 | serge | 467 | #define AVIVO_D1MODE_VBLANK_STATUS 0x6534 |
468 | # define AVIVO_VBLANK_ACK (1 << 4) |
||
469 | #define AVIVO_D1MODE_VLINE_START_END 0x6538 |
||
1221 | serge | 470 | #define AVIVO_D1MODE_VLINE_STATUS 0x653c |
471 | # define AVIVO_D1MODE_VLINE_STAT (1 << 12) |
||
1179 | serge | 472 | #define AVIVO_DxMODE_INT_MASK 0x6540 |
473 | # define AVIVO_D1MODE_INT_MASK (1 << 0) |
||
474 | # define AVIVO_D2MODE_INT_MASK (1 << 8) |
||
1117 | serge | 475 | #define AVIVO_D1MODE_VIEWPORT_START 0x6580 |
476 | #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 |
||
477 | #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 |
||
478 | #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c |
||
479 | |||
480 | #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 |
||
481 | #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 |
||
482 | #define AVIVO_D1SCL_UPDATE 0x65cc |
||
483 | # define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) |
||
484 | |||
485 | /* second crtc */ |
||
486 | #define AVIVO_D2CRTC_H_TOTAL 0x6800 |
||
487 | #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 |
||
488 | #define AVIVO_D2CRTC_H_SYNC_A 0x6808 |
||
489 | #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c |
||
490 | #define AVIVO_D2CRTC_H_SYNC_B 0x6810 |
||
491 | #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 |
||
492 | |||
493 | #define AVIVO_D2CRTC_V_TOTAL 0x6820 |
||
494 | #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 |
||
495 | #define AVIVO_D2CRTC_V_SYNC_A 0x6828 |
||
496 | #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c |
||
497 | #define AVIVO_D2CRTC_V_SYNC_B 0x6830 |
||
498 | #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 |
||
499 | |||
500 | #define AVIVO_D2CRTC_CONTROL 0x6880 |
||
501 | #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 |
||
502 | #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 |
||
503 | #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c |
||
1963 | serge | 504 | #define AVIVO_D2CRTC_STATUS_POSITION 0x68a0 |
1179 | serge | 505 | #define AVIVO_D2CRTC_FRAME_COUNT 0x68a4 |
1117 | serge | 506 | #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 |
507 | |||
508 | #define AVIVO_D2GRPH_ENABLE 0x6900 |
||
509 | #define AVIVO_D2GRPH_CONTROL 0x6904 |
||
510 | #define AVIVO_D2GRPH_LUT_SEL 0x6908 |
||
511 | #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 |
||
512 | #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 |
||
513 | #define AVIVO_D2GRPH_PITCH 0x6920 |
||
514 | #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 |
||
515 | #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 |
||
516 | #define AVIVO_D2GRPH_X_START 0x692c |
||
517 | #define AVIVO_D2GRPH_Y_START 0x6930 |
||
518 | #define AVIVO_D2GRPH_X_END 0x6934 |
||
519 | #define AVIVO_D2GRPH_Y_END 0x6938 |
||
520 | #define AVIVO_D2GRPH_UPDATE 0x6944 |
||
521 | #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 |
||
522 | |||
523 | #define AVIVO_D2CUR_CONTROL 0x6c00 |
||
524 | #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 |
||
525 | #define AVIVO_D2CUR_SIZE 0x6c10 |
||
526 | #define AVIVO_D2CUR_POSITION 0x6c14 |
||
527 | |||
1179 | serge | 528 | #define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 |
529 | #define AVIVO_D2MODE_VLINE_START_END 0x6d38 |
||
1221 | serge | 530 | #define AVIVO_D2MODE_VLINE_STATUS 0x6d3c |
1117 | serge | 531 | #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
532 | #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
||
533 | #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
||
534 | #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c |
||
535 | |||
536 | #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 |
||
537 | #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 |
||
538 | |||
539 | #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 |
||
540 | |||
541 | #define AVIVO_DACA_ENABLE 0x7800 |
||
542 | # define AVIVO_DAC_ENABLE (1 << 0) |
||
543 | #define AVIVO_DACA_SOURCE_SELECT 0x7804 |
||
544 | # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) |
||
545 | # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) |
||
546 | # define AVIVO_DAC_SOURCE_TV (2 << 0) |
||
547 | |||
548 | #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c |
||
549 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
||
550 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
||
551 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
||
552 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
||
553 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
||
554 | # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
||
555 | #define AVIVO_DACA_POWERDOWN 0x7850 |
||
556 | # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) |
||
557 | # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) |
||
558 | # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) |
||
559 | # define AVIVO_DACA_POWERDOWN_RED (1 << 24) |
||
560 | |||
561 | #define AVIVO_DACB_ENABLE 0x7a00 |
||
562 | #define AVIVO_DACB_SOURCE_SELECT 0x7a04 |
||
563 | #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c |
||
564 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
||
565 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
||
566 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
||
567 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
||
568 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
||
569 | # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
||
570 | #define AVIVO_DACB_POWERDOWN 0x7a50 |
||
571 | # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) |
||
572 | # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) |
||
573 | # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) |
||
574 | # define AVIVO_DACB_POWERDOWN_RED |
||
575 | |||
576 | #define AVIVO_TMDSA_CNTL 0x7880 |
||
577 | # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) |
||
2997 | Serge | 578 | # define AVIVO_TMDSA_CNTL_HDMI_EN (1 << 2) |
1117 | serge | 579 | # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) |
580 | # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) |
||
581 | # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) |
||
582 | # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) |
||
583 | # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
||
584 | # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) |
||
585 | #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 |
||
586 | /* 78a8 appears to be some kind of (reasonably tolerant) clock? |
||
587 | * 78d0 definitely hits the transmitter, definitely clock. */ |
||
588 | /* MYSTERY1 This appears to control dithering? */ |
||
589 | #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 |
||
590 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
||
591 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
||
592 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
||
593 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
||
594 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
||
595 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
||
596 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
||
597 | # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
||
598 | #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 |
||
599 | # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) |
||
600 | # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
||
601 | # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
||
602 | # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) |
||
603 | #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 |
||
604 | # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
||
605 | # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
||
606 | #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 |
||
607 | #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 |
||
608 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) |
||
609 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
||
610 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
||
611 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
||
612 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
||
613 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) |
||
614 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
||
615 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
||
616 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
||
617 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) |
||
618 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
||
619 | # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
||
620 | |||
621 | #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 |
||
622 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
||
623 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
||
624 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
||
625 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
||
626 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
||
627 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
||
628 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
||
629 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
||
630 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
||
631 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
||
632 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
||
633 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
||
634 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
||
635 | # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
||
636 | |||
637 | #define AVIVO_LVTMA_CNTL 0x7a80 |
||
638 | # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) |
||
2997 | Serge | 639 | # define AVIVO_LVTMA_CNTL_HDMI_EN (1 << 2) |
1117 | serge | 640 | # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) |
641 | # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) |
||
642 | # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) |
||
643 | # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) |
||
644 | # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
||
645 | # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) |
||
646 | #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 |
||
647 | #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 |
||
648 | #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 |
||
649 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
||
650 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
||
651 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
||
652 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
||
653 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
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654 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
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655 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
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656 | # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
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657 | |||
658 | |||
659 | |||
660 | #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 |
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661 | # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) |
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662 | # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
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663 | # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
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664 | # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) |
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665 | |||
666 | #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 |
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667 | # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
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668 | # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
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669 | #define R500_LVTMA_CLOCK_ENABLE 0x7b00 |
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670 | #define R600_LVTMA_CLOCK_ENABLE 0x7b04 |
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671 | |||
672 | #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 |
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673 | #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 |
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674 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
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675 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
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676 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
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677 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
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678 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) |
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679 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) |
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680 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
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681 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
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682 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
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683 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
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684 | # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
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685 | |||
686 | #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 |
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687 | #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 |
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688 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
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689 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
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690 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
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691 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
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692 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
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693 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
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694 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
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695 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
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696 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
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697 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
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698 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
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699 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
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700 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
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701 | # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
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702 | |||
703 | #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 |
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704 | #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 |
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705 | # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) |
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706 | # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) |
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707 | # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) |
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708 | # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) |
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709 | # define AVIVO_LVTMA_SYNCEN (1 << 8) |
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710 | # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) |
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711 | # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) |
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712 | # define AVIVO_LVTMA_DIGON (1 << 16) |
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713 | # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) |
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714 | # define AVIVO_LVTMA_DIGON_POL (1 << 18) |
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715 | # define AVIVO_LVTMA_BLON (1 << 24) |
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716 | # define AVIVO_LVTMA_BLON_OVRD (1 << 25) |
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717 | # define AVIVO_LVTMA_BLON_POL (1 << 26) |
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718 | |||
719 | #define R500_LVTMA_PWRSEQ_STATE 0x7af4 |
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720 | #define R600_LVTMA_PWRSEQ_STATE 0x7af8 |
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721 | # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) |
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722 | # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) |
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723 | # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) |
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724 | # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) |
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725 | # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) |
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726 | # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) |
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727 | |||
728 | #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 |
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729 | # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) |
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730 | # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 |
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731 | # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 |
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732 | |||
733 | #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 |
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734 | |||
1321 | serge | 735 | #define AVIVO_DC_GPIO_HPD_A 0x7e94 |
1430 | serge | 736 | #define AVIVO_DC_GPIO_HPD_Y 0x7e9c |
1321 | serge | 737 | |
1430 | serge | 738 | #define AVIVO_DC_I2C_STATUS1 0x7d30 |
739 | # define AVIVO_DC_I2C_DONE (1 << 0) |
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740 | # define AVIVO_DC_I2C_NACK (1 << 1) |
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741 | # define AVIVO_DC_I2C_HALT (1 << 2) |
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742 | # define AVIVO_DC_I2C_GO (1 << 3) |
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743 | #define AVIVO_DC_I2C_RESET 0x7d34 |
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744 | # define AVIVO_DC_I2C_SOFT_RESET (1 << 0) |
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745 | # define AVIVO_DC_I2C_ABORT (1 << 8) |
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746 | #define AVIVO_DC_I2C_CONTROL1 0x7d38 |
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747 | # define AVIVO_DC_I2C_START (1 << 0) |
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748 | # define AVIVO_DC_I2C_STOP (1 << 1) |
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749 | # define AVIVO_DC_I2C_RECEIVE (1 << 2) |
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750 | # define AVIVO_DC_I2C_EN (1 << 8) |
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751 | # define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) |
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752 | # define AVIVO_SEL_DDC1 0 |
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753 | # define AVIVO_SEL_DDC2 1 |
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754 | # define AVIVO_SEL_DDC3 2 |
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755 | #define AVIVO_DC_I2C_CONTROL2 0x7d3c |
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756 | # define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) |
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757 | # define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) |
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758 | #define AVIVO_DC_I2C_CONTROL3 0x7d40 |
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759 | # define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) |
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760 | # define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) |
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761 | # define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) |
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762 | # define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) |
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763 | # define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) |
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764 | # define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) |
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765 | #define AVIVO_DC_I2C_DATA 0x7d44 |
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766 | #define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 |
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767 | # define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) |
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768 | # define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) |
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769 | # define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) |
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770 | #define AVIVO_DC_I2C_ARBITRATION 0x7d50 |
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771 | # define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) |
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772 | # define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) |
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773 | # define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) |
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774 | # define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) |
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775 | # define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) |
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776 | # define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) |
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1117 | serge | 777 | |
1430 | serge | 778 | #define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 |
779 | #define AVIVO_DC_GPIO_DDC1_A 0x7e44 |
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780 | #define AVIVO_DC_GPIO_DDC1_EN 0x7e48 |
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781 | #define AVIVO_DC_GPIO_DDC1_Y 0x7e4c |
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1117 | serge | 782 | |
1430 | serge | 783 | #define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 |
784 | #define AVIVO_DC_GPIO_DDC2_A 0x7e54 |
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785 | #define AVIVO_DC_GPIO_DDC2_EN 0x7e58 |
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786 | #define AVIVO_DC_GPIO_DDC2_Y 0x7e5c |
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1117 | serge | 787 | |
1430 | serge | 788 | #define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 |
789 | #define AVIVO_DC_GPIO_DDC3_A 0x7e64 |
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790 | #define AVIVO_DC_GPIO_DDC3_EN 0x7e68 |
||
791 | #define AVIVO_DC_GPIO_DDC3_Y 0x7e6c |
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792 | |||
1179 | serge | 793 | #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc |
794 | # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) |
||
795 | # define AVIVO_D2_VBLANK_INTERRUPT (1 << 5) |
||
796 | |||
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