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3764 | Serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __R500_REG_H__ |
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29 | #define __R500_REG_H__ |
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30 | |||
31 | /* pipe config regs */ |
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32 | #define R300_GA_POLY_MODE 0x4288 |
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33 | # define R300_FRONT_PTYPE_POINT (0 << 4) |
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34 | # define R300_FRONT_PTYPE_LINE (1 << 4) |
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35 | # define R300_FRONT_PTYPE_TRIANGE (2 << 4) |
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36 | # define R300_BACK_PTYPE_POINT (0 << 7) |
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37 | # define R300_BACK_PTYPE_LINE (1 << 7) |
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38 | # define R300_BACK_PTYPE_TRIANGE (2 << 7) |
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39 | #define R300_GA_ROUND_MODE 0x428c |
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40 | # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) |
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41 | # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) |
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42 | # define R300_COLOR_ROUND_TRUNC (0 << 2) |
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43 | # define R300_COLOR_ROUND_NEAREST (1 << 2) |
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44 | #define R300_GB_MSPOS0 0x4010 |
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45 | # define R300_MS_X0_SHIFT 0 |
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46 | # define R300_MS_Y0_SHIFT 4 |
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47 | # define R300_MS_X1_SHIFT 8 |
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48 | # define R300_MS_Y1_SHIFT 12 |
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49 | # define R300_MS_X2_SHIFT 16 |
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50 | # define R300_MS_Y2_SHIFT 20 |
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51 | # define R300_MSBD0_Y_SHIFT 24 |
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52 | # define R300_MSBD0_X_SHIFT 28 |
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53 | #define R300_GB_MSPOS1 0x4014 |
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54 | # define R300_MS_X3_SHIFT 0 |
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55 | # define R300_MS_Y3_SHIFT 4 |
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56 | # define R300_MS_X4_SHIFT 8 |
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57 | # define R300_MS_Y4_SHIFT 12 |
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58 | # define R300_MS_X5_SHIFT 16 |
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59 | # define R300_MS_Y5_SHIFT 20 |
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60 | # define R300_MSBD1_SHIFT 24 |
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61 | |||
62 | #define R300_GA_ENHANCE 0x4274 |
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63 | # define R300_GA_DEADLOCK_CNTL (1 << 0) |
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64 | # define R300_GA_FASTSYNC_CNTL (1 << 1) |
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65 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
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66 | # define R300_RB3D_DC_FLUSH (2 << 0) |
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67 | # define R300_RB3D_DC_FREE (2 << 2) |
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68 | # define R300_RB3D_DC_FINISH (1 << 4) |
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69 | #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 |
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70 | # define R300_ZC_FLUSH (1 << 0) |
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71 | # define R300_ZC_FREE (1 << 1) |
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72 | # define R300_ZC_FLUSH_ALL 0x3 |
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73 | #define R400_GB_PIPE_SELECT 0x402c |
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74 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
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75 | #define R500_SU_REG_DEST 0x42c8 |
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76 | #define R300_GB_TILE_CONFIG 0x4018 |
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77 | # define R300_ENABLE_TILING (1 << 0) |
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78 | # define R300_PIPE_COUNT_RV350 (0 << 1) |
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79 | # define R300_PIPE_COUNT_R300 (3 << 1) |
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80 | # define R300_PIPE_COUNT_R420_3P (6 << 1) |
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81 | # define R300_PIPE_COUNT_R420 (7 << 1) |
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82 | # define R300_TILE_SIZE_8 (0 << 4) |
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83 | # define R300_TILE_SIZE_16 (1 << 4) |
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84 | # define R300_TILE_SIZE_32 (2 << 4) |
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85 | # define R300_SUBPIXEL_1_12 (0 << 16) |
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86 | # define R300_SUBPIXEL_1_16 (1 << 16) |
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87 | #define R300_DST_PIPE_CONFIG 0x170c |
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88 | # define R300_PIPE_AUTO_CONFIG (1 << 31) |
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89 | #define R300_RB2D_DSTCACHE_MODE 0x3428 |
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90 | # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) |
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91 | # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) |
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92 | |||
93 | #define RADEON_CP_STAT 0x7C0 |
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94 | #define RADEON_RBBM_CMDFIFO_ADDR 0xE70 |
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95 | #define RADEON_RBBM_CMDFIFO_DATA 0xE74 |
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96 | #define RADEON_ISYNC_CNTL 0x1724 |
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97 | # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
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98 | # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
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99 | # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
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100 | # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
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101 | # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
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102 | # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
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103 | |||
104 | #define RS480_NB_MC_INDEX 0x168 |
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105 | # define RS480_NB_MC_IND_WR_EN (1 << 8) |
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106 | #define RS480_NB_MC_DATA 0x16c |
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107 | |||
108 | /* |
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109 | * RS690 |
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110 | */ |
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111 | #define RS690_MCCFG_FB_LOCATION 0x100 |
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112 | #define RS690_MC_FB_START_MASK 0x0000FFFF |
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113 | #define RS690_MC_FB_START_SHIFT 0 |
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114 | #define RS690_MC_FB_TOP_MASK 0xFFFF0000 |
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115 | #define RS690_MC_FB_TOP_SHIFT 16 |
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116 | #define RS690_MCCFG_AGP_LOCATION 0x101 |
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117 | #define RS690_MC_AGP_START_MASK 0x0000FFFF |
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118 | #define RS690_MC_AGP_START_SHIFT 0 |
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119 | #define RS690_MC_AGP_TOP_MASK 0xFFFF0000 |
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120 | #define RS690_MC_AGP_TOP_SHIFT 16 |
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121 | #define RS690_MCCFG_AGP_BASE 0x102 |
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122 | #define RS690_MCCFG_AGP_BASE_2 0x103 |
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123 | #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 |
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124 | #define RS690_HDP_FB_LOCATION 0x0134 |
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125 | #define RS690_MC_INDEX 0x78 |
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126 | # define RS690_MC_INDEX_MASK 0x1ff |
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127 | # define RS690_MC_INDEX_WR_EN (1 << 9) |
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128 | # define RS690_MC_INDEX_WR_ACK 0x7f |
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129 | #define RS690_MC_DATA 0x7c |
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130 | #define RS690_MC_STATUS 0x90 |
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131 | #define RS690_MC_STATUS_IDLE (1 << 0) |
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132 | #define RS480_AGP_BASE_2 0x0164 |
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133 | #define RS480_MC_MISC_CNTL 0x18 |
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134 | # define RS480_DISABLE_GTW (1 << 1) |
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135 | # define RS480_GART_INDEX_REG_EN (1 << 12) |
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136 | # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
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137 | #define RS480_GART_FEATURE_ID 0x2b |
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138 | # define RS480_HANG_EN (1 << 11) |
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139 | # define RS480_TLB_ENABLE (1 << 18) |
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140 | # define RS480_P2P_ENABLE (1 << 19) |
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141 | # define RS480_GTW_LAC_EN (1 << 25) |
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142 | # define RS480_2LEVEL_GART (0 << 30) |
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143 | # define RS480_1LEVEL_GART (1 << 30) |
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144 | # define RS480_PDC_EN (1 << 31) |
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145 | #define RS480_GART_BASE 0x2c |
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146 | #define RS480_GART_CACHE_CNTRL 0x2e |
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147 | # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ |
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148 | #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 |
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149 | # define RS480_GART_EN (1 << 0) |
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150 | # define RS480_VA_SIZE_32MB (0 << 1) |
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151 | # define RS480_VA_SIZE_64MB (1 << 1) |
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152 | # define RS480_VA_SIZE_128MB (2 << 1) |
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153 | # define RS480_VA_SIZE_256MB (3 << 1) |
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154 | # define RS480_VA_SIZE_512MB (4 << 1) |
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155 | # define RS480_VA_SIZE_1GB (5 << 1) |
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156 | # define RS480_VA_SIZE_2GB (6 << 1) |
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157 | #define RS480_AGP_MODE_CNTL 0x39 |
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158 | # define RS480_POST_GART_Q_SIZE (1 << 18) |
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159 | # define RS480_NONGART_SNOOP (1 << 19) |
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160 | # define RS480_AGP_RD_BUF_SIZE (1 << 20) |
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161 | # define RS480_REQ_TYPE_SNOOP_SHIFT 22 |
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162 | # define RS480_REQ_TYPE_SNOOP_MASK 0x3 |
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163 | # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) |
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164 | |||
165 | #define RS690_AIC_CTRL_SCRATCH 0x3A |
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166 | # define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) |
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167 | |||
168 | /* |
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169 | * RS600 |
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170 | */ |
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171 | #define RS600_MC_STATUS 0x0 |
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172 | #define RS600_MC_STATUS_IDLE (1 << 0) |
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173 | #define RS600_MC_INDEX 0x70 |
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174 | # define RS600_MC_ADDR_MASK 0xffff |
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175 | # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) |
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176 | # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) |
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177 | # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) |
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178 | # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) |
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179 | # define RS600_MC_IND_AIC_RBS (1 << 20) |
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180 | # define RS600_MC_IND_CITF_ARB0 (1 << 21) |
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181 | # define RS600_MC_IND_CITF_ARB1 (1 << 22) |
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182 | # define RS600_MC_IND_WR_EN (1 << 23) |
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183 | #define RS600_MC_DATA 0x74 |
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184 | #define RS600_MC_STATUS 0x0 |
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185 | # define RS600_MC_IDLE (1 << 1) |
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186 | #define RS600_MC_FB_LOCATION 0x4 |
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187 | #define RS600_MC_FB_START_MASK 0x0000FFFF |
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188 | #define RS600_MC_FB_START_SHIFT 0 |
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189 | #define RS600_MC_FB_TOP_MASK 0xFFFF0000 |
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190 | #define RS600_MC_FB_TOP_SHIFT 16 |
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191 | #define RS600_MC_AGP_LOCATION 0x5 |
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192 | #define RS600_MC_AGP_START_MASK 0x0000FFFF |
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193 | #define RS600_MC_AGP_START_SHIFT 0 |
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194 | #define RS600_MC_AGP_TOP_MASK 0xFFFF0000 |
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195 | #define RS600_MC_AGP_TOP_SHIFT 16 |
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196 | #define RS600_MC_AGP_BASE 0x6 |
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197 | #define RS600_MC_AGP_BASE_2 0x7 |
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198 | #define RS600_MC_CNTL1 0x9 |
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199 | # define RS600_ENABLE_PAGE_TABLES (1 << 26) |
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200 | #define RS600_MC_PT0_CNTL 0x100 |
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201 | # define RS600_ENABLE_PT (1 << 0) |
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202 | # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) |
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203 | # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) |
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204 | # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) |
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205 | # define RS600_INVALIDATE_L2_CACHE (1 << 29) |
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206 | #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 |
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207 | # define RS600_ENABLE_PAGE_TABLE (1 << 0) |
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208 | # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) |
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209 | #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 |
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210 | #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 |
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211 | #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c |
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212 | #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c |
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213 | #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c |
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214 | #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c |
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215 | #define RS600_MC_PT0_CLIENT0_CNTL 0x16c |
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216 | # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) |
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217 | # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) |
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218 | # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) |
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219 | # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) |
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220 | # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) |
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221 | # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) |
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222 | # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) |
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223 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) |
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224 | # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) |
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225 | # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) |
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226 | # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) |
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227 | # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) |
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228 | # define RS600_INVALIDATE_L1_TLB (1 << 20) |
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229 | /* rs600/rs690/rs740 */ |
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230 | # define RS600_BUS_MASTER_DIS (1 << 14) |
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231 | # define RS600_MSI_REARM (1 << 20) |
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232 | /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ |
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233 | |||
234 | |||
235 | |||
236 | #define RV515_MC_FB_LOCATION 0x01 |
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237 | #define RV515_MC_FB_START_MASK 0x0000FFFF |
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238 | #define RV515_MC_FB_START_SHIFT 0 |
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239 | #define RV515_MC_FB_TOP_MASK 0xFFFF0000 |
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240 | #define RV515_MC_FB_TOP_SHIFT 16 |
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241 | #define RV515_MC_AGP_LOCATION 0x02 |
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242 | #define RV515_MC_AGP_START_MASK 0x0000FFFF |
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243 | #define RV515_MC_AGP_START_SHIFT 0 |
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244 | #define RV515_MC_AGP_TOP_MASK 0xFFFF0000 |
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245 | #define RV515_MC_AGP_TOP_SHIFT 16 |
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246 | #define RV515_MC_AGP_BASE 0x03 |
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247 | #define RV515_MC_AGP_BASE_2 0x04 |
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248 | |||
249 | #define R520_MC_FB_LOCATION 0x04 |
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250 | #define R520_MC_FB_START_MASK 0x0000FFFF |
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251 | #define R520_MC_FB_START_SHIFT 0 |
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252 | <