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1179 serge 1
/*
2
 * Copyright 2008 Advanced Micro Devices, Inc.
3
 * Copyright 2008 Red Hat Inc.
4
 * Copyright 2009 Jerome Glisse.
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a
7
 * copy of this software and associated documentation files (the "Software"),
8
 * to deal in the Software without restriction, including without limitation
9
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10
 * and/or sell copies of the Software, and to permit persons to whom the
11
 * Software is furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22
 * OTHER DEALINGS IN THE SOFTWARE.
23
 *
24
 * Authors: Dave Airlie
25
 *          Alex Deucher
26
 *          Jerome Glisse
27
 */
28
#include 
1963 serge 29
#include 
2997 Serge 30
#include 
1179 serge 31
#include "radeon_reg.h"
32
#include "radeon.h"
1963 serge 33
#include "radeon_asic.h"
1179 serge 34
#include "atom.h"
1403 serge 35
#include "r100d.h"
1179 serge 36
#include "r420d.h"
1403 serge 37
#include "r420_reg_safe.h"
1179 serge 38
 
1403 serge 39
static void r420_set_reg_safe(struct radeon_device *rdev)
40
{
41
	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
42
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
43
}
44
 
1179 serge 45
void r420_pipes_init(struct radeon_device *rdev)
46
{
47
	unsigned tmp;
48
	unsigned gb_pipe_select;
49
	unsigned num_pipes;
50
 
51
	/* GA_ENHANCE workaround TCL deadlock issue */
1430 serge 52
	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
53
	       (1 << 2) | (1 << 3));
1179 serge 54
	/* add idle wait as per freedesktop.org bug 24041 */
55
	if (r100_gui_wait_for_idle(rdev)) {
56
		printk(KERN_WARNING "Failed to wait GUI idle while "
57
		       "programming pipes. Bad things might happen.\n");
58
	}
59
	/* get max number of pipes */
1963 serge 60
	gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
1179 serge 61
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
1963 serge 62
 
63
	/* SE chips have 1 pipe */
64
	if ((rdev->pdev->device == 0x5e4c) ||
65
	    (rdev->pdev->device == 0x5e4f))
66
		num_pipes = 1;
67
 
1179 serge 68
	rdev->num_gb_pipes = num_pipes;
69
	tmp = 0;
70
	switch (num_pipes) {
71
	default:
72
		/* force to 1 pipe */
73
		num_pipes = 1;
74
	case 1:
75
		tmp = (0 << 1);
76
		break;
77
	case 2:
78
		tmp = (3 << 1);
79
		break;
80
	case 3:
81
		tmp = (6 << 1);
82
		break;
83
	case 4:
84
		tmp = (7 << 1);
85
		break;
86
	}
1430 serge 87
	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
1179 serge 88
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
1430 serge 89
	tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
90
	WREG32(R300_GB_TILE_CONFIG, tmp);
1179 serge 91
	if (r100_gui_wait_for_idle(rdev)) {
92
		printk(KERN_WARNING "Failed to wait GUI idle while "
93
		       "programming pipes. Bad things might happen.\n");
94
	}
95
 
1430 serge 96
	tmp = RREG32(R300_DST_PIPE_CONFIG);
97
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
1179 serge 98
 
99
	WREG32(R300_RB2D_DSTCACHE_MODE,
100
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
101
	       R300_DC_AUTOFLUSH_ENABLE |
102
	       R300_DC_DC_DISABLE_IGNORE_PE);
103
 
104
	if (r100_gui_wait_for_idle(rdev)) {
105
		printk(KERN_WARNING "Failed to wait GUI idle while "
106
		       "programming pipes. Bad things might happen.\n");
107
	}
108
 
109
	if (rdev->family == CHIP_RV530) {
110
		tmp = RREG32(RV530_GB_PIPE_SELECT2);
111
		if ((tmp & 3) == 3)
112
			rdev->num_z_pipes = 2;
113
		else
114
			rdev->num_z_pipes = 1;
115
	} else
116
		rdev->num_z_pipes = 1;
117
 
118
	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
119
		 rdev->num_gb_pipes, rdev->num_z_pipes);
120
}
121
 
122
u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
123
{
124
	u32 r;
125
 
126
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
127
	r = RREG32(R_0001FC_MC_IND_DATA);
128
	return r;
129
}
130
 
131
void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
132
{
133
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
134
		S_0001F8_MC_IND_WR_EN(1));
135
	WREG32(R_0001FC_MC_IND_DATA, v);
136
}
137
 
138
static void r420_debugfs(struct radeon_device *rdev)
139
{
140
	if (r100_debugfs_rbbm_init(rdev)) {
141
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
142
	}
143
	if (r420_debugfs_pipes_info_init(rdev)) {
144
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
145
	}
146
}
147
 
148
static void r420_clock_resume(struct radeon_device *rdev)
149
{
150
	u32 sclk_cntl;
1221 serge 151
 
152
	if (radeon_dynclks != -1 && radeon_dynclks)
153
		radeon_atom_set_clock_gating(rdev, 1);
1179 serge 154
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
155
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
156
	if (rdev->family == CHIP_R420)
157
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
158
	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
159
}
160
 
1403 serge 161
static void r420_cp_errata_init(struct radeon_device *rdev)
162
{
2997 Serge 163
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
164
 
1403 serge 165
	/* RV410 and R420 can lock up if CP DMA to host memory happens
166
	 * while the 2D engine is busy.
167
	 *
168
	 * The proper workaround is to queue a RESYNC at the beginning
169
	 * of the CP init, apparently.
170
	 */
171
	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
2997 Serge 172
	radeon_ring_lock(rdev, ring, 8);
173
	radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
174
	radeon_ring_write(ring, rdev->config.r300.resync_scratch);
175
	radeon_ring_write(ring, 0xDEADBEEF);
176
	radeon_ring_unlock_commit(rdev, ring);
1403 serge 177
}
178
 
179
static void r420_cp_errata_fini(struct radeon_device *rdev)
180
{
2997 Serge 181
	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
182
 
1403 serge 183
	/* Catch the RESYNC we dispatched all the way back,
184
	 * at the very beginning of the CP init.
185
	 */
2997 Serge 186
	radeon_ring_lock(rdev, ring, 8);
187
	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
188
	radeon_ring_write(ring, R300_RB3D_DC_FINISH);
189
	radeon_ring_unlock_commit(rdev, ring);
1403 serge 190
	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
191
}
192
 
1179 serge 193
static int r420_startup(struct radeon_device *rdev)
194
{
195
	int r;
196
 
1321 serge 197
	/* set common regs */
198
	r100_set_common_regs(rdev);
199
	/* program mc */
1179 serge 200
	r300_mc_program(rdev);
1221 serge 201
	/* Resume clock */
202
	r420_clock_resume(rdev);
1179 serge 203
	/* Initialize GART (initialize after TTM so we can allocate
204
	 * memory through TTM but finalize after TTM) */
205
	if (rdev->flags & RADEON_IS_PCIE) {
206
		r = rv370_pcie_gart_enable(rdev);
207
		if (r)
208
			return r;
209
	}
210
	if (rdev->flags & RADEON_IS_PCI) {
211
		r = r100_pci_gart_enable(rdev);
212
		if (r)
213
			return r;
214
	}
215
	r420_pipes_init(rdev);
2005 serge 216
 
217
	/* allocate wb buffer */
218
	r = radeon_wb_init(rdev);
219
	if (r)
220
		return r;
221
 
1179 serge 222
	/* Enable IRQ */
2005 serge 223
	r100_irq_set(rdev);
1403 serge 224
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1179 serge 225
	/* 1M ring buffer */
1412 serge 226
	r = r100_cp_init(rdev, 1024 * 1024);
227
	if (r) {
1963 serge 228
		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1412 serge 229
		return r;
230
	}
231
	r420_cp_errata_init(rdev);
2997 Serge 232
 
233
	r = radeon_ib_pool_init(rdev);
2005 serge 234
	if (r) {
2997 Serge 235
		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2005 serge 236
		return r;
237
	}
2997 Serge 238
 
1179 serge 239
	return 0;
240
}
241
 
242
 
243
 
244
 
2997 Serge 245
 
246
 
1179 serge 247
int r420_init(struct radeon_device *rdev)
248
{
249
	int r;
250
 
251
	/* Initialize scratch registers */
252
	radeon_scratch_init(rdev);
253
	/* Initialize surface registers */
254
	radeon_surface_init(rdev);
255
	/* TODO: disable VGA need to use VGA request */
1963 serge 256
	/* restore some register to sane defaults */
257
	r100_restore_sanity(rdev);
1179 serge 258
	/* BIOS*/
259
	if (!radeon_get_bios(rdev)) {
260
		if (ASIC_IS_AVIVO(rdev))
261
			return -EINVAL;
262
	}
263
	if (rdev->is_atom_bios) {
264
		r = radeon_atombios_init(rdev);
265
		if (r) {
266
			return r;
267
		}
268
	} else {
269
		r = radeon_combios_init(rdev);
270
		if (r) {
271
			return r;
272
		}
273
	}
274
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
1963 serge 275
	if (radeon_asic_reset(rdev)) {
1179 serge 276
		dev_warn(rdev->dev,
277
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
278
			RREG32(R_000E40_RBBM_STATUS),
279
			RREG32(R_0007C0_CP_STAT));
280
	}
281
	/* check if cards are posted or not */
1321 serge 282
	if (radeon_boot_test_post_card(rdev) == false)
283
		return -EINVAL;
284
 
1179 serge 285
	/* Initialize clocks */
286
	radeon_get_clock_info(rdev->ddev);
1430 serge 287
	/* initialize AGP */
288
	if (rdev->flags & RADEON_IS_AGP) {
289
		r = radeon_agp_init(rdev);
1179 serge 290
	if (r) {
1430 serge 291
			radeon_agp_disable(rdev);
1179 serge 292
	}
1430 serge 293
	}
294
	/* initialize memory controller */
295
	r300_mc_init(rdev);
1179 serge 296
	r420_debugfs(rdev);
297
	/* Fence driver */
2005 serge 298
	r = radeon_fence_driver_init(rdev);
299
	if (r) {
300
		return r;
301
	}
302
	r = radeon_irq_kms_init(rdev);
303
	if (r) {
304
		return r;
305
	}
1179 serge 306
	/* Memory manager */
1321 serge 307
	r = radeon_bo_init(rdev);
1179 serge 308
	if (r) {
309
		return r;
310
	}
1321 serge 311
	if (rdev->family == CHIP_R420)
312
		r100_enable_bm(rdev);
313
 
1179 serge 314
	if (rdev->flags & RADEON_IS_PCIE) {
315
		r = rv370_pcie_gart_init(rdev);
316
		if (r)
317
			return r;
318
	}
319
	if (rdev->flags & RADEON_IS_PCI) {
320
		r = r100_pci_gart_init(rdev);
321
		if (r)
322
			return r;
323
	}
1404 serge 324
	r420_set_reg_safe(rdev);
2997 Serge 325
 
1179 serge 326
	rdev->accel_working = true;
327
	r = r420_startup(rdev);
328
	if (r) {
329
		/* Somethings want wront with the accel init stop accel */
330
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
331
		if (rdev->flags & RADEON_IS_PCIE)
332
			rv370_pcie_gart_fini(rdev);
333
		if (rdev->flags & RADEON_IS_PCI)
334
			r100_pci_gart_fini(rdev);
335
		rdev->accel_working = false;
336
	}
337
	return 0;
338
}
339
 
340
/*
341
 * Debugfs info
342
 */
343
#if defined(CONFIG_DEBUG_FS)
344
static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
345
{
346
	struct drm_info_node *node = (struct drm_info_node *) m->private;
347
	struct drm_device *dev = node->minor->dev;
348
	struct radeon_device *rdev = dev->dev_private;
349
	uint32_t tmp;
350
 
351
	tmp = RREG32(R400_GB_PIPE_SELECT);
352
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
353
	tmp = RREG32(R300_GB_TILE_CONFIG);
354
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
355
	tmp = RREG32(R300_DST_PIPE_CONFIG);
356
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
357
	return 0;
358
}
359
 
360
static struct drm_info_list r420_pipes_info_list[] = {
361
	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
362
};
363
#endif
364
 
365
int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
366
{
367
#if defined(CONFIG_DEBUG_FS)
368
	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
369
#else
370
	return 0;
371
#endif
372
}